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lxdream.org :: lxdream/src/sh4/sh4.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4.c
changeset 736:a02d1475ccfd
prev671:a530ea88eebd
next740:dd11269ee48b
author nkeynes
date Mon Jul 14 07:44:42 2008 +0000 (13 years ago)
permissions -rw-r--r--
last change Re-indent everything consistently
Fix include guards for consistency as well
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     1 /**
     2  * $Id$
     3  * 
     4  * SH4 parent module for all CPU modes and SH4 peripheral
     5  * modules.
     6  *
     7  * Copyright (c) 2005 Nathan Keynes.
     8  *
     9  * This program is free software; you can redistribute it and/or modify
    10  * it under the terms of the GNU General Public License as published by
    11  * the Free Software Foundation; either version 2 of the License, or
    12  * (at your option) any later version.
    13  *
    14  * This program is distributed in the hope that it will be useful,
    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17  * GNU General Public License for more details.
    18  */
    20 #define MODULE sh4_module
    21 #include <math.h>
    22 #include <assert.h>
    23 #include "lxdream.h"
    24 #include "dreamcast.h"
    25 #include "mem.h"
    26 #include "clock.h"
    27 #include "eventq.h"
    28 #include "syscall.h"
    29 #include "sh4/intc.h"
    30 #include "sh4/sh4core.h"
    31 #include "sh4/sh4mmio.h"
    32 #include "sh4/sh4stat.h"
    33 #include "sh4/sh4trans.h"
    34 #include "sh4/xltcache.h"
    36 void sh4_init( void );
    37 void sh4_xlat_init( void );
    38 void sh4_reset( void );
    39 void sh4_start( void );
    40 void sh4_stop( void );
    41 void sh4_save_state( FILE *f );
    42 int sh4_load_state( FILE *f );
    44 uint32_t sh4_run_slice( uint32_t );
    45 uint32_t sh4_xlat_run_slice( uint32_t );
    47 struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset, 
    48         sh4_start, sh4_run_slice, sh4_stop,
    49         sh4_save_state, sh4_load_state };
    51 struct sh4_registers sh4r;
    52 struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
    53 int sh4_breakpoint_count = 0;
    54 sh4ptr_t sh4_main_ram;
    55 gboolean sh4_starting = FALSE;
    56 static gboolean sh4_use_translator = FALSE;
    57 struct sh4_icache_struct sh4_icache = { NULL, -1, -1, 0 };
    59 void sh4_set_use_xlat( gboolean use )
    60 {
    61     // No-op if the translator was not built
    62 #ifdef SH4_TRANSLATOR
    63     if( use ) {
    64         xlat_cache_init();
    65         sh4_translate_init();
    66         sh4_module.run_time_slice = sh4_xlat_run_slice;
    67     } else {
    68         sh4_module.run_time_slice = sh4_run_slice;
    69     }
    70     sh4_use_translator = use;
    71 #endif
    72 }
    74 gboolean sh4_is_using_xlat()
    75 {
    76     return sh4_use_translator;
    77 }
    79 void sh4_init(void)
    80 {
    81     register_io_regions( mmio_list_sh4mmio );
    82     sh4_main_ram = mem_get_region_by_name(MEM_REGION_MAIN);
    83     MMU_init();
    84     TMU_init();
    85     sh4_reset();
    86 #ifdef ENABLE_SH4STATS
    87     sh4_stats_reset();
    88 #endif
    89 }
    91 void sh4_start(void)
    92 {
    93     sh4_starting = TRUE;
    94 }
    96 void sh4_reset(void)
    97 {
    98     if(	sh4_use_translator ) {
    99         xlat_flush_cache();
   100     }
   102     /* zero everything out, for the sake of having a consistent state. */
   103     memset( &sh4r, 0, sizeof(sh4r) );
   105     /* Resume running if we were halted */
   106     sh4r.sh4_state = SH4_STATE_RUNNING;
   108     sh4r.pc    = 0xA0000000;
   109     sh4r.new_pc= 0xA0000002;
   110     sh4r.vbr   = 0x00000000;
   111     sh4r.fpscr = 0x00040001;
   112     sh4r.sr    = 0x700000F0;
   114     /* Mem reset will do this, but if we want to reset _just_ the SH4... */
   115     MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
   117     /* Peripheral modules */
   118     CPG_reset();
   119     INTC_reset();
   120     MMU_reset();
   121     TMU_reset();
   122     SCIF_reset();
   124 #ifdef ENABLE_SH4STATS
   125     sh4_stats_reset();
   126 #endif
   127 }
   129 void sh4_stop(void)
   130 {
   131     if(	sh4_use_translator ) {
   132         /* If we were running with the translator, update new_pc and in_delay_slot */
   133         sh4r.new_pc = sh4r.pc+2;
   134         sh4r.in_delay_slot = FALSE;
   135     }
   137 }
   139 void sh4_save_state( FILE *f )
   140 {
   141     if(	sh4_use_translator ) {
   142         /* If we were running with the translator, update new_pc and in_delay_slot */
   143         sh4r.new_pc = sh4r.pc+2;
   144         sh4r.in_delay_slot = FALSE;
   145     }
   147     fwrite( &sh4r, sizeof(sh4r), 1, f );
   148     MMU_save_state( f );
   149     INTC_save_state( f );
   150     TMU_save_state( f );
   151     SCIF_save_state( f );
   152 }
   154 int sh4_load_state( FILE * f )
   155 {
   156     if(	sh4_use_translator ) {
   157         xlat_flush_cache();
   158     }
   159     fread( &sh4r, sizeof(sh4r), 1, f );
   160     MMU_load_state( f );
   161     INTC_load_state( f );
   162     TMU_load_state( f );
   163     return SCIF_load_state( f );
   164 }
   167 void sh4_set_breakpoint( uint32_t pc, breakpoint_type_t type )
   168 {
   169     sh4_breakpoints[sh4_breakpoint_count].address = pc;
   170     sh4_breakpoints[sh4_breakpoint_count].type = type;
   171     if( sh4_use_translator ) {
   172         xlat_invalidate_word( pc );
   173     }
   174     sh4_breakpoint_count++;
   175 }
   177 gboolean sh4_clear_breakpoint( uint32_t pc, breakpoint_type_t type )
   178 {
   179     int i;
   181     for( i=0; i<sh4_breakpoint_count; i++ ) {
   182         if( sh4_breakpoints[i].address == pc && 
   183                 sh4_breakpoints[i].type == type ) {
   184             while( ++i < sh4_breakpoint_count ) {
   185                 sh4_breakpoints[i-1].address = sh4_breakpoints[i].address;
   186                 sh4_breakpoints[i-1].type = sh4_breakpoints[i].type;
   187             }
   188             if( sh4_use_translator ) {
   189                 xlat_invalidate_word( pc );
   190             }
   191             sh4_breakpoint_count--;
   192             return TRUE;
   193         }
   194     }
   195     return FALSE;
   196 }
   198 int sh4_get_breakpoint( uint32_t pc )
   199 {
   200     int i;
   201     for( i=0; i<sh4_breakpoint_count; i++ ) {
   202         if( sh4_breakpoints[i].address == pc )
   203             return sh4_breakpoints[i].type;
   204     }
   205     return 0;
   206 }
   208 void sh4_set_pc( int pc )
   209 {
   210     sh4r.pc = pc;
   211     sh4r.new_pc = pc+2;
   212 }
   215 /******************************* Support methods ***************************/
   217 static void sh4_switch_banks( )
   218 {
   219     uint32_t tmp[8];
   221     memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
   222     memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
   223     memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
   224 }
   226 void sh4_switch_fr_banks()
   227 {
   228     int i;
   229     for( i=0; i<16; i++ ) {
   230         float tmp = sh4r.fr[0][i];
   231         sh4r.fr[0][i] = sh4r.fr[1][i];
   232         sh4r.fr[1][i] = tmp;
   233     }
   234 }
   236 void sh4_write_sr( uint32_t newval )
   237 {
   238     int oldbank = (sh4r.sr&SR_MDRB) == SR_MDRB;
   239     int newbank = (newval&SR_MDRB) == SR_MDRB;
   240     if( oldbank != newbank )
   241         sh4_switch_banks();
   242     sh4r.sr = newval;
   243     sh4r.t = (newval&SR_T) ? 1 : 0;
   244     sh4r.s = (newval&SR_S) ? 1 : 0;
   245     sh4r.m = (newval&SR_M) ? 1 : 0;
   246     sh4r.q = (newval&SR_Q) ? 1 : 0;
   247     intc_mask_changed();
   248 }
   250 void sh4_write_fpscr( uint32_t newval )
   251 {
   252     if( (sh4r.fpscr ^ newval) & FPSCR_FR ) {
   253         sh4_switch_fr_banks();
   254     }
   255     sh4r.fpscr = newval;
   256 }
   258 uint32_t sh4_read_sr( void )
   259 {
   260     /* synchronize sh4r.sr with the various bitflags */
   261     sh4r.sr &= SR_MQSTMASK;
   262     if( sh4r.t ) sh4r.sr |= SR_T;
   263     if( sh4r.s ) sh4r.sr |= SR_S;
   264     if( sh4r.m ) sh4r.sr |= SR_M;
   265     if( sh4r.q ) sh4r.sr |= SR_Q;
   266     return sh4r.sr;
   267 }
   271 #define RAISE( x, v ) do{			\
   272     if( sh4r.vbr == 0 ) { \
   273         ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
   274         dreamcast_stop(); return FALSE;	\
   275     } else { \
   276         sh4r.spc = sh4r.pc;	\
   277         sh4r.ssr = sh4_read_sr(); \
   278         sh4r.sgr = sh4r.r[15]; \
   279         MMIO_WRITE(MMU,EXPEVT,x); \
   280         sh4r.pc = sh4r.vbr + v; \
   281         sh4r.new_pc = sh4r.pc + 2; \
   282         sh4_write_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
   283         if( sh4r.in_delay_slot ) { \
   284             sh4r.in_delay_slot = 0; \
   285             sh4r.spc -= 2; \
   286         } \
   287     } \
   288     return TRUE; } while(0)
   290 /**
   291  * Raise a general CPU exception for the specified exception code.
   292  * (NOT for TRAPA or TLB exceptions)
   293  */
   294 gboolean sh4_raise_exception( int code )
   295 {
   296     RAISE( code, EXV_EXCEPTION );
   297 }
   299 /**
   300  * Raise a CPU reset exception with the specified exception code.
   301  */
   302 gboolean sh4_raise_reset( int code )
   303 {
   304     // FIXME: reset modules as per "manual reset"
   305     sh4_reset();
   306     MMIO_WRITE(MMU,EXPEVT,code);
   307     sh4r.vbr = 0;
   308     sh4r.pc = 0xA0000000;
   309     sh4r.new_pc = sh4r.pc + 2;
   310     sh4_write_sr( (sh4r.sr|SR_MD|SR_BL|SR_RB|SR_IMASK)
   311                   &(~SR_FD) );
   312     return TRUE;
   313 }
   315 gboolean sh4_raise_trap( int trap )
   316 {
   317     MMIO_WRITE( MMU, TRA, trap<<2 );
   318     RAISE( EXC_TRAP, EXV_EXCEPTION );
   319 }
   321 gboolean sh4_raise_slot_exception( int normal_code, int slot_code ) {
   322     if( sh4r.in_delay_slot ) {
   323         return sh4_raise_exception(slot_code);
   324     } else {
   325         return sh4_raise_exception(normal_code);
   326     }
   327 }
   329 gboolean sh4_raise_tlb_exception( int code )
   330 {
   331     RAISE( code, EXV_TLBMISS );
   332 }
   334 void sh4_accept_interrupt( void )
   335 {
   336     uint32_t code = intc_accept_interrupt();
   337     sh4r.ssr = sh4_read_sr();
   338     sh4r.spc = sh4r.pc;
   339     sh4r.sgr = sh4r.r[15];
   340     sh4_write_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
   341     MMIO_WRITE( MMU, INTEVT, code );
   342     sh4r.pc = sh4r.vbr + 0x600;
   343     sh4r.new_pc = sh4r.pc + 2;
   344     //    WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
   345 }
   347 void signsat48( void )
   348 {
   349     if( ((int64_t)sh4r.mac) < (int64_t)0xFFFF800000000000LL )
   350         sh4r.mac = 0xFFFF800000000000LL;
   351     else if( ((int64_t)sh4r.mac) > (int64_t)0x00007FFFFFFFFFFFLL )
   352         sh4r.mac = 0x00007FFFFFFFFFFFLL;
   353 }
   355 void sh4_fsca( uint32_t anglei, float *fr )
   356 {
   357     float angle = (((float)(anglei&0xFFFF))/65536.0) * 2 * M_PI;
   358     *fr++ = cosf(angle);
   359     *fr = sinf(angle);
   360 }
   362 /**
   363  * Enter sleep mode (eg by executing a SLEEP instruction).
   364  * Sets sh4_state appropriately and ensures any stopping peripheral modules
   365  * are up to date.
   366  */
   367 void sh4_sleep(void)
   368 {
   369     if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
   370         sh4r.sh4_state = SH4_STATE_STANDBY;
   371         /* Bring all running peripheral modules up to date, and then halt them. */
   372         TMU_run_slice( sh4r.slice_cycle );
   373         SCIF_run_slice( sh4r.slice_cycle );
   374     } else {
   375         if( MMIO_READ( CPG, STBCR2 ) & 0x80 ) {
   376             sh4r.sh4_state = SH4_STATE_DEEP_SLEEP;
   377             /* Halt DMAC but other peripherals still running */
   379         } else {
   380             sh4r.sh4_state = SH4_STATE_SLEEP;
   381         }
   382     }
   383     if( sh4_xlat_is_running() ) {
   384         sh4_translate_exit( XLAT_EXIT_SLEEP );
   385     }
   386 }
   388 /**
   389  * Wakeup following sleep mode (IRQ or reset). Sets state back to running,
   390  * and restarts any peripheral devices that were stopped.
   391  */
   392 void sh4_wakeup(void)
   393 {
   394     switch( sh4r.sh4_state ) {
   395     case SH4_STATE_STANDBY:
   396         break;
   397     case SH4_STATE_DEEP_SLEEP:
   398         break;
   399     case SH4_STATE_SLEEP:
   400         break;
   401     }
   402     sh4r.sh4_state = SH4_STATE_RUNNING;
   403 }
   405 /**
   406  * Run a time slice (or portion of a timeslice) while the SH4 is sleeping.
   407  * Returns when either the SH4 wakes up (interrupt received) or the end of
   408  * the slice is reached. Updates sh4.slice_cycle with the exit time and
   409  * returns the same value.
   410  */
   411 uint32_t sh4_sleep_run_slice( uint32_t nanosecs )
   412 {
   413     int sleep_state = sh4r.sh4_state;
   414     assert( sleep_state != SH4_STATE_RUNNING );
   416     while( sh4r.event_pending < nanosecs ) {
   417         sh4r.slice_cycle = sh4r.event_pending;
   418         if( sh4r.event_types & PENDING_EVENT ) {
   419             event_execute();
   420         }
   421         if( sh4r.event_types & PENDING_IRQ ) {
   422             sh4_wakeup();
   423             return sh4r.slice_cycle;
   424         }
   425     }
   426     sh4r.slice_cycle = nanosecs;
   427     return sh4r.slice_cycle;
   428 }
   431 /**
   432  * Compute the matrix tranform of fv given the matrix xf.
   433  * Both fv and xf are word-swapped as per the sh4r.fr banks
   434  */
   435 void sh4_ftrv( float *target )
   436 {
   437     float fv[4] = { target[1], target[0], target[3], target[2] };
   438     target[1] = sh4r.fr[1][1] * fv[0] + sh4r.fr[1][5]*fv[1] +
   439     sh4r.fr[1][9]*fv[2] + sh4r.fr[1][13]*fv[3];
   440     target[0] = sh4r.fr[1][0] * fv[0] + sh4r.fr[1][4]*fv[1] +
   441     sh4r.fr[1][8]*fv[2] + sh4r.fr[1][12]*fv[3];
   442     target[3] = sh4r.fr[1][3] * fv[0] + sh4r.fr[1][7]*fv[1] +
   443     sh4r.fr[1][11]*fv[2] + sh4r.fr[1][15]*fv[3];
   444     target[2] = sh4r.fr[1][2] * fv[0] + sh4r.fr[1][6]*fv[1] +
   445     sh4r.fr[1][10]*fv[2] + sh4r.fr[1][14]*fv[3];
   446 }
   448 gboolean sh4_has_page( sh4vma_t vma )
   449 {
   450     sh4addr_t addr = mmu_vma_to_phys_disasm(vma);
   451     return addr != MMU_VMA_ERROR && mem_has_page(addr);
   452 }
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