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lxdream.org :: lxdream/src/sh4/sh4core.in
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4core.in
changeset 736:a02d1475ccfd
prev732:f05753bbe723
next740:dd11269ee48b
author nkeynes
date Mon Jul 14 07:44:42 2008 +0000 (11 years ago)
permissions -rw-r--r--
last change Re-indent everything consistently
Fix include guards for consistency as well
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     1 /**
     2  * $Id$
     3  * 
     4  * SH4 emulation core, and parent module for all the SH4 peripheral
     5  * modules.
     6  *
     7  * Copyright (c) 2005 Nathan Keynes.
     8  *
     9  * This program is free software; you can redistribute it and/or modify
    10  * it under the terms of the GNU General Public License as published by
    11  * the Free Software Foundation; either version 2 of the License, or
    12  * (at your option) any later version.
    13  *
    14  * This program is distributed in the hope that it will be useful,
    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17  * GNU General Public License for more details.
    18  */
    20 #define MODULE sh4_module
    21 #include <assert.h>
    22 #include <math.h>
    23 #include "dream.h"
    24 #include "dreamcast.h"
    25 #include "eventq.h"
    26 #include "mem.h"
    27 #include "clock.h"
    28 #include "syscall.h"
    29 #include "sh4/sh4core.h"
    30 #include "sh4/sh4mmio.h"
    31 #include "sh4/sh4stat.h"
    32 #include "sh4/intc.h"
    34 #define SH4_CALLTRACE 1
    36 #define MAX_INT 0x7FFFFFFF
    37 #define MIN_INT 0x80000000
    38 #define MAX_INTF 2147483647.0
    39 #define MIN_INTF -2147483648.0
    41 /********************** SH4 Module Definition ****************************/
    43 uint32_t sh4_run_slice( uint32_t nanosecs ) 
    44 {
    45     int i;
    46     sh4r.slice_cycle = 0;
    48     if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
    49 	sh4_sleep_run_slice(nanosecs);
    50     }
    52     if( sh4_breakpoint_count == 0 ) {
    53 	for( ; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
    54 	    if( SH4_EVENT_PENDING() ) {
    55 		if( sh4r.event_types & PENDING_EVENT ) {
    56 		    event_execute();
    57 		}
    58 		/* Eventq execute may (quite likely) deliver an immediate IRQ */
    59 		if( sh4r.event_types & PENDING_IRQ ) {
    60 		    sh4_accept_interrupt();
    61 		}
    62 	    }
    63 	    if( !sh4_execute_instruction() ) {
    64 		break;
    65 	    }
    66 	}
    67     } else {
    68 	for( ;sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
    69 	    if( SH4_EVENT_PENDING() ) {
    70 		if( sh4r.event_types & PENDING_EVENT ) {
    71 		    event_execute();
    72 		}
    73 		/* Eventq execute may (quite likely) deliver an immediate IRQ */
    74 		if( sh4r.event_types & PENDING_IRQ ) {
    75 		    sh4_accept_interrupt();
    76 		}
    77 	    }
    79 	    if( !sh4_execute_instruction() )
    80 		break;
    81 #ifdef ENABLE_DEBUG_MODE
    82 	    for( i=0; i<sh4_breakpoint_count; i++ ) {
    83 		if( sh4_breakpoints[i].address == sh4r.pc ) {
    84 		    break;
    85 		}
    86 	    }
    87 	    if( i != sh4_breakpoint_count ) {
    88 		dreamcast_stop();
    89 		if( sh4_breakpoints[i].type == BREAK_ONESHOT )
    90 		    sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );
    91 		break;
    92 	    }
    93 #endif	
    94 	}
    95     }
    97     /* If we aborted early, but the cpu is still technically running,
    98      * we're doing a hard abort - cut the timeslice back to what we
    99      * actually executed
   100      */
   101     if( sh4r.slice_cycle != nanosecs && sh4r.sh4_state == SH4_STATE_RUNNING ) {
   102 	nanosecs = sh4r.slice_cycle;
   103     }
   104     if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
   105 	TMU_run_slice( nanosecs );
   106 	SCIF_run_slice( nanosecs );
   107     }
   108     return nanosecs;
   109 }
   111 /********************** SH4 emulation core  ****************************/
   113 #define UNDEF(ir) return sh4_raise_slot_exception(EXC_ILLEGAL, EXC_SLOT_ILLEGAL)
   114 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)
   116 #if(SH4_CALLTRACE == 1)
   117 #define MAX_CALLSTACK 32
   118 static struct call_stack {
   119     sh4addr_t call_addr;
   120     sh4addr_t target_addr;
   121     sh4addr_t stack_pointer;
   122 } call_stack[MAX_CALLSTACK];
   124 static int call_stack_depth = 0;
   125 int sh4_call_trace_on = 0;
   127 static inline void trace_call( sh4addr_t source, sh4addr_t dest ) 
   128 {
   129     if( call_stack_depth < MAX_CALLSTACK ) {
   130 	call_stack[call_stack_depth].call_addr = source;
   131 	call_stack[call_stack_depth].target_addr = dest;
   132 	call_stack[call_stack_depth].stack_pointer = sh4r.r[15];
   133     }
   134     call_stack_depth++;
   135 }
   137 static inline void trace_return( sh4addr_t source, sh4addr_t dest )
   138 {
   139     if( call_stack_depth > 0 ) {
   140 	call_stack_depth--;
   141     }
   142 }
   144 void fprint_stack_trace( FILE *f )
   145 {
   146     int i = call_stack_depth -1;
   147     if( i >= MAX_CALLSTACK )
   148 	i = MAX_CALLSTACK - 1;
   149     for( ; i >= 0; i-- ) {
   150 	fprintf( f, "%d. Call from %08X => %08X, SP=%08X\n", 
   151 		 (call_stack_depth - i), call_stack[i].call_addr,
   152 		 call_stack[i].target_addr, call_stack[i].stack_pointer );
   153     }
   154 }
   156 #define TRACE_CALL( source, dest ) trace_call(source, dest)
   157 #define TRACE_RETURN( source, dest ) trace_return(source, dest)
   158 #else
   159 #define TRACE_CALL( dest, rts ) 
   160 #define TRACE_RETURN( source, dest )
   161 #endif
   163 #define CHECKPRIV() if( !IS_SH4_PRIVMODE() ) return sh4_raise_slot_exception( EXC_ILLEGAL, EXC_SLOT_ILLEGAL )
   164 #define CHECKRALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )
   165 #define CHECKRALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )
   166 #define CHECKRALIGN64(addr) if( (addr)&0x07 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )
   167 #define CHECKWALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )
   168 #define CHECKWALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )
   169 #define CHECKWALIGN64(addr) if( (addr)&0x07 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )
   171 #define CHECKFPUEN() if( !IS_FPU_ENABLED() ) { if( ir == 0xFFFD ) { UNDEF(ir); } else { return sh4_raise_slot_exception( EXC_FPU_DISABLED, EXC_SLOT_FPU_DISABLED ); } }
   172 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); dreamcast_stop(); return FALSE; }
   173 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) return sh4_raise_exception(EXC_SLOT_ILLEGAL)
   175 #define MEM_READ_BYTE( addr, val ) memtmp = mmu_vma_to_phys_read(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { val = sh4_read_byte(memtmp); }
   176 #define MEM_READ_WORD( addr, val ) memtmp = mmu_vma_to_phys_read(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { val = sh4_read_word(memtmp); }
   177 #define MEM_READ_LONG( addr, val ) memtmp = mmu_vma_to_phys_read(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { val = sh4_read_long(memtmp); }
   178 #define MEM_WRITE_BYTE( addr, val ) memtmp = mmu_vma_to_phys_write(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { sh4_write_byte(memtmp, val); }
   179 #define MEM_WRITE_WORD( addr, val ) memtmp = mmu_vma_to_phys_write(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { sh4_write_word(memtmp, val); }
   180 #define MEM_WRITE_LONG( addr, val ) memtmp = mmu_vma_to_phys_write(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { sh4_write_long(memtmp, val); }
   182 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
   184 #define MEM_FP_READ( addr, reg ) \
   185     if( IS_FPU_DOUBLESIZE() ) { \
   186 	CHECKRALIGN64(addr); \
   187 	memtmp = mmu_vma_to_phys_read(addr); \
   188 	if( memtmp == MMU_VMA_ERROR ) { \
   189 	    return TRUE; \
   190 	} else { \
   191 	    if( reg & 1 ) { \
   192                 *((uint32_t *)&XF((reg) & 0x0E)) = sh4_read_long(memtmp); \
   193 	        *((uint32_t *)&XF(reg)) = sh4_read_long(memtmp+4); \
   194 	    } else { \
   195 	        *((uint32_t *)&FR(reg)) = sh4_read_long(memtmp); \
   196 	        *((uint32_t *)&FR((reg) | 0x01)) = sh4_read_long(memtmp+4); \
   197 	    } \
   198 	} \
   199     } else { \
   200         CHECKRALIGN32(addr); \
   201         memtmp = mmu_vma_to_phys_read(addr); \
   202         if( memtmp == MMU_VMA_ERROR ) { \
   203             return TRUE; \
   204         } else { \
   205 	    *((uint32_t *)&FR(reg)) = sh4_read_long(memtmp); \
   206 	} \
   207     }
   208 #define MEM_FP_WRITE( addr, reg ) \
   209     if( IS_FPU_DOUBLESIZE() ) { \
   210         CHECKWALIGN64(addr); \
   211 	memtmp = mmu_vma_to_phys_write(addr); \
   212 	if( memtmp == MMU_VMA_ERROR ) { \
   213 	    return TRUE; \
   214 	} else { \
   215             if( reg & 1 ) { \
   216 	        sh4_write_long( memtmp, *((uint32_t *)&XF((reg)&0x0E)) ); \
   217 	        sh4_write_long( memtmp+4, *((uint32_t *)&XF(reg)) ); \
   218 	    } else { \
   219 	        sh4_write_long( memtmp, *((uint32_t *)&FR(reg)) ); \
   220 	        sh4_write_long( memtmp+4, *((uint32_t *)&FR((reg)|0x01)) ); \
   221 	    } \
   222 	} \
   223     } else { \
   224     	CHECKWALIGN32(addr); \
   225 	memtmp = mmu_vma_to_phys_write(addr); \
   226 	if( memtmp == MMU_VMA_ERROR ) { \
   227 	    return TRUE; \
   228 	} else { \
   229 	    sh4_write_long( memtmp, *((uint32_t *)&FR((reg))) ); \
   230 	} \
   231     }
   233 gboolean sh4_execute_instruction( void )
   234 {
   235     uint32_t pc;
   236     unsigned short ir;
   237     uint32_t tmp;
   238     float ftmp;
   239     double dtmp;
   240     int64_t memtmp; // temporary holder for memory reads
   242 #define R0 sh4r.r[0]
   243     pc = sh4r.pc;
   244     if( pc > 0xFFFFFF00 ) {
   245 	/* SYSCALL Magic */
   246 	syscall_invoke( pc );
   247 	sh4r.in_delay_slot = 0;
   248 	pc = sh4r.pc = sh4r.pr;
   249 	sh4r.new_pc = sh4r.pc + 2;
   250         return TRUE;
   251     }
   252     CHECKRALIGN16(pc);
   254 #ifdef ENABLE_SH4STATS
   255     sh4_stats_add_by_pc(sh4r.pc);
   256 #endif
   258     /* Read instruction */
   259     if( !IS_IN_ICACHE(pc) ) {
   260 	if( !mmu_update_icache(pc) ) {
   261 	    // Fault - look for the fault handler
   262 	    if( !mmu_update_icache(sh4r.pc) ) {
   263 		// double fault - halt
   264 		ERROR( "Double fault - halting" );
   265 		dreamcast_stop();
   266 		return FALSE;
   267 	    }
   268 	}
   269 	pc = sh4r.pc;
   270     }
   271     assert( IS_IN_ICACHE(pc) );
   272     ir = *(uint16_t *)GET_ICACHE_PTR(sh4r.pc);
   273 %%
   274 AND Rm, Rn {: sh4r.r[Rn] &= sh4r.r[Rm]; :}
   275 AND #imm, R0 {: R0 &= imm; :}
   276  AND.B #imm, @(R0, GBR) {: MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm & tmp ); :}
   277 NOT Rm, Rn {: sh4r.r[Rn] = ~sh4r.r[Rm]; :}
   278 OR Rm, Rn {: sh4r.r[Rn] |= sh4r.r[Rm]; :}
   279 OR #imm, R0  {: R0 |= imm; :}
   280  OR.B #imm, @(R0, GBR) {: MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm | tmp ); :}
   281 TAS.B @Rn {:
   282     MEM_READ_BYTE( sh4r.r[Rn], tmp );
   283     sh4r.t = ( tmp == 0 ? 1 : 0 );
   284     MEM_WRITE_BYTE( sh4r.r[Rn], tmp | 0x80 );
   285 :}
   286 TST Rm, Rn {: sh4r.t = (sh4r.r[Rn]&sh4r.r[Rm] ? 0 : 1); :}
   287 TST #imm, R0 {: sh4r.t = (R0 & imm ? 0 : 1); :}
   288  TST.B #imm, @(R0, GBR) {: MEM_READ_BYTE(R0+sh4r.gbr, tmp); sh4r.t = ( tmp & imm ? 0 : 1 ); :}
   289 XOR Rm, Rn {: sh4r.r[Rn] ^= sh4r.r[Rm]; :}
   290 XOR #imm, R0 {: R0 ^= imm; :}
   291  XOR.B #imm, @(R0, GBR) {: MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm ^ tmp ); :}
   292 XTRCT Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rn]>>16) | (sh4r.r[Rm]<<16); :}
   294 ROTL Rn {:
   295     sh4r.t = sh4r.r[Rn] >> 31;
   296     sh4r.r[Rn] <<= 1;
   297     sh4r.r[Rn] |= sh4r.t;
   298 :}
   299 ROTR Rn {:
   300     sh4r.t = sh4r.r[Rn] & 0x00000001;
   301     sh4r.r[Rn] >>= 1;
   302     sh4r.r[Rn] |= (sh4r.t << 31);
   303 :}
   304 ROTCL Rn {:
   305     tmp = sh4r.r[Rn] >> 31;
   306     sh4r.r[Rn] <<= 1;
   307     sh4r.r[Rn] |= sh4r.t;
   308     sh4r.t = tmp;
   309 :}
   310 ROTCR Rn {:
   311     tmp = sh4r.r[Rn] & 0x00000001;
   312     sh4r.r[Rn] >>= 1;
   313     sh4r.r[Rn] |= (sh4r.t << 31 );
   314     sh4r.t = tmp;
   315 :}
   316 SHAD Rm, Rn {:
   317     tmp = sh4r.r[Rm];
   318     if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
   319     else if( (tmp & 0x1F) == 0 )  
   320         sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 31;
   321     else 
   322 	sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> (((~sh4r.r[Rm]) & 0x1F)+1);
   323 :}
   324 SHLD Rm, Rn {:
   325     tmp = sh4r.r[Rm];
   326     if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
   327     else if( (tmp & 0x1F) == 0 ) sh4r.r[Rn] = 0;
   328     else sh4r.r[Rn] >>= (((~tmp) & 0x1F)+1);
   329 :}
   330 SHAL Rn {:
   331     sh4r.t = sh4r.r[Rn] >> 31;
   332     sh4r.r[Rn] <<= 1;
   333 :}
   334 SHAR Rn {:
   335     sh4r.t = sh4r.r[Rn] & 0x00000001;
   336     sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 1;
   337 :}
   338 SHLL Rn {: sh4r.t = sh4r.r[Rn] >> 31; sh4r.r[Rn] <<= 1; :}
   339 SHLR Rn {: sh4r.t = sh4r.r[Rn] & 0x00000001; sh4r.r[Rn] >>= 1; :}
   340 SHLL2 Rn {: sh4r.r[Rn] <<= 2; :}
   341 SHLR2 Rn {: sh4r.r[Rn] >>= 2; :}
   342 SHLL8 Rn {: sh4r.r[Rn] <<= 8; :}
   343 SHLR8 Rn {: sh4r.r[Rn] >>= 8; :}
   344 SHLL16 Rn {: sh4r.r[Rn] <<= 16; :}
   345 SHLR16 Rn {: sh4r.r[Rn] >>= 16; :}
   347 EXTU.B Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]&0x000000FF; :}
   348 EXTU.W Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]&0x0000FFFF; :}
   349 EXTS.B Rm, Rn {: sh4r.r[Rn] = SIGNEXT8( sh4r.r[Rm]&0x000000FF ); :}
   350 EXTS.W Rm, Rn {: sh4r.r[Rn] = SIGNEXT16( sh4r.r[Rm]&0x0000FFFF ); :}
   351 SWAP.B Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rm]&0xFFFF0000) | ((sh4r.r[Rm]&0x0000FF00)>>8) | ((sh4r.r[Rm]&0x000000FF)<<8); :}
   352 SWAP.W Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rm]>>16) | (sh4r.r[Rm]<<16); :}
   354 CLRT {: sh4r.t = 0; :}
   355 SETT {: sh4r.t = 1; :}
   356 CLRMAC {: sh4r.mac = 0; :}
   357 LDTLB {: MMU_ldtlb(); :}
   358 CLRS {: sh4r.s = 0; :}
   359 SETS {: sh4r.s = 1; :}
   360 MOVT Rn {: sh4r.r[Rn] = sh4r.t; :}
   361 NOP {: /* NOP */ :}
   363 PREF @Rn {:
   364      tmp = sh4r.r[Rn];
   365      if( (tmp & 0xFC000000) == 0xE0000000 ) {
   366 	 sh4_flush_store_queue(tmp);
   367      }
   368 :}
   369 OCBI @Rn {: :}
   370 OCBP @Rn {: :}
   371 OCBWB @Rn {: :}
   372 MOVCA.L R0, @Rn {:
   373     tmp = sh4r.r[Rn];
   374     CHECKWALIGN32(tmp);
   375     MEM_WRITE_LONG( tmp, R0 );
   376 :}
   377 MOV.B Rm, @(R0, Rn) {: MEM_WRITE_BYTE( R0 + sh4r.r[Rn], sh4r.r[Rm] ); :}
   378 MOV.W Rm, @(R0, Rn) {: 
   379     CHECKWALIGN16( R0 + sh4r.r[Rn] );
   380     MEM_WRITE_WORD( R0 + sh4r.r[Rn], sh4r.r[Rm] );
   381 :}
   382 MOV.L Rm, @(R0, Rn) {:
   383     CHECKWALIGN32( R0 + sh4r.r[Rn] );
   384     MEM_WRITE_LONG( R0 + sh4r.r[Rn], sh4r.r[Rm] );
   385 :}
   386 MOV.B @(R0, Rm), Rn {: MEM_READ_BYTE( R0 + sh4r.r[Rm], sh4r.r[Rn] ); :}
   387 MOV.W @(R0, Rm), Rn {: CHECKRALIGN16( R0 + sh4r.r[Rm] );
   388     MEM_READ_WORD( R0 + sh4r.r[Rm], sh4r.r[Rn] );
   389 :}
   390 MOV.L @(R0, Rm), Rn {: CHECKRALIGN32( R0 + sh4r.r[Rm] );
   391     MEM_READ_LONG( R0 + sh4r.r[Rm], sh4r.r[Rn] );
   392 :}
   393 MOV.L Rm, @(disp, Rn) {:
   394     tmp = sh4r.r[Rn] + disp;
   395     CHECKWALIGN32( tmp );
   396     MEM_WRITE_LONG( tmp, sh4r.r[Rm] );
   397 :}
   398 MOV.B Rm, @Rn {: MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] ); :}
   399 MOV.W Rm, @Rn {: CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] ); :}
   400 MOV.L Rm, @Rn {: CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] ); :}
   401  MOV.B Rm, @-Rn {: MEM_WRITE_BYTE( sh4r.r[Rn]-1, sh4r.r[Rm] ); sh4r.r[Rn]--; :}
   402  MOV.W Rm, @-Rn {: CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn]-2, sh4r.r[Rm] ); sh4r.r[Rn] -= 2; :}
   403  MOV.L Rm, @-Rn {: CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.r[Rm] ); sh4r.r[Rn] -= 4; :}
   404 MOV.L @(disp, Rm), Rn {:
   405     tmp = sh4r.r[Rm] + disp;
   406     CHECKRALIGN32( tmp );
   407     MEM_READ_LONG( tmp, sh4r.r[Rn] );
   408 :}
   409 MOV.B @Rm, Rn {: MEM_READ_BYTE( sh4r.r[Rm], sh4r.r[Rn] ); :}
   410  MOV.W @Rm, Rn {: CHECKRALIGN16( sh4r.r[Rm] ); MEM_READ_WORD( sh4r.r[Rm], sh4r.r[Rn] ); :}
   411  MOV.L @Rm, Rn {: CHECKRALIGN32( sh4r.r[Rm] ); MEM_READ_LONG( sh4r.r[Rm], sh4r.r[Rn] ); :}
   412 MOV Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]; :}
   413  MOV.B @Rm+, Rn {: MEM_READ_BYTE( sh4r.r[Rm], sh4r.r[Rn] ); sh4r.r[Rm] ++; :}
   414  MOV.W @Rm+, Rn {: CHECKRALIGN16( sh4r.r[Rm] ); MEM_READ_WORD( sh4r.r[Rm], sh4r.r[Rn] ); sh4r.r[Rm] += 2; :}
   415  MOV.L @Rm+, Rn {: CHECKRALIGN32( sh4r.r[Rm] ); MEM_READ_LONG( sh4r.r[Rm], sh4r.r[Rn] ); sh4r.r[Rm] += 4; :}
   416 MOV.L @(disp, PC), Rn {:
   417     CHECKSLOTILLEGAL();
   418     tmp = (pc&0xFFFFFFFC) + disp + 4;
   419     MEM_READ_LONG( tmp, sh4r.r[Rn] );
   420 :}
   421 MOV.B R0, @(disp, GBR) {: MEM_WRITE_BYTE( sh4r.gbr + disp, R0 ); :}
   422 MOV.W R0, @(disp, GBR) {:
   423     tmp = sh4r.gbr + disp;
   424     CHECKWALIGN16( tmp );
   425     MEM_WRITE_WORD( tmp, R0 );
   426 :}
   427 MOV.L R0, @(disp, GBR) {:
   428     tmp = sh4r.gbr + disp;
   429     CHECKWALIGN32( tmp );
   430     MEM_WRITE_LONG( tmp, R0 );
   431 :}
   432  MOV.B @(disp, GBR), R0 {: MEM_READ_BYTE( sh4r.gbr + disp, R0 ); :}
   433 MOV.W @(disp, GBR), R0 {: 
   434     tmp = sh4r.gbr + disp;
   435     CHECKRALIGN16( tmp );
   436     MEM_READ_WORD( tmp, R0 );
   437 :}
   438 MOV.L @(disp, GBR), R0 {:
   439     tmp = sh4r.gbr + disp;
   440     CHECKRALIGN32( tmp );
   441     MEM_READ_LONG( tmp, R0 );
   442 :}
   443 MOV.B R0, @(disp, Rn) {: MEM_WRITE_BYTE( sh4r.r[Rn] + disp, R0 ); :}
   444 MOV.W R0, @(disp, Rn) {: 
   445     tmp = sh4r.r[Rn] + disp;
   446     CHECKWALIGN16( tmp );
   447     MEM_WRITE_WORD( tmp, R0 );
   448 :}
   449  MOV.B @(disp, Rm), R0 {: MEM_READ_BYTE( sh4r.r[Rm] + disp, R0 ); :}
   450 MOV.W @(disp, Rm), R0 {: 
   451     tmp = sh4r.r[Rm] + disp;
   452     CHECKRALIGN16( tmp );
   453     MEM_READ_WORD( tmp, R0 );
   454 :}
   455 MOV.W @(disp, PC), Rn {:
   456     CHECKSLOTILLEGAL();
   457     tmp = pc + 4 + disp;
   458     MEM_READ_WORD( tmp, sh4r.r[Rn] );
   459 :}
   460 MOVA @(disp, PC), R0 {:
   461     CHECKSLOTILLEGAL();
   462     R0 = (pc&0xFFFFFFFC) + disp + 4;
   463 :}
   464 MOV #imm, Rn {:  sh4r.r[Rn] = imm; :}
   466 FMOV @(R0, Rm), FRn {: MEM_FP_READ( sh4r.r[Rm] + R0, FRn ); :}
   467 FMOV FRm, @(R0, Rn) {: MEM_FP_WRITE( sh4r.r[Rn] + R0, FRm ); :}
   468 FMOV @Rm, FRn {: MEM_FP_READ( sh4r.r[Rm], FRn ); :}
   469 FMOV @Rm+, FRn {: MEM_FP_READ( sh4r.r[Rm], FRn ); sh4r.r[Rm] += FP_WIDTH; :}
   470 FMOV FRm, @Rn {: MEM_FP_WRITE( sh4r.r[Rn], FRm ); :}
   471  FMOV FRm, @-Rn {: MEM_FP_WRITE( sh4r.r[Rn] - FP_WIDTH, FRm ); sh4r.r[Rn] -= FP_WIDTH; :}
   472 FMOV FRm, FRn {: 
   473     if( IS_FPU_DOUBLESIZE() )
   474 	DR(FRn) = DR(FRm);
   475     else
   476 	FR(FRn) = FR(FRm);
   477 :}
   479 CMP/EQ #imm, R0 {: sh4r.t = ( R0 == imm ? 1 : 0 ); :}
   480 CMP/EQ Rm, Rn {: sh4r.t = ( sh4r.r[Rm] == sh4r.r[Rn] ? 1 : 0 ); :}
   481 CMP/GE Rm, Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= ((int32_t)sh4r.r[Rm]) ? 1 : 0 ); :}
   482 CMP/GT Rm, Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) > ((int32_t)sh4r.r[Rm]) ? 1 : 0 ); :}
   483 CMP/HI Rm, Rn {: sh4r.t = ( sh4r.r[Rn] > sh4r.r[Rm] ? 1 : 0 ); :}
   484 CMP/HS Rm, Rn {: sh4r.t = ( sh4r.r[Rn] >= sh4r.r[Rm] ? 1 : 0 ); :}
   485 CMP/PL Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) > 0 ? 1 : 0 ); :}
   486 CMP/PZ Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= 0 ? 1 : 0 ); :}
   487 CMP/STR Rm, Rn {: 
   488     /* set T = 1 if any byte in RM & RN is the same */
   489     tmp = sh4r.r[Rm] ^ sh4r.r[Rn];
   490     sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
   491              (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
   492 :}
   494 ADD Rm, Rn {: sh4r.r[Rn] += sh4r.r[Rm]; :}
   495 ADD #imm, Rn {: sh4r.r[Rn] += imm; :}
   496 ADDC Rm, Rn {:
   497     tmp = sh4r.r[Rn];
   498     sh4r.r[Rn] += sh4r.r[Rm] + sh4r.t;
   499     sh4r.t = ( sh4r.r[Rn] < tmp || (sh4r.r[Rn] == tmp && sh4r.t != 0) ? 1 : 0 );
   500 :}
   501 ADDV Rm, Rn {:
   502     tmp = sh4r.r[Rn] + sh4r.r[Rm];
   503     sh4r.t = ( (sh4r.r[Rn]>>31) == (sh4r.r[Rm]>>31) && ((sh4r.r[Rn]>>31) != (tmp>>31)) );
   504     sh4r.r[Rn] = tmp;
   505 :}
   506 DIV0U {: sh4r.m = sh4r.q = sh4r.t = 0; :}
   507 DIV0S Rm, Rn {: 
   508     sh4r.q = sh4r.r[Rn]>>31;
   509     sh4r.m = sh4r.r[Rm]>>31;
   510     sh4r.t = sh4r.q ^ sh4r.m;
   511 :}
   512 DIV1 Rm, Rn {:
   513     /* This is derived from the sh4 manual with some simplifications */
   514     uint32_t tmp0, tmp1, tmp2, dir;
   516     dir = sh4r.q ^ sh4r.m;
   517     sh4r.q = (sh4r.r[Rn] >> 31);
   518     tmp2 = sh4r.r[Rm];
   519     sh4r.r[Rn] = (sh4r.r[Rn] << 1) | sh4r.t;
   520     tmp0 = sh4r.r[Rn];
   521     if( dir ) {
   522          sh4r.r[Rn] += tmp2;
   523          tmp1 = (sh4r.r[Rn]<tmp0 ? 1 : 0 );
   524     } else {
   525          sh4r.r[Rn] -= tmp2;
   526          tmp1 = (sh4r.r[Rn]>tmp0 ? 1 : 0 );
   527     }
   528     sh4r.q ^= sh4r.m ^ tmp1;
   529     sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
   530 :}
   531 DMULS.L Rm, Rn {: sh4r.mac = SIGNEXT32(sh4r.r[Rm]) * SIGNEXT32(sh4r.r[Rn]); :}
   532 DMULU.L Rm, Rn {: sh4r.mac = ((uint64_t)sh4r.r[Rm]) * ((uint64_t)sh4r.r[Rn]); :}
   533 DT Rn {:
   534     sh4r.r[Rn] --;
   535     sh4r.t = ( sh4r.r[Rn] == 0 ? 1 : 0 );
   536 :}
   537 MAC.W @Rm+, @Rn+ {:
   538     int32_t stmp;
   539     if( Rm == Rn ) {
   540 	CHECKRALIGN16(sh4r.r[Rn]);
   541 	MEM_READ_WORD( sh4r.r[Rn], tmp );
   542 	stmp = SIGNEXT16(tmp);
   543 	MEM_READ_WORD( sh4r.r[Rn]+2, tmp );
   544 	stmp *= SIGNEXT16(tmp);
   545 	sh4r.r[Rn] += 4;
   546     } else {
   547 	CHECKRALIGN16( sh4r.r[Rn] );
   548 	CHECKRALIGN16( sh4r.r[Rm] );
   549 	MEM_READ_WORD(sh4r.r[Rn], tmp);
   550 	stmp = SIGNEXT16(tmp);
   551 	MEM_READ_WORD(sh4r.r[Rm], tmp);
   552 	stmp = stmp * SIGNEXT16(tmp);
   553 	sh4r.r[Rn] += 2;
   554 	sh4r.r[Rm] += 2;
   555     }
   556     if( sh4r.s ) {
   557 	int64_t tmpl = (int64_t)((int32_t)sh4r.mac) + (int64_t)stmp;
   558 	if( tmpl > (int64_t)0x000000007FFFFFFFLL ) {
   559 	    sh4r.mac = 0x000000017FFFFFFFLL;
   560 	} else if( tmpl < (int64_t)0xFFFFFFFF80000000LL ) {
   561 	    sh4r.mac = 0x0000000180000000LL;
   562 	} else {
   563 	    sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
   564 		((uint32_t)(sh4r.mac + stmp));
   565 	}
   566     } else {
   567 	sh4r.mac += SIGNEXT32(stmp);
   568     }
   569 :}
   570 MAC.L @Rm+, @Rn+ {:
   571     int64_t tmpl;
   572     if( Rm == Rn ) {
   573 	CHECKRALIGN32( sh4r.r[Rn] );
   574 	MEM_READ_LONG(sh4r.r[Rn], tmp);
   575 	tmpl = SIGNEXT32(tmp);
   576 	MEM_READ_LONG(sh4r.r[Rn]+4, tmp);
   577 	tmpl = tmpl * SIGNEXT32(tmp) + sh4r.mac;
   578 	sh4r.r[Rn] += 8;
   579     } else {
   580 	CHECKRALIGN32( sh4r.r[Rm] );
   581 	CHECKRALIGN32( sh4r.r[Rn] );
   582 	MEM_READ_LONG(sh4r.r[Rn], tmp);
   583 	tmpl = SIGNEXT32(tmp);
   584 	MEM_READ_LONG(sh4r.r[Rm], tmp);
   585 	tmpl = tmpl * SIGNEXT32(tmp) + sh4r.mac;
   586 	sh4r.r[Rn] += 4;
   587 	sh4r.r[Rm] += 4;
   588     }
   589     if( sh4r.s ) {
   590         /* 48-bit Saturation. Yuch */
   591         if( tmpl < (int64_t)0xFFFF800000000000LL )
   592             tmpl = 0xFFFF800000000000LL;
   593         else if( tmpl > (int64_t)0x00007FFFFFFFFFFFLL )
   594             tmpl = 0x00007FFFFFFFFFFFLL;
   595     }
   596     sh4r.mac = tmpl;
   597 :}
   598 MUL.L Rm, Rn {: sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   599                         (sh4r.r[Rm] * sh4r.r[Rn]); :}
   600 MULU.W Rm, Rn {:
   601     sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   602                (uint32_t)((sh4r.r[Rm]&0xFFFF) * (sh4r.r[Rn]&0xFFFF));
   603 :}
   604 MULS.W Rm, Rn {:
   605     sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   606                (uint32_t)(SIGNEXT32(sh4r.r[Rm]&0xFFFF) * SIGNEXT32(sh4r.r[Rn]&0xFFFF));
   607 :}
   608 NEGC Rm, Rn {:
   609     tmp = 0 - sh4r.r[Rm];
   610     sh4r.r[Rn] = tmp - sh4r.t;
   611     sh4r.t = ( 0<tmp || tmp<sh4r.r[Rn] ? 1 : 0 );
   612 :}
   613 NEG Rm, Rn {: sh4r.r[Rn] = 0 - sh4r.r[Rm]; :}
   614 SUB Rm, Rn {: sh4r.r[Rn] -= sh4r.r[Rm]; :}
   615 SUBC Rm, Rn {: 
   616     tmp = sh4r.r[Rn];
   617     sh4r.r[Rn] = sh4r.r[Rn] - sh4r.r[Rm] - sh4r.t;
   618     sh4r.t = (sh4r.r[Rn] > tmp || (sh4r.r[Rn] == tmp && sh4r.t == 1));
   619 :}
   621 BRAF Rn {:
   622      CHECKSLOTILLEGAL();
   623      CHECKDEST( pc + 4 + sh4r.r[Rn] );
   624      sh4r.in_delay_slot = 1;
   625      sh4r.pc = sh4r.new_pc;
   626      sh4r.new_pc = pc + 4 + sh4r.r[Rn];
   627      return TRUE;
   628 :}
   629 BSRF Rn {:
   630      CHECKSLOTILLEGAL();
   631      CHECKDEST( pc + 4 + sh4r.r[Rn] );
   632      sh4r.in_delay_slot = 1;
   633      sh4r.pr = sh4r.pc + 4;
   634      sh4r.pc = sh4r.new_pc;
   635      sh4r.new_pc = pc + 4 + sh4r.r[Rn];
   636      TRACE_CALL( pc, sh4r.new_pc );
   637      return TRUE;
   638 :}
   639 BT disp {:
   640     CHECKSLOTILLEGAL();
   641     if( sh4r.t ) {
   642         CHECKDEST( sh4r.pc + disp + 4 )
   643         sh4r.pc += disp + 4;
   644         sh4r.new_pc = sh4r.pc + 2;
   645         return TRUE;
   646     }
   647 :}
   648 BF disp {:
   649     CHECKSLOTILLEGAL();
   650     if( !sh4r.t ) {
   651         CHECKDEST( sh4r.pc + disp + 4 )
   652         sh4r.pc += disp + 4;
   653         sh4r.new_pc = sh4r.pc + 2;
   654         return TRUE;
   655     }
   656 :}
   657 BT/S disp {:
   658     CHECKSLOTILLEGAL();
   659     if( sh4r.t ) {
   660         CHECKDEST( sh4r.pc + disp + 4 )
   661         sh4r.in_delay_slot = 1;
   662         sh4r.pc = sh4r.new_pc;
   663         sh4r.new_pc = pc + disp + 4;
   664         sh4r.in_delay_slot = 1;
   665         return TRUE;
   666     }
   667 :}
   668 BF/S disp {:
   669     CHECKSLOTILLEGAL();
   670     if( !sh4r.t ) {
   671         CHECKDEST( sh4r.pc + disp + 4 )
   672         sh4r.in_delay_slot = 1;
   673         sh4r.pc = sh4r.new_pc;
   674         sh4r.new_pc = pc + disp + 4;
   675         return TRUE;
   676     }
   677 :}
   678 BRA disp {:
   679     CHECKSLOTILLEGAL();
   680     CHECKDEST( sh4r.pc + disp + 4 );
   681     sh4r.in_delay_slot = 1;
   682     sh4r.pc = sh4r.new_pc;
   683     sh4r.new_pc = pc + 4 + disp;
   684     return TRUE;
   685 :}
   686 BSR disp {:
   687     CHECKDEST( sh4r.pc + disp + 4 );
   688     CHECKSLOTILLEGAL();
   689     sh4r.in_delay_slot = 1;
   690     sh4r.pr = pc + 4;
   691     sh4r.pc = sh4r.new_pc;
   692     sh4r.new_pc = pc + 4 + disp;
   693     TRACE_CALL( pc, sh4r.new_pc );
   694     return TRUE;
   695 :}
   696 TRAPA #imm {:
   697     CHECKSLOTILLEGAL();
   698     sh4r.pc += 2;
   699     sh4_raise_trap( imm );
   700     return TRUE;
   701 :}
   702 RTS {: 
   703     CHECKSLOTILLEGAL();
   704     CHECKDEST( sh4r.pr );
   705     sh4r.in_delay_slot = 1;
   706     sh4r.pc = sh4r.new_pc;
   707     sh4r.new_pc = sh4r.pr;
   708     TRACE_RETURN( pc, sh4r.new_pc );
   709     return TRUE;
   710 :}
   711 SLEEP {:
   712     if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
   713 	sh4r.sh4_state = SH4_STATE_STANDBY;
   714     } else {
   715 	sh4r.sh4_state = SH4_STATE_SLEEP;
   716     }
   717     return FALSE; /* Halt CPU */
   718 :}
   719 RTE {:
   720     CHECKPRIV();
   721     CHECKDEST( sh4r.spc );
   722     CHECKSLOTILLEGAL();
   723     sh4r.in_delay_slot = 1;
   724     sh4r.pc = sh4r.new_pc;
   725     sh4r.new_pc = sh4r.spc;
   726     sh4_write_sr( sh4r.ssr );
   727     return TRUE;
   728 :}
   729 JMP @Rn {:
   730     CHECKDEST( sh4r.r[Rn] );
   731     CHECKSLOTILLEGAL();
   732     sh4r.in_delay_slot = 1;
   733     sh4r.pc = sh4r.new_pc;
   734     sh4r.new_pc = sh4r.r[Rn];
   735     return TRUE;
   736 :}
   737 JSR @Rn {:
   738     CHECKDEST( sh4r.r[Rn] );
   739     CHECKSLOTILLEGAL();
   740     sh4r.in_delay_slot = 1;
   741     sh4r.pc = sh4r.new_pc;
   742     sh4r.new_pc = sh4r.r[Rn];
   743     sh4r.pr = pc + 4;
   744     TRACE_CALL( pc, sh4r.new_pc );
   745     return TRUE;
   746 :}
   747 STS MACH, Rn {: sh4r.r[Rn] = (sh4r.mac>>32); :}
   748 STS.L MACH, @-Rn {:
   749     CHECKWALIGN32( sh4r.r[Rn] );
   750     MEM_WRITE_LONG( sh4r.r[Rn]-4, (sh4r.mac>>32) );
   751     sh4r.r[Rn] -= 4;
   752 :}
   753 STC.L SR, @-Rn {:
   754     CHECKPRIV();
   755     CHECKWALIGN32( sh4r.r[Rn] );
   756     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4_read_sr() );
   757     sh4r.r[Rn] -= 4;
   758 :}
   759 LDS.L @Rm+, MACH {:
   760     CHECKRALIGN32( sh4r.r[Rm] );
   761     MEM_READ_LONG(sh4r.r[Rm], tmp);
   762     sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
   763 	(((uint64_t)tmp)<<32);
   764     sh4r.r[Rm] += 4;
   765 :}
   766 LDC.L @Rm+, SR {:
   767     CHECKSLOTILLEGAL();
   768     CHECKPRIV();
   769     CHECKWALIGN32( sh4r.r[Rm] );
   770     MEM_READ_LONG(sh4r.r[Rm], tmp);
   771     sh4_write_sr( tmp );
   772     sh4r.r[Rm] +=4;
   773 :}
   774 LDS Rm, MACH {:
   775     sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
   776                (((uint64_t)sh4r.r[Rm])<<32);
   777 :}
   778 LDC Rm, SR {:
   779     CHECKSLOTILLEGAL();
   780     CHECKPRIV();
   781     sh4_write_sr( sh4r.r[Rm] );
   782 :}
   783 LDC Rm, SGR {:
   784     CHECKPRIV();
   785     sh4r.sgr = sh4r.r[Rm];
   786 :}
   787 LDC.L @Rm+, SGR {:
   788     CHECKPRIV();
   789     CHECKRALIGN32( sh4r.r[Rm] );
   790     MEM_READ_LONG(sh4r.r[Rm], sh4r.sgr);
   791     sh4r.r[Rm] +=4;
   792 :}
   793 STS MACL, Rn {: sh4r.r[Rn] = (uint32_t)sh4r.mac; :}
   794 STS.L MACL, @-Rn {:
   795     CHECKWALIGN32( sh4r.r[Rn] );
   796     MEM_WRITE_LONG( sh4r.r[Rn]-4, (uint32_t)sh4r.mac );
   797     sh4r.r[Rn] -= 4;
   798 :}
   799 STC.L GBR, @-Rn {:
   800     CHECKWALIGN32( sh4r.r[Rn] );
   801     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.gbr );
   802     sh4r.r[Rn] -= 4;
   803 :}
   804 LDS.L @Rm+, MACL {:
   805     CHECKRALIGN32( sh4r.r[Rm] );
   806     MEM_READ_LONG(sh4r.r[Rm], tmp);
   807     sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
   808                (uint64_t)((uint32_t)tmp);
   809     sh4r.r[Rm] += 4;
   810 :}
   811 LDC.L @Rm+, GBR {:
   812     CHECKRALIGN32( sh4r.r[Rm] );
   813     MEM_READ_LONG(sh4r.r[Rm], sh4r.gbr);
   814     sh4r.r[Rm] +=4;
   815 :}
   816 LDS Rm, MACL {:
   817     sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
   818                (uint64_t)((uint32_t)(sh4r.r[Rm]));
   819 :}
   820 LDC Rm, GBR {: sh4r.gbr = sh4r.r[Rm]; :}
   821 STS PR, Rn {: sh4r.r[Rn] = sh4r.pr; :}
   822 STS.L PR, @-Rn {:
   823     CHECKWALIGN32( sh4r.r[Rn] );
   824     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.pr );
   825     sh4r.r[Rn] -= 4;
   826 :}
   827 STC.L VBR, @-Rn {:
   828     CHECKPRIV();
   829     CHECKWALIGN32( sh4r.r[Rn] );
   830     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.vbr );
   831     sh4r.r[Rn] -= 4;
   832 :}
   833 LDS.L @Rm+, PR {:
   834     CHECKRALIGN32( sh4r.r[Rm] );
   835     MEM_READ_LONG( sh4r.r[Rm], sh4r.pr );
   836     sh4r.r[Rm] += 4;
   837 :}
   838 LDC.L @Rm+, VBR {:
   839     CHECKPRIV();
   840     CHECKRALIGN32( sh4r.r[Rm] );
   841     MEM_READ_LONG(sh4r.r[Rm], sh4r.vbr);
   842     sh4r.r[Rm] +=4;
   843 :}
   844 LDS Rm, PR {: sh4r.pr = sh4r.r[Rm]; :}
   845 LDC Rm, VBR {:
   846     CHECKPRIV();
   847     sh4r.vbr = sh4r.r[Rm];
   848 :}
   849 STC SGR, Rn {:
   850     CHECKPRIV();
   851     sh4r.r[Rn] = sh4r.sgr;
   852 :}
   853 STC.L SGR, @-Rn {:
   854     CHECKPRIV();
   855     CHECKWALIGN32( sh4r.r[Rn] );
   856     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.sgr );
   857     sh4r.r[Rn] -= 4;
   858 :}
   859 STC.L SSR, @-Rn {:
   860     CHECKPRIV();
   861     CHECKWALIGN32( sh4r.r[Rn] );
   862     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.ssr );
   863     sh4r.r[Rn] -= 4;
   864 :}
   865 LDC.L @Rm+, SSR {:
   866     CHECKPRIV();
   867     CHECKRALIGN32( sh4r.r[Rm] );
   868     MEM_READ_LONG(sh4r.r[Rm], sh4r.ssr);
   869     sh4r.r[Rm] +=4;
   870 :}
   871 LDC Rm, SSR {:
   872     CHECKPRIV();
   873     sh4r.ssr = sh4r.r[Rm];
   874 :}
   875 STC.L SPC, @-Rn {:
   876     CHECKPRIV();
   877     CHECKWALIGN32( sh4r.r[Rn] );
   878     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.spc );
   879     sh4r.r[Rn] -= 4;
   880 :}
   881 LDC.L @Rm+, SPC {:
   882     CHECKPRIV();
   883     CHECKRALIGN32( sh4r.r[Rm] );
   884     MEM_READ_LONG(sh4r.r[Rm], sh4r.spc);
   885     sh4r.r[Rm] +=4;
   886 :}
   887 LDC Rm, SPC {:
   888     CHECKPRIV();
   889     sh4r.spc = sh4r.r[Rm];
   890 :}
   891 STS FPUL, Rn {: 
   892     CHECKFPUEN();
   893     sh4r.r[Rn] = FPULi; 
   894 :}
   895 STS.L FPUL, @-Rn {:
   896     CHECKFPUEN();
   897     CHECKWALIGN32( sh4r.r[Rn] );
   898     MEM_WRITE_LONG( sh4r.r[Rn]-4, FPULi );
   899     sh4r.r[Rn] -= 4;
   900 :}
   901 LDS.L @Rm+, FPUL {:
   902     CHECKFPUEN();
   903     CHECKRALIGN32( sh4r.r[Rm] );
   904     MEM_READ_LONG(sh4r.r[Rm], FPULi);
   905     sh4r.r[Rm] +=4;
   906 :}
   907 LDS Rm, FPUL {:
   908     CHECKFPUEN();
   909     FPULi = sh4r.r[Rm]; 
   910 :}
   911 STS FPSCR, Rn {: 
   912     CHECKFPUEN();
   913     sh4r.r[Rn] = sh4r.fpscr; 
   914 :}
   915 STS.L FPSCR, @-Rn {:
   916     CHECKFPUEN();
   917     CHECKWALIGN32( sh4r.r[Rn] );
   918     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.fpscr );
   919     sh4r.r[Rn] -= 4;
   920 :}
   921 LDS.L @Rm+, FPSCR {:
   922     CHECKFPUEN();
   923     CHECKRALIGN32( sh4r.r[Rm] );
   924     MEM_READ_LONG(sh4r.r[Rm], tmp);
   925     sh4r.r[Rm] +=4;
   926     sh4_write_fpscr( tmp );
   927 :}
   928 LDS Rm, FPSCR {: 
   929     CHECKFPUEN();
   930     sh4_write_fpscr( sh4r.r[Rm] );
   931 :}
   932 STC DBR, Rn {: CHECKPRIV(); sh4r.r[Rn] = sh4r.dbr; :}
   933 STC.L DBR, @-Rn {:
   934     CHECKPRIV();
   935     CHECKWALIGN32( sh4r.r[Rn] );
   936     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.dbr );
   937     sh4r.r[Rn] -= 4;
   938 :}
   939 LDC.L @Rm+, DBR {:
   940     CHECKPRIV();
   941     CHECKRALIGN32( sh4r.r[Rm] );
   942     MEM_READ_LONG(sh4r.r[Rm], sh4r.dbr);
   943     sh4r.r[Rm] +=4;
   944 :}
   945 LDC Rm, DBR {:
   946     CHECKPRIV();
   947     sh4r.dbr = sh4r.r[Rm];
   948 :}
   949 STC.L Rm_BANK, @-Rn {:
   950     CHECKPRIV();
   951     CHECKWALIGN32( sh4r.r[Rn] );
   952     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.r_bank[Rm_BANK] );
   953     sh4r.r[Rn] -= 4;
   954 :}
   955 LDC.L @Rm+, Rn_BANK {:
   956     CHECKPRIV();
   957     CHECKRALIGN32( sh4r.r[Rm] );
   958     MEM_READ_LONG( sh4r.r[Rm], sh4r.r_bank[Rn_BANK] );
   959     sh4r.r[Rm] += 4;
   960 :}
   961 LDC Rm, Rn_BANK {:
   962     CHECKPRIV();
   963     sh4r.r_bank[Rn_BANK] = sh4r.r[Rm];
   964 :}
   965 STC SR, Rn {: 
   966     CHECKPRIV();
   967     sh4r.r[Rn] = sh4_read_sr();
   968 :}
   969 STC GBR, Rn {:
   970     sh4r.r[Rn] = sh4r.gbr;
   971 :}
   972 STC VBR, Rn {:
   973     CHECKPRIV();
   974     sh4r.r[Rn] = sh4r.vbr;
   975 :}
   976 STC SSR, Rn {:
   977     CHECKPRIV();
   978     sh4r.r[Rn] = sh4r.ssr;
   979 :}
   980 STC SPC, Rn {:
   981     CHECKPRIV();
   982     sh4r.r[Rn] = sh4r.spc;
   983 :}
   984 STC Rm_BANK, Rn {:
   985     CHECKPRIV();
   986     sh4r.r[Rn] = sh4r.r_bank[Rm_BANK];
   987 :}
   989 FADD FRm, FRn {:
   990     CHECKFPUEN();
   991     if( IS_FPU_DOUBLEPREC() ) {
   992 	DR(FRn) += DR(FRm);
   993     } else {
   994 	FR(FRn) += FR(FRm);
   995     }
   996 :}
   997 FSUB FRm, FRn {:
   998     CHECKFPUEN();
   999     if( IS_FPU_DOUBLEPREC() ) {
  1000 	DR(FRn) -= DR(FRm);
  1001     } else {
  1002 	FR(FRn) -= FR(FRm);
  1004 :}
  1006 FMUL FRm, FRn {:
  1007     CHECKFPUEN();
  1008     if( IS_FPU_DOUBLEPREC() ) {
  1009 	DR(FRn) *= DR(FRm);
  1010     } else {
  1011 	FR(FRn) *= FR(FRm);
  1013 :}
  1015 FDIV FRm, FRn {:
  1016     CHECKFPUEN();
  1017     if( IS_FPU_DOUBLEPREC() ) {
  1018 	DR(FRn) /= DR(FRm);
  1019     } else {
  1020 	FR(FRn) /= FR(FRm);
  1022 :}
  1024 FCMP/EQ FRm, FRn {:
  1025     CHECKFPUEN();
  1026     if( IS_FPU_DOUBLEPREC() ) {
  1027 	sh4r.t = ( DR(FRn) == DR(FRm) ? 1 : 0 );
  1028     } else {
  1029 	sh4r.t = ( FR(FRn) == FR(FRm) ? 1 : 0 );
  1031 :}
  1033 FCMP/GT FRm, FRn {:
  1034     CHECKFPUEN();
  1035     if( IS_FPU_DOUBLEPREC() ) {
  1036 	sh4r.t = ( DR(FRn) > DR(FRm) ? 1 : 0 );
  1037     } else {
  1038 	sh4r.t = ( FR(FRn) > FR(FRm) ? 1 : 0 );
  1040 :}
  1042 FSTS FPUL, FRn {: CHECKFPUEN(); FR(FRn) = FPULf; :}
  1043 FLDS FRm, FPUL {: CHECKFPUEN(); FPULf = FR(FRm); :}
  1044 FLOAT FPUL, FRn {: 
  1045     CHECKFPUEN();
  1046     if( IS_FPU_DOUBLEPREC() ) {
  1047 	if( FRn&1 ) { // No, really...
  1048 	    dtmp = (double)FPULi;
  1049 	    FR(FRn) = *(((float *)&dtmp)+1);
  1050 	} else {
  1051 	    DRF(FRn>>1) = (double)FPULi;
  1053     } else {
  1054 	FR(FRn) = (float)FPULi;
  1056 :}
  1057 FTRC FRm, FPUL {:
  1058     CHECKFPUEN();
  1059     if( IS_FPU_DOUBLEPREC() ) {
  1060 	if( FRm&1 ) {
  1061 	    dtmp = 0;
  1062 	    *(((float *)&dtmp)+1) = FR(FRm);
  1063 	} else {
  1064 	    dtmp = DRF(FRm>>1);
  1066         if( dtmp >= MAX_INTF )
  1067             FPULi = MAX_INT;
  1068         else if( dtmp <= MIN_INTF )
  1069             FPULi = MIN_INT;
  1070         else 
  1071             FPULi = (int32_t)dtmp;
  1072     } else {
  1073 	ftmp = FR(FRm);
  1074 	if( ftmp >= MAX_INTF )
  1075 	    FPULi = MAX_INT;
  1076 	else if( ftmp <= MIN_INTF )
  1077 	    FPULi = MIN_INT;
  1078 	else
  1079 	    FPULi = (int32_t)ftmp;
  1081 :}
  1082 FNEG FRn {:
  1083     CHECKFPUEN();
  1084     if( IS_FPU_DOUBLEPREC() ) {
  1085 	DR(FRn) = -DR(FRn);
  1086     } else {
  1087         FR(FRn) = -FR(FRn);
  1089 :}
  1090 FABS FRn {:
  1091     CHECKFPUEN();
  1092     if( IS_FPU_DOUBLEPREC() ) {
  1093 	DR(FRn) = fabs(DR(FRn));
  1094     } else {
  1095         FR(FRn) = fabsf(FR(FRn));
  1097 :}
  1098 FSQRT FRn {:
  1099     CHECKFPUEN();
  1100     if( IS_FPU_DOUBLEPREC() ) {
  1101 	DR(FRn) = sqrt(DR(FRn));
  1102     } else {
  1103         FR(FRn) = sqrtf(FR(FRn));
  1105 :}
  1106 FLDI0 FRn {:
  1107     CHECKFPUEN();
  1108     if( IS_FPU_DOUBLEPREC() ) {
  1109 	DR(FRn) = 0.0;
  1110     } else {
  1111         FR(FRn) = 0.0;
  1113 :}
  1114 FLDI1 FRn {:
  1115     CHECKFPUEN();
  1116     if( IS_FPU_DOUBLEPREC() ) {
  1117 	DR(FRn) = 1.0;
  1118     } else {
  1119         FR(FRn) = 1.0;
  1121 :}
  1122 FMAC FR0, FRm, FRn {:
  1123     CHECKFPUEN();
  1124     if( IS_FPU_DOUBLEPREC() ) {
  1125         DR(FRn) += DR(FRm)*DR(0);
  1126     } else {
  1127 	FR(FRn) += FR(FRm)*FR(0);
  1129 :}
  1130 FRCHG {: 
  1131     CHECKFPUEN(); 
  1132     sh4r.fpscr ^= FPSCR_FR; 
  1133     sh4_switch_fr_banks();
  1134 :}
  1135 FSCHG {: CHECKFPUEN(); sh4r.fpscr ^= FPSCR_SZ; :}
  1136 FCNVSD FPUL, FRn {:
  1137     CHECKFPUEN();
  1138     if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
  1139 	DR(FRn) = (double)FPULf;
  1141 :}
  1142 FCNVDS FRm, FPUL {:
  1143     CHECKFPUEN();
  1144     if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
  1145 	FPULf = (float)DR(FRm);
  1147 :}
  1149 FSRRA FRn {:
  1150     CHECKFPUEN();
  1151     if( !IS_FPU_DOUBLEPREC() ) {
  1152 	FR(FRn) = 1.0/sqrtf(FR(FRn));
  1154 :}
  1155 FIPR FVm, FVn {:
  1156     CHECKFPUEN();
  1157     if( !IS_FPU_DOUBLEPREC() ) {
  1158         int tmp2 = FVn<<2;
  1159         tmp = FVm<<2;
  1160         FR(tmp2+3) = FR(tmp)*FR(tmp2) +
  1161             FR(tmp+1)*FR(tmp2+1) +
  1162             FR(tmp+2)*FR(tmp2+2) +
  1163             FR(tmp+3)*FR(tmp2+3);
  1165 :}
  1166 FSCA FPUL, FRn {:
  1167     CHECKFPUEN();
  1168     if( !IS_FPU_DOUBLEPREC() ) {
  1169 	sh4_fsca( FPULi, &(DRF(FRn>>1)) );
  1170 	/*
  1171         float angle = (((float)(FPULi&0xFFFF))/65536.0) * 2 * M_PI;
  1172         FR(FRn) = sinf(angle);
  1173         FR((FRn)+1) = cosf(angle);
  1174 	*/
  1176 :}
  1177 FTRV XMTRX, FVn {:
  1178     CHECKFPUEN();
  1179     if( !IS_FPU_DOUBLEPREC() ) {
  1180 	sh4_ftrv(&(DRF(FVn<<1)) );
  1182 :}
  1183 UNDEF {:
  1184     UNDEF(ir);
  1185 :}
  1186 %%
  1187     sh4r.pc = sh4r.new_pc;
  1188     sh4r.new_pc += 2;
  1189     sh4r.in_delay_slot = 0;
  1190     return TRUE;
.