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lxdream.org :: lxdream/src/sh4/sh4.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4.c
changeset 569:a1c49e1e8776
prev566:59be465e5f01
next571:9bc09948d0f2
author nkeynes
date Fri Jan 04 11:54:17 2008 +0000 (14 years ago)
branchlxdream-mmu
permissions -rw-r--r--
last change Bring icache partially into line with the mmu, a little less slow with AT off
now.
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     1 /**
     2  * $Id$
     3  * 
     4  * SH4 parent module for all CPU modes and SH4 peripheral
     5  * modules.
     6  *
     7  * Copyright (c) 2005 Nathan Keynes.
     8  *
     9  * This program is free software; you can redistribute it and/or modify
    10  * it under the terms of the GNU General Public License as published by
    11  * the Free Software Foundation; either version 2 of the License, or
    12  * (at your option) any later version.
    13  *
    14  * This program is distributed in the hope that it will be useful,
    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17  * GNU General Public License for more details.
    18  */
    20 #define MODULE sh4_module
    21 #include <math.h>
    22 #include "dream.h"
    23 #include "dreamcast.h"
    24 #include "sh4/sh4core.h"
    25 #include "sh4/sh4mmio.h"
    26 #include "sh4/intc.h"
    27 #include "sh4/xltcache.h"
    28 #include "sh4/sh4stat.h"
    29 #include "mem.h"
    30 #include "clock.h"
    31 #include "syscall.h"
    33 void sh4_init( void );
    34 void sh4_xlat_init( void );
    35 void sh4_reset( void );
    36 void sh4_start( void );
    37 void sh4_stop( void );
    38 void sh4_save_state( FILE *f );
    39 int sh4_load_state( FILE *f );
    41 uint32_t sh4_run_slice( uint32_t );
    42 uint32_t sh4_xlat_run_slice( uint32_t );
    44 struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset, 
    45 				       NULL, sh4_run_slice, sh4_stop,
    46 				       sh4_save_state, sh4_load_state };
    48 struct sh4_registers sh4r;
    49 struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
    50 int sh4_breakpoint_count = 0;
    51 sh4ptr_t sh4_main_ram;
    52 static gboolean sh4_use_translator = FALSE;
    53 struct sh4_icache_struct sh4_icache = { NULL, -1, -1, 0 };
    55 void sh4_set_use_xlat( gboolean use )
    56 {
    57 // No-op if the translator was not built
    58 #ifdef SH4_TRANSLATOR
    59     if( use ) {
    60 	xlat_cache_init();
    61 	sh4_x86_init();
    62 	sh4_module.run_time_slice = sh4_xlat_run_slice;
    63     } else {
    64 	sh4_module.run_time_slice = sh4_run_slice;
    65     }
    66     sh4_use_translator = use;
    67 #endif
    68 }
    70 void sh4_init(void)
    71 {
    72     register_io_regions( mmio_list_sh4mmio );
    73     sh4_main_ram = mem_get_region_by_name(MEM_REGION_MAIN);
    74     MMU_init();
    75     sh4_reset();
    76 }
    78 void sh4_reset(void)
    79 {
    80     if(	sh4_use_translator ) {
    81 	xlat_flush_cache();
    82     }
    84     /* zero everything out, for the sake of having a consistent state. */
    85     memset( &sh4r, 0, sizeof(sh4r) );
    87     /* Resume running if we were halted */
    88     sh4r.sh4_state = SH4_STATE_RUNNING;
    90     sh4r.pc    = 0xA0000000;
    91     sh4r.new_pc= 0xA0000002;
    92     sh4r.vbr   = 0x00000000;
    93     sh4r.fpscr = 0x00040001;
    94     sh4r.sr    = 0x700000F0;
    95     sh4r.fr_bank = &sh4r.fr[0][0];
    97     /* Mem reset will do this, but if we want to reset _just_ the SH4... */
    98     MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
   100     /* Peripheral modules */
   101     CPG_reset();
   102     INTC_reset();
   103     MMU_reset();
   104     TMU_reset();
   105     SCIF_reset();
   106     sh4_stats_reset();
   107 }
   109 void sh4_stop(void)
   110 {
   111     if(	sh4_use_translator ) {
   112 	/* If we were running with the translator, update new_pc and in_delay_slot */
   113 	sh4r.new_pc = sh4r.pc+2;
   114 	sh4r.in_delay_slot = FALSE;
   115     }
   117 }
   119 void sh4_save_state( FILE *f )
   120 {
   121     if(	sh4_use_translator ) {
   122 	/* If we were running with the translator, update new_pc and in_delay_slot */
   123 	sh4r.new_pc = sh4r.pc+2;
   124 	sh4r.in_delay_slot = FALSE;
   125     }
   127     fwrite( &sh4r, sizeof(sh4r), 1, f );
   128     MMU_save_state( f );
   129     INTC_save_state( f );
   130     TMU_save_state( f );
   131     SCIF_save_state( f );
   132 }
   134 int sh4_load_state( FILE * f )
   135 {
   136     if(	sh4_use_translator ) {
   137 	xlat_flush_cache();
   138     }
   139     fread( &sh4r, sizeof(sh4r), 1, f );
   140     sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0]; // Fixup internal FR pointer
   141     MMU_load_state( f );
   142     INTC_load_state( f );
   143     TMU_load_state( f );
   144     return SCIF_load_state( f );
   145 }
   148 void sh4_set_breakpoint( uint32_t pc, breakpoint_type_t type )
   149 {
   150     sh4_breakpoints[sh4_breakpoint_count].address = pc;
   151     sh4_breakpoints[sh4_breakpoint_count].type = type;
   152     sh4_breakpoint_count++;
   153 }
   155 gboolean sh4_clear_breakpoint( uint32_t pc, breakpoint_type_t type )
   156 {
   157     int i;
   159     for( i=0; i<sh4_breakpoint_count; i++ ) {
   160 	if( sh4_breakpoints[i].address == pc && 
   161 	    sh4_breakpoints[i].type == type ) {
   162 	    while( ++i < sh4_breakpoint_count ) {
   163 		sh4_breakpoints[i-1].address = sh4_breakpoints[i].address;
   164 		sh4_breakpoints[i-1].type = sh4_breakpoints[i].type;
   165 	    }
   166 	    sh4_breakpoint_count--;
   167 	    return TRUE;
   168 	}
   169     }
   170     return FALSE;
   171 }
   173 int sh4_get_breakpoint( uint32_t pc )
   174 {
   175     int i;
   176     for( i=0; i<sh4_breakpoint_count; i++ ) {
   177 	if( sh4_breakpoints[i].address == pc )
   178 	    return sh4_breakpoints[i].type;
   179     }
   180     return 0;
   181 }
   183 void sh4_set_pc( int pc )
   184 {
   185     sh4r.pc = pc;
   186     sh4r.new_pc = pc+2;
   187 }
   190 /******************************* Support methods ***************************/
   192 static void sh4_switch_banks( )
   193 {
   194     uint32_t tmp[8];
   196     memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
   197     memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
   198     memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
   199 }
   201 void sh4_write_sr( uint32_t newval )
   202 {
   203     if( (newval ^ sh4r.sr) & SR_RB )
   204         sh4_switch_banks();
   205     sh4r.sr = newval;
   206     sh4r.t = (newval&SR_T) ? 1 : 0;
   207     sh4r.s = (newval&SR_S) ? 1 : 0;
   208     sh4r.m = (newval&SR_M) ? 1 : 0;
   209     sh4r.q = (newval&SR_Q) ? 1 : 0;
   210     intc_mask_changed();
   211 }
   213 uint32_t sh4_read_sr( void )
   214 {
   215     /* synchronize sh4r.sr with the various bitflags */
   216     sh4r.sr &= SR_MQSTMASK;
   217     if( sh4r.t ) sh4r.sr |= SR_T;
   218     if( sh4r.s ) sh4r.sr |= SR_S;
   219     if( sh4r.m ) sh4r.sr |= SR_M;
   220     if( sh4r.q ) sh4r.sr |= SR_Q;
   221     return sh4r.sr;
   222 }
   226 #define RAISE( x, v ) do{			\
   227     if( sh4r.vbr == 0 ) { \
   228         ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
   229         dreamcast_stop(); return FALSE;	\
   230     } else { \
   231         sh4r.spc = sh4r.pc;	\
   232         sh4r.ssr = sh4_read_sr(); \
   233         sh4r.sgr = sh4r.r[15]; \
   234         MMIO_WRITE(MMU,EXPEVT,x); \
   235         sh4r.pc = sh4r.vbr + v; \
   236         sh4r.new_pc = sh4r.pc + 2; \
   237         sh4_write_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
   238 	if( sh4r.in_delay_slot ) { \
   239 	    sh4r.in_delay_slot = 0; \
   240 	    sh4r.spc -= 2; \
   241 	} \
   242     } \
   243     return TRUE; } while(0)
   245 /**
   246  * Raise a general CPU exception for the specified exception code.
   247  * (NOT for TRAPA or TLB exceptions)
   248  */
   249 gboolean sh4_raise_exception( int code )
   250 {
   251     RAISE( code, EXV_EXCEPTION );
   252 }
   254 /**
   255  * Raise a CPU reset exception with the specified exception code.
   256  */
   257 gboolean sh4_raise_reset( int code )
   258 {
   259     // FIXME: reset modules as per "manual reset"
   260     sh4_reset();
   261     MMIO_WRITE(MMU,EXPEVT,code);
   262     sh4r.vbr = 0;
   263     sh4r.pc = 0xA0000000;
   264     sh4r.new_pc = sh4r.pc + 2;
   265     sh4_write_sr( (sh4r.sr|SR_MD|SR_BL|SR_RB|SR_IMASK)
   266 		  &(~SR_FD) );
   267 }
   269 gboolean sh4_raise_trap( int trap )
   270 {
   271     MMIO_WRITE( MMU, TRA, trap<<2 );
   272     return sh4_raise_exception( EXC_TRAP );
   273 }
   275 gboolean sh4_raise_slot_exception( int normal_code, int slot_code ) {
   276     if( sh4r.in_delay_slot ) {
   277 	return sh4_raise_exception(slot_code);
   278     } else {
   279 	return sh4_raise_exception(normal_code);
   280     }
   281 }
   283 gboolean sh4_raise_tlb_exception( int code )
   284 {
   285     RAISE( code, EXV_TLBMISS );
   286 }
   288 void sh4_accept_interrupt( void )
   289 {
   290     uint32_t code = intc_accept_interrupt();
   291     sh4r.ssr = sh4_read_sr();
   292     sh4r.spc = sh4r.pc;
   293     sh4r.sgr = sh4r.r[15];
   294     sh4_write_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
   295     MMIO_WRITE( MMU, INTEVT, code );
   296     sh4r.pc = sh4r.vbr + 0x600;
   297     sh4r.new_pc = sh4r.pc + 2;
   298     //    WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
   299 }
   301 void signsat48( void )
   302 {
   303     if( ((int64_t)sh4r.mac) < (int64_t)0xFFFF800000000000LL )
   304 	sh4r.mac = 0xFFFF800000000000LL;
   305     else if( ((int64_t)sh4r.mac) > (int64_t)0x00007FFFFFFFFFFFLL )
   306 	sh4r.mac = 0x00007FFFFFFFFFFFLL;
   307 }
   309 void sh4_fsca( uint32_t anglei, float *fr )
   310 {
   311     float angle = (((float)(anglei&0xFFFF))/65536.0) * 2 * M_PI;
   312     *fr++ = cosf(angle);
   313     *fr = sinf(angle);
   314 }
   316 void sh4_sleep(void)
   317 {
   318     if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
   319 	sh4r.sh4_state = SH4_STATE_STANDBY;
   320     } else {
   321 	sh4r.sh4_state = SH4_STATE_SLEEP;
   322     }
   323 }
   325 /**
   326  * Compute the matrix tranform of fv given the matrix xf.
   327  * Both fv and xf are word-swapped as per the sh4r.fr banks
   328  */
   329 void sh4_ftrv( float *target, float *xf )
   330 {
   331     float fv[4] = { target[1], target[0], target[3], target[2] };
   332     target[1] = xf[1] * fv[0] + xf[5]*fv[1] +
   333 	xf[9]*fv[2] + xf[13]*fv[3];
   334     target[0] = xf[0] * fv[0] + xf[4]*fv[1] +
   335 	xf[8]*fv[2] + xf[12]*fv[3];
   336     target[3] = xf[3] * fv[0] + xf[7]*fv[1] +
   337 	xf[11]*fv[2] + xf[15]*fv[3];
   338     target[2] = xf[2] * fv[0] + xf[6]*fv[1] +
   339 	xf[10]*fv[2] + xf[14]*fv[3];
   340 }
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