lxdream 0.9.1| filename | src/sh4/sh4core.h |
| changeset | 569:a1c49e1e8776 |
| prev | 564:dc7b5ffb0535 |
| next | 570:d2893980fbf5 |
| author | nkeynes |
| date | Fri Jan 04 11:54:17 2008 +0000 (16 years ago) |
| branch | lxdream-mmu |
| permissions | -rw-r--r-- |
| last change | Bring icache partially into line with the mmu, a little less slow with AT off now. |
| view | annotate | diff | log | raw |
1 /**
2 * $Id$
3 *
4 * This file defines the internal functions exported/used by the SH4 core,
5 * except for disassembly functions defined in sh4dasm.h
6 *
7 * Copyright (c) 2005 Nathan Keynes.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
20 #ifndef sh4core_H
21 #define sh4core_H 1
23 #include <glib/gtypes.h>
24 #include <stdint.h>
25 #include <stdio.h>
26 #include "mem.h"
27 #include "sh4/sh4.h"
29 #ifdef __cplusplus
30 extern "C" {
31 #endif
33 /* Breakpoint data structure */
34 extern struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
35 extern int sh4_breakpoint_count;
36 extern sh4ptr_t sh4_main_ram;
38 /**
39 * Cached direct pointer to the current instruction page. If AT is on, this
40 * is derived from the ITLB, otherwise this will be the entire memory region.
41 * This is actually a fairly useful optimization, as we can make a lot of
42 * assumptions about the "current page" that we can't make in general for
43 * arbitrary virtual addresses.
44 */
45 struct sh4_icache_struct {
46 sh4ptr_t page; // Page pointer (NULL if no page)
47 sh4vma_t page_vma; // virtual address of the page.
48 sh4addr_t page_ppa; // physical address of the page
49 uint32_t mask; // page mask
50 };
51 extern struct sh4_icache_struct sh4_icache;
53 /**
54 * Test if a given address is contained in the current icache entry
55 */
56 #define IS_IN_ICACHE(addr) (sh4_icache.page_vma == ((addr) & sh4_icache.mask))
57 /**
58 * Return a pointer for the given vma, under the assumption that it is
59 * actually contained in the current icache entry.
60 */
61 #define GET_ICACHE_PTR(addr) (sh4_icache.page + ((addr)-sh4_icache.page_vma))
62 /**
63 * Return the physical (external) address for the given vma, assuming that it is
64 * actually contained in the current icache entry.
65 */
66 #define GET_ICACHE_PHYS(addr) (sh4_icache.page_ppa + ((addr)-sh4_icache.page_vma))
68 /* SH4 module functions */
69 void sh4_init( void );
70 void sh4_reset( void );
71 void sh4_run( void );
72 void sh4_stop( void );
74 /* SH4 peripheral module functions */
75 void CPG_reset( void );
76 void DMAC_reset( void );
77 void DMAC_run_slice( uint32_t );
78 void DMAC_save_state( FILE * );
79 int DMAC_load_state( FILE * );
80 void INTC_reset( void );
81 void INTC_save_state( FILE *f );
82 int INTC_load_state( FILE *f );
83 void MMU_init( void );
84 void MMU_reset( void );
85 void MMU_save_state( FILE *f );
86 int MMU_load_state( FILE *f );
87 void MMU_ldtlb();
88 void SCIF_reset( void );
89 void SCIF_run_slice( uint32_t );
90 void SCIF_save_state( FILE *f );
91 int SCIF_load_state( FILE *f );
92 void SCIF_update_line_speed(void);
93 void TMU_reset( void );
94 void TMU_run_slice( uint32_t );
95 void TMU_save_state( FILE * );
96 int TMU_load_state( FILE * );
97 void TMU_update_clocks( void );
99 /* SH4 instruction support methods */
100 void sh4_sleep( void );
101 void sh4_fsca( uint32_t angle, float *fr );
102 void sh4_ftrv( float *fv, float *xmtrx );
103 uint32_t sh4_read_sr(void);
104 void sh4_write_sr(uint32_t val);
105 void signsat48(void);
107 /* SH4 Memory */
108 gboolean mmu_update_icache( sh4vma_t addr );
109 uint64_t mmu_vma_to_phys_read( sh4vma_t addr );
110 uint64_t mmu_vma_to_phys_write( sh4vma_t addr );
111 uint64_t mmu_vma_to_phys_exec( sh4vma_t addr );
113 int64_t sh4_read_quad( sh4addr_t addr );
114 int64_t sh4_read_long( sh4addr_t addr );
115 int64_t sh4_read_word( sh4addr_t addr );
116 int64_t sh4_read_byte( sh4addr_t addr );
117 void sh4_write_quad( sh4addr_t addr, uint64_t val );
118 int32_t sh4_write_long( sh4addr_t addr, uint32_t val );
119 int32_t sh4_write_word( sh4addr_t addr, uint32_t val );
120 int32_t sh4_write_byte( sh4addr_t addr, uint32_t val );
121 int32_t sh4_read_phys_word( sh4addr_t addr );
122 void sh4_flush_store_queue( sh4addr_t addr );
123 sh4ptr_t sh4_get_region_by_vma( sh4addr_t addr );
125 /* SH4 Exceptions */
126 #define EXC_POWER_RESET 0x000 /* reset vector */
127 #define EXC_MANUAL_RESET 0x020 /* reset vector */
128 #define EXC_TLB_MISS_READ 0x040 /* TLB vector */
129 #define EXC_TLB_MISS_WRITE 0x060 /* TLB vector */
130 #define EXC_INIT_PAGE_WRITE 0x080
131 #define EXC_TLB_PROT_READ 0x0A0
132 #define EXC_TLB_PROT_WRITE 0x0C0
133 #define EXC_DATA_ADDR_READ 0x0E0
134 #define EXC_DATA_ADDR_WRITE 0x100
135 #define EXC_TLB_MULTI_HIT 0x140
136 #define EXC_SLOT_ILLEGAL 0x1A0
137 #define EXC_ILLEGAL 0x180
138 #define EXC_TRAP 0x160
139 #define EXC_FPU_DISABLED 0x800
140 #define EXC_SLOT_FPU_DISABLED 0x820
142 #define EXV_EXCEPTION 0x100 /* General exception vector */
143 #define EXV_TLBMISS 0x400 /* TLB-miss exception vector */
144 #define EXV_INTERRUPT 0x600 /* External interrupt vector */
146 gboolean sh4_raise_exception( int );
147 gboolean sh4_raise_reset( int );
148 gboolean sh4_raise_trap( int );
149 gboolean sh4_raise_slot_exception( int, int );
150 gboolean sh4_raise_tlb_exception( int );
151 void sh4_accept_interrupt( void );
153 #define SIGNEXT4(n) ((((int32_t)(n))<<28)>>28)
154 #define SIGNEXT8(n) ((int32_t)((int8_t)(n)))
155 #define SIGNEXT12(n) ((((int32_t)(n))<<20)>>20)
156 #define SIGNEXT16(n) ((int32_t)((int16_t)(n)))
157 #define SIGNEXT32(n) ((int64_t)((int32_t)(n)))
158 #define SIGNEXT48(n) ((((int64_t)(n))<<16)>>16)
159 #define ZEROEXT32(n) ((int64_t)((uint64_t)((uint32_t)(n))))
161 /* Status Register (SR) bits */
162 #define SR_MD 0x40000000 /* Processor mode ( User=0, Privileged=1 ) */
163 #define SR_RB 0x20000000 /* Register bank (priviledged mode only) */
164 #define SR_BL 0x10000000 /* Exception/interupt block (1 = masked) */
165 #define SR_FD 0x00008000 /* FPU disable */
166 #define SR_M 0x00000200
167 #define SR_Q 0x00000100
168 #define SR_IMASK 0x000000F0 /* Interrupt mask level */
169 #define SR_S 0x00000002 /* Saturation operation for MAC instructions */
170 #define SR_T 0x00000001 /* True/false or carry/borrow */
171 #define SR_MASK 0x700083F3
172 #define SR_MQSTMASK 0xFFFFFCFC /* Mask to clear the flags we're keeping separately */
174 #define IS_SH4_PRIVMODE() (sh4r.sr&SR_MD)
175 #define SH4_INTMASK() ((sh4r.sr&SR_IMASK)>>4)
176 #define SH4_EVENT_PENDING() (sh4r.event_pending <= sh4r.slice_cycle && !sh4r.in_delay_slot)
178 #define FPSCR_FR 0x00200000 /* FPU register bank */
179 #define FPSCR_SZ 0x00100000 /* FPU transfer size (0=32 bits, 1=64 bits) */
180 #define FPSCR_PR 0x00080000 /* Precision (0=32 bites, 1=64 bits) */
181 #define FPSCR_DN 0x00040000 /* Denormalization mode (1 = treat as 0) */
182 #define FPSCR_CAUSE 0x0003F000
183 #define FPSCR_ENABLE 0x00000F80
184 #define FPSCR_FLAG 0x0000007C
185 #define FPSCR_RM 0x00000003 /* Rounding mode (0=nearest, 1=to zero) */
187 #define IS_FPU_DOUBLEPREC() (sh4r.fpscr&FPSCR_PR)
188 #define IS_FPU_DOUBLESIZE() (sh4r.fpscr&FPSCR_SZ)
189 #define IS_FPU_ENABLED() ((sh4r.sr&SR_FD)==0)
191 #define FR(x) sh4r.fr_bank[(x)^1]
192 #define DRF(x) ((double *)sh4r.fr_bank)[x]
193 #define XF(x) sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21][(x)^1]
194 #define XDR(x) ((double *)(sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21]))[x]
195 #define DRb(x,b) ((double *)(sh4r.fr[((b ? (~sh4r.fpscr) : sh4r.fpscr)&FPSCR_FR)>>21]))[x]
196 #define DR(x) DRb((x>>1), (x&1))
197 #define FPULf *((float *)&sh4r.fpul)
198 #define FPULi (sh4r.fpul)
200 #define SH4_WRITE_STORE_QUEUE(addr,val) sh4r.store_queue[(addr>>2)&0xF] = val;
202 #ifdef __cplusplus
203 }
204 #endif
205 #endif
.