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lxdream.org :: lxdream/src/sh4/sh4x86.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.c
changeset 550:a27e31340147
prev547:d6e00ffc4adc
next553:4e6166258c22
author nkeynes
date Thu Dec 06 10:43:30 2007 +0000 (12 years ago)
permissions -rw-r--r--
last change Add support for the MMIO side of the TLB (and LDTLB)
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     1 /**
     2  * $Id: sh4x86.in,v 1.20 2007-11-08 11:54:16 nkeynes Exp $
     3  * 
     4  * SH4 => x86 translation. This version does no real optimization, it just
     5  * outputs straight-line x86 code - it mainly exists to provide a baseline
     6  * to test the optimizing versions against.
     7  *
     8  * Copyright (c) 2007 Nathan Keynes.
     9  *
    10  * This program is free software; you can redistribute it and/or modify
    11  * it under the terms of the GNU General Public License as published by
    12  * the Free Software Foundation; either version 2 of the License, or
    13  * (at your option) any later version.
    14  *
    15  * This program is distributed in the hope that it will be useful,
    16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    18  * GNU General Public License for more details.
    19  */
    21 #include <assert.h>
    22 #include <math.h>
    24 #ifndef NDEBUG
    25 #define DEBUG_JUMPS 1
    26 #endif
    28 #include "sh4/xltcache.h"
    29 #include "sh4/sh4core.h"
    30 #include "sh4/sh4trans.h"
    31 #include "sh4/sh4mmio.h"
    32 #include "sh4/x86op.h"
    33 #include "clock.h"
    35 #define DEFAULT_BACKPATCH_SIZE 4096
    37 /** 
    38  * Struct to manage internal translation state. This state is not saved -
    39  * it is only valid between calls to sh4_translate_begin_block() and
    40  * sh4_translate_end_block()
    41  */
    42 struct sh4_x86_state {
    43     gboolean in_delay_slot;
    44     gboolean priv_checked; /* true if we've already checked the cpu mode. */
    45     gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
    46     gboolean branch_taken; /* true if we branched unconditionally */
    47     uint32_t block_start_pc;
    48     uint32_t stack_posn;   /* Trace stack height for alignment purposes */
    49     int tstate;
    51     /* Allocated memory for the (block-wide) back-patch list */
    52     uint32_t **backpatch_list;
    53     uint32_t backpatch_posn;
    54     uint32_t backpatch_size;
    55 };
    57 #define TSTATE_NONE -1
    58 #define TSTATE_O    0
    59 #define TSTATE_C    2
    60 #define TSTATE_E    4
    61 #define TSTATE_NE   5
    62 #define TSTATE_G    0xF
    63 #define TSTATE_GE   0xD
    64 #define TSTATE_A    7
    65 #define TSTATE_AE   3
    67 /** Branch if T is set (either in the current cflags, or in sh4r.t) */
    68 #define JT_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
    69 	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
    70     OP(0x70+sh4_x86.tstate); OP(rel8); \
    71     MARK_JMP(rel8,label)
    72 /** Branch if T is clear (either in the current cflags or in sh4r.t) */
    73 #define JF_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
    74 	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
    75     OP(0x70+ (sh4_x86.tstate^1)); OP(rel8); \
    76     MARK_JMP(rel8, label)
    79 #define EXIT_DATA_ADDR_READ 0
    80 #define EXIT_DATA_ADDR_WRITE 7
    81 #define EXIT_ILLEGAL 14
    82 #define EXIT_SLOT_ILLEGAL 21
    83 #define EXIT_FPU_DISABLED 28
    84 #define EXIT_SLOT_FPU_DISABLED 35
    86 static struct sh4_x86_state sh4_x86;
    88 static uint32_t max_int = 0x7FFFFFFF;
    89 static uint32_t min_int = 0x80000000;
    90 static uint32_t save_fcw; /* save value for fpu control word */
    91 static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
    93 void sh4_x86_init()
    94 {
    95     sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
    96     sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(uint32_t *);
    97 }
   100 static void sh4_x86_add_backpatch( uint8_t *ptr )
   101 {
   102     if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
   103 	sh4_x86.backpatch_size <<= 1;
   104 	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, sh4_x86.backpatch_size * sizeof(uint32_t *) );
   105 	assert( sh4_x86.backpatch_list != NULL );
   106     }
   107     sh4_x86.backpatch_list[sh4_x86.backpatch_posn++] = (uint32_t *)ptr;
   108 }
   110 static void sh4_x86_do_backpatch( uint8_t *reloc_base )
   111 {
   112     unsigned int i;
   113     for( i=0; i<sh4_x86.backpatch_posn; i++ ) {
   114 	*sh4_x86.backpatch_list[i] += (reloc_base - ((uint8_t *)sh4_x86.backpatch_list[i]) - 4);
   115     }
   116 }
   118 /**
   119  * Emit an instruction to load an SH4 reg into a real register
   120  */
   121 static inline void load_reg( int x86reg, int sh4reg ) 
   122 {
   123     /* mov [bp+n], reg */
   124     OP(0x8B);
   125     OP(0x45 + (x86reg<<3));
   126     OP(REG_OFFSET(r[sh4reg]));
   127 }
   129 static inline void load_reg16s( int x86reg, int sh4reg )
   130 {
   131     OP(0x0F);
   132     OP(0xBF);
   133     MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
   134 }
   136 static inline void load_reg16u( int x86reg, int sh4reg )
   137 {
   138     OP(0x0F);
   139     OP(0xB7);
   140     MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
   142 }
   144 #define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
   145 #define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
   146 /**
   147  * Emit an instruction to load an immediate value into a register
   148  */
   149 static inline void load_imm32( int x86reg, uint32_t value ) {
   150     /* mov #value, reg */
   151     OP(0xB8 + x86reg);
   152     OP32(value);
   153 }
   155 /**
   156  * Load an immediate 64-bit quantity (note: x86-64 only)
   157  */
   158 static inline void load_imm64( int x86reg, uint32_t value ) {
   159     /* mov #value, reg */
   160     REXW();
   161     OP(0xB8 + x86reg);
   162     OP64(value);
   163 }
   166 /**
   167  * Emit an instruction to store an SH4 reg (RN)
   168  */
   169 void static inline store_reg( int x86reg, int sh4reg ) {
   170     /* mov reg, [bp+n] */
   171     OP(0x89);
   172     OP(0x45 + (x86reg<<3));
   173     OP(REG_OFFSET(r[sh4reg]));
   174 }
   176 #define load_fr_bank(bankreg) load_spreg( bankreg, REG_OFFSET(fr_bank))
   178 /**
   179  * Load an FR register (single-precision floating point) into an integer x86
   180  * register (eg for register-to-register moves)
   181  */
   182 void static inline load_fr( int bankreg, int x86reg, int frm )
   183 {
   184     OP(0x8B); OP(0x40+bankreg+(x86reg<<3)); OP((frm^1)<<2);
   185 }
   187 /**
   188  * Store an FR register (single-precision floating point) into an integer x86
   189  * register (eg for register-to-register moves)
   190  */
   191 void static inline store_fr( int bankreg, int x86reg, int frn )
   192 {
   193     OP(0x89);  OP(0x40+bankreg+(x86reg<<3)); OP((frn^1)<<2);
   194 }
   197 /**
   198  * Load a pointer to the back fp back into the specified x86 register. The
   199  * bankreg must have been previously loaded with FPSCR.
   200  * NB: 12 bytes
   201  */
   202 static inline void load_xf_bank( int bankreg )
   203 {
   204     NOT_r32( bankreg );
   205     SHR_imm8_r32( (21 - 6), bankreg ); // Extract bit 21 then *64 for bank size
   206     AND_imm8s_r32( 0x40, bankreg );    // Complete extraction
   207     OP(0x8D); OP(0x44+(bankreg<<3)); OP(0x28+bankreg); OP(REG_OFFSET(fr)); // LEA [ebp+bankreg+disp], bankreg
   208 }
   210 /**
   211  * Update the fr_bank pointer based on the current fpscr value.
   212  */
   213 static inline void update_fr_bank( int fpscrreg )
   214 {
   215     SHR_imm8_r32( (21 - 6), fpscrreg ); // Extract bit 21 then *64 for bank size
   216     AND_imm8s_r32( 0x40, fpscrreg );    // Complete extraction
   217     OP(0x8D); OP(0x44+(fpscrreg<<3)); OP(0x28+fpscrreg); OP(REG_OFFSET(fr)); // LEA [ebp+fpscrreg+disp], fpscrreg
   218     store_spreg( fpscrreg, REG_OFFSET(fr_bank) );
   219 }
   220 /**
   221  * Push FPUL (as a 32-bit float) onto the FPU stack
   222  */
   223 static inline void push_fpul( )
   224 {
   225     OP(0xD9); OP(0x45); OP(R_FPUL);
   226 }
   228 /**
   229  * Pop FPUL (as a 32-bit float) from the FPU stack
   230  */
   231 static inline void pop_fpul( )
   232 {
   233     OP(0xD9); OP(0x5D); OP(R_FPUL);
   234 }
   236 /**
   237  * Push a 32-bit float onto the FPU stack, with bankreg previously loaded
   238  * with the location of the current fp bank.
   239  */
   240 static inline void push_fr( int bankreg, int frm ) 
   241 {
   242     OP(0xD9); OP(0x40 + bankreg); OP((frm^1)<<2);  // FLD.S [bankreg + frm^1*4]
   243 }
   245 /**
   246  * Pop a 32-bit float from the FPU stack and store it back into the fp bank, 
   247  * with bankreg previously loaded with the location of the current fp bank.
   248  */
   249 static inline void pop_fr( int bankreg, int frm )
   250 {
   251     OP(0xD9); OP(0x58 + bankreg); OP((frm^1)<<2); // FST.S [bankreg + frm^1*4]
   252 }
   254 /**
   255  * Push a 64-bit double onto the FPU stack, with bankreg previously loaded
   256  * with the location of the current fp bank.
   257  */
   258 static inline void push_dr( int bankreg, int frm )
   259 {
   260     OP(0xDD); OP(0x40 + bankreg); OP(frm<<2); // FLD.D [bankreg + frm*4]
   261 }
   263 static inline void pop_dr( int bankreg, int frm )
   264 {
   265     OP(0xDD); OP(0x58 + bankreg); OP(frm<<2); // FST.D [bankreg + frm*4]
   266 }
   268 /* Exception checks - Note that all exception checks will clobber EAX */
   269 #define precheck() load_imm32(R_EDX, (pc-sh4_x86.block_start_pc-(sh4_x86.in_delay_slot?2:0))>>1)
   271 #define check_priv( ) \
   272     if( !sh4_x86.priv_checked ) { \
   273 	sh4_x86.priv_checked = TRUE;\
   274 	precheck();\
   275 	load_spreg( R_EAX, R_SR );\
   276 	AND_imm32_r32( SR_MD, R_EAX );\
   277 	if( sh4_x86.in_delay_slot ) {\
   278 	    JE_exit( EXIT_SLOT_ILLEGAL );\
   279 	} else {\
   280 	    JE_exit( EXIT_ILLEGAL );\
   281 	}\
   282     }\
   285 static void check_priv_no_precheck()
   286 {
   287     if( !sh4_x86.priv_checked ) {
   288 	sh4_x86.priv_checked = TRUE;
   289 	load_spreg( R_EAX, R_SR );
   290 	AND_imm32_r32( SR_MD, R_EAX );
   291 	if( sh4_x86.in_delay_slot ) {
   292 	    JE_exit( EXIT_SLOT_ILLEGAL );
   293 	} else {
   294 	    JE_exit( EXIT_ILLEGAL );
   295 	}
   296     }
   297 }
   299 #define check_fpuen( ) \
   300     if( !sh4_x86.fpuen_checked ) {\
   301 	sh4_x86.fpuen_checked = TRUE;\
   302 	precheck();\
   303 	load_spreg( R_EAX, R_SR );\
   304 	AND_imm32_r32( SR_FD, R_EAX );\
   305 	if( sh4_x86.in_delay_slot ) {\
   306 	    JNE_exit(EXIT_SLOT_FPU_DISABLED);\
   307 	} else {\
   308 	    JNE_exit(EXIT_FPU_DISABLED);\
   309 	}\
   310     }
   312 static void check_fpuen_no_precheck()
   313 {
   314     if( !sh4_x86.fpuen_checked ) {
   315 	sh4_x86.fpuen_checked = TRUE;
   316 	load_spreg( R_EAX, R_SR );
   317 	AND_imm32_r32( SR_FD, R_EAX );
   318 	if( sh4_x86.in_delay_slot ) {
   319 	    JNE_exit(EXIT_SLOT_FPU_DISABLED);
   320 	} else {
   321 	    JNE_exit(EXIT_FPU_DISABLED);
   322 	}
   323     }
   325 }
   327 static void check_ralign16( int x86reg )
   328 {
   329     TEST_imm32_r32( 0x00000001, x86reg );
   330     JNE_exit(EXIT_DATA_ADDR_READ);
   331 }
   333 static void check_walign16( int x86reg )
   334 {
   335     TEST_imm32_r32( 0x00000001, x86reg );
   336     JNE_exit(EXIT_DATA_ADDR_WRITE);
   337 }
   339 static void check_ralign32( int x86reg )
   340 {
   341     TEST_imm32_r32( 0x00000003, x86reg );
   342     JNE_exit(EXIT_DATA_ADDR_READ);
   343 }
   344 static void check_walign32( int x86reg )
   345 {
   346     TEST_imm32_r32( 0x00000003, x86reg );
   347     JNE_exit(EXIT_DATA_ADDR_WRITE);
   348 }
   350 #define UNDEF()
   351 #define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
   352 #define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
   353 #define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
   354 #define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
   355 #define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
   356 #define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
   357 #define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
   359 #define SLOTILLEGAL() precheck(); JMP_exit(EXIT_SLOT_ILLEGAL); sh4_x86.in_delay_slot = FALSE; return 1;
   361 extern uint16_t *sh4_icache;
   362 extern uint32_t sh4_icache_addr;
   364 /****** Import appropriate calling conventions ******/
   365 #if SH4_TRANSLATOR == TARGET_X86_64
   366 #include "sh4/ia64abi.h"
   367 #else /* SH4_TRANSLATOR == TARGET_X86 */
   368 #ifdef APPLE_BUILD
   369 #include "sh4/ia32mac.h"
   370 #else
   371 #include "sh4/ia32abi.h"
   372 #endif
   373 #endif
   376 /**
   377  * Translate a single instruction. Delayed branches are handled specially
   378  * by translating both branch and delayed instruction as a single unit (as
   379  * 
   380  *
   381  * @return true if the instruction marks the end of a basic block
   382  * (eg a branch or 
   383  */
   384 uint32_t sh4_translate_instruction( sh4addr_t pc )
   385 {
   386     uint32_t ir;
   387     /* Read instruction */
   388     uint32_t pageaddr = pc >> 12;
   389     if( sh4_icache != NULL && pageaddr == sh4_icache_addr ) {
   390 	ir = sh4_icache[(pc&0xFFF)>>1];
   391     } else {
   392 	sh4_icache = (uint16_t *)mem_get_page(pc);
   393 	if( ((uintptr_t)sh4_icache) < MAX_IO_REGIONS ) {
   394 	    /* If someone's actually been so daft as to try to execute out of an IO
   395 	     * region, fallback on the full-blown memory read
   396 	     */
   397 	    sh4_icache = NULL;
   398 	    ir = sh4_read_word(pc);
   399 	} else {
   400 	    sh4_icache_addr = pageaddr;
   401 	    ir = sh4_icache[(pc&0xFFF)>>1];
   402 	}
   403     }
   405         switch( (ir&0xF000) >> 12 ) {
   406             case 0x0:
   407                 switch( ir&0xF ) {
   408                     case 0x2:
   409                         switch( (ir&0x80) >> 7 ) {
   410                             case 0x0:
   411                                 switch( (ir&0x70) >> 4 ) {
   412                                     case 0x0:
   413                                         { /* STC SR, Rn */
   414                                         uint32_t Rn = ((ir>>8)&0xF); 
   415                                         check_priv();
   416                                         call_func0(sh4_read_sr);
   417                                         store_reg( R_EAX, Rn );
   418                                         sh4_x86.tstate = TSTATE_NONE;
   419                                         }
   420                                         break;
   421                                     case 0x1:
   422                                         { /* STC GBR, Rn */
   423                                         uint32_t Rn = ((ir>>8)&0xF); 
   424                                         load_spreg( R_EAX, R_GBR );
   425                                         store_reg( R_EAX, Rn );
   426                                         }
   427                                         break;
   428                                     case 0x2:
   429                                         { /* STC VBR, Rn */
   430                                         uint32_t Rn = ((ir>>8)&0xF); 
   431                                         check_priv();
   432                                         load_spreg( R_EAX, R_VBR );
   433                                         store_reg( R_EAX, Rn );
   434                                         sh4_x86.tstate = TSTATE_NONE;
   435                                         }
   436                                         break;
   437                                     case 0x3:
   438                                         { /* STC SSR, Rn */
   439                                         uint32_t Rn = ((ir>>8)&0xF); 
   440                                         check_priv();
   441                                         load_spreg( R_EAX, R_SSR );
   442                                         store_reg( R_EAX, Rn );
   443                                         sh4_x86.tstate = TSTATE_NONE;
   444                                         }
   445                                         break;
   446                                     case 0x4:
   447                                         { /* STC SPC, Rn */
   448                                         uint32_t Rn = ((ir>>8)&0xF); 
   449                                         check_priv();
   450                                         load_spreg( R_EAX, R_SPC );
   451                                         store_reg( R_EAX, Rn );
   452                                         sh4_x86.tstate = TSTATE_NONE;
   453                                         }
   454                                         break;
   455                                     default:
   456                                         UNDEF();
   457                                         break;
   458                                 }
   459                                 break;
   460                             case 0x1:
   461                                 { /* STC Rm_BANK, Rn */
   462                                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
   463                                 check_priv();
   464                                 load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
   465                                 store_reg( R_EAX, Rn );
   466                                 sh4_x86.tstate = TSTATE_NONE;
   467                                 }
   468                                 break;
   469                         }
   470                         break;
   471                     case 0x3:
   472                         switch( (ir&0xF0) >> 4 ) {
   473                             case 0x0:
   474                                 { /* BSRF Rn */
   475                                 uint32_t Rn = ((ir>>8)&0xF); 
   476                                 if( sh4_x86.in_delay_slot ) {
   477                             	SLOTILLEGAL();
   478                                 } else {
   479                             	load_imm32( R_ECX, pc + 4 );
   480                             	store_spreg( R_ECX, R_PR );
   481                             	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_ECX );
   482                             	store_spreg( R_ECX, REG_OFFSET(pc) );
   483                             	sh4_x86.in_delay_slot = TRUE;
   484                             	sh4_x86.tstate = TSTATE_NONE;
   485                             	sh4_translate_instruction( pc + 2 );
   486                             	exit_block_pcset(pc+2);
   487                             	sh4_x86.branch_taken = TRUE;
   488                             	return 4;
   489                                 }
   490                                 }
   491                                 break;
   492                             case 0x2:
   493                                 { /* BRAF Rn */
   494                                 uint32_t Rn = ((ir>>8)&0xF); 
   495                                 if( sh4_x86.in_delay_slot ) {
   496                             	SLOTILLEGAL();
   497                                 } else {
   498                             	load_reg( R_EAX, Rn );
   499                             	ADD_imm32_r32( pc + 4, R_EAX );
   500                             	store_spreg( R_EAX, REG_OFFSET(pc) );
   501                             	sh4_x86.in_delay_slot = TRUE;
   502                             	sh4_x86.tstate = TSTATE_NONE;
   503                             	sh4_translate_instruction( pc + 2 );
   504                             	exit_block_pcset(pc+2);
   505                             	sh4_x86.branch_taken = TRUE;
   506                             	return 4;
   507                                 }
   508                                 }
   509                                 break;
   510                             case 0x8:
   511                                 { /* PREF @Rn */
   512                                 uint32_t Rn = ((ir>>8)&0xF); 
   513                                 load_reg( R_EAX, Rn );
   514                                 MOV_r32_r32( R_EAX, R_ECX );
   515                                 AND_imm32_r32( 0xFC000000, R_EAX );
   516                                 CMP_imm32_r32( 0xE0000000, R_EAX );
   517                                 JNE_rel8(CALL_FUNC1_SIZE, end);
   518                                 call_func1( sh4_flush_store_queue, R_ECX );
   519                                 JMP_TARGET(end);
   520                                 sh4_x86.tstate = TSTATE_NONE;
   521                                 }
   522                                 break;
   523                             case 0x9:
   524                                 { /* OCBI @Rn */
   525                                 uint32_t Rn = ((ir>>8)&0xF); 
   526                                 }
   527                                 break;
   528                             case 0xA:
   529                                 { /* OCBP @Rn */
   530                                 uint32_t Rn = ((ir>>8)&0xF); 
   531                                 }
   532                                 break;
   533                             case 0xB:
   534                                 { /* OCBWB @Rn */
   535                                 uint32_t Rn = ((ir>>8)&0xF); 
   536                                 }
   537                                 break;
   538                             case 0xC:
   539                                 { /* MOVCA.L R0, @Rn */
   540                                 uint32_t Rn = ((ir>>8)&0xF); 
   541                                 load_reg( R_EAX, 0 );
   542                                 load_reg( R_ECX, Rn );
   543                                 precheck();
   544                                 check_walign32( R_ECX );
   545                                 MEM_WRITE_LONG( R_ECX, R_EAX );
   546                                 sh4_x86.tstate = TSTATE_NONE;
   547                                 }
   548                                 break;
   549                             default:
   550                                 UNDEF();
   551                                 break;
   552                         }
   553                         break;
   554                     case 0x4:
   555                         { /* MOV.B Rm, @(R0, Rn) */
   556                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   557                         load_reg( R_EAX, 0 );
   558                         load_reg( R_ECX, Rn );
   559                         ADD_r32_r32( R_EAX, R_ECX );
   560                         load_reg( R_EAX, Rm );
   561                         MEM_WRITE_BYTE( R_ECX, R_EAX );
   562                         sh4_x86.tstate = TSTATE_NONE;
   563                         }
   564                         break;
   565                     case 0x5:
   566                         { /* MOV.W Rm, @(R0, Rn) */
   567                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   568                         load_reg( R_EAX, 0 );
   569                         load_reg( R_ECX, Rn );
   570                         ADD_r32_r32( R_EAX, R_ECX );
   571                         precheck();
   572                         check_walign16( R_ECX );
   573                         load_reg( R_EAX, Rm );
   574                         MEM_WRITE_WORD( R_ECX, R_EAX );
   575                         sh4_x86.tstate = TSTATE_NONE;
   576                         }
   577                         break;
   578                     case 0x6:
   579                         { /* MOV.L Rm, @(R0, Rn) */
   580                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   581                         load_reg( R_EAX, 0 );
   582                         load_reg( R_ECX, Rn );
   583                         ADD_r32_r32( R_EAX, R_ECX );
   584                         precheck();
   585                         check_walign32( R_ECX );
   586                         load_reg( R_EAX, Rm );
   587                         MEM_WRITE_LONG( R_ECX, R_EAX );
   588                         sh4_x86.tstate = TSTATE_NONE;
   589                         }
   590                         break;
   591                     case 0x7:
   592                         { /* MUL.L Rm, Rn */
   593                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   594                         load_reg( R_EAX, Rm );
   595                         load_reg( R_ECX, Rn );
   596                         MUL_r32( R_ECX );
   597                         store_spreg( R_EAX, R_MACL );
   598                         sh4_x86.tstate = TSTATE_NONE;
   599                         }
   600                         break;
   601                     case 0x8:
   602                         switch( (ir&0xFF0) >> 4 ) {
   603                             case 0x0:
   604                                 { /* CLRT */
   605                                 CLC();
   606                                 SETC_t();
   607                                 sh4_x86.tstate = TSTATE_C;
   608                                 }
   609                                 break;
   610                             case 0x1:
   611                                 { /* SETT */
   612                                 STC();
   613                                 SETC_t();
   614                                 sh4_x86.tstate = TSTATE_C;
   615                                 }
   616                                 break;
   617                             case 0x2:
   618                                 { /* CLRMAC */
   619                                 XOR_r32_r32(R_EAX, R_EAX);
   620                                 store_spreg( R_EAX, R_MACL );
   621                                 store_spreg( R_EAX, R_MACH );
   622                                 sh4_x86.tstate = TSTATE_NONE;
   623                                 }
   624                                 break;
   625                             case 0x3:
   626                                 { /* LDTLB */
   627                                 MMU_ldtlb();
   628                                 }
   629                                 break;
   630                             case 0x4:
   631                                 { /* CLRS */
   632                                 CLC();
   633                                 SETC_sh4r(R_S);
   634                                 sh4_x86.tstate = TSTATE_C;
   635                                 }
   636                                 break;
   637                             case 0x5:
   638                                 { /* SETS */
   639                                 STC();
   640                                 SETC_sh4r(R_S);
   641                                 sh4_x86.tstate = TSTATE_C;
   642                                 }
   643                                 break;
   644                             default:
   645                                 UNDEF();
   646                                 break;
   647                         }
   648                         break;
   649                     case 0x9:
   650                         switch( (ir&0xF0) >> 4 ) {
   651                             case 0x0:
   652                                 { /* NOP */
   653                                 /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */
   654                                 }
   655                                 break;
   656                             case 0x1:
   657                                 { /* DIV0U */
   658                                 XOR_r32_r32( R_EAX, R_EAX );
   659                                 store_spreg( R_EAX, R_Q );
   660                                 store_spreg( R_EAX, R_M );
   661                                 store_spreg( R_EAX, R_T );
   662                                 sh4_x86.tstate = TSTATE_C; // works for DIV1
   663                                 }
   664                                 break;
   665                             case 0x2:
   666                                 { /* MOVT Rn */
   667                                 uint32_t Rn = ((ir>>8)&0xF); 
   668                                 load_spreg( R_EAX, R_T );
   669                                 store_reg( R_EAX, Rn );
   670                                 }
   671                                 break;
   672                             default:
   673                                 UNDEF();
   674                                 break;
   675                         }
   676                         break;
   677                     case 0xA:
   678                         switch( (ir&0xF0) >> 4 ) {
   679                             case 0x0:
   680                                 { /* STS MACH, Rn */
   681                                 uint32_t Rn = ((ir>>8)&0xF); 
   682                                 load_spreg( R_EAX, R_MACH );
   683                                 store_reg( R_EAX, Rn );
   684                                 }
   685                                 break;
   686                             case 0x1:
   687                                 { /* STS MACL, Rn */
   688                                 uint32_t Rn = ((ir>>8)&0xF); 
   689                                 load_spreg( R_EAX, R_MACL );
   690                                 store_reg( R_EAX, Rn );
   691                                 }
   692                                 break;
   693                             case 0x2:
   694                                 { /* STS PR, Rn */
   695                                 uint32_t Rn = ((ir>>8)&0xF); 
   696                                 load_spreg( R_EAX, R_PR );
   697                                 store_reg( R_EAX, Rn );
   698                                 }
   699                                 break;
   700                             case 0x3:
   701                                 { /* STC SGR, Rn */
   702                                 uint32_t Rn = ((ir>>8)&0xF); 
   703                                 check_priv();
   704                                 load_spreg( R_EAX, R_SGR );
   705                                 store_reg( R_EAX, Rn );
   706                                 sh4_x86.tstate = TSTATE_NONE;
   707                                 }
   708                                 break;
   709                             case 0x5:
   710                                 { /* STS FPUL, Rn */
   711                                 uint32_t Rn = ((ir>>8)&0xF); 
   712                                 load_spreg( R_EAX, R_FPUL );
   713                                 store_reg( R_EAX, Rn );
   714                                 }
   715                                 break;
   716                             case 0x6:
   717                                 { /* STS FPSCR, Rn */
   718                                 uint32_t Rn = ((ir>>8)&0xF); 
   719                                 load_spreg( R_EAX, R_FPSCR );
   720                                 store_reg( R_EAX, Rn );
   721                                 }
   722                                 break;
   723                             case 0xF:
   724                                 { /* STC DBR, Rn */
   725                                 uint32_t Rn = ((ir>>8)&0xF); 
   726                                 check_priv();
   727                                 load_spreg( R_EAX, R_DBR );
   728                                 store_reg( R_EAX, Rn );
   729                                 sh4_x86.tstate = TSTATE_NONE;
   730                                 }
   731                                 break;
   732                             default:
   733                                 UNDEF();
   734                                 break;
   735                         }
   736                         break;
   737                     case 0xB:
   738                         switch( (ir&0xFF0) >> 4 ) {
   739                             case 0x0:
   740                                 { /* RTS */
   741                                 if( sh4_x86.in_delay_slot ) {
   742                             	SLOTILLEGAL();
   743                                 } else {
   744                             	load_spreg( R_ECX, R_PR );
   745                             	store_spreg( R_ECX, REG_OFFSET(pc) );
   746                             	sh4_x86.in_delay_slot = TRUE;
   747                             	sh4_translate_instruction(pc+2);
   748                             	exit_block_pcset(pc+2);
   749                             	sh4_x86.branch_taken = TRUE;
   750                             	return 4;
   751                                 }
   752                                 }
   753                                 break;
   754                             case 0x1:
   755                                 { /* SLEEP */
   756                                 check_priv();
   757                                 call_func0( sh4_sleep );
   758                                 sh4_x86.tstate = TSTATE_NONE;
   759                                 sh4_x86.in_delay_slot = FALSE;
   760                                 return 2;
   761                                 }
   762                                 break;
   763                             case 0x2:
   764                                 { /* RTE */
   765                                 if( sh4_x86.in_delay_slot ) {
   766                             	SLOTILLEGAL();
   767                                 } else {
   768                             	check_priv();
   769                             	load_spreg( R_ECX, R_SPC );
   770                             	store_spreg( R_ECX, REG_OFFSET(pc) );
   771                             	load_spreg( R_EAX, R_SSR );
   772                             	call_func1( sh4_write_sr, R_EAX );
   773                             	sh4_x86.in_delay_slot = TRUE;
   774                             	sh4_x86.priv_checked = FALSE;
   775                             	sh4_x86.fpuen_checked = FALSE;
   776                             	sh4_x86.tstate = TSTATE_NONE;
   777                             	sh4_translate_instruction(pc+2);
   778                             	exit_block_pcset(pc+2);
   779                             	sh4_x86.branch_taken = TRUE;
   780                             	return 4;
   781                                 }
   782                                 }
   783                                 break;
   784                             default:
   785                                 UNDEF();
   786                                 break;
   787                         }
   788                         break;
   789                     case 0xC:
   790                         { /* MOV.B @(R0, Rm), Rn */
   791                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   792                         load_reg( R_EAX, 0 );
   793                         load_reg( R_ECX, Rm );
   794                         ADD_r32_r32( R_EAX, R_ECX );
   795                         MEM_READ_BYTE( R_ECX, R_EAX );
   796                         store_reg( R_EAX, Rn );
   797                         sh4_x86.tstate = TSTATE_NONE;
   798                         }
   799                         break;
   800                     case 0xD:
   801                         { /* MOV.W @(R0, Rm), Rn */
   802                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   803                         load_reg( R_EAX, 0 );
   804                         load_reg( R_ECX, Rm );
   805                         ADD_r32_r32( R_EAX, R_ECX );
   806                         precheck();
   807                         check_ralign16( R_ECX );
   808                         MEM_READ_WORD( R_ECX, R_EAX );
   809                         store_reg( R_EAX, Rn );
   810                         sh4_x86.tstate = TSTATE_NONE;
   811                         }
   812                         break;
   813                     case 0xE:
   814                         { /* MOV.L @(R0, Rm), Rn */
   815                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   816                         load_reg( R_EAX, 0 );
   817                         load_reg( R_ECX, Rm );
   818                         ADD_r32_r32( R_EAX, R_ECX );
   819                         precheck();
   820                         check_ralign32( R_ECX );
   821                         MEM_READ_LONG( R_ECX, R_EAX );
   822                         store_reg( R_EAX, Rn );
   823                         sh4_x86.tstate = TSTATE_NONE;
   824                         }
   825                         break;
   826                     case 0xF:
   827                         { /* MAC.L @Rm+, @Rn+ */
   828                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   829                         load_reg( R_ECX, Rm );
   830                         precheck();
   831                         check_ralign32( R_ECX );
   832                         load_reg( R_ECX, Rn );
   833                         check_ralign32( R_ECX );
   834                         ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
   835                         MEM_READ_LONG( R_ECX, R_EAX );
   836                         PUSH_realigned_r32( R_EAX );
   837                         load_reg( R_ECX, Rm );
   838                         ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
   839                         MEM_READ_LONG( R_ECX, R_EAX );
   840                         POP_realigned_r32( R_ECX );
   841                         IMUL_r32( R_ECX );
   842                         ADD_r32_sh4r( R_EAX, R_MACL );
   843                         ADC_r32_sh4r( R_EDX, R_MACH );
   845                         load_spreg( R_ECX, R_S );
   846                         TEST_r32_r32(R_ECX, R_ECX);
   847                         JE_rel8( CALL_FUNC0_SIZE, nosat );
   848                         call_func0( signsat48 );
   849                         JMP_TARGET( nosat );
   850                         sh4_x86.tstate = TSTATE_NONE;
   851                         }
   852                         break;
   853                     default:
   854                         UNDEF();
   855                         break;
   856                 }
   857                 break;
   858             case 0x1:
   859                 { /* MOV.L Rm, @(disp, Rn) */
   860                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
   861                 load_reg( R_ECX, Rn );
   862                 load_reg( R_EAX, Rm );
   863                 ADD_imm32_r32( disp, R_ECX );
   864                 precheck();
   865                 check_walign32( R_ECX );
   866                 MEM_WRITE_LONG( R_ECX, R_EAX );
   867                 sh4_x86.tstate = TSTATE_NONE;
   868                 }
   869                 break;
   870             case 0x2:
   871                 switch( ir&0xF ) {
   872                     case 0x0:
   873                         { /* MOV.B Rm, @Rn */
   874                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   875                         load_reg( R_EAX, Rm );
   876                         load_reg( R_ECX, Rn );
   877                         MEM_WRITE_BYTE( R_ECX, R_EAX );
   878                         sh4_x86.tstate = TSTATE_NONE;
   879                         }
   880                         break;
   881                     case 0x1:
   882                         { /* MOV.W Rm, @Rn */
   883                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   884                         load_reg( R_ECX, Rn );
   885                         precheck();
   886                         check_walign16( R_ECX );
   887                         load_reg( R_EAX, Rm );
   888                         MEM_WRITE_WORD( R_ECX, R_EAX );
   889                         sh4_x86.tstate = TSTATE_NONE;
   890                         }
   891                         break;
   892                     case 0x2:
   893                         { /* MOV.L Rm, @Rn */
   894                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   895                         load_reg( R_EAX, Rm );
   896                         load_reg( R_ECX, Rn );
   897                         precheck();
   898                         check_walign32(R_ECX);
   899                         MEM_WRITE_LONG( R_ECX, R_EAX );
   900                         sh4_x86.tstate = TSTATE_NONE;
   901                         }
   902                         break;
   903                     case 0x4:
   904                         { /* MOV.B Rm, @-Rn */
   905                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   906                         load_reg( R_EAX, Rm );
   907                         load_reg( R_ECX, Rn );
   908                         ADD_imm8s_r32( -1, R_ECX );
   909                         store_reg( R_ECX, Rn );
   910                         MEM_WRITE_BYTE( R_ECX, R_EAX );
   911                         sh4_x86.tstate = TSTATE_NONE;
   912                         }
   913                         break;
   914                     case 0x5:
   915                         { /* MOV.W Rm, @-Rn */
   916                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   917                         load_reg( R_ECX, Rn );
   918                         precheck();
   919                         check_walign16( R_ECX );
   920                         load_reg( R_EAX, Rm );
   921                         ADD_imm8s_r32( -2, R_ECX );
   922                         store_reg( R_ECX, Rn );
   923                         MEM_WRITE_WORD( R_ECX, R_EAX );
   924                         sh4_x86.tstate = TSTATE_NONE;
   925                         }
   926                         break;
   927                     case 0x6:
   928                         { /* MOV.L Rm, @-Rn */
   929                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   930                         load_reg( R_EAX, Rm );
   931                         load_reg( R_ECX, Rn );
   932                         precheck();
   933                         check_walign32( R_ECX );
   934                         ADD_imm8s_r32( -4, R_ECX );
   935                         store_reg( R_ECX, Rn );
   936                         MEM_WRITE_LONG( R_ECX, R_EAX );
   937                         sh4_x86.tstate = TSTATE_NONE;
   938                         }
   939                         break;
   940                     case 0x7:
   941                         { /* DIV0S Rm, Rn */
   942                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   943                         load_reg( R_EAX, Rm );
   944                         load_reg( R_ECX, Rn );
   945                         SHR_imm8_r32( 31, R_EAX );
   946                         SHR_imm8_r32( 31, R_ECX );
   947                         store_spreg( R_EAX, R_M );
   948                         store_spreg( R_ECX, R_Q );
   949                         CMP_r32_r32( R_EAX, R_ECX );
   950                         SETNE_t();
   951                         sh4_x86.tstate = TSTATE_NE;
   952                         }
   953                         break;
   954                     case 0x8:
   955                         { /* TST Rm, Rn */
   956                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   957                         load_reg( R_EAX, Rm );
   958                         load_reg( R_ECX, Rn );
   959                         TEST_r32_r32( R_EAX, R_ECX );
   960                         SETE_t();
   961                         sh4_x86.tstate = TSTATE_E;
   962                         }
   963                         break;
   964                     case 0x9:
   965                         { /* AND Rm, Rn */
   966                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   967                         load_reg( R_EAX, Rm );
   968                         load_reg( R_ECX, Rn );
   969                         AND_r32_r32( R_EAX, R_ECX );
   970                         store_reg( R_ECX, Rn );
   971                         sh4_x86.tstate = TSTATE_NONE;
   972                         }
   973                         break;
   974                     case 0xA:
   975                         { /* XOR Rm, Rn */
   976                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   977                         load_reg( R_EAX, Rm );
   978                         load_reg( R_ECX, Rn );
   979                         XOR_r32_r32( R_EAX, R_ECX );
   980                         store_reg( R_ECX, Rn );
   981                         sh4_x86.tstate = TSTATE_NONE;
   982                         }
   983                         break;
   984                     case 0xB:
   985                         { /* OR Rm, Rn */
   986                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   987                         load_reg( R_EAX, Rm );
   988                         load_reg( R_ECX, Rn );
   989                         OR_r32_r32( R_EAX, R_ECX );
   990                         store_reg( R_ECX, Rn );
   991                         sh4_x86.tstate = TSTATE_NONE;
   992                         }
   993                         break;
   994                     case 0xC:
   995                         { /* CMP/STR Rm, Rn */
   996                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   997                         load_reg( R_EAX, Rm );
   998                         load_reg( R_ECX, Rn );
   999                         XOR_r32_r32( R_ECX, R_EAX );
  1000                         TEST_r8_r8( R_AL, R_AL );
  1001                         JE_rel8(13, target1);
  1002                         TEST_r8_r8( R_AH, R_AH ); // 2
  1003                         JE_rel8(9, target2);
  1004                         SHR_imm8_r32( 16, R_EAX ); // 3
  1005                         TEST_r8_r8( R_AL, R_AL ); // 2
  1006                         JE_rel8(2, target3);
  1007                         TEST_r8_r8( R_AH, R_AH ); // 2
  1008                         JMP_TARGET(target1);
  1009                         JMP_TARGET(target2);
  1010                         JMP_TARGET(target3);
  1011                         SETE_t();
  1012                         sh4_x86.tstate = TSTATE_E;
  1014                         break;
  1015                     case 0xD:
  1016                         { /* XTRCT Rm, Rn */
  1017                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1018                         load_reg( R_EAX, Rm );
  1019                         load_reg( R_ECX, Rn );
  1020                         SHL_imm8_r32( 16, R_EAX );
  1021                         SHR_imm8_r32( 16, R_ECX );
  1022                         OR_r32_r32( R_EAX, R_ECX );
  1023                         store_reg( R_ECX, Rn );
  1024                         sh4_x86.tstate = TSTATE_NONE;
  1026                         break;
  1027                     case 0xE:
  1028                         { /* MULU.W Rm, Rn */
  1029                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1030                         load_reg16u( R_EAX, Rm );
  1031                         load_reg16u( R_ECX, Rn );
  1032                         MUL_r32( R_ECX );
  1033                         store_spreg( R_EAX, R_MACL );
  1034                         sh4_x86.tstate = TSTATE_NONE;
  1036                         break;
  1037                     case 0xF:
  1038                         { /* MULS.W Rm, Rn */
  1039                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1040                         load_reg16s( R_EAX, Rm );
  1041                         load_reg16s( R_ECX, Rn );
  1042                         MUL_r32( R_ECX );
  1043                         store_spreg( R_EAX, R_MACL );
  1044                         sh4_x86.tstate = TSTATE_NONE;
  1046                         break;
  1047                     default:
  1048                         UNDEF();
  1049                         break;
  1051                 break;
  1052             case 0x3:
  1053                 switch( ir&0xF ) {
  1054                     case 0x0:
  1055                         { /* CMP/EQ Rm, Rn */
  1056                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1057                         load_reg( R_EAX, Rm );
  1058                         load_reg( R_ECX, Rn );
  1059                         CMP_r32_r32( R_EAX, R_ECX );
  1060                         SETE_t();
  1061                         sh4_x86.tstate = TSTATE_E;
  1063                         break;
  1064                     case 0x2:
  1065                         { /* CMP/HS Rm, Rn */
  1066                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1067                         load_reg( R_EAX, Rm );
  1068                         load_reg( R_ECX, Rn );
  1069                         CMP_r32_r32( R_EAX, R_ECX );
  1070                         SETAE_t();
  1071                         sh4_x86.tstate = TSTATE_AE;
  1073                         break;
  1074                     case 0x3:
  1075                         { /* CMP/GE Rm, Rn */
  1076                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1077                         load_reg( R_EAX, Rm );
  1078                         load_reg( R_ECX, Rn );
  1079                         CMP_r32_r32( R_EAX, R_ECX );
  1080                         SETGE_t();
  1081                         sh4_x86.tstate = TSTATE_GE;
  1083                         break;
  1084                     case 0x4:
  1085                         { /* DIV1 Rm, Rn */
  1086                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1087                         load_spreg( R_ECX, R_M );
  1088                         load_reg( R_EAX, Rn );
  1089                         if( sh4_x86.tstate != TSTATE_C ) {
  1090                     	LDC_t();
  1092                         RCL1_r32( R_EAX );
  1093                         SETC_r8( R_DL ); // Q'
  1094                         CMP_sh4r_r32( R_Q, R_ECX );
  1095                         JE_rel8(5, mqequal);
  1096                         ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
  1097                         JMP_rel8(3, end);
  1098                         JMP_TARGET(mqequal);
  1099                         SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
  1100                         JMP_TARGET(end);
  1101                         store_reg( R_EAX, Rn ); // Done with Rn now
  1102                         SETC_r8(R_AL); // tmp1
  1103                         XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
  1104                         XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
  1105                         store_spreg( R_ECX, R_Q );
  1106                         XOR_imm8s_r32( 1, R_AL );   // T = !Q'
  1107                         MOVZX_r8_r32( R_AL, R_EAX );
  1108                         store_spreg( R_EAX, R_T );
  1109                         sh4_x86.tstate = TSTATE_NONE;
  1111                         break;
  1112                     case 0x5:
  1113                         { /* DMULU.L Rm, Rn */
  1114                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1115                         load_reg( R_EAX, Rm );
  1116                         load_reg( R_ECX, Rn );
  1117                         MUL_r32(R_ECX);
  1118                         store_spreg( R_EDX, R_MACH );
  1119                         store_spreg( R_EAX, R_MACL );    
  1120                         sh4_x86.tstate = TSTATE_NONE;
  1122                         break;
  1123                     case 0x6:
  1124                         { /* CMP/HI Rm, Rn */
  1125                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1126                         load_reg( R_EAX, Rm );
  1127                         load_reg( R_ECX, Rn );
  1128                         CMP_r32_r32( R_EAX, R_ECX );
  1129                         SETA_t();
  1130                         sh4_x86.tstate = TSTATE_A;
  1132                         break;
  1133                     case 0x7:
  1134                         { /* CMP/GT Rm, Rn */
  1135                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1136                         load_reg( R_EAX, Rm );
  1137                         load_reg( R_ECX, Rn );
  1138                         CMP_r32_r32( R_EAX, R_ECX );
  1139                         SETG_t();
  1140                         sh4_x86.tstate = TSTATE_G;
  1142                         break;
  1143                     case 0x8:
  1144                         { /* SUB Rm, Rn */
  1145                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1146                         load_reg( R_EAX, Rm );
  1147                         load_reg( R_ECX, Rn );
  1148                         SUB_r32_r32( R_EAX, R_ECX );
  1149                         store_reg( R_ECX, Rn );
  1150                         sh4_x86.tstate = TSTATE_NONE;
  1152                         break;
  1153                     case 0xA:
  1154                         { /* SUBC Rm, Rn */
  1155                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1156                         load_reg( R_EAX, Rm );
  1157                         load_reg( R_ECX, Rn );
  1158                         if( sh4_x86.tstate != TSTATE_C ) {
  1159                     	LDC_t();
  1161                         SBB_r32_r32( R_EAX, R_ECX );
  1162                         store_reg( R_ECX, Rn );
  1163                         SETC_t();
  1164                         sh4_x86.tstate = TSTATE_C;
  1166                         break;
  1167                     case 0xB:
  1168                         { /* SUBV Rm, Rn */
  1169                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1170                         load_reg( R_EAX, Rm );
  1171                         load_reg( R_ECX, Rn );
  1172                         SUB_r32_r32( R_EAX, R_ECX );
  1173                         store_reg( R_ECX, Rn );
  1174                         SETO_t();
  1175                         sh4_x86.tstate = TSTATE_O;
  1177                         break;
  1178                     case 0xC:
  1179                         { /* ADD Rm, Rn */
  1180                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1181                         load_reg( R_EAX, Rm );
  1182                         load_reg( R_ECX, Rn );
  1183                         ADD_r32_r32( R_EAX, R_ECX );
  1184                         store_reg( R_ECX, Rn );
  1185                         sh4_x86.tstate = TSTATE_NONE;
  1187                         break;
  1188                     case 0xD:
  1189                         { /* DMULS.L Rm, Rn */
  1190                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1191                         load_reg( R_EAX, Rm );
  1192                         load_reg( R_ECX, Rn );
  1193                         IMUL_r32(R_ECX);
  1194                         store_spreg( R_EDX, R_MACH );
  1195                         store_spreg( R_EAX, R_MACL );
  1196                         sh4_x86.tstate = TSTATE_NONE;
  1198                         break;
  1199                     case 0xE:
  1200                         { /* ADDC Rm, Rn */
  1201                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1202                         if( sh4_x86.tstate != TSTATE_C ) {
  1203                     	LDC_t();
  1205                         load_reg( R_EAX, Rm );
  1206                         load_reg( R_ECX, Rn );
  1207                         ADC_r32_r32( R_EAX, R_ECX );
  1208                         store_reg( R_ECX, Rn );
  1209                         SETC_t();
  1210                         sh4_x86.tstate = TSTATE_C;
  1212                         break;
  1213                     case 0xF:
  1214                         { /* ADDV Rm, Rn */
  1215                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1216                         load_reg( R_EAX, Rm );
  1217                         load_reg( R_ECX, Rn );
  1218                         ADD_r32_r32( R_EAX, R_ECX );
  1219                         store_reg( R_ECX, Rn );
  1220                         SETO_t();
  1221                         sh4_x86.tstate = TSTATE_O;
  1223                         break;
  1224                     default:
  1225                         UNDEF();
  1226                         break;
  1228                 break;
  1229             case 0x4:
  1230                 switch( ir&0xF ) {
  1231                     case 0x0:
  1232                         switch( (ir&0xF0) >> 4 ) {
  1233                             case 0x0:
  1234                                 { /* SHLL Rn */
  1235                                 uint32_t Rn = ((ir>>8)&0xF); 
  1236                                 load_reg( R_EAX, Rn );
  1237                                 SHL1_r32( R_EAX );
  1238                                 SETC_t();
  1239                                 store_reg( R_EAX, Rn );
  1240                                 sh4_x86.tstate = TSTATE_C;
  1242                                 break;
  1243                             case 0x1:
  1244                                 { /* DT Rn */
  1245                                 uint32_t Rn = ((ir>>8)&0xF); 
  1246                                 load_reg( R_EAX, Rn );
  1247                                 ADD_imm8s_r32( -1, R_EAX );
  1248                                 store_reg( R_EAX, Rn );
  1249                                 SETE_t();
  1250                                 sh4_x86.tstate = TSTATE_E;
  1252                                 break;
  1253                             case 0x2:
  1254                                 { /* SHAL Rn */
  1255                                 uint32_t Rn = ((ir>>8)&0xF); 
  1256                                 load_reg( R_EAX, Rn );
  1257                                 SHL1_r32( R_EAX );
  1258                                 SETC_t();
  1259                                 store_reg( R_EAX, Rn );
  1260                                 sh4_x86.tstate = TSTATE_C;
  1262                                 break;
  1263                             default:
  1264                                 UNDEF();
  1265                                 break;
  1267                         break;
  1268                     case 0x1:
  1269                         switch( (ir&0xF0) >> 4 ) {
  1270                             case 0x0:
  1271                                 { /* SHLR Rn */
  1272                                 uint32_t Rn = ((ir>>8)&0xF); 
  1273                                 load_reg( R_EAX, Rn );
  1274                                 SHR1_r32( R_EAX );
  1275                                 SETC_t();
  1276                                 store_reg( R_EAX, Rn );
  1277                                 sh4_x86.tstate = TSTATE_C;
  1279                                 break;
  1280                             case 0x1:
  1281                                 { /* CMP/PZ Rn */
  1282                                 uint32_t Rn = ((ir>>8)&0xF); 
  1283                                 load_reg( R_EAX, Rn );
  1284                                 CMP_imm8s_r32( 0, R_EAX );
  1285                                 SETGE_t();
  1286                                 sh4_x86.tstate = TSTATE_GE;
  1288                                 break;
  1289                             case 0x2:
  1290                                 { /* SHAR Rn */
  1291                                 uint32_t Rn = ((ir>>8)&0xF); 
  1292                                 load_reg( R_EAX, Rn );
  1293                                 SAR1_r32( R_EAX );
  1294                                 SETC_t();
  1295                                 store_reg( R_EAX, Rn );
  1296                                 sh4_x86.tstate = TSTATE_C;
  1298                                 break;
  1299                             default:
  1300                                 UNDEF();
  1301                                 break;
  1303                         break;
  1304                     case 0x2:
  1305                         switch( (ir&0xF0) >> 4 ) {
  1306                             case 0x0:
  1307                                 { /* STS.L MACH, @-Rn */
  1308                                 uint32_t Rn = ((ir>>8)&0xF); 
  1309                                 load_reg( R_ECX, Rn );
  1310                                 precheck();
  1311                                 check_walign32( R_ECX );
  1312                                 ADD_imm8s_r32( -4, R_ECX );
  1313                                 store_reg( R_ECX, Rn );
  1314                                 load_spreg( R_EAX, R_MACH );
  1315                                 MEM_WRITE_LONG( R_ECX, R_EAX );
  1316                                 sh4_x86.tstate = TSTATE_NONE;
  1318                                 break;
  1319                             case 0x1:
  1320                                 { /* STS.L MACL, @-Rn */
  1321                                 uint32_t Rn = ((ir>>8)&0xF); 
  1322                                 load_reg( R_ECX, Rn );
  1323                                 precheck();
  1324                                 check_walign32( R_ECX );
  1325                                 ADD_imm8s_r32( -4, R_ECX );
  1326                                 store_reg( R_ECX, Rn );
  1327                                 load_spreg( R_EAX, R_MACL );
  1328                                 MEM_WRITE_LONG( R_ECX, R_EAX );
  1329                                 sh4_x86.tstate = TSTATE_NONE;
  1331                                 break;
  1332                             case 0x2:
  1333                                 { /* STS.L PR, @-Rn */
  1334                                 uint32_t Rn = ((ir>>8)&0xF); 
  1335                                 load_reg( R_ECX, Rn );
  1336                                 precheck();
  1337                                 check_walign32( R_ECX );
  1338                                 ADD_imm8s_r32( -4, R_ECX );
  1339                                 store_reg( R_ECX, Rn );
  1340                                 load_spreg( R_EAX, R_PR );
  1341                                 MEM_WRITE_LONG( R_ECX, R_EAX );
  1342                                 sh4_x86.tstate = TSTATE_NONE;
  1344                                 break;
  1345                             case 0x3:
  1346                                 { /* STC.L SGR, @-Rn */
  1347                                 uint32_t Rn = ((ir>>8)&0xF); 
  1348                                 precheck();
  1349                                 check_priv_no_precheck();
  1350                                 load_reg( R_ECX, Rn );
  1351                                 check_walign32( R_ECX );
  1352                                 ADD_imm8s_r32( -4, R_ECX );
  1353                                 store_reg( R_ECX, Rn );
  1354                                 load_spreg( R_EAX, R_SGR );
  1355                                 MEM_WRITE_LONG( R_ECX, R_EAX );
  1356                                 sh4_x86.tstate = TSTATE_NONE;
  1358                                 break;
  1359                             case 0x5:
  1360                                 { /* STS.L FPUL, @-Rn */
  1361                                 uint32_t Rn = ((ir>>8)&0xF); 
  1362                                 load_reg( R_ECX, Rn );
  1363                                 precheck();
  1364                                 check_walign32( R_ECX );
  1365                                 ADD_imm8s_r32( -4, R_ECX );
  1366                                 store_reg( R_ECX, Rn );
  1367                                 load_spreg( R_EAX, R_FPUL );
  1368                                 MEM_WRITE_LONG( R_ECX, R_EAX );
  1369                                 sh4_x86.tstate = TSTATE_NONE;
  1371                                 break;
  1372                             case 0x6:
  1373                                 { /* STS.L FPSCR, @-Rn */
  1374                                 uint32_t Rn = ((ir>>8)&0xF); 
  1375                                 load_reg( R_ECX, Rn );
  1376                                 precheck();
  1377                                 check_walign32( R_ECX );
  1378                                 ADD_imm8s_r32( -4, R_ECX );
  1379                                 store_reg( R_ECX, Rn );
  1380                                 load_spreg( R_EAX, R_FPSCR );
  1381                                 MEM_WRITE_LONG( R_ECX, R_EAX );
  1382                                 sh4_x86.tstate = TSTATE_NONE;
  1384                                 break;
  1385                             case 0xF:
  1386                                 { /* STC.L DBR, @-Rn */
  1387                                 uint32_t Rn = ((ir>>8)&0xF); 
  1388                                 precheck();
  1389                                 check_priv_no_precheck();
  1390                                 load_reg( R_ECX, Rn );
  1391                                 check_walign32( R_ECX );
  1392                                 ADD_imm8s_r32( -4, R_ECX );
  1393                                 store_reg( R_ECX, Rn );
  1394                                 load_spreg( R_EAX, R_DBR );
  1395                                 MEM_WRITE_LONG( R_ECX, R_EAX );
  1396                                 sh4_x86.tstate = TSTATE_NONE;
  1398                                 break;
  1399                             default:
  1400                                 UNDEF();
  1401                                 break;
  1403                         break;
  1404                     case 0x3:
  1405                         switch( (ir&0x80) >> 7 ) {
  1406                             case 0x0:
  1407                                 switch( (ir&0x70) >> 4 ) {
  1408                                     case 0x0:
  1409                                         { /* STC.L SR, @-Rn */
  1410                                         uint32_t Rn = ((ir>>8)&0xF); 
  1411                                         precheck();
  1412                                         check_priv_no_precheck();
  1413                                         call_func0( sh4_read_sr );
  1414                                         load_reg( R_ECX, Rn );
  1415                                         check_walign32( R_ECX );
  1416                                         ADD_imm8s_r32( -4, R_ECX );
  1417                                         store_reg( R_ECX, Rn );
  1418                                         MEM_WRITE_LONG( R_ECX, R_EAX );
  1419                                         sh4_x86.tstate = TSTATE_NONE;
  1421                                         break;
  1422                                     case 0x1:
  1423                                         { /* STC.L GBR, @-Rn */
  1424                                         uint32_t Rn = ((ir>>8)&0xF); 
  1425                                         load_reg( R_ECX, Rn );
  1426                                         precheck();
  1427                                         check_walign32( R_ECX );
  1428                                         ADD_imm8s_r32( -4, R_ECX );
  1429                                         store_reg( R_ECX, Rn );
  1430                                         load_spreg( R_EAX, R_GBR );
  1431                                         MEM_WRITE_LONG( R_ECX, R_EAX );
  1432                                         sh4_x86.tstate = TSTATE_NONE;
  1434                                         break;
  1435                                     case 0x2:
  1436                                         { /* STC.L VBR, @-Rn */
  1437                                         uint32_t Rn = ((ir>>8)&0xF); 
  1438                                         precheck();
  1439                                         check_priv_no_precheck();
  1440                                         load_reg( R_ECX, Rn );
  1441                                         check_walign32( R_ECX );
  1442                                         ADD_imm8s_r32( -4, R_ECX );
  1443                                         store_reg( R_ECX, Rn );
  1444                                         load_spreg( R_EAX, R_VBR );
  1445                                         MEM_WRITE_LONG( R_ECX, R_EAX );
  1446                                         sh4_x86.tstate = TSTATE_NONE;
  1448                                         break;
  1449                                     case 0x3:
  1450                                         { /* STC.L SSR, @-Rn */
  1451                                         uint32_t Rn = ((ir>>8)&0xF); 
  1452                                         precheck();
  1453                                         check_priv_no_precheck();
  1454                                         load_reg( R_ECX, Rn );
  1455                                         check_walign32( R_ECX );
  1456                                         ADD_imm8s_r32( -4, R_ECX );
  1457                                         store_reg( R_ECX, Rn );
  1458                                         load_spreg( R_EAX, R_SSR );
  1459                                         MEM_WRITE_LONG( R_ECX, R_EAX );
  1460                                         sh4_x86.tstate = TSTATE_NONE;
  1462                                         break;
  1463                                     case 0x4:
  1464                                         { /* STC.L SPC, @-Rn */
  1465                                         uint32_t Rn = ((ir>>8)&0xF); 
  1466                                         precheck();
  1467                                         check_priv_no_precheck();
  1468                                         load_reg( R_ECX, Rn );
  1469                                         check_walign32( R_ECX );
  1470                                         ADD_imm8s_r32( -4, R_ECX );
  1471                                         store_reg( R_ECX, Rn );
  1472                                         load_spreg( R_EAX, R_SPC );
  1473                                         MEM_WRITE_LONG( R_ECX, R_EAX );
  1474                                         sh4_x86.tstate = TSTATE_NONE;
  1476                                         break;
  1477                                     default:
  1478                                         UNDEF();
  1479                                         break;
  1481                                 break;
  1482                             case 0x1:
  1483                                 { /* STC.L Rm_BANK, @-Rn */
  1484                                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
  1485                                 precheck();
  1486                                 check_priv_no_precheck();
  1487                                 load_reg( R_ECX, Rn );
  1488                                 check_walign32( R_ECX );
  1489                                 ADD_imm8s_r32( -4, R_ECX );
  1490                                 store_reg( R_ECX, Rn );
  1491                                 load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
  1492                                 MEM_WRITE_LONG( R_ECX, R_EAX );
  1493                                 sh4_x86.tstate = TSTATE_NONE;
  1495                                 break;
  1497                         break;
  1498                     case 0x4:
  1499                         switch( (ir&0xF0) >> 4 ) {
  1500                             case 0x0:
  1501                                 { /* ROTL Rn */
  1502                                 uint32_t Rn = ((ir>>8)&0xF); 
  1503                                 load_reg( R_EAX, Rn );
  1504                                 ROL1_r32( R_EAX );
  1505                                 store_reg( R_EAX, Rn );
  1506                                 SETC_t();
  1507                                 sh4_x86.tstate = TSTATE_C;
  1509                                 break;
  1510                             case 0x2:
  1511                                 { /* ROTCL Rn */
  1512                                 uint32_t Rn = ((ir>>8)&0xF); 
  1513                                 load_reg( R_EAX, Rn );
  1514                                 if( sh4_x86.tstate != TSTATE_C ) {
  1515                             	LDC_t();
  1517                                 RCL1_r32( R_EAX );
  1518                                 store_reg( R_EAX, Rn );
  1519                                 SETC_t();
  1520                                 sh4_x86.tstate = TSTATE_C;
  1522                                 break;
  1523                             default:
  1524                                 UNDEF();
  1525                                 break;
  1527                         break;
  1528                     case 0x5:
  1529                         switch( (ir&0xF0) >> 4 ) {
  1530                             case 0x0:
  1531                                 { /* ROTR Rn */
  1532                                 uint32_t Rn = ((ir>>8)&0xF); 
  1533                                 load_reg( R_EAX, Rn );
  1534                                 ROR1_r32( R_EAX );
  1535                                 store_reg( R_EAX, Rn );
  1536                                 SETC_t();
  1537                                 sh4_x86.tstate = TSTATE_C;
  1539                                 break;
  1540                             case 0x1:
  1541                                 { /* CMP/PL Rn */
  1542                                 uint32_t Rn = ((ir>>8)&0xF); 
  1543                                 load_reg( R_EAX, Rn );
  1544                                 CMP_imm8s_r32( 0, R_EAX );
  1545                                 SETG_t();
  1546                                 sh4_x86.tstate = TSTATE_G;
  1548                                 break;
  1549                             case 0x2:
  1550                                 { /* ROTCR Rn */
  1551                                 uint32_t Rn = ((ir>>8)&0xF); 
  1552                                 load_reg( R_EAX, Rn );
  1553                                 if( sh4_x86.tstate != TSTATE_C ) {
  1554                             	LDC_t();
  1556                                 RCR1_r32( R_EAX );
  1557                                 store_reg( R_EAX, Rn );
  1558                                 SETC_t();
  1559                                 sh4_x86.tstate = TSTATE_C;
  1561                                 break;
  1562                             default:
  1563                                 UNDEF();
  1564                                 break;
  1566                         break;
  1567                     case 0x6:
  1568                         switch( (ir&0xF0) >> 4 ) {
  1569                             case 0x0:
  1570                                 { /* LDS.L @Rm+, MACH */
  1571                                 uint32_t Rm = ((ir>>8)&0xF); 
  1572                                 load_reg( R_EAX, Rm );
  1573                                 precheck();
  1574                                 check_ralign32( R_EAX );
  1575                                 MOV_r32_r32( R_EAX, R_ECX );
  1576                                 ADD_imm8s_r32( 4, R_EAX );
  1577                                 store_reg( R_EAX, Rm );
  1578                                 MEM_READ_LONG( R_ECX, R_EAX );
  1579                                 store_spreg( R_EAX, R_MACH );
  1580                                 sh4_x86.tstate = TSTATE_NONE;
  1582                                 break;
  1583                             case 0x1:
  1584                                 { /* LDS.L @Rm+, MACL */
  1585                                 uint32_t Rm = ((ir>>8)&0xF); 
  1586                                 load_reg( R_EAX, Rm );
  1587                                 precheck();
  1588                                 check_ralign32( R_EAX );
  1589                                 MOV_r32_r32( R_EAX, R_ECX );
  1590                                 ADD_imm8s_r32( 4, R_EAX );
  1591                                 store_reg( R_EAX, Rm );
  1592                                 MEM_READ_LONG( R_ECX, R_EAX );
  1593                                 store_spreg( R_EAX, R_MACL );
  1594                                 sh4_x86.tstate = TSTATE_NONE;
  1596                                 break;
  1597                             case 0x2:
  1598                                 { /* LDS.L @Rm+, PR */
  1599                                 uint32_t Rm = ((ir>>8)&0xF); 
  1600                                 load_reg( R_EAX, Rm );
  1601                                 precheck();
  1602                                 check_ralign32( R_EAX );
  1603                                 MOV_r32_r32( R_EAX, R_ECX );
  1604                                 ADD_imm8s_r32( 4, R_EAX );
  1605                                 store_reg( R_EAX, Rm );
  1606                                 MEM_READ_LONG( R_ECX, R_EAX );
  1607                                 store_spreg( R_EAX, R_PR );
  1608                                 sh4_x86.tstate = TSTATE_NONE;
  1610                                 break;
  1611                             case 0x3:
  1612                                 { /* LDC.L @Rm+, SGR */
  1613                                 uint32_t Rm = ((ir>>8)&0xF); 
  1614                                 precheck();
  1615                                 check_priv_no_precheck();
  1616                                 load_reg( R_EAX, Rm );
  1617                                 check_ralign32( R_EAX );
  1618                                 MOV_r32_r32( R_EAX, R_ECX );
  1619                                 ADD_imm8s_r32( 4, R_EAX );
  1620                                 store_reg( R_EAX, Rm );
  1621                                 MEM_READ_LONG( R_ECX, R_EAX );
  1622                                 store_spreg( R_EAX, R_SGR );
  1623                                 sh4_x86.tstate = TSTATE_NONE;
  1625                                 break;
  1626                             case 0x5:
  1627                                 { /* LDS.L @Rm+, FPUL */
  1628                                 uint32_t Rm = ((ir>>8)&0xF); 
  1629                                 load_reg( R_EAX, Rm );
  1630                                 precheck();
  1631                                 check_ralign32( R_EAX );
  1632                                 MOV_r32_r32( R_EAX, R_ECX );
  1633                                 ADD_imm8s_r32( 4, R_EAX );
  1634                                 store_reg( R_EAX, Rm );
  1635                                 MEM_READ_LONG( R_ECX, R_EAX );
  1636                                 store_spreg( R_EAX, R_FPUL );
  1637                                 sh4_x86.tstate = TSTATE_NONE;
  1639                                 break;
  1640                             case 0x6:
  1641                                 { /* LDS.L @Rm+, FPSCR */
  1642                                 uint32_t Rm = ((ir>>8)&0xF); 
  1643                                 load_reg( R_EAX, Rm );
  1644                                 precheck();
  1645                                 check_ralign32( R_EAX );
  1646                                 MOV_r32_r32( R_EAX, R_ECX );
  1647                                 ADD_imm8s_r32( 4, R_EAX );
  1648                                 store_reg( R_EAX, Rm );
  1649                                 MEM_READ_LONG( R_ECX, R_EAX );
  1650                                 store_spreg( R_EAX, R_FPSCR );
  1651                                 update_fr_bank( R_EAX );
  1652                                 sh4_x86.tstate = TSTATE_NONE;
  1654                                 break;
  1655                             case 0xF:
  1656                                 { /* LDC.L @Rm+, DBR */
  1657                                 uint32_t Rm = ((ir>>8)&0xF); 
  1658                                 precheck();
  1659                                 check_priv_no_precheck();
  1660                                 load_reg( R_EAX, Rm );
  1661                                 check_ralign32( R_EAX );
  1662                                 MOV_r32_r32( R_EAX, R_ECX );
  1663                                 ADD_imm8s_r32( 4, R_EAX );
  1664                                 store_reg( R_EAX, Rm );
  1665                                 MEM_READ_LONG( R_ECX, R_EAX );
  1666                                 store_spreg( R_EAX, R_DBR );
  1667                                 sh4_x86.tstate = TSTATE_NONE;
  1669                                 break;
  1670                             default:
  1671                                 UNDEF();
  1672                                 break;
  1674                         break;
  1675                     case 0x7:
  1676                         switch( (ir&0x80) >> 7 ) {
  1677                             case 0x0:
  1678                                 switch( (ir&0x70) >> 4 ) {
  1679                                     case 0x0:
  1680                                         { /* LDC.L @Rm+, SR */
  1681                                         uint32_t Rm = ((ir>>8)&0xF); 
  1682                                         if( sh4_x86.in_delay_slot ) {
  1683                                     	SLOTILLEGAL();
  1684                                         } else {
  1685                                     	precheck();
  1686                                     	check_priv_no_precheck();
  1687                                     	load_reg( R_EAX, Rm );
  1688                                     	check_ralign32( R_EAX );
  1689                                     	MOV_r32_r32( R_EAX, R_ECX );
  1690                                     	ADD_imm8s_r32( 4, R_EAX );
  1691                                     	store_reg( R_EAX, Rm );
  1692                                     	MEM_READ_LONG( R_ECX, R_EAX );
  1693                                     	call_func1( sh4_write_sr, R_EAX );
  1694                                     	sh4_x86.priv_checked = FALSE;
  1695                                     	sh4_x86.fpuen_checked = FALSE;
  1696                                     	sh4_x86.tstate = TSTATE_NONE;
  1699                                         break;
  1700                                     case 0x1:
  1701                                         { /* LDC.L @Rm+, GBR */
  1702                                         uint32_t Rm = ((ir>>8)&0xF); 
  1703                                         load_reg( R_EAX, Rm );
  1704                                         precheck();
  1705                                         check_ralign32( R_EAX );
  1706                                         MOV_r32_r32( R_EAX, R_ECX );
  1707                                         ADD_imm8s_r32( 4, R_EAX );
  1708                                         store_reg( R_EAX, Rm );
  1709                                         MEM_READ_LONG( R_ECX, R_EAX );
  1710                                         store_spreg( R_EAX, R_GBR );
  1711                                         sh4_x86.tstate = TSTATE_NONE;
  1713                                         break;
  1714                                     case 0x2:
  1715                                         { /* LDC.L @Rm+, VBR */
  1716                                         uint32_t Rm = ((ir>>8)&0xF); 
  1717                                         precheck();
  1718                                         check_priv_no_precheck();
  1719                                         load_reg( R_EAX, Rm );
  1720                                         check_ralign32( R_EAX );
  1721                                         MOV_r32_r32( R_EAX, R_ECX );
  1722                                         ADD_imm8s_r32( 4, R_EAX );
  1723                                         store_reg( R_EAX, Rm );
  1724                                         MEM_READ_LONG( R_ECX, R_EAX );
  1725                                         store_spreg( R_EAX, R_VBR );
  1726                                         sh4_x86.tstate = TSTATE_NONE;
  1728                                         break;
  1729                                     case 0x3:
  1730                                         { /* LDC.L @Rm+, SSR */
  1731                                         uint32_t Rm = ((ir>>8)&0xF); 
  1732                                         precheck();
  1733                                         check_priv_no_precheck();
  1734                                         load_reg( R_EAX, Rm );
  1735                                         check_ralign32( R_EAX );
  1736                                         MOV_r32_r32( R_EAX, R_ECX );
  1737                                         ADD_imm8s_r32( 4, R_EAX );
  1738                                         store_reg( R_EAX, Rm );
  1739                                         MEM_READ_LONG( R_ECX, R_EAX );
  1740                                         store_spreg( R_EAX, R_SSR );
  1741                                         sh4_x86.tstate = TSTATE_NONE;
  1743                                         break;
  1744                                     case 0x4:
  1745                                         { /* LDC.L @Rm+, SPC */
  1746                                         uint32_t Rm = ((ir>>8)&0xF); 
  1747                                         precheck();
  1748                                         check_priv_no_precheck();
  1749                                         load_reg( R_EAX, Rm );
  1750                                         check_ralign32( R_EAX );
  1751                                         MOV_r32_r32( R_EAX, R_ECX );
  1752                                         ADD_imm8s_r32( 4, R_EAX );
  1753                                         store_reg( R_EAX, Rm );
  1754                                         MEM_READ_LONG( R_ECX, R_EAX );
  1755                                         store_spreg( R_EAX, R_SPC );
  1756                                         sh4_x86.tstate = TSTATE_NONE;
  1758                                         break;
  1759                                     default:
  1760                                         UNDEF();
  1761                                         break;
  1763                                 break;
  1764                             case 0x1:
  1765                                 { /* LDC.L @Rm+, Rn_BANK */
  1766                                 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
  1767                                 precheck();
  1768                                 check_priv_no_precheck();
  1769                                 load_reg( R_EAX, Rm );
  1770                                 check_ralign32( R_EAX );
  1771                                 MOV_r32_r32( R_EAX, R_ECX );
  1772                                 ADD_imm8s_r32( 4, R_EAX );
  1773                                 store_reg( R_EAX, Rm );
  1774                                 MEM_READ_LONG( R_ECX, R_EAX );
  1775                                 store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
  1776                                 sh4_x86.tstate = TSTATE_NONE;
  1778                                 break;
  1780                         break;
  1781                     case 0x8:
  1782                         switch( (ir&0xF0) >> 4 ) {
  1783                             case 0x0:
  1784                                 { /* SHLL2 Rn */
  1785                                 uint32_t Rn = ((ir>>8)&0xF); 
  1786                                 load_reg( R_EAX, Rn );
  1787                                 SHL_imm8_r32( 2, R_EAX );
  1788                                 store_reg( R_EAX, Rn );
  1789                                 sh4_x86.tstate = TSTATE_NONE;
  1791                                 break;
  1792                             case 0x1:
  1793                                 { /* SHLL8 Rn */
  1794                                 uint32_t Rn = ((ir>>8)&0xF); 
  1795                                 load_reg( R_EAX, Rn );
  1796                                 SHL_imm8_r32( 8, R_EAX );
  1797                                 store_reg( R_EAX, Rn );
  1798                                 sh4_x86.tstate = TSTATE_NONE;
  1800                                 break;
  1801                             case 0x2:
  1802                                 { /* SHLL16 Rn */
  1803                                 uint32_t Rn = ((ir>>8)&0xF); 
  1804                                 load_reg( R_EAX, Rn );
  1805                                 SHL_imm8_r32( 16, R_EAX );
  1806                                 store_reg( R_EAX, Rn );
  1807                                 sh4_x86.tstate = TSTATE_NONE;
  1809                                 break;
  1810                             default:
  1811                                 UNDEF();
  1812                                 break;
  1814                         break;
  1815                     case 0x9:
  1816                         switch( (ir&0xF0) >> 4 ) {
  1817                             case 0x0:
  1818                                 { /* SHLR2 Rn */
  1819                                 uint32_t Rn = ((ir>>8)&0xF); 
  1820                                 load_reg( R_EAX, Rn );
  1821                                 SHR_imm8_r32( 2, R_EAX );
  1822                                 store_reg( R_EAX, Rn );
  1823                                 sh4_x86.tstate = TSTATE_NONE;
  1825                                 break;
  1826                             case 0x1:
  1827                                 { /* SHLR8 Rn */
  1828                                 uint32_t Rn = ((ir>>8)&0xF); 
  1829                                 load_reg( R_EAX, Rn );
  1830                                 SHR_imm8_r32( 8, R_EAX );
  1831                                 store_reg( R_EAX, Rn );
  1832                                 sh4_x86.tstate = TSTATE_NONE;
  1834                                 break;
  1835                             case 0x2:
  1836                                 { /* SHLR16 Rn */
  1837                                 uint32_t Rn = ((ir>>8)&0xF); 
  1838                                 load_reg( R_EAX, Rn );
  1839                                 SHR_imm8_r32( 16, R_EAX );
  1840                                 store_reg( R_EAX, Rn );
  1841                                 sh4_x86.tstate = TSTATE_NONE;
  1843                                 break;
  1844                             default:
  1845                                 UNDEF();
  1846                                 break;
  1848                         break;
  1849                     case 0xA:
  1850                         switch( (ir&0xF0) >> 4 ) {
  1851                             case 0x0:
  1852                                 { /* LDS Rm, MACH */
  1853                                 uint32_t Rm = ((ir>>8)&0xF); 
  1854                                 load_reg( R_EAX, Rm );
  1855                                 store_spreg( R_EAX, R_MACH );
  1857                                 break;
  1858                             case 0x1:
  1859                                 { /* LDS Rm, MACL */
  1860                                 uint32_t Rm = ((ir>>8)&0xF); 
  1861                                 load_reg( R_EAX, Rm );
  1862                                 store_spreg( R_EAX, R_MACL );
  1864                                 break;
  1865                             case 0x2:
  1866                                 { /* LDS Rm, PR */
  1867                                 uint32_t Rm = ((ir>>8)&0xF); 
  1868                                 load_reg( R_EAX, Rm );
  1869                                 store_spreg( R_EAX, R_PR );
  1871                                 break;
  1872                             case 0x3:
  1873                                 { /* LDC Rm, SGR */
  1874                                 uint32_t Rm = ((ir>>8)&0xF); 
  1875                                 check_priv();
  1876                                 load_reg( R_EAX, Rm );
  1877                                 store_spreg( R_EAX, R_SGR );
  1878                                 sh4_x86.tstate = TSTATE_NONE;
  1880                                 break;
  1881                             case 0x5:
  1882                                 { /* LDS Rm, FPUL */
  1883                                 uint32_t Rm = ((ir>>8)&0xF); 
  1884                                 load_reg( R_EAX, Rm );
  1885                                 store_spreg( R_EAX, R_FPUL );
  1887                                 break;
  1888                             case 0x6:
  1889                                 { /* LDS Rm, FPSCR */
  1890                                 uint32_t Rm = ((ir>>8)&0xF); 
  1891                                 load_reg( R_EAX, Rm );
  1892                                 store_spreg( R_EAX, R_FPSCR );
  1893                                 update_fr_bank( R_EAX );
  1894                                 sh4_x86.tstate = TSTATE_NONE;
  1896                                 break;
  1897                             case 0xF:
  1898                                 { /* LDC Rm, DBR */
  1899                                 uint32_t Rm = ((ir>>8)&0xF); 
  1900                                 check_priv();
  1901                                 load_reg( R_EAX, Rm );
  1902                                 store_spreg( R_EAX, R_DBR );
  1903                                 sh4_x86.tstate = TSTATE_NONE;
  1905                                 break;
  1906                             default:
  1907                                 UNDEF();
  1908                                 break;
  1910                         break;
  1911                     case 0xB:
  1912                         switch( (ir&0xF0) >> 4 ) {
  1913                             case 0x0:
  1914                                 { /* JSR @Rn */
  1915                                 uint32_t Rn = ((ir>>8)&0xF); 
  1916                                 if( sh4_x86.in_delay_slot ) {
  1917                             	SLOTILLEGAL();
  1918                                 } else {
  1919                             	load_imm32( R_EAX, pc + 4 );
  1920                             	store_spreg( R_EAX, R_PR );
  1921                             	load_reg( R_ECX, Rn );
  1922                             	store_spreg( R_ECX, REG_OFFSET(pc) );
  1923                             	sh4_x86.in_delay_slot = TRUE;
  1924                             	sh4_translate_instruction(pc+2);
  1925                             	exit_block_pcset(pc+2);
  1926                             	sh4_x86.branch_taken = TRUE;
  1927                             	return 4;
  1930                                 break;
  1931                             case 0x1:
  1932                                 { /* TAS.B @Rn */
  1933                                 uint32_t Rn = ((ir>>8)&0xF); 
  1934                                 load_reg( R_ECX, Rn );
  1935                                 MEM_READ_BYTE( R_ECX, R_EAX );
  1936                                 TEST_r8_r8( R_AL, R_AL );
  1937                                 SETE_t();
  1938                                 OR_imm8_r8( 0x80, R_AL );
  1939                                 load_reg( R_ECX, Rn );
  1940                                 MEM_WRITE_BYTE( R_ECX, R_EAX );
  1941                                 sh4_x86.tstate = TSTATE_NONE;
  1943                                 break;
  1944                             case 0x2:
  1945                                 { /* JMP @Rn */
  1946                                 uint32_t Rn = ((ir>>8)&0xF); 
  1947                                 if( sh4_x86.in_delay_slot ) {
  1948                             	SLOTILLEGAL();
  1949                                 } else {
  1950                             	load_reg( R_ECX, Rn );
  1951                             	store_spreg( R_ECX, REG_OFFSET(pc) );
  1952                             	sh4_x86.in_delay_slot = TRUE;
  1953                             	sh4_translate_instruction(pc+2);
  1954                             	exit_block_pcset(pc+2);
  1955                             	sh4_x86.branch_taken = TRUE;
  1956                             	return 4;
  1959                                 break;
  1960                             default:
  1961                                 UNDEF();
  1962                                 break;
  1964                         break;
  1965                     case 0xC:
  1966                         { /* SHAD Rm, Rn */
  1967                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1968                         /* Annoyingly enough, not directly convertible */
  1969                         load_reg( R_EAX, Rn );
  1970                         load_reg( R_ECX, Rm );
  1971                         CMP_imm32_r32( 0, R_ECX );
  1972                         JGE_rel8(16, doshl);
  1974                         NEG_r32( R_ECX );      // 2
  1975                         AND_imm8_r8( 0x1F, R_CL ); // 3
  1976                         JE_rel8( 4, emptysar);     // 2
  1977                         SAR_r32_CL( R_EAX );       // 2
  1978                         JMP_rel8(10, end);          // 2
  1980                         JMP_TARGET(emptysar);
  1981                         SAR_imm8_r32(31, R_EAX );  // 3
  1982                         JMP_rel8(5, end2);
  1984                         JMP_TARGET(doshl);
  1985                         AND_imm8_r8( 0x1F, R_CL ); // 3
  1986                         SHL_r32_CL( R_EAX );       // 2
  1987                         JMP_TARGET(end);
  1988                         JMP_TARGET(end2);
  1989                         store_reg( R_EAX, Rn );
  1990                         sh4_x86.tstate = TSTATE_NONE;
  1992                         break;
  1993                     case 0xD:
  1994                         { /* SHLD Rm, Rn */
  1995                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1996                         load_reg( R_EAX, Rn );
  1997                         load_reg( R_ECX, Rm );
  1998                         CMP_imm32_r32( 0, R_ECX );
  1999                         JGE_rel8(15, doshl);
  2001                         NEG_r32( R_ECX );      // 2
  2002                         AND_imm8_r8( 0x1F, R_CL ); // 3
  2003                         JE_rel8( 4, emptyshr );
  2004                         SHR_r32_CL( R_EAX );       // 2
  2005                         JMP_rel8(9, end);          // 2
  2007                         JMP_TARGET(emptyshr);
  2008                         XOR_r32_r32( R_EAX, R_EAX );
  2009                         JMP_rel8(5, end2);
  2011                         JMP_TARGET(doshl);
  2012                         AND_imm8_r8( 0x1F, R_CL ); // 3
  2013                         SHL_r32_CL( R_EAX );       // 2
  2014                         JMP_TARGET(end);
  2015                         JMP_TARGET(end2);
  2016                         store_reg( R_EAX, Rn );
  2017                         sh4_x86.tstate = TSTATE_NONE;
  2019                         break;
  2020                     case 0xE:
  2021                         switch( (ir&0x80) >> 7 ) {
  2022                             case 0x0:
  2023                                 switch( (ir&0x70) >> 4 ) {
  2024                                     case 0x0:
  2025                                         { /* LDC Rm, SR */
  2026                                         uint32_t Rm = ((ir>>8)&0xF); 
  2027                                         if( sh4_x86.in_delay_slot ) {
  2028                                     	SLOTILLEGAL();
  2029                                         } else {
  2030                                     	check_priv();
  2031                                     	load_reg( R_EAX, Rm );
  2032                                     	call_func1( sh4_write_sr, R_EAX );
  2033                                     	sh4_x86.priv_checked = FALSE;
  2034                                     	sh4_x86.fpuen_checked = FALSE;
  2035                                     	sh4_x86.tstate = TSTATE_NONE;
  2038                                         break;
  2039                                     case 0x1:
  2040                                         { /* LDC Rm, GBR */
  2041                                         uint32_t Rm = ((ir>>8)&0xF); 
  2042                                         load_reg( R_EAX, Rm );
  2043                                         store_spreg( R_EAX, R_GBR );
  2045                                         break;
  2046                                     case 0x2:
  2047                                         { /* LDC Rm, VBR */
  2048                                         uint32_t Rm = ((ir>>8)&0xF); 
  2049                                         check_priv();
  2050                                         load_reg( R_EAX, Rm );
  2051                                         store_spreg( R_EAX, R_VBR );
  2052                                         sh4_x86.tstate = TSTATE_NONE;
  2054                                         break;
  2055                                     case 0x3:
  2056                                         { /* LDC Rm, SSR */
  2057                                         uint32_t Rm = ((ir>>8)&0xF); 
  2058                                         check_priv();
  2059                                         load_reg( R_EAX, Rm );
  2060                                         store_spreg( R_EAX, R_SSR );
  2061                                         sh4_x86.tstate = TSTATE_NONE;
  2063                                         break;
  2064                                     case 0x4:
  2065                                         { /* LDC Rm, SPC */
  2066                                         uint32_t Rm = ((ir>>8)&0xF); 
  2067                                         check_priv();
  2068                                         load_reg( R_EAX, Rm );
  2069                                         store_spreg( R_EAX, R_SPC );
  2070                                         sh4_x86.tstate = TSTATE_NONE;
  2072                                         break;
  2073                                     default:
  2074                                         UNDEF();
  2075                                         break;
  2077                                 break;
  2078                             case 0x1:
  2079                                 { /* LDC Rm, Rn_BANK */
  2080                                 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
  2081                                 check_priv();
  2082                                 load_reg( R_EAX, Rm );
  2083                                 store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
  2084                                 sh4_x86.tstate = TSTATE_NONE;
  2086                                 break;
  2088                         break;
  2089                     case 0xF:
  2090                         { /* MAC.W @Rm+, @Rn+ */
  2091                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2092                         load_reg( R_ECX, Rm );
  2093                         precheck();
  2094                         check_ralign16( R_ECX );
  2095                         load_reg( R_ECX, Rn );
  2096                         check_ralign16( R_ECX );
  2097                         ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
  2098                         MEM_READ_WORD( R_ECX, R_EAX );
  2099                         PUSH_realigned_r32( R_EAX );
  2100                         load_reg( R_ECX, Rm );
  2101                         ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
  2102                         MEM_READ_WORD( R_ECX, R_EAX );
  2103                         POP_realigned_r32( R_ECX );
  2104                         IMUL_r32( R_ECX );
  2106                         load_spreg( R_ECX, R_S );
  2107                         TEST_r32_r32( R_ECX, R_ECX );
  2108                         JE_rel8( 47, nosat );
  2110                         ADD_r32_sh4r( R_EAX, R_MACL );  // 6
  2111                         JNO_rel8( 51, end );            // 2
  2112                         load_imm32( R_EDX, 1 );         // 5
  2113                         store_spreg( R_EDX, R_MACH );   // 6
  2114                         JS_rel8( 13, positive );        // 2
  2115                         load_imm32( R_EAX, 0x80000000 );// 5
  2116                         store_spreg( R_EAX, R_MACL );   // 6
  2117                         JMP_rel8( 25, end2 );           // 2
  2119                         JMP_TARGET(positive);
  2120                         load_imm32( R_EAX, 0x7FFFFFFF );// 5
  2121                         store_spreg( R_EAX, R_MACL );   // 6
  2122                         JMP_rel8( 12, end3);            // 2
  2124                         JMP_TARGET(nosat);
  2125                         ADD_r32_sh4r( R_EAX, R_MACL );  // 6
  2126                         ADC_r32_sh4r( R_EDX, R_MACH );  // 6
  2127                         JMP_TARGET(end);
  2128                         JMP_TARGET(end2);
  2129                         JMP_TARGET(end3);
  2130                         sh4_x86.tstate = TSTATE_NONE;
  2132                         break;
  2134                 break;
  2135             case 0x5:
  2136                 { /* MOV.L @(disp, Rm), Rn */
  2137                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
  2138                 load_reg( R_ECX, Rm );
  2139                 ADD_imm8s_r32( disp, R_ECX );
  2140                 precheck();
  2141                 check_ralign32( R_ECX );
  2142                 MEM_READ_LONG( R_ECX, R_EAX );
  2143                 store_reg( R_EAX, Rn );
  2144                 sh4_x86.tstate = TSTATE_NONE;
  2146                 break;
  2147             case 0x6:
  2148                 switch( ir&0xF ) {
  2149                     case 0x0:
  2150                         { /* MOV.B @Rm, Rn */
  2151                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2152                         load_reg( R_ECX, Rm );
  2153                         MEM_READ_BYTE( R_ECX, R_EAX );
  2154                         store_reg( R_EAX, Rn );
  2155                         sh4_x86.tstate = TSTATE_NONE;
  2157                         break;
  2158                     case 0x1:
  2159                         { /* MOV.W @Rm, Rn */
  2160                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2161                         load_reg( R_ECX, Rm );
  2162                         precheck();
  2163                         check_ralign16( R_ECX );
  2164                         MEM_READ_WORD( R_ECX, R_EAX );
  2165                         store_reg( R_EAX, Rn );
  2166                         sh4_x86.tstate = TSTATE_NONE;
  2168                         break;
  2169                     case 0x2:
  2170                         { /* MOV.L @Rm, Rn */
  2171                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2172                         load_reg( R_ECX, Rm );
  2173                         precheck();
  2174                         check_ralign32( R_ECX );
  2175                         MEM_READ_LONG( R_ECX, R_EAX );
  2176                         store_reg( R_EAX, Rn );
  2177                         sh4_x86.tstate = TSTATE_NONE;
  2179                         break;
  2180                     case 0x3:
  2181                         { /* MOV Rm, Rn */
  2182                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2183                         load_reg( R_EAX, Rm );
  2184                         store_reg( R_EAX, Rn );
  2186                         break;
  2187                     case 0x4:
  2188                         { /* MOV.B @Rm+, Rn */
  2189                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2190                         load_reg( R_ECX, Rm );
  2191                         MOV_r32_r32( R_ECX, R_EAX );
  2192                         ADD_imm8s_r32( 1, R_EAX );
  2193                         store_reg( R_EAX, Rm );
  2194                         MEM_READ_BYTE( R_ECX, R_EAX );
  2195                         store_reg( R_EAX, Rn );
  2196                         sh4_x86.tstate = TSTATE_NONE;
  2198                         break;
  2199                     case 0x5:
  2200                         { /* MOV.W @Rm+, Rn */
  2201                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2202                         load_reg( R_EAX, Rm );
  2203                         precheck();
  2204                         check_ralign16( R_EAX );
  2205                         MOV_r32_r32( R_EAX, R_ECX );
  2206                         ADD_imm8s_r32( 2, R_EAX );
  2207                         store_reg( R_EAX, Rm );
  2208                         MEM_READ_WORD( R_ECX, R_EAX );
  2209                         store_reg( R_EAX, Rn );
  2210                         sh4_x86.tstate = TSTATE_NONE;
  2212                         break;
  2213                     case 0x6:
  2214                         { /* MOV.L @Rm+, Rn */
  2215                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2216                         load_reg( R_EAX, Rm );
  2217                         precheck();
  2218                         check_ralign32( R_EAX );
  2219                         MOV_r32_r32( R_EAX, R_ECX );
  2220                         ADD_imm8s_r32( 4, R_EAX );
  2221                         store_reg( R_EAX, Rm );
  2222                         MEM_READ_LONG( R_ECX, R_EAX );
  2223                         store_reg( R_EAX, Rn );
  2224                         sh4_x86.tstate = TSTATE_NONE;
  2226                         break;
  2227                     case 0x7:
  2228                         { /* NOT Rm, Rn */
  2229                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2230                         load_reg( R_EAX, Rm );
  2231                         NOT_r32( R_EAX );
  2232                         store_reg( R_EAX, Rn );
  2233                         sh4_x86.tstate = TSTATE_NONE;
  2235                         break;
  2236                     case 0x8:
  2237                         { /* SWAP.B Rm, Rn */
  2238                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2239                         load_reg( R_EAX, Rm );
  2240                         XCHG_r8_r8( R_AL, R_AH );
  2241                         store_reg( R_EAX, Rn );
  2243                         break;
  2244                     case 0x9:
  2245                         { /* SWAP.W Rm, Rn */
  2246                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2247                         load_reg( R_EAX, Rm );
  2248                         MOV_r32_r32( R_EAX, R_ECX );
  2249                         SHL_imm8_r32( 16, R_ECX );
  2250                         SHR_imm8_r32( 16, R_EAX );
  2251                         OR_r32_r32( R_EAX, R_ECX );
  2252                         store_reg( R_ECX, Rn );
  2253                         sh4_x86.tstate = TSTATE_NONE;
  2255                         break;
  2256                     case 0xA:
  2257                         { /* NEGC Rm, Rn */
  2258                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2259                         load_reg( R_EAX, Rm );
  2260                         XOR_r32_r32( R_ECX, R_ECX );
  2261                         LDC_t();
  2262                         SBB_r32_r32( R_EAX, R_ECX );
  2263                         store_reg( R_ECX, Rn );
  2264                         SETC_t();
  2265                         sh4_x86.tstate = TSTATE_C;
  2267                         break;
  2268                     case 0xB:
  2269                         { /* NEG Rm, Rn */
  2270                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2271                         load_reg( R_EAX, Rm );
  2272                         NEG_r32( R_EAX );
  2273                         store_reg( R_EAX, Rn );
  2274                         sh4_x86.tstate = TSTATE_NONE;
  2276                         break;
  2277                     case 0xC:
  2278                         { /* EXTU.B Rm, Rn */
  2279                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2280                         load_reg( R_EAX, Rm );
  2281                         MOVZX_r8_r32( R_EAX, R_EAX );
  2282                         store_reg( R_EAX, Rn );
  2284                         break;
  2285                     case 0xD:
  2286                         { /* EXTU.W Rm, Rn */
  2287                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2288                         load_reg( R_EAX, Rm );
  2289                         MOVZX_r16_r32( R_EAX, R_EAX );
  2290                         store_reg( R_EAX, Rn );
  2292                         break;
  2293                     case 0xE:
  2294                         { /* EXTS.B Rm, Rn */
  2295                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2296                         load_reg( R_EAX, Rm );
  2297                         MOVSX_r8_r32( R_EAX, R_EAX );
  2298                         store_reg( R_EAX, Rn );
  2300                         break;
  2301                     case 0xF:
  2302                         { /* EXTS.W Rm, Rn */
  2303                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2304                         load_reg( R_EAX, Rm );
  2305                         MOVSX_r16_r32( R_EAX, R_EAX );
  2306                         store_reg( R_EAX, Rn );
  2308                         break;
  2310                 break;
  2311             case 0x7:
  2312                 { /* ADD #imm, Rn */
  2313                 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
  2314                 load_reg( R_EAX, Rn );
  2315                 ADD_imm8s_r32( imm, R_EAX );
  2316                 store_reg( R_EAX, Rn );
  2317                 sh4_x86.tstate = TSTATE_NONE;
  2319                 break;
  2320             case 0x8:
  2321                 switch( (ir&0xF00) >> 8 ) {
  2322                     case 0x0:
  2323                         { /* MOV.B R0, @(disp, Rn) */
  2324                         uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
  2325                         load_reg( R_EAX, 0 );
  2326                         load_reg( R_ECX, Rn );
  2327                         ADD_imm32_r32( disp, R_ECX );
  2328                         MEM_WRITE_BYTE( R_ECX, R_EAX );
  2329                         sh4_x86.tstate = TSTATE_NONE;
  2331                         break;
  2332                     case 0x1:
  2333                         { /* MOV.W R0, @(disp, Rn) */
  2334                         uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
  2335                         load_reg( R_ECX, Rn );
  2336                         load_reg( R_EAX, 0 );
  2337                         ADD_imm32_r32( disp, R_ECX );
  2338                         precheck();
  2339                         check_walign16( R_ECX );
  2340                         MEM_WRITE_WORD( R_ECX, R_EAX );
  2341                         sh4_x86.tstate = TSTATE_NONE;
  2343                         break;
  2344                     case 0x4:
  2345                         { /* MOV.B @(disp, Rm), R0 */
  2346                         uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
  2347                         load_reg( R_ECX, Rm );
  2348                         ADD_imm32_r32( disp, R_ECX );
  2349                         MEM_READ_BYTE( R_ECX, R_EAX );
  2350                         store_reg( R_EAX, 0 );
  2351                         sh4_x86.tstate = TSTATE_NONE;
  2353                         break;
  2354                     case 0x5:
  2355                         { /* MOV.W @(disp, Rm), R0 */
  2356                         uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
  2357                         load_reg( R_ECX, Rm );
  2358                         ADD_imm32_r32( disp, R_ECX );
  2359                         precheck();
  2360                         check_ralign16( R_ECX );
  2361                         MEM_READ_WORD( R_ECX, R_EAX );
  2362                         store_reg( R_EAX, 0 );
  2363                         sh4_x86.tstate = TSTATE_NONE;
  2365                         break;
  2366                     case 0x8:
  2367                         { /* CMP/EQ #imm, R0 */
  2368                         int32_t imm = SIGNEXT8(ir&0xFF); 
  2369                         load_reg( R_EAX, 0 );
  2370                         CMP_imm8s_r32(imm, R_EAX);
  2371                         SETE_t();
  2372                         sh4_x86.tstate = TSTATE_E;
  2374                         break;
  2375                     case 0x9:
  2376                         { /* BT disp */
  2377                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  2378                         if( sh4_x86.in_delay_slot ) {
  2379                     	SLOTILLEGAL();
  2380                         } else {
  2381                     	JF_rel8( EXIT_BLOCK_SIZE, nottaken );
  2382                     	exit_block( disp + pc + 4, pc+2 );
  2383                     	JMP_TARGET(nottaken);
  2384                     	return 2;
  2387                         break;
  2388                     case 0xB:
  2389                         { /* BF disp */
  2390                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  2391                         if( sh4_x86.in_delay_slot ) {
  2392                     	SLOTILLEGAL();
  2393                         } else {
  2394                     	JT_rel8( EXIT_BLOCK_SIZE, nottaken );
  2395                     	exit_block( disp + pc + 4, pc+2 );
  2396                     	JMP_TARGET(nottaken);
  2397                     	return 2;
  2400                         break;
  2401                     case 0xD:
  2402                         { /* BT/S disp */
  2403                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  2404                         if( sh4_x86.in_delay_slot ) {
  2405                     	SLOTILLEGAL();
  2406                         } else {
  2407                     	sh4_x86.in_delay_slot = TRUE;
  2408                     	if( sh4_x86.tstate == TSTATE_NONE ) {
  2409                     	    CMP_imm8s_sh4r( 1, R_T );
  2410                     	    sh4_x86.tstate = TSTATE_E;
  2412                     	OP(0x0F); OP(0x80+(sh4_x86.tstate^1)); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JE rel32
  2413                     	sh4_translate_instruction(pc+2);
  2414                     	exit_block( disp + pc + 4, pc+4 );
  2415                     	// not taken
  2416                     	*patch = (xlat_output - ((uint8_t *)patch)) - 4;
  2417                     	sh4_translate_instruction(pc+2);
  2418                     	return 4;
  2421                         break;
  2422                     case 0xF:
  2423                         { /* BF/S disp */
  2424                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  2425                         if( sh4_x86.in_delay_slot ) {
  2426                     	SLOTILLEGAL();
  2427                         } else {
  2428                     	sh4_x86.in_delay_slot = TRUE;
  2429                     	if( sh4_x86.tstate == TSTATE_NONE ) {
  2430                     	    CMP_imm8s_sh4r( 1, R_T );
  2431                     	    sh4_x86.tstate = TSTATE_E;
  2433                     	OP(0x0F); OP(0x80+sh4_x86.tstate); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JNE rel32
  2434                     	sh4_translate_instruction(pc+2);
  2435                     	exit_block( disp + pc + 4, pc+4 );
  2436                     	// not taken
  2437                     	*patch = (xlat_output - ((uint8_t *)patch)) - 4;
  2438                     	sh4_translate_instruction(pc+2);
  2439                     	return 4;
  2442                         break;
  2443                     default:
  2444                         UNDEF();
  2445                         break;
  2447                 break;
  2448             case 0x9:
  2449                 { /* MOV.W @(disp, PC), Rn */
  2450                 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1; 
  2451                 if( sh4_x86.in_delay_slot ) {
  2452             	SLOTILLEGAL();
  2453                 } else {
  2454             	load_imm32( R_ECX, pc + disp + 4 );
  2455             	MEM_READ_WORD( R_ECX, R_EAX );
  2456             	store_reg( R_EAX, Rn );
  2457             	sh4_x86.tstate = TSTATE_NONE;
  2460                 break;
  2461             case 0xA:
  2462                 { /* BRA disp */
  2463                 int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
  2464                 if( sh4_x86.in_delay_slot ) {
  2465             	SLOTILLEGAL();
  2466                 } else {
  2467             	sh4_x86.in_delay_slot = TRUE;
  2468             	sh4_translate_instruction( pc + 2 );
  2469             	exit_block( disp + pc + 4, pc+4 );
  2470             	sh4_x86.branch_taken = TRUE;
  2471             	return 4;
  2474                 break;
  2475             case 0xB:
  2476                 { /* BSR disp */
  2477                 int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
  2478                 if( sh4_x86.in_delay_slot ) {
  2479             	SLOTILLEGAL();
  2480                 } else {
  2481             	load_imm32( R_EAX, pc + 4 );
  2482             	store_spreg( R_EAX, R_PR );
  2483             	sh4_x86.in_delay_slot = TRUE;
  2484             	sh4_translate_instruction( pc + 2 );
  2485             	exit_block( disp + pc + 4, pc+4 );
  2486             	sh4_x86.branch_taken = TRUE;
  2487             	return 4;
  2490                 break;
  2491             case 0xC:
  2492                 switch( (ir&0xF00) >> 8 ) {
  2493                     case 0x0:
  2494                         { /* MOV.B R0, @(disp, GBR) */
  2495                         uint32_t disp = (ir&0xFF); 
  2496                         load_reg( R_EAX, 0 );
  2497                         load_spreg( R_ECX, R_GBR );
  2498                         ADD_imm32_r32( disp, R_ECX );
  2499                         MEM_WRITE_BYTE( R_ECX, R_EAX );
  2500                         sh4_x86.tstate = TSTATE_NONE;
  2502                         break;
  2503                     case 0x1:
  2504                         { /* MOV.W R0, @(disp, GBR) */
  2505                         uint32_t disp = (ir&0xFF)<<1; 
  2506                         load_spreg( R_ECX, R_GBR );
  2507                         load_reg( R_EAX, 0 );
  2508                         ADD_imm32_r32( disp, R_ECX );
  2509                         precheck();
  2510                         check_walign16( R_ECX );
  2511                         MEM_WRITE_WORD( R_ECX, R_EAX );
  2512                         sh4_x86.tstate = TSTATE_NONE;
  2514                         break;
  2515                     case 0x2:
  2516                         { /* MOV.L R0, @(disp, GBR) */
  2517                         uint32_t disp = (ir&0xFF)<<2; 
  2518                         load_spreg( R_ECX, R_GBR );
  2519                         load_reg( R_EAX, 0 );
  2520                         ADD_imm32_r32( disp, R_ECX );
  2521                         precheck();
  2522                         check_walign32( R_ECX );
  2523                         MEM_WRITE_LONG( R_ECX, R_EAX );
  2524                         sh4_x86.tstate = TSTATE_NONE;
  2526                         break;
  2527                     case 0x3:
  2528                         { /* TRAPA #imm */
  2529                         uint32_t imm = (ir&0xFF); 
  2530                         if( sh4_x86.in_delay_slot ) {
  2531                     	SLOTILLEGAL();
  2532                         } else {
  2533                     	load_imm32( R_ECX, pc+2 );
  2534                     	store_spreg( R_ECX, REG_OFFSET(pc) );
  2535                     	load_imm32( R_EAX, imm );
  2536                     	call_func1( sh4_raise_trap, R_EAX );
  2537                     	sh4_x86.tstate = TSTATE_NONE;
  2538                     	exit_block_pcset(pc);
  2539                     	sh4_x86.branch_taken = TRUE;
  2540                     	return 2;
  2543                         break;
  2544                     case 0x4:
  2545                         { /* MOV.B @(disp, GBR), R0 */
  2546                         uint32_t disp = (ir&0xFF); 
  2547                         load_spreg( R_ECX, R_GBR );
  2548                         ADD_imm32_r32( disp, R_ECX );
  2549                         MEM_READ_BYTE( R_ECX, R_EAX );
  2550                         store_reg( R_EAX, 0 );
  2551                         sh4_x86.tstate = TSTATE_NONE;
  2553                         break;
  2554                     case 0x5:
  2555                         { /* MOV.W @(disp, GBR), R0 */
  2556                         uint32_t disp = (ir&0xFF)<<1; 
  2557                         load_spreg( R_ECX, R_GBR );
  2558                         ADD_imm32_r32( disp, R_ECX );
  2559                         precheck();
  2560                         check_ralign16( R_ECX );
  2561                         MEM_READ_WORD( R_ECX, R_EAX );
  2562                         store_reg( R_EAX, 0 );
  2563                         sh4_x86.tstate = TSTATE_NONE;
  2565                         break;
  2566                     case 0x6:
  2567                         { /* MOV.L @(disp, GBR), R0 */
  2568                         uint32_t disp = (ir&0xFF)<<2; 
  2569                         load_spreg( R_ECX, R_GBR );
  2570                         ADD_imm32_r32( disp, R_ECX );
  2571                         precheck();
  2572                         check_ralign32( R_ECX );
  2573                         MEM_READ_LONG( R_ECX, R_EAX );
  2574                         store_reg( R_EAX, 0 );
  2575                         sh4_x86.tstate = TSTATE_NONE;
  2577                         break;
  2578                     case 0x7:
  2579                         { /* MOVA @(disp, PC), R0 */
  2580                         uint32_t disp = (ir&0xFF)<<2; 
  2581                         if( sh4_x86.in_delay_slot ) {
  2582                     	SLOTILLEGAL();
  2583                         } else {
  2584                     	load_imm32( R_ECX, (pc & 0xFFFFFFFC) + disp + 4 );
  2585                     	store_reg( R_ECX, 0 );
  2588                         break;
  2589                     case 0x8:
  2590                         { /* TST #imm, R0 */
  2591                         uint32_t imm = (ir&0xFF); 
  2592                         load_reg( R_EAX, 0 );
  2593                         TEST_imm32_r32( imm, R_EAX );
  2594                         SETE_t();
  2595                         sh4_x86.tstate = TSTATE_E;
  2597                         break;
  2598                     case 0x9:
  2599                         { /* AND #imm, R0 */
  2600                         uint32_t imm = (ir&0xFF); 
  2601                         load_reg( R_EAX, 0 );
  2602                         AND_imm32_r32(imm, R_EAX); 
  2603                         store_reg( R_EAX, 0 );
  2604                         sh4_x86.tstate = TSTATE_NONE;
  2606                         break;
  2607                     case 0xA:
  2608                         { /* XOR #imm, R0 */
  2609                         uint32_t imm = (ir&0xFF); 
  2610                         load_reg( R_EAX, 0 );
  2611                         XOR_imm32_r32( imm, R_EAX );
  2612                         store_reg( R_EAX, 0 );
  2613                         sh4_x86.tstate = TSTATE_NONE;
  2615                         break;
  2616                     case 0xB:
  2617                         { /* OR #imm, R0 */
  2618                         uint32_t imm = (ir&0xFF); 
  2619                         load_reg( R_EAX, 0 );
  2620                         OR_imm32_r32(imm, R_EAX);
  2621                         store_reg( R_EAX, 0 );
  2622                         sh4_x86.tstate = TSTATE_NONE;
  2624                         break;
  2625                     case 0xC:
  2626                         { /* TST.B #imm, @(R0, GBR) */
  2627                         uint32_t imm = (ir&0xFF); 
  2628                         load_reg( R_EAX, 0);
  2629                         load_reg( R_ECX, R_GBR);
  2630                         ADD_r32_r32( R_EAX, R_ECX );
  2631                         MEM_READ_BYTE( R_ECX, R_EAX );
  2632                         TEST_imm8_r8( imm, R_AL );
  2633                         SETE_t();
  2634                         sh4_x86.tstate = TSTATE_E;
  2636                         break;
  2637                     case 0xD:
  2638                         { /* AND.B #imm, @(R0, GBR) */
  2639                         uint32_t imm = (ir&0xFF); 
  2640                         load_reg( R_EAX, 0 );
  2641                         load_spreg( R_ECX, R_GBR );
  2642                         ADD_r32_r32( R_EAX, R_ECX );
  2643                         PUSH_realigned_r32(R_ECX);
  2644                         MEM_READ_BYTE( R_ECX, R_EAX );
  2645                         POP_realigned_r32(R_ECX);
  2646                         AND_imm32_r32(imm, R_EAX );
  2647                         MEM_WRITE_BYTE( R_ECX, R_EAX );
  2648                         sh4_x86.tstate = TSTATE_NONE;
  2650                         break;
  2651                     case 0xE:
  2652                         { /* XOR.B #imm, @(R0, GBR) */
  2653                         uint32_t imm = (ir&0xFF); 
  2654                         load_reg( R_EAX, 0 );
  2655                         load_spreg( R_ECX, R_GBR );
  2656                         ADD_r32_r32( R_EAX, R_ECX );
  2657                         PUSH_realigned_r32(R_ECX);
  2658                         MEM_READ_BYTE(R_ECX, R_EAX);
  2659                         POP_realigned_r32(R_ECX);
  2660                         XOR_imm32_r32( imm, R_EAX );
  2661                         MEM_WRITE_BYTE( R_ECX, R_EAX );
  2662                         sh4_x86.tstate = TSTATE_NONE;
  2664                         break;
  2665                     case 0xF:
  2666                         { /* OR.B #imm, @(R0, GBR) */
  2667                         uint32_t imm = (ir&0xFF); 
  2668                         load_reg( R_EAX, 0 );
  2669                         load_spreg( R_ECX, R_GBR );
  2670                         ADD_r32_r32( R_EAX, R_ECX );
  2671                         PUSH_realigned_r32(R_ECX);
  2672                         MEM_READ_BYTE( R_ECX, R_EAX );
  2673                         POP_realigned_r32(R_ECX);
  2674                         OR_imm32_r32(imm, R_EAX );
  2675                         MEM_WRITE_BYTE( R_ECX, R_EAX );
  2676                         sh4_x86.tstate = TSTATE_NONE;
  2678                         break;
  2680                 break;
  2681             case 0xD:
  2682                 { /* MOV.L @(disp, PC), Rn */
  2683                 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<2; 
  2684                 if( sh4_x86.in_delay_slot ) {
  2685             	SLOTILLEGAL();
  2686                 } else {
  2687             	uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
  2688             	sh4ptr_t ptr = mem_get_region(target);
  2689             	if( ptr != NULL ) {
  2690             	    MOV_moff32_EAX( ptr );
  2691             	} else {
  2692             	    load_imm32( R_ECX, target );
  2693             	    MEM_READ_LONG( R_ECX, R_EAX );
  2695             	store_reg( R_EAX, Rn );
  2696             	sh4_x86.tstate = TSTATE_NONE;
  2699                 break;
  2700             case 0xE:
  2701                 { /* MOV #imm, Rn */
  2702                 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
  2703                 load_imm32( R_EAX, imm );
  2704                 store_reg( R_EAX, Rn );
  2706                 break;
  2707             case 0xF:
  2708                 switch( ir&0xF ) {
  2709                     case 0x0:
  2710                         { /* FADD FRm, FRn */
  2711                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2712                         check_fpuen();
  2713                         load_spreg( R_ECX, R_FPSCR );
  2714                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  2715                         load_fr_bank( R_EDX );
  2716                         JNE_rel8(13,doubleprec);
  2717                         push_fr(R_EDX, FRm);
  2718                         push_fr(R_EDX, FRn);
  2719                         FADDP_st(1);
  2720                         pop_fr(R_EDX, FRn);
  2721                         JMP_rel8(11,end);
  2722                         JMP_TARGET(doubleprec);
  2723                         push_dr(R_EDX, FRm);
  2724                         push_dr(R_EDX, FRn);
  2725                         FADDP_st(1);
  2726                         pop_dr(R_EDX, FRn);
  2727                         JMP_TARGET(end);
  2728                         sh4_x86.tstate = TSTATE_NONE;
  2730                         break;
  2731                     case 0x1:
  2732                         { /* FSUB FRm, FRn */
  2733                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2734                         check_fpuen();
  2735                         load_spreg( R_ECX, R_FPSCR );
  2736                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  2737                         load_fr_bank( R_EDX );
  2738                         JNE_rel8(13, doubleprec);
  2739                         push_fr(R_EDX, FRn);
  2740                         push_fr(R_EDX, FRm);
  2741                         FSUBP_st(1);
  2742                         pop_fr(R_EDX, FRn);
  2743                         JMP_rel8(11, end);
  2744                         JMP_TARGET(doubleprec);
  2745                         push_dr(R_EDX, FRn);
  2746                         push_dr(R_EDX, FRm);
  2747                         FSUBP_st(1);
  2748                         pop_dr(R_EDX, FRn);
  2749                         JMP_TARGET(end);
  2750                         sh4_x86.tstate = TSTATE_NONE;
  2752                         break;
  2753                     case 0x2:
  2754                         { /* FMUL FRm, FRn */
  2755                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2756                         check_fpuen();
  2757                         load_spreg( R_ECX, R_FPSCR );
  2758                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  2759                         load_fr_bank( R_EDX );
  2760                         JNE_rel8(13, doubleprec);
  2761                         push_fr(R_EDX, FRm);
  2762                         push_fr(R_EDX, FRn);
  2763                         FMULP_st(1);
  2764                         pop_fr(R_EDX, FRn);
  2765                         JMP_rel8(11, end);
  2766                         JMP_TARGET(doubleprec);
  2767                         push_dr(R_EDX, FRm);
  2768                         push_dr(R_EDX, FRn);
  2769                         FMULP_st(1);
  2770                         pop_dr(R_EDX, FRn);
  2771                         JMP_TARGET(end);
  2772                         sh4_x86.tstate = TSTATE_NONE;
  2774                         break;
  2775                     case 0x3:
  2776                         { /* FDIV FRm, FRn */
  2777                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2778                         check_fpuen();
  2779                         load_spreg( R_ECX, R_FPSCR );
  2780                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  2781                         load_fr_bank( R_EDX );
  2782                         JNE_rel8(13, doubleprec);
  2783                         push_fr(R_EDX, FRn);
  2784                         push_fr(R_EDX, FRm);
  2785                         FDIVP_st(1);
  2786                         pop_fr(R_EDX, FRn);
  2787                         JMP_rel8(11, end);
  2788                         JMP_TARGET(doubleprec);
  2789                         push_dr(R_EDX, FRn);
  2790                         push_dr(R_EDX, FRm);
  2791                         FDIVP_st(1);
  2792                         pop_dr(R_EDX, FRn);
  2793                         JMP_TARGET(end);
  2794                         sh4_x86.tstate = TSTATE_NONE;
  2796                         break;
  2797                     case 0x4:
  2798                         { /* FCMP/EQ FRm, FRn */
  2799                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2800                         check_fpuen();
  2801                         load_spreg( R_ECX, R_FPSCR );
  2802                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  2803                         load_fr_bank( R_EDX );
  2804                         JNE_rel8(8, doubleprec);
  2805                         push_fr(R_EDX, FRm);
  2806                         push_fr(R_EDX, FRn);
  2807                         JMP_rel8(6, end);
  2808                         JMP_TARGET(doubleprec);
  2809                         push_dr(R_EDX, FRm);
  2810                         push_dr(R_EDX, FRn);
  2811                         JMP_TARGET(end);
  2812                         FCOMIP_st(1);
  2813                         SETE_t();
  2814                         FPOP_st();
  2815                         sh4_x86.tstate = TSTATE_NONE;
  2817                         break;
  2818                     case 0x5:
  2819                         { /* FCMP/GT FRm, FRn */
  2820                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2821                         check_fpuen();
  2822                         load_spreg( R_ECX, R_FPSCR );
  2823                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  2824                         load_fr_bank( R_EDX );
  2825                         JNE_rel8(8, doubleprec);
  2826                         push_fr(R_EDX, FRm);
  2827                         push_fr(R_EDX, FRn);
  2828                         JMP_rel8(6, end);
  2829                         JMP_TARGET(doubleprec);
  2830                         push_dr(R_EDX, FRm);
  2831                         push_dr(R_EDX, FRn);
  2832                         JMP_TARGET(end);
  2833                         FCOMIP_st(1);
  2834                         SETA_t();
  2835                         FPOP_st();
  2836                         sh4_x86.tstate = TSTATE_NONE;
  2838                         break;
  2839                     case 0x6:
  2840                         { /* FMOV @(R0, Rm), FRn */
  2841                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2842                         precheck();
  2843                         check_fpuen_no_precheck();
  2844                         load_reg( R_ECX, Rm );
  2845                         ADD_sh4r_r32( REG_OFFSET(r[0]), R_ECX );
  2846                         check_ralign32( R_ECX );
  2847                         load_spreg( R_EDX, R_FPSCR );
  2848                         TEST_imm32_r32( FPSCR_SZ, R_EDX );
  2849                         JNE_rel8(8 + CALL_FUNC1_SIZE, doublesize);
  2850                         MEM_READ_LONG( R_ECX, R_EAX );
  2851                         load_fr_bank( R_EDX );
  2852                         store_fr( R_EDX, R_EAX, FRn );
  2853                         if( FRn&1 ) {
  2854                     	JMP_rel8(21 + MEM_READ_DOUBLE_SIZE, end);
  2855                     	JMP_TARGET(doublesize);
  2856                     	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
  2857                     	load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
  2858                     	load_xf_bank( R_EDX );
  2859                     	store_fr( R_EDX, R_EAX, FRn&0x0E );
  2860                     	store_fr( R_EDX, R_ECX, FRn|0x01 );
  2861                     	JMP_TARGET(end);
  2862                         } else {
  2863                     	JMP_rel8(9 + MEM_READ_DOUBLE_SIZE, end);
  2864                     	JMP_TARGET(doublesize);
  2865                     	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
  2866                     	load_fr_bank( R_EDX );
  2867                     	store_fr( R_EDX, R_EAX, FRn&0x0E );
  2868                     	store_fr( R_EDX, R_ECX, FRn|0x01 );
  2869                     	JMP_TARGET(end);
  2871                         sh4_x86.tstate = TSTATE_NONE;
  2873                         break;
  2874                     case 0x7:
  2875                         { /* FMOV FRm, @(R0, Rn) */
  2876                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2877                         precheck();
  2878                         check_fpuen_no_precheck();
  2879                         load_reg( R_ECX, Rn );
  2880                         ADD_sh4r_r32( REG_OFFSET(r[0]), R_ECX );
  2881                         check_walign32( R_ECX );
  2882                         load_spreg( R_EDX, R_FPSCR );
  2883                         TEST_imm32_r32( FPSCR_SZ, R_EDX );
  2884                         JNE_rel8(8 + CALL_FUNC2_SIZE, doublesize);
  2885                         load_fr_bank( R_EDX );
  2886                         load_fr( R_EDX, R_EAX, FRm );
  2887                         MEM_WRITE_LONG( R_ECX, R_EAX ); // 12
  2888                         if( FRm&1 ) {
  2889                     	JMP_rel8( 18 + MEM_WRITE_DOUBLE_SIZE, end );
  2890                     	JMP_TARGET(doublesize);
  2891                     	load_xf_bank( R_EDX );
  2892                     	load_fr( R_EDX, R_EAX, FRm&0x0E );
  2893                     	load_fr( R_EDX, R_EDX, FRm|0x01 );
  2894                     	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
  2895                     	JMP_TARGET(end);
  2896                         } else {
  2897                     	JMP_rel8( 9 + MEM_WRITE_DOUBLE_SIZE, end );
  2898                     	JMP_TARGET(doublesize);
  2899                     	load_fr_bank( R_EDX );
  2900                     	load_fr( R_EDX, R_EAX, FRm&0x0E );
  2901                     	load_fr( R_EDX, R_EDX, FRm|0x01 );
  2902                     	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
  2903                     	JMP_TARGET(end);
  2905                         sh4_x86.tstate = TSTATE_NONE;
  2907                         break;
  2908                     case 0x8:
  2909                         { /* FMOV @Rm, FRn */
  2910                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2911                         precheck();
  2912                         check_fpuen_no_precheck();
  2913                         load_reg( R_ECX, Rm );
  2914                         check_ralign32( R_ECX );
  2915                         load_spreg( R_EDX, R_FPSCR );
  2916                         TEST_imm32_r32( FPSCR_SZ, R_EDX );
  2917                         JNE_rel8(8 + CALL_FUNC1_SIZE, doublesize);
  2918                         MEM_READ_LONG( R_ECX, R_EAX );
  2919                         load_fr_bank( R_EDX );
  2920                         store_fr( R_EDX, R_EAX, FRn );
  2921                         if( FRn&1 ) {
  2922                     	JMP_rel8(21 + MEM_READ_DOUBLE_SIZE, end);
  2923                     	JMP_TARGET(doublesize);
  2924                     	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
  2925                     	load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
  2926                     	load_xf_bank( R_EDX );
  2927                     	store_fr( R_EDX, R_EAX, FRn&0x0E );
  2928                     	store_fr( R_EDX, R_ECX, FRn|0x01 );
  2929                     	JMP_TARGET(end);
  2930                         } else {
  2931                     	JMP_rel8(9 + MEM_READ_DOUBLE_SIZE, end);
  2932                     	JMP_TARGET(doublesize);
  2933                     	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
  2934                     	load_fr_bank( R_EDX );
  2935                     	store_fr( R_EDX, R_EAX, FRn&0x0E );
  2936                     	store_fr( R_EDX, R_ECX, FRn|0x01 );
  2937                     	JMP_TARGET(end);
  2939                         sh4_x86.tstate = TSTATE_NONE;
  2941                         break;
  2942                     case 0x9:
  2943                         { /* FMOV @Rm+, FRn */
  2944                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2945                         precheck();
  2946                         check_fpuen_no_precheck();
  2947                         load_reg( R_ECX, Rm );
  2948                         check_ralign32( R_ECX );
  2949                         MOV_r32_r32( R_ECX, R_EAX );
  2950                         load_spreg( R_EDX, R_FPSCR );
  2951                         TEST_imm32_r32( FPSCR_SZ, R_EDX );
  2952                         JNE_rel8(14 + CALL_FUNC1_SIZE, doublesize);
  2953                         ADD_imm8s_r32( 4, R_EAX );
  2954                         store_reg( R_EAX, Rm );
  2955                         MEM_READ_LONG( R_ECX, R_EAX );
  2956                         load_fr_bank( R_EDX );
  2957                         store_fr( R_EDX, R_EAX, FRn );
  2958                         if( FRn&1 ) {
  2959                     	JMP_rel8(27 + MEM_READ_DOUBLE_SIZE, end);
  2960                     	JMP_TARGET(doublesize);
  2961                     	ADD_imm8s_r32( 8, R_EAX );
  2962                     	store_reg(R_EAX, Rm);
  2963                     	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
  2964                     	load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
  2965                     	load_xf_bank( R_EDX );
  2966                     	store_fr( R_EDX, R_EAX, FRn&0x0E );
  2967                     	store_fr( R_EDX, R_ECX, FRn|0x01 );
  2968                     	JMP_TARGET(end);
  2969                         } else {
  2970                     	JMP_rel8(15 + MEM_READ_DOUBLE_SIZE, end);
  2971                     	ADD_imm8s_r32( 8, R_EAX );
  2972                     	store_reg(R_EAX, Rm);
  2973                     	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
  2974                     	load_fr_bank( R_EDX );
  2975                     	store_fr( R_EDX, R_EAX, FRn&0x0E );
  2976                     	store_fr( R_EDX, R_ECX, FRn|0x01 );
  2977                     	JMP_TARGET(end);
  2979                         sh4_x86.tstate = TSTATE_NONE;
  2981                         break;
  2982                     case 0xA:
  2983                         { /* FMOV FRm, @Rn */
  2984                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2985                         precheck();
  2986                         check_fpuen_no_precheck();
  2987                         load_reg( R_ECX, Rn );
  2988                         check_walign32( R_ECX );
  2989                         load_spreg( R_EDX, R_FPSCR );
  2990                         TEST_imm32_r32( FPSCR_SZ, R_EDX );
  2991                         JNE_rel8(8 + CALL_FUNC2_SIZE, doublesize);
  2992                         load_fr_bank( R_EDX );
  2993                         load_fr( R_EDX, R_EAX, FRm );
  2994                         MEM_WRITE_LONG( R_ECX, R_EAX ); // 12
  2995                         if( FRm&1 ) {
  2996                     	JMP_rel8( 18 + MEM_WRITE_DOUBLE_SIZE, end );
  2997                     	JMP_TARGET(doublesize);
  2998                     	load_xf_bank( R_EDX );
  2999                     	load_fr( R_EDX, R_EAX, FRm&0x0E );
  3000                     	load_fr( R_EDX, R_EDX, FRm|0x01 );
  3001                     	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
  3002                     	JMP_TARGET(end);
  3003                         } else {
  3004                     	JMP_rel8( 9 + MEM_WRITE_DOUBLE_SIZE, end );
  3005                     	JMP_TARGET(doublesize);
  3006                     	load_fr_bank( R_EDX );
  3007                     	load_fr( R_EDX, R_EAX, FRm&0x0E );
  3008                     	load_fr( R_EDX, R_EDX, FRm|0x01 );
  3009                     	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
  3010                     	JMP_TARGET(end);
  3012                         sh4_x86.tstate = TSTATE_NONE;
  3014                         break;
  3015                     case 0xB:
  3016                         { /* FMOV FRm, @-Rn */
  3017                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  3018                         precheck();
  3019                         check_fpuen_no_precheck();
  3020                         load_reg( R_ECX, Rn );
  3021                         check_walign32( R_ECX );
  3022                         load_spreg( R_EDX, R_FPSCR );
  3023                         TEST_imm32_r32( FPSCR_SZ, R_EDX );
  3024                         JNE_rel8(14 + CALL_FUNC2_SIZE, doublesize);
  3025                         load_fr_bank( R_EDX );
  3026                         load_fr( R_EDX, R_EAX, FRm );
  3027                         ADD_imm8s_r32(-4,R_ECX);
  3028                         store_reg( R_ECX, Rn );
  3029                         MEM_WRITE_LONG( R_ECX, R_EAX ); // 12
  3030                         if( FRm&1 ) {
  3031                     	JMP_rel8( 24 + MEM_WRITE_DOUBLE_SIZE, end );
  3032                     	JMP_TARGET(doublesize);
  3033                     	load_xf_bank( R_EDX );
  3034                     	load_fr( R_EDX, R_EAX, FRm&0x0E );
  3035                     	load_fr( R_EDX, R_EDX, FRm|0x01 );
  3036                     	ADD_imm8s_r32(-8,R_ECX);
  3037                     	store_reg( R_ECX, Rn );
  3038                     	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
  3039                     	JMP_TARGET(end);
  3040                         } else {
  3041                     	JMP_rel8( 15 + MEM_WRITE_DOUBLE_SIZE, end );
  3042                     	JMP_TARGET(doublesize);
  3043                     	load_fr_bank( R_EDX );
  3044                     	load_fr( R_EDX, R_EAX, FRm&0x0E );
  3045                     	load_fr( R_EDX, R_EDX, FRm|0x01 );
  3046                     	ADD_imm8s_r32(-8,R_ECX);
  3047                     	store_reg( R_ECX, Rn );
  3048                     	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
  3049                     	JMP_TARGET(end);
  3051                         sh4_x86.tstate = TSTATE_NONE;
  3053                         break;
  3054                     case 0xC:
  3055                         { /* FMOV FRm, FRn */
  3056                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  3057                         /* As horrible as this looks, it's actually covering 5 separate cases:
  3058                          * 1. 32-bit fr-to-fr (PR=0)
  3059                          * 2. 64-bit dr-to-dr (PR=1, FRm&1 == 0, FRn&1 == 0 )
  3060                          * 3. 64-bit dr-to-xd (PR=1, FRm&1 == 0, FRn&1 == 1 )
  3061                          * 4. 64-bit xd-to-dr (PR=1, FRm&1 == 1, FRn&1 == 0 )
  3062                          * 5. 64-bit xd-to-xd (PR=1, FRm&1 == 1, FRn&1 == 1 )
  3063                          */
  3064                         check_fpuen();
  3065                         load_spreg( R_ECX, R_FPSCR );
  3066                         load_fr_bank( R_EDX );
  3067                         TEST_imm32_r32( FPSCR_SZ, R_ECX );
  3068                         JNE_rel8(8, doublesize);
  3069                         load_fr( R_EDX, R_EAX, FRm ); // PR=0 branch
  3070                         store_fr( R_EDX, R_EAX, FRn );
  3071                         if( FRm&1 ) {
  3072                     	JMP_rel8(24, end);
  3073                     	JMP_TARGET(doublesize);
  3074                     	load_xf_bank( R_ECX ); 
  3075                     	load_fr( R_ECX, R_EAX, FRm-1 );
  3076                     	if( FRn&1 ) {
  3077                     	    load_fr( R_ECX, R_EDX, FRm );
  3078                     	    store_fr( R_ECX, R_EAX, FRn-1 );
  3079                     	    store_fr( R_ECX, R_EDX, FRn );
  3080                     	} else /* FRn&1 == 0 */ {
  3081                     	    load_fr( R_ECX, R_ECX, FRm );
  3082                     	    store_fr( R_EDX, R_EAX, FRn );
  3083                     	    store_fr( R_EDX, R_ECX, FRn+1 );
  3085                     	JMP_TARGET(end);
  3086                         } else /* FRm&1 == 0 */ {
  3087                     	if( FRn&1 ) {
  3088                     	    JMP_rel8(24, end);
  3089                     	    load_xf_bank( R_ECX );
  3090                     	    load_fr( R_EDX, R_EAX, FRm );
  3091                     	    load_fr( R_EDX, R_EDX, FRm+1 );
  3092                     	    store_fr( R_ECX, R_EAX, FRn-1 );
  3093                     	    store_fr( R_ECX, R_EDX, FRn );
  3094                     	    JMP_TARGET(end);
  3095                     	} else /* FRn&1 == 0 */ {
  3096                     	    JMP_rel8(12, end);
  3097                     	    load_fr( R_EDX, R_EAX, FRm );
  3098                     	    load_fr( R_EDX, R_ECX, FRm+1 );
  3099                     	    store_fr( R_EDX, R_EAX, FRn );
  3100                     	    store_fr( R_EDX, R_ECX, FRn+1 );
  3101                     	    JMP_TARGET(end);
  3104                         sh4_x86.tstate = TSTATE_NONE;
  3106                         break;
  3107                     case 0xD:
  3108                         switch( (ir&0xF0) >> 4 ) {
  3109                             case 0x0:
  3110                                 { /* FSTS FPUL, FRn */
  3111                                 uint32_t FRn = ((ir>>8)&0xF); 
  3112                                 check_fpuen();
  3113                                 load_fr_bank( R_ECX );
  3114                                 load_spreg( R_EAX, R_FPUL );
  3115                                 store_fr( R_ECX, R_EAX, FRn );
  3116                                 sh4_x86.tstate = TSTATE_NONE;
  3118                                 break;
  3119                             case 0x1:
  3120                                 { /* FLDS FRm, FPUL */
  3121                                 uint32_t FRm = ((ir>>8)&0xF); 
  3122                                 check_fpuen();
  3123                                 load_fr_bank( R_ECX );
  3124                                 load_fr( R_ECX, R_EAX, FRm );
  3125                                 store_spreg( R_EAX, R_FPUL );
  3126                                 sh4_x86.tstate = TSTATE_NONE;
  3128                                 break;
  3129                             case 0x2:
  3130                                 { /* FLOAT FPUL, FRn */
  3131                                 uint32_t FRn = ((ir>>8)&0xF); 
  3132                                 check_fpuen();
  3133                                 load_spreg( R_ECX, R_FPSCR );
  3134                                 load_spreg(R_EDX, REG_OFFSET(fr_bank));
  3135                                 FILD_sh4r(R_FPUL);
  3136                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3137                                 JNE_rel8(5, doubleprec);
  3138                                 pop_fr( R_EDX, FRn );
  3139                                 JMP_rel8(3, end);
  3140                                 JMP_TARGET(doubleprec);
  3141                                 pop_dr( R_EDX, FRn );
  3142                                 JMP_TARGET(end);
  3143                                 sh4_x86.tstate = TSTATE_NONE;
  3145                                 break;
  3146                             case 0x3:
  3147                                 { /* FTRC FRm, FPUL */
  3148                                 uint32_t FRm = ((ir>>8)&0xF); 
  3149                                 check_fpuen();
  3150                                 load_spreg( R_ECX, R_FPSCR );
  3151                                 load_fr_bank( R_EDX );
  3152                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3153                                 JNE_rel8(5, doubleprec);
  3154                                 push_fr( R_EDX, FRm );
  3155                                 JMP_rel8(3, doop);
  3156                                 JMP_TARGET(doubleprec);
  3157                                 push_dr( R_EDX, FRm );
  3158                                 JMP_TARGET( doop );
  3159                                 load_imm32( R_ECX, (uint32_t)&max_int );
  3160                                 FILD_r32ind( R_ECX );
  3161                                 FCOMIP_st(1);
  3162                                 JNA_rel8( 32, sat );
  3163                                 load_imm32( R_ECX, (uint32_t)&min_int );  // 5
  3164                                 FILD_r32ind( R_ECX );           // 2
  3165                                 FCOMIP_st(1);                   // 2
  3166                                 JAE_rel8( 21, sat2 );            // 2
  3167                                 load_imm32( R_EAX, (uint32_t)&save_fcw );
  3168                                 FNSTCW_r32ind( R_EAX );
  3169                                 load_imm32( R_EDX, (uint32_t)&trunc_fcw );
  3170                                 FLDCW_r32ind( R_EDX );
  3171                                 FISTP_sh4r(R_FPUL);             // 3
  3172                                 FLDCW_r32ind( R_EAX );
  3173                                 JMP_rel8( 9, end );             // 2
  3175                                 JMP_TARGET(sat);
  3176                                 JMP_TARGET(sat2);
  3177                                 MOV_r32ind_r32( R_ECX, R_ECX ); // 2
  3178                                 store_spreg( R_ECX, R_FPUL );
  3179                                 FPOP_st();
  3180                                 JMP_TARGET(end);
  3181                                 sh4_x86.tstate = TSTATE_NONE;
  3183                                 break;
  3184                             case 0x4:
  3185                                 { /* FNEG FRn */
  3186                                 uint32_t FRn = ((ir>>8)&0xF); 
  3187                                 check_fpuen();
  3188                                 load_spreg( R_ECX, R_FPSCR );
  3189                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3190                                 load_fr_bank( R_EDX );
  3191                                 JNE_rel8(10, doubleprec);
  3192                                 push_fr(R_EDX, FRn);
  3193                                 FCHS_st0();
  3194                                 pop_fr(R_EDX, FRn);
  3195                                 JMP_rel8(8, end);
  3196                                 JMP_TARGET(doubleprec);
  3197                                 push_dr(R_EDX, FRn);
  3198                                 FCHS_st0();
  3199                                 pop_dr(R_EDX, FRn);
  3200                                 JMP_TARGET(end);
  3201                                 sh4_x86.tstate = TSTATE_NONE;
  3203                                 break;
  3204                             case 0x5:
  3205                                 { /* FABS FRn */
  3206                                 uint32_t FRn = ((ir>>8)&0xF); 
  3207                                 check_fpuen();
  3208                                 load_spreg( R_ECX, R_FPSCR );
  3209                                 load_fr_bank( R_EDX );
  3210                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3211                                 JNE_rel8(10, doubleprec);
  3212                                 push_fr(R_EDX, FRn); // 3
  3213                                 FABS_st0(); // 2
  3214                                 pop_fr( R_EDX, FRn); //3
  3215                                 JMP_rel8(8,end); // 2
  3216                                 JMP_TARGET(doubleprec);
  3217                                 push_dr(R_EDX, FRn);
  3218                                 FABS_st0();
  3219                                 pop_dr(R_EDX, FRn);
  3220                                 JMP_TARGET(end);
  3221                                 sh4_x86.tstate = TSTATE_NONE;
  3223                                 break;
  3224                             case 0x6:
  3225                                 { /* FSQRT FRn */
  3226                                 uint32_t FRn = ((ir>>8)&0xF); 
  3227                                 check_fpuen();
  3228                                 load_spreg( R_ECX, R_FPSCR );
  3229                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3230                                 load_fr_bank( R_EDX );
  3231                                 JNE_rel8(10, doubleprec);
  3232                                 push_fr(R_EDX, FRn);
  3233                                 FSQRT_st0();
  3234                                 pop_fr(R_EDX, FRn);
  3235                                 JMP_rel8(8, end);
  3236                                 JMP_TARGET(doubleprec);
  3237                                 push_dr(R_EDX, FRn);
  3238                                 FSQRT_st0();
  3239                                 pop_dr(R_EDX, FRn);
  3240                                 JMP_TARGET(end);
  3241                                 sh4_x86.tstate = TSTATE_NONE;
  3243                                 break;
  3244                             case 0x7:
  3245                                 { /* FSRRA FRn */
  3246                                 uint32_t FRn = ((ir>>8)&0xF); 
  3247                                 check_fpuen();
  3248                                 load_spreg( R_ECX, R_FPSCR );
  3249                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3250                                 load_fr_bank( R_EDX );
  3251                                 JNE_rel8(12, end); // PR=0 only
  3252                                 FLD1_st0();
  3253                                 push_fr(R_EDX, FRn);
  3254                                 FSQRT_st0();
  3255                                 FDIVP_st(1);
  3256                                 pop_fr(R_EDX, FRn);
  3257                                 JMP_TARGET(end);
  3258                                 sh4_x86.tstate = TSTATE_NONE;
  3260                                 break;
  3261                             case 0x8:
  3262                                 { /* FLDI0 FRn */
  3263                                 uint32_t FRn = ((ir>>8)&0xF); 
  3264                                 /* IFF PR=0 */
  3265                                   check_fpuen();
  3266                                   load_spreg( R_ECX, R_FPSCR );
  3267                                   TEST_imm32_r32( FPSCR_PR, R_ECX );
  3268                                   JNE_rel8(8, end);
  3269                                   XOR_r32_r32( R_EAX, R_EAX );
  3270                                   load_spreg( R_ECX, REG_OFFSET(fr_bank) );
  3271                                   store_fr( R_ECX, R_EAX, FRn );
  3272                                   JMP_TARGET(end);
  3273                                   sh4_x86.tstate = TSTATE_NONE;
  3275                                 break;
  3276                             case 0x9:
  3277                                 { /* FLDI1 FRn */
  3278                                 uint32_t FRn = ((ir>>8)&0xF); 
  3279                                 /* IFF PR=0 */
  3280                                   check_fpuen();
  3281                                   load_spreg( R_ECX, R_FPSCR );
  3282                                   TEST_imm32_r32( FPSCR_PR, R_ECX );
  3283                                   JNE_rel8(11, end);
  3284                                   load_imm32(R_EAX, 0x3F800000);
  3285                                   load_spreg( R_ECX, REG_OFFSET(fr_bank) );
  3286                                   store_fr( R_ECX, R_EAX, FRn );
  3287                                   JMP_TARGET(end);
  3288                                   sh4_x86.tstate = TSTATE_NONE;
  3290                                 break;
  3291                             case 0xA:
  3292                                 { /* FCNVSD FPUL, FRn */
  3293                                 uint32_t FRn = ((ir>>8)&0xF); 
  3294                                 check_fpuen();
  3295                                 load_spreg( R_ECX, R_FPSCR );
  3296                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3297                                 JE_rel8(9, end); // only when PR=1
  3298                                 load_fr_bank( R_ECX );
  3299                                 push_fpul();
  3300                                 pop_dr( R_ECX, FRn );
  3301                                 JMP_TARGET(end);
  3302                                 sh4_x86.tstate = TSTATE_NONE;
  3304                                 break;
  3305                             case 0xB:
  3306                                 { /* FCNVDS FRm, FPUL */
  3307                                 uint32_t FRm = ((ir>>8)&0xF); 
  3308                                 check_fpuen();
  3309                                 load_spreg( R_ECX, R_FPSCR );
  3310                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3311                                 JE_rel8(9, end); // only when PR=1
  3312                                 load_fr_bank( R_ECX );
  3313                                 push_dr( R_ECX, FRm );
  3314                                 pop_fpul();
  3315                                 JMP_TARGET(end);
  3316                                 sh4_x86.tstate = TSTATE_NONE;
  3318                                 break;
  3319                             case 0xE:
  3320                                 { /* FIPR FVm, FVn */
  3321                                 uint32_t FVn = ((ir>>10)&0x3); uint32_t FVm = ((ir>>8)&0x3); 
  3322                                 check_fpuen();
  3323                                 load_spreg( R_ECX, R_FPSCR );
  3324                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3325                                 JNE_rel8(44, doubleprec);
  3327                                 load_fr_bank( R_ECX );
  3328                                 push_fr( R_ECX, FVm<<2 );
  3329                                 push_fr( R_ECX, FVn<<2 );
  3330                                 FMULP_st(1);
  3331                                 push_fr( R_ECX, (FVm<<2)+1);
  3332                                 push_fr( R_ECX, (FVn<<2)+1);
  3333                                 FMULP_st(1);
  3334                                 FADDP_st(1);
  3335                                 push_fr( R_ECX, (FVm<<2)+2);
  3336                                 push_fr( R_ECX, (FVn<<2)+2);
  3337                                 FMULP_st(1);
  3338                                 FADDP_st(1);
  3339                                 push_fr( R_ECX, (FVm<<2)+3);
  3340                                 push_fr( R_ECX, (FVn<<2)+3);
  3341                                 FMULP_st(1);
  3342                                 FADDP_st(1);
  3343                                 pop_fr( R_ECX, (FVn<<2)+3);
  3344                                 JMP_TARGET(doubleprec);
  3345                                 sh4_x86.tstate = TSTATE_NONE;
  3347                                 break;
  3348                             case 0xF:
  3349                                 switch( (ir&0x100) >> 8 ) {
  3350                                     case 0x0:
  3351                                         { /* FSCA FPUL, FRn */
  3352                                         uint32_t FRn = ((ir>>9)&0x7)<<1; 
  3353                                         check_fpuen();
  3354                                         load_spreg( R_ECX, R_FPSCR );
  3355                                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  3356                                         JNE_rel8( CALL_FUNC2_SIZE + 9, doubleprec );
  3357                                         load_fr_bank( R_ECX );
  3358                                         ADD_imm8s_r32( (FRn&0x0E)<<2, R_ECX );
  3359                                         load_spreg( R_EDX, R_FPUL );
  3360                                         call_func2( sh4_fsca, R_EDX, R_ECX );
  3361                                         JMP_TARGET(doubleprec);
  3362                                         sh4_x86.tstate = TSTATE_NONE;
  3364                                         break;
  3365                                     case 0x1:
  3366                                         switch( (ir&0x200) >> 9 ) {
  3367                                             case 0x0:
  3368                                                 { /* FTRV XMTRX, FVn */
  3369                                                 uint32_t FVn = ((ir>>10)&0x3); 
  3370                                                 check_fpuen();
  3371                                                 load_spreg( R_ECX, R_FPSCR );
  3372                                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3373                                                 JNE_rel8( 18 + CALL_FUNC2_SIZE, doubleprec );
  3374                                                 load_fr_bank( R_EDX );                 // 3
  3375                                                 ADD_imm8s_r32( FVn<<4, R_EDX );        // 3
  3376                                                 load_xf_bank( R_ECX );                 // 12
  3377                                                 call_func2( sh4_ftrv, R_EDX, R_ECX );  // 12
  3378                                                 JMP_TARGET(doubleprec);
  3379                                                 sh4_x86.tstate = TSTATE_NONE;
  3381                                                 break;
  3382                                             case 0x1:
  3383                                                 switch( (ir&0xC00) >> 10 ) {
  3384                                                     case 0x0:
  3385                                                         { /* FSCHG */
  3386                                                         check_fpuen();
  3387                                                         load_spreg( R_ECX, R_FPSCR );
  3388                                                         XOR_imm32_r32( FPSCR_SZ, R_ECX );
  3389                                                         store_spreg( R_ECX, R_FPSCR );
  3390                                                         sh4_x86.tstate = TSTATE_NONE;
  3392                                                         break;
  3393                                                     case 0x2:
  3394                                                         { /* FRCHG */
  3395                                                         check_fpuen();
  3396                                                         load_spreg( R_ECX, R_FPSCR );
  3397                                                         XOR_imm32_r32( FPSCR_FR, R_ECX );
  3398                                                         store_spreg( R_ECX, R_FPSCR );
  3399                                                         update_fr_bank( R_ECX );
  3400                                                         sh4_x86.tstate = TSTATE_NONE;
  3402                                                         break;
  3403                                                     case 0x3:
  3404                                                         { /* UNDEF */
  3405                                                         if( sh4_x86.in_delay_slot ) {
  3406                                                     	SLOTILLEGAL();
  3407                                                         } else {
  3408                                                     	precheck();
  3409                                                     	JMP_exit(EXIT_ILLEGAL);
  3410                                                     	return 2;
  3413                                                         break;
  3414                                                     default:
  3415                                                         UNDEF();
  3416                                                         break;
  3418                                                 break;
  3420                                         break;
  3422                                 break;
  3423                             default:
  3424                                 UNDEF();
  3425                                 break;
  3427                         break;
  3428                     case 0xE:
  3429                         { /* FMAC FR0, FRm, FRn */
  3430                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  3431                         check_fpuen();
  3432                         load_spreg( R_ECX, R_FPSCR );
  3433                         load_spreg( R_EDX, REG_OFFSET(fr_bank));
  3434                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  3435                         JNE_rel8(18, doubleprec);
  3436                         push_fr( R_EDX, 0 );
  3437                         push_fr( R_EDX, FRm );
  3438                         FMULP_st(1);
  3439                         push_fr( R_EDX, FRn );
  3440                         FADDP_st(1);
  3441                         pop_fr( R_EDX, FRn );
  3442                         JMP_rel8(16, end);
  3443                         JMP_TARGET(doubleprec);
  3444                         push_dr( R_EDX, 0 );
  3445                         push_dr( R_EDX, FRm );
  3446                         FMULP_st(1);
  3447                         push_dr( R_EDX, FRn );
  3448                         FADDP_st(1);
  3449                         pop_dr( R_EDX, FRn );
  3450                         JMP_TARGET(end);
  3451                         sh4_x86.tstate = TSTATE_NONE;
  3453                         break;
  3454                     default:
  3455                         UNDEF();
  3456                         break;
  3458                 break;
  3461     sh4_x86.in_delay_slot = FALSE;
  3462     return 0;
.