lxdream 0.9.1| filename | src/pvr2/pvr2.c |
| changeset | 736:a02d1475ccfd |
| prev | 728:4dfc293b9d96 |
| next | 805:b355f7b3ff2e |
| author | nkeynes |
| date | Wed Jul 30 22:50:44 2008 +0000 (15 years ago) |
| permissions | -rw-r--r-- |
| last change | Bug #61: OpenBSD support (Modified) patch from bsdmaniak, thanks! |
| view | annotate | diff | log | raw |
1 /**
2 * $Id$
3 *
4 * PVR2 (Video) Core module implementation and MMIO registers.
5 *
6 * Copyright (c) 2005 Nathan Keynes.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18 #define MODULE pvr2_module
20 #include <assert.h>
21 #include "dream.h"
22 #include "eventq.h"
23 #include "display.h"
24 #include "mem.h"
25 #include "asic.h"
26 #include "clock.h"
27 #include "pvr2/pvr2.h"
28 #include "pvr2/pvr2mmio.h"
29 #include "pvr2/scene.h"
30 #include "sh4/sh4.h"
31 #define MMIO_IMPL
32 #include "pvr2/pvr2mmio.h"
34 unsigned char *video_base;
36 #define MAX_RENDER_BUFFERS 4
38 #define HPOS_PER_FRAME 0
39 #define HPOS_PER_LINECOUNT 1
41 static void pvr2_init( void );
42 static void pvr2_reset( void );
43 static uint32_t pvr2_run_slice( uint32_t );
44 static void pvr2_save_state( FILE *f );
45 static int pvr2_load_state( FILE *f );
46 static void pvr2_update_raster_posn( uint32_t nanosecs );
47 static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int line_time_ns );
48 static render_buffer_t pvr2_get_render_buffer( frame_buffer_t frame );
49 static render_buffer_t pvr2_next_render_buffer( );
50 static render_buffer_t pvr2_frame_buffer_to_render_buffer( frame_buffer_t frame );
51 uint32_t pvr2_get_sync_status();
53 void pvr2_display_frame( void );
55 static int output_colour_formats[] = { COLFMT_BGRA1555, COLFMT_RGB565, COLFMT_BGR888, COLFMT_BGRA8888 };
57 struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, pvr2_reset, NULL,
58 pvr2_run_slice, NULL,
59 pvr2_save_state, pvr2_load_state };
62 display_driver_t display_driver = NULL;
64 struct pvr2_state {
65 uint32_t frame_count;
66 uint32_t line_count;
67 uint32_t line_remainder;
68 uint32_t cycles_run; /* Cycles already executed prior to main time slice */
69 uint32_t irq_hpos_line;
70 uint32_t irq_hpos_line_count;
71 uint32_t irq_hpos_mode;
72 uint32_t irq_hpos_time_ns; /* Time within the line */
73 uint32_t irq_vpos1;
74 uint32_t irq_vpos2;
75 uint32_t odd_even_field; /* 1 = odd, 0 = even */
76 int32_t palette_changed; /* TRUE if palette has changed since last render */
77 uint32_t padding; /* FIXME: Remove in next DST version */
78 /* timing */
79 uint32_t dot_clock;
80 uint32_t total_lines;
81 uint32_t line_size;
82 uint32_t line_time_ns;
83 uint32_t vsync_lines;
84 uint32_t hsync_width_ns;
85 uint32_t front_porch_ns;
86 uint32_t back_porch_ns;
87 uint32_t retrace_start_line;
88 uint32_t retrace_end_line;
89 int32_t interlaced;
90 } pvr2_state;
92 static gchar *save_next_render_filename;
93 static render_buffer_t render_buffers[MAX_RENDER_BUFFERS];
94 static uint32_t render_buffer_count = 0;
95 static render_buffer_t displayed_render_buffer = NULL;
96 static uint32_t displayed_border_colour = 0;
98 /**
99 * Event handler for the hpos callback
100 */
101 static void pvr2_hpos_callback( int eventid ) {
102 asic_event( eventid );
103 pvr2_update_raster_posn(sh4r.slice_cycle);
104 if( pvr2_state.irq_hpos_mode == HPOS_PER_LINECOUNT ) {
105 pvr2_state.irq_hpos_line += pvr2_state.irq_hpos_line_count;
106 while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {
107 pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);
108 }
109 }
110 pvr2_schedule_scanline_event( eventid, pvr2_state.irq_hpos_line, 1,
111 pvr2_state.irq_hpos_time_ns );
112 }
114 /**
115 * Event handler for the scanline callbacks. Fires the corresponding
116 * ASIC event, and resets the timer for the next field.
117 */
118 static void pvr2_scanline_callback( int eventid ) {
119 asic_event( eventid );
120 pvr2_update_raster_posn(sh4r.slice_cycle);
121 if( eventid == EVENT_SCANLINE1 ) {
122 pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos1, 1, 0 );
123 } else {
124 pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos2, 1, 0 );
125 }
126 }
128 static void pvr2_init( void )
129 {
130 int i;
131 register_io_region( &mmio_region_PVR2 );
132 register_io_region( &mmio_region_PVR2PAL );
133 register_io_region( &mmio_region_PVR2TA );
134 register_event_callback( EVENT_HPOS, pvr2_hpos_callback );
135 register_event_callback( EVENT_SCANLINE1, pvr2_scanline_callback );
136 register_event_callback( EVENT_SCANLINE2, pvr2_scanline_callback );
137 video_base = mem_get_region_by_name( MEM_REGION_VIDEO );
138 texcache_init();
139 pvr2_reset();
140 pvr2_ta_reset();
141 save_next_render_filename = NULL;
142 for( i=0; i<MAX_RENDER_BUFFERS; i++ ) {
143 render_buffers[i] = NULL;
144 }
145 render_buffer_count = 0;
146 displayed_render_buffer = NULL;
147 displayed_border_colour = 0;
148 }
150 static void pvr2_reset( void )
151 {
152 int i;
153 pvr2_state.line_count = 0;
154 pvr2_state.line_remainder = 0;
155 pvr2_state.cycles_run = 0;
156 pvr2_state.irq_vpos1 = 0;
157 pvr2_state.irq_vpos2 = 0;
158 pvr2_state.dot_clock = PVR2_DOT_CLOCK;
159 pvr2_state.back_porch_ns = 4000;
160 pvr2_state.palette_changed = FALSE;
161 mmio_region_PVR2_write( DISP_TOTAL, 0x0270035F );
162 mmio_region_PVR2_write( DISP_SYNCTIME, 0x07D6A53F );
163 mmio_region_PVR2_write( YUV_ADDR, 0 );
164 mmio_region_PVR2_write( YUV_CFG, 0 );
166 pvr2_ta_init();
167 texcache_flush();
168 if( display_driver ) {
169 display_driver->display_blank(0);
170 for( i=0; i<render_buffer_count; i++ ) {
171 display_driver->destroy_render_buffer(render_buffers[i]);
172 render_buffers[i] = NULL;
173 }
174 render_buffer_count = 0;
175 }
176 }
178 void pvr2_save_render_buffer( FILE *f, render_buffer_t buffer )
179 {
180 struct frame_buffer fbuf;
182 fbuf.width = buffer->width;
183 fbuf.height = buffer->height;
184 fbuf.rowstride = fbuf.width*3;
185 fbuf.colour_format = COLFMT_BGR888;
186 fbuf.inverted = buffer->inverted;
187 fbuf.data = g_malloc0( buffer->width * buffer->height * 3 );
189 display_driver->read_render_buffer( fbuf.data, buffer, fbuf.rowstride, COLFMT_BGR888 );
190 write_png_to_stream( f, &fbuf );
191 g_free( fbuf.data );
193 fwrite( &buffer->rowstride, sizeof(buffer->rowstride), 1, f );
194 fwrite( &buffer->colour_format, sizeof(buffer->colour_format), 1, f );
195 fwrite( &buffer->address, sizeof(buffer->address), 1, f );
196 fwrite( &buffer->scale, sizeof(buffer->scale), 1, f );
197 int32_t flushed = (int32_t)buffer->flushed; // Force to 32-bits for save-file consistency
198 fwrite( &flushed, sizeof(flushed), 1, f );
200 }
202 render_buffer_t pvr2_load_render_buffer( FILE *f )
203 {
204 frame_buffer_t frame = read_png_from_stream( f );
205 if( frame == NULL ) {
206 return NULL;
207 }
209 render_buffer_t buffer = pvr2_frame_buffer_to_render_buffer(frame);
210 if( buffer != NULL ) {
211 int32_t flushed;
212 fread( &buffer->rowstride, sizeof(buffer->rowstride), 1, f );
213 fread( &buffer->colour_format, sizeof(buffer->colour_format), 1, f );
214 fread( &buffer->address, sizeof(buffer->address), 1, f );
215 fread( &buffer->scale, sizeof(buffer->scale), 1, f );
216 fread( &flushed, sizeof(flushed), 1, f );
217 buffer->flushed = (gboolean)flushed;
218 } else {
219 fseek( f, sizeof(buffer->rowstride)+sizeof(buffer->colour_format)+
220 sizeof(buffer->address)+sizeof(buffer->scale)+
221 sizeof(int32_t), SEEK_CUR );
222 }
223 return buffer;
224 }
229 void pvr2_save_render_buffers( FILE *f )
230 {
231 int i;
232 uint32_t has_frontbuffer;
233 fwrite( &render_buffer_count, sizeof(render_buffer_count), 1, f );
234 if( displayed_render_buffer != NULL ) {
235 has_frontbuffer = 1;
236 fwrite( &has_frontbuffer, sizeof(has_frontbuffer), 1, f );
237 pvr2_save_render_buffer( f, displayed_render_buffer );
238 } else {
239 has_frontbuffer = 0;
240 fwrite( &has_frontbuffer, sizeof(has_frontbuffer), 1, f );
241 }
243 for( i=0; i<render_buffer_count; i++ ) {
244 if( render_buffers[i] != displayed_render_buffer && render_buffers[i] != NULL ) {
245 pvr2_save_render_buffer( f, render_buffers[i] );
246 }
247 }
248 }
250 gboolean pvr2_load_render_buffers( FILE *f )
251 {
252 uint32_t count, has_frontbuffer;
253 int i;
255 fread( &count, sizeof(count), 1, f );
256 if( count > MAX_RENDER_BUFFERS ) {
257 return FALSE;
258 }
259 fread( &has_frontbuffer, sizeof(has_frontbuffer), 1, f );
260 for( i=0; i<render_buffer_count; i++ ) {
261 display_driver->destroy_render_buffer(render_buffers[i]);
262 render_buffers[i] = NULL;
263 }
264 render_buffer_count = 0;
266 if( has_frontbuffer ) {
267 displayed_render_buffer = pvr2_load_render_buffer(f);
268 display_driver->display_render_buffer( displayed_render_buffer );
269 count--;
270 }
272 for( i=0; i<count; i++ ) {
273 pvr2_load_render_buffer( f );
274 }
275 return TRUE;
276 }
279 static void pvr2_save_state( FILE *f )
280 {
281 pvr2_save_render_buffers( f );
282 fwrite( &pvr2_state, sizeof(pvr2_state), 1, f );
283 pvr2_ta_save_state( f );
284 pvr2_yuv_save_state( f );
285 }
287 static int pvr2_load_state( FILE *f )
288 {
289 if( !pvr2_load_render_buffers(f) )
290 return 1;
291 if( fread( &pvr2_state, sizeof(pvr2_state), 1, f ) != 1 )
292 return 1;
293 if( pvr2_ta_load_state(f) ) {
294 return 1;
295 }
296 return pvr2_yuv_load_state(f);
297 }
299 /**
300 * Update the current raster position to the given number of nanoseconds,
301 * relative to the last time slice. (ie the raster will be adjusted forward
302 * by nanosecs - nanosecs_already_run_this_timeslice)
303 */
304 static void pvr2_update_raster_posn( uint32_t nanosecs )
305 {
306 uint32_t old_line_count = pvr2_state.line_count;
307 if( pvr2_state.line_time_ns == 0 ) {
308 return; /* do nothing */
309 }
310 pvr2_state.line_remainder += (nanosecs - pvr2_state.cycles_run);
311 pvr2_state.cycles_run = nanosecs;
312 while( pvr2_state.line_remainder >= pvr2_state.line_time_ns ) {
313 pvr2_state.line_count ++;
314 pvr2_state.line_remainder -= pvr2_state.line_time_ns;
315 }
317 if( pvr2_state.line_count >= pvr2_state.total_lines ) {
318 pvr2_state.line_count -= pvr2_state.total_lines;
319 if( pvr2_state.interlaced ) {
320 pvr2_state.odd_even_field = !pvr2_state.odd_even_field;
321 }
322 }
323 if( pvr2_state.line_count >= pvr2_state.retrace_end_line &&
324 (old_line_count < pvr2_state.retrace_end_line ||
325 old_line_count > pvr2_state.line_count) ) {
326 pvr2_state.frame_count++;
327 pvr2_display_frame();
328 }
329 }
331 static uint32_t pvr2_run_slice( uint32_t nanosecs )
332 {
333 pvr2_update_raster_posn( nanosecs );
334 pvr2_state.cycles_run = 0;
335 return nanosecs;
336 }
338 int pvr2_get_frame_count()
339 {
340 return pvr2_state.frame_count;
341 }
343 void pvr2_redraw_display()
344 {
345 if( display_driver != NULL ) {
346 if( displayed_render_buffer == NULL ) {
347 display_driver->display_blank(displayed_border_colour);
348 } else {
349 display_driver->display_render_buffer(displayed_render_buffer);
350 }
351 }
352 }
354 gboolean pvr2_save_next_scene( const gchar *filename )
355 {
356 if( save_next_render_filename != NULL ) {
357 g_free( save_next_render_filename );
358 }
359 save_next_render_filename = g_strdup(filename);
360 return TRUE;
361 }
365 /**
366 * Display the next frame, copying the current contents of video ram to
367 * the window. If the video configuration has changed, first recompute the
368 * new frame size/depth.
369 */
370 void pvr2_display_frame( void )
371 {
372 int dispmode = MMIO_READ( PVR2, DISP_MODE );
373 int vidcfg = MMIO_READ( PVR2, DISP_SYNCCFG );
374 gboolean bEnabled = (dispmode & DISPMODE_ENABLE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE;
376 if( display_driver == NULL ) {
377 return; /* can't really do anything much */
378 } else if( !bEnabled ) {
379 /* Output disabled == black */
380 displayed_render_buffer = NULL;
381 displayed_border_colour = 0;
382 display_driver->display_blank( 0 );
383 } else if( MMIO_READ( PVR2, DISP_CFG2 ) & 0x08 ) {
384 /* Enabled but blanked - border colour */
385 displayed_border_colour = MMIO_READ( PVR2, DISP_BORDER );
386 displayed_render_buffer = NULL;
387 display_driver->display_blank( displayed_border_colour );
388 } else {
389 /* Real output - determine dimensions etc */
390 struct frame_buffer fbuf;
391 uint32_t dispsize = MMIO_READ( PVR2, DISP_SIZE );
392 int vid_stride = (((dispsize & DISPSIZE_MODULO) >> 20) - 1);
393 int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
395 fbuf.colour_format = output_colour_formats[(dispmode & DISPMODE_COLFMT) >> 2];
396 fbuf.width = vid_ppl << 2 / colour_formats[fbuf.colour_format].bpp;
397 fbuf.height = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
398 fbuf.size = vid_ppl << 2 * fbuf.height;
399 fbuf.rowstride = (vid_ppl + vid_stride) << 2;
401 /* Determine the field to display, and deinterlace if possible */
402 if( pvr2_state.interlaced ) {
403 if( vid_ppl == vid_stride ) { /* Magic deinterlace */
404 fbuf.height = fbuf.height << 1;
405 fbuf.rowstride = vid_ppl << 2;
406 fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
407 } else {
408 /* Just display the field as is, folks. This is slightly tricky -
409 * we pick the field based on which frame is about to come through,
410 * which may not be the same as the odd_even_field.
411 */
412 gboolean oddfield = pvr2_state.odd_even_field;
413 if( pvr2_state.line_count >= pvr2_state.retrace_start_line ) {
414 oddfield = !oddfield;
415 }
416 if( oddfield ) {
417 fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
418 } else {
419 fbuf.address = MMIO_READ( PVR2, DISP_ADDR2 );
420 }
421 }
422 } else {
423 fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
424 }
425 fbuf.address = (fbuf.address & 0x00FFFFFF) + PVR2_RAM_BASE;
426 fbuf.inverted = FALSE;
427 fbuf.data = video_base + (fbuf.address&0x00FFFFFF);
429 render_buffer_t rbuf = pvr2_get_render_buffer( &fbuf );
430 if( rbuf == NULL ) {
431 rbuf = pvr2_frame_buffer_to_render_buffer( &fbuf );
432 }
433 displayed_render_buffer = rbuf;
434 if( rbuf != NULL ) {
435 display_driver->display_render_buffer( rbuf );
436 }
437 }
438 }
440 /**
441 * This has to handle every single register individually as they all get masked
442 * off differently (and its easier to do it at write time)
443 */
444 void mmio_region_PVR2_write( uint32_t reg, uint32_t val )
445 {
446 if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
447 MMIO_WRITE( PVR2, reg, val );
448 return;
449 }
451 switch(reg) {
452 case PVRID:
453 case PVRVER:
454 case GUNPOS: /* Read only registers */
455 break;
456 case PVRRESET:
457 val &= 0x00000007; /* Do stuff? */
458 MMIO_WRITE( PVR2, reg, val );
459 break;
460 case RENDER_START: /* Don't really care what value */
461 if( save_next_render_filename != NULL ) {
462 if( pvr2_render_save_scene(save_next_render_filename) == 0 ) {
463 INFO( "Saved scene to %s", save_next_render_filename);
464 }
465 g_free( save_next_render_filename );
466 save_next_render_filename = NULL;
467 }
468 pvr2_scene_read();
469 render_buffer_t buffer = pvr2_next_render_buffer();
470 if( buffer != NULL ) {
471 pvr2_scene_render( buffer );
472 }
473 asic_event( EVENT_PVR_RENDER_DONE );
474 break;
475 case RENDER_POLYBASE:
476 MMIO_WRITE( PVR2, reg, val&0x00F00000 );
477 break;
478 case RENDER_TSPCFG:
479 MMIO_WRITE( PVR2, reg, val&0x00010101 );
480 break;
481 case DISP_BORDER:
482 MMIO_WRITE( PVR2, reg, val&0x01FFFFFF );
483 break;
484 case DISP_MODE:
485 MMIO_WRITE( PVR2, reg, val&0x00FFFF7F );
486 break;
487 case RENDER_MODE:
488 MMIO_WRITE( PVR2, reg, val&0x00FFFF0F );
489 break;
490 case RENDER_SIZE:
491 MMIO_WRITE( PVR2, reg, val&0x000001FF );
492 break;
493 case DISP_ADDR1:
494 val &= 0x00FFFFFC;
495 MMIO_WRITE( PVR2, reg, val );
496 pvr2_update_raster_posn(sh4r.slice_cycle);
497 break;
498 case DISP_ADDR2:
499 MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
500 pvr2_update_raster_posn(sh4r.slice_cycle);
501 break;
502 case DISP_SIZE:
503 MMIO_WRITE( PVR2, reg, val&0x3FFFFFFF );
504 break;
505 case RENDER_ADDR1:
506 case RENDER_ADDR2:
507 MMIO_WRITE( PVR2, reg, val&0x01FFFFFC );
508 break;
509 case RENDER_HCLIP:
510 MMIO_WRITE( PVR2, reg, val&0x07FF07FF );
511 break;
512 case RENDER_VCLIP:
513 MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
514 break;
515 case DISP_HPOSIRQ:
516 MMIO_WRITE( PVR2, reg, val&0x03FF33FF );
517 pvr2_state.irq_hpos_line = val & 0x03FF;
518 pvr2_state.irq_hpos_time_ns = 2000000*((val>>16)&0x03FF)/pvr2_state.dot_clock;
519 pvr2_state.irq_hpos_mode = (val >> 12) & 0x03;
520 switch( pvr2_state.irq_hpos_mode ) {
521 case 3: /* Reserved - treat as 0 */
522 case 0: /* Once per frame at specified line */
523 pvr2_state.irq_hpos_mode = HPOS_PER_FRAME;
524 break;
525 case 2: /* Once per line - as per-line-count */
526 pvr2_state.irq_hpos_line = 1;
527 pvr2_state.irq_hpos_mode = 1;
528 case 1: /* Once per N lines */
529 pvr2_state.irq_hpos_line_count = pvr2_state.irq_hpos_line;
530 pvr2_state.irq_hpos_line = (pvr2_state.line_count >> 1) +
531 pvr2_state.irq_hpos_line_count;
532 while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {
533 pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);
534 }
535 pvr2_state.irq_hpos_mode = HPOS_PER_LINECOUNT;
536 }
537 pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0,
538 pvr2_state.irq_hpos_time_ns );
539 break;
540 case DISP_VPOSIRQ:
541 val = val & 0x03FF03FF;
542 pvr2_state.irq_vpos1 = (val >> 16);
543 pvr2_state.irq_vpos2 = val & 0x03FF;
544 pvr2_update_raster_posn(sh4r.slice_cycle);
545 pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );
546 pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );
547 MMIO_WRITE( PVR2, reg, val );
548 break;
549 case RENDER_NEARCLIP:
550 MMIO_WRITE( PVR2, reg, val & 0x7FFFFFFF );
551 break;
552 case RENDER_SHADOW:
553 MMIO_WRITE( PVR2, reg, val&0x000001FF );
554 break;
555 case RENDER_OBJCFG:
556 MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
557 break;
558 case RENDER_TSPCLIP:
559 MMIO_WRITE( PVR2, reg, val&0x7FFFFFFF );
560 break;
561 case RENDER_FARCLIP:
562 MMIO_WRITE( PVR2, reg, val&0xFFFFFFF0 );
563 break;
564 case RENDER_BGPLANE:
565 MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
566 break;
567 case RENDER_ISPCFG:
568 MMIO_WRITE( PVR2, reg, val&0x00FFFFF9 );
569 break;
570 case VRAM_CFG1:
571 MMIO_WRITE( PVR2, reg, val&0x000000FF );
572 break;
573 case VRAM_CFG2:
574 MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
575 break;
576 case VRAM_CFG3:
577 MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
578 break;
579 case RENDER_FOGTBLCOL:
580 case RENDER_FOGVRTCOL:
581 MMIO_WRITE( PVR2, reg, val&0x00FFFFFF );
582 break;
583 case RENDER_FOGCOEFF:
584 MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
585 break;
586 case RENDER_CLAMPHI:
587 case RENDER_CLAMPLO:
588 MMIO_WRITE( PVR2, reg, val );
589 break;
590 case RENDER_TEXSIZE:
591 MMIO_WRITE( PVR2, reg, val&0x00031F1F );
592 break;
593 case RENDER_PALETTE:
594 MMIO_WRITE( PVR2, reg, val&0x00000003 );
595 break;
596 case RENDER_ALPHA_REF:
597 MMIO_WRITE( PVR2, reg, val&0x000000FF );
598 break;
599 /********** CRTC registers *************/
600 case DISP_HBORDER:
601 case DISP_VBORDER:
602 MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
603 break;
604 case DISP_TOTAL:
605 val = val & 0x03FF03FF;
606 MMIO_WRITE( PVR2, reg, val );
607 pvr2_update_raster_posn(sh4r.slice_cycle);
608 pvr2_state.total_lines = (val >> 16) + 1;
609 pvr2_state.line_size = (val & 0x03FF) + 1;
610 pvr2_state.line_time_ns = 1000000 * pvr2_state.line_size / pvr2_state.dot_clock;
611 pvr2_state.retrace_end_line = 0x2A;
612 pvr2_state.retrace_start_line = pvr2_state.total_lines - 6;
613 pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );
614 pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );
615 pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0,
616 pvr2_state.irq_hpos_time_ns );
617 break;
618 case DISP_SYNCCFG:
619 MMIO_WRITE( PVR2, reg, val&0x000003FF );
620 pvr2_state.interlaced = (val & 0x0010) ? TRUE : FALSE;
621 break;
622 case DISP_SYNCTIME:
623 pvr2_state.vsync_lines = (val >> 8) & 0x0F;
624 pvr2_state.hsync_width_ns = ((val & 0x7F) + 1) * 2000000 / pvr2_state.dot_clock;
625 MMIO_WRITE( PVR2, reg, val&0xFFFFFF7F );
626 break;
627 case DISP_CFG2:
628 MMIO_WRITE( PVR2, reg, val&0x003F01FF );
629 break;
630 case DISP_HPOS:
631 val = val & 0x03FF;
632 pvr2_state.front_porch_ns = (val + 1) * 1000000 / pvr2_state.dot_clock;
633 MMIO_WRITE( PVR2, reg, val );
634 break;
635 case DISP_VPOS:
636 MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
637 break;
639 /*********** Tile accelerator registers ***********/
640 case TA_POLYPOS:
641 case TA_LISTPOS:
642 /* Readonly registers */
643 break;
644 case TA_TILEBASE:
645 case TA_LISTEND:
646 case TA_LISTBASE:
647 MMIO_WRITE( PVR2, reg, val&0x00FFFFE0 );
648 break;
649 case RENDER_TILEBASE:
650 case TA_POLYBASE:
651 case TA_POLYEND:
652 MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
653 break;
654 case TA_TILESIZE:
655 MMIO_WRITE( PVR2, reg, val&0x000F003F );
656 break;
657 case TA_TILECFG:
658 MMIO_WRITE( PVR2, reg, val&0x00133333 );
659 break;
660 case TA_INIT:
661 if( val & 0x80000000 )
662 pvr2_ta_init();
663 break;
664 case TA_REINIT:
665 break;
666 /**************** Scaler registers? ****************/
667 case RENDER_SCALER:
668 MMIO_WRITE( PVR2, reg, val&0x0007FFFF );
669 break;
671 case YUV_ADDR:
672 val = val & 0x00FFFFF8;
673 MMIO_WRITE( PVR2, reg, val );
674 pvr2_yuv_init( val );
675 break;
676 case YUV_CFG:
677 MMIO_WRITE( PVR2, reg, val&0x01013F3F );
678 pvr2_yuv_set_config(val);
679 break;
681 /**************** Unknowns ***************/
682 case PVRUNK1:
683 MMIO_WRITE( PVR2, reg, val&0x000007FF );
684 break;
685 case PVRUNK2:
686 MMIO_WRITE( PVR2, reg, val&0x00000007 );
687 break;
688 case PVRUNK3:
689 MMIO_WRITE( PVR2, reg, val&0x000FFF3F );
690 break;
691 case PVRUNK5:
692 MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
693 break;
694 case PVRUNK7:
695 MMIO_WRITE( PVR2, reg, val&0x00000001 );
696 break;
697 case PVRUNK8:
698 MMIO_WRITE( PVR2, reg, val&0x0300FFFF );
699 break;
700 }
701 }
703 /**
704 * Calculate the current read value of the syncstat register, using
705 * the current SH4 clock time as an offset from the last timeslice.
706 * The register reads (LSB to MSB) as:
707 * 0..9 Current scan line
708 * 10 Odd/even field (1 = odd, 0 = even)
709 * 11 Display active (including border and overscan)
710 * 12 Horizontal sync off
711 * 13 Vertical sync off
712 * Note this method is probably incorrect for anything other than straight
713 * interlaced PAL/NTSC, and needs further testing.
714 */
715 uint32_t pvr2_get_sync_status()
716 {
717 pvr2_update_raster_posn(sh4r.slice_cycle);
718 uint32_t result = pvr2_state.line_count;
720 if( pvr2_state.odd_even_field ) {
721 result |= 0x0400;
722 }
723 if( (pvr2_state.line_count & 0x01) == pvr2_state.odd_even_field ) {
724 if( pvr2_state.line_remainder > pvr2_state.hsync_width_ns ) {
725 result |= 0x1000; /* !HSYNC */
726 }
727 if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
728 if( pvr2_state.line_remainder > pvr2_state.front_porch_ns ) {
729 result |= 0x2800; /* Display active */
730 } else {
731 result |= 0x2000; /* Front porch */
732 }
733 }
734 } else {
735 if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
736 if( pvr2_state.line_remainder < (pvr2_state.line_time_ns - pvr2_state.back_porch_ns)) {
737 result |= 0x3800; /* Display active */
738 } else {
739 result |= 0x3000;
740 }
741 } else {
742 result |= 0x1000; /* Back porch */
743 }
744 }
745 return result;
746 }
748 /**
749 * Schedule a "scanline" event. This actually goes off at
750 * 2 * line in even fields and 2 * line + 1 in odd fields.
751 * Otherwise this behaves as per pvr2_schedule_line_event().
752 * The raster position should be updated before calling this
753 * method.
754 * @param eventid Event to fire at the specified time
755 * @param line Line on which to fire the event (this is 2n/2n+1 for interlaced
756 * displays).
757 * @param hpos_ns Nanoseconds into the line at which to fire.
758 */
759 static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int hpos_ns )
760 {
761 uint32_t field = pvr2_state.odd_even_field;
762 if( line <= pvr2_state.line_count && pvr2_state.interlaced ) {
763 field = !field;
764 }
765 if( hpos_ns > pvr2_state.line_time_ns ) {
766 hpos_ns = pvr2_state.line_time_ns;
767 }
769 line <<= 1;
770 if( field ) {
771 line += 1;
772 }
774 if( line < pvr2_state.total_lines ) {
775 uint32_t lines;
776 uint32_t time;
777 if( line <= pvr2_state.line_count ) {
778 lines = (pvr2_state.total_lines - pvr2_state.line_count + line);
779 } else {
780 lines = (line - pvr2_state.line_count);
781 }
782 if( lines <= minimum_lines ) {
783 lines += pvr2_state.total_lines;
784 }
785 time = (lines * pvr2_state.line_time_ns) - pvr2_state.line_remainder + hpos_ns;
786 event_schedule( eventid, time );
787 } else {
788 event_cancel( eventid );
789 }
790 }
792 MMIO_REGION_READ_FN( PVR2, reg )
793 {
794 switch( reg ) {
795 case DISP_SYNCSTAT:
796 return pvr2_get_sync_status();
797 default:
798 return MMIO_READ( PVR2, reg );
799 }
800 }
802 MMIO_REGION_WRITE_FN( PVR2PAL, reg, val )
803 {
804 MMIO_WRITE( PVR2PAL, reg, val );
805 pvr2_state.palette_changed = TRUE;
806 }
808 void pvr2_check_palette_changed()
809 {
810 if( pvr2_state.palette_changed ) {
811 texcache_invalidate_palette();
812 pvr2_state.palette_changed = FALSE;
813 }
814 }
816 MMIO_REGION_READ_DEFFN( PVR2PAL );
818 void pvr2_set_base_address( uint32_t base )
819 {
820 mmio_region_PVR2_write( DISP_ADDR1, base );
821 }
826 int32_t mmio_region_PVR2TA_read( uint32_t reg )
827 {
828 return 0xFFFFFFFF;
829 }
831 void mmio_region_PVR2TA_write( uint32_t reg, uint32_t val )
832 {
833 pvr2_ta_write( (unsigned char *)&val, sizeof(uint32_t) );
834 }
836 /**
837 * Find the render buffer corresponding to the requested output frame
838 * (does not consider texture renders).
839 * @return the render_buffer if found, or null if no such buffer.
840 *
841 * Note: Currently does not consider "partial matches", ie partial
842 * frame overlap - it probably needs to do this.
843 */
844 render_buffer_t pvr2_get_render_buffer( frame_buffer_t frame )
845 {
846 int i;
847 for( i=0; i<render_buffer_count; i++ ) {
848 if( render_buffers[i] != NULL && render_buffers[i]->address == frame->address ) {
849 return render_buffers[i];
850 }
851 }
852 return NULL;
853 }
855 /**
856 * Allocate a render buffer with the requested parameters.
857 * The order of preference is:
858 * 1. An existing buffer with the same address. (not flushed unless the new
859 * size is smaller than the old one).
860 * 2. An existing buffer with the same size chosen by LRU order. Old buffer
861 * is flushed to vram.
862 * 3. A new buffer if one can be created.
863 * 4. The current display buff
864 * Note: The current display field(s) will never be overwritten except as a last
865 * resort.
866 */
867 render_buffer_t pvr2_alloc_render_buffer( sh4addr_t render_addr, int width, int height )
868 {
869 int i;
870 render_buffer_t result = NULL;
872 /* Check existing buffers for an available buffer */
873 for( i=0; i<render_buffer_count; i++ ) {
874 if( render_buffers[i]->width == width && render_buffers[i]->height == height ) {
875 /* needs to be the right dimensions */
876 if( render_buffers[i]->address == render_addr ) {
877 if( displayed_render_buffer == render_buffers[i] ) {
878 /* Same address, but we can't use it because the
879 * display has it. Mark it as unaddressed for later.
880 */
881 render_buffers[i]->address = -1;
882 } else {
883 /* perfect */
884 result = render_buffers[i];
885 break;
886 }
887 } else if( render_buffers[i]->address == -1 && result == NULL &&
888 displayed_render_buffer != render_buffers[i] ) {
889 result = render_buffers[i];
890 }
892 } else if( render_buffers[i]->address == render_addr ) {
893 /* right address, wrong size - if it's larger, flush it, otherwise
894 * nuke it quietly */
895 if( render_buffers[i]->width * render_buffers[i]->height >
896 width*height ) {
897 pvr2_render_buffer_copy_to_sh4( render_buffers[i] );
898 }
899 render_buffers[i]->address = -1;
900 }
901 }
903 /* Nothing available - make one */
904 if( result == NULL ) {
905 if( render_buffer_count == MAX_RENDER_BUFFERS ) {
906 /* maximum buffers reached - need to throw one away */
907 uint32_t field1_addr = MMIO_READ( PVR2, DISP_ADDR1 );
908 uint32_t field2_addr = MMIO_READ( PVR2, DISP_ADDR2 );
909 for( i=0; i<render_buffer_count; i++ ) {
910 if( render_buffers[i]->address != field1_addr &&
911 render_buffers[i]->address != field2_addr &&
912 render_buffers[i] != displayed_render_buffer ) {
913 /* Never throw away the current "front buffer(s)" */
914 result = render_buffers[i];
915 if( !result->flushed ) {
916 pvr2_render_buffer_copy_to_sh4( result );
917 }
918 if( result->width != width || result->height != height ) {
919 display_driver->destroy_render_buffer(render_buffers[i]);
920 result = display_driver->create_render_buffer(width,height);
921 render_buffers[i] = result;
922 }
923 break;
924 }
925 }
926 } else {
927 result = display_driver->create_render_buffer(width,height);
928 if( result != NULL ) {
929 render_buffers[render_buffer_count++] = result;
930 }
931 }
932 }
934 if( result != NULL ) {
935 result->address = render_addr;
936 }
937 return result;
938 }
940 /**
941 * Allocate a render buffer based on the current rendering settings
942 */
943 render_buffer_t pvr2_next_render_buffer()
944 {
945 render_buffer_t result = NULL;
946 uint32_t render_addr = MMIO_READ( PVR2, RENDER_ADDR1 );
947 uint32_t render_mode = MMIO_READ( PVR2, RENDER_MODE );
948 uint32_t render_scale = MMIO_READ( PVR2, RENDER_SCALER );
949 uint32_t render_stride = MMIO_READ( PVR2, RENDER_SIZE ) << 3;
951 if( render_addr & 0x01000000 ) { /* vram64 */
952 render_addr = (render_addr & 0x00FFFFFF) + PVR2_RAM_BASE_INT;
953 } else { /* vram32 */
954 render_addr = (render_addr & 0x00FFFFFF) + PVR2_RAM_BASE;
955 }
957 int width = pvr2_scene_buffer_width();
958 int height = pvr2_scene_buffer_height();
959 int colour_format = pvr2_render_colour_format[render_mode&0x07];
961 result = pvr2_alloc_render_buffer( render_addr, width, height );
962 /* Setup the buffer */
963 if( result != NULL ) {
964 result->rowstride = render_stride;
965 result->colour_format = colour_format;
966 result->scale = render_scale;
967 result->size = width * height * colour_formats[colour_format].bpp;
968 result->flushed = FALSE;
969 result->inverted = TRUE; // render buffers are inverted normally
970 }
971 return result;
972 }
974 static render_buffer_t pvr2_frame_buffer_to_render_buffer( frame_buffer_t frame )
975 {
976 render_buffer_t result = pvr2_alloc_render_buffer( frame->address, frame->width, frame->height );
977 if( result != NULL ) {
978 int bpp = colour_formats[frame->colour_format].bpp;
979 result->rowstride = frame->rowstride;
980 result->colour_format = frame->colour_format;
981 result->scale = 0x400;
982 result->size = frame->width * frame->height * bpp;
983 result->flushed = TRUE;
984 result->inverted = frame->inverted;
985 display_driver->load_frame_buffer( frame, result );
986 }
987 return result;
988 }
991 /**
992 * Invalidate any caching on the supplied address. Specifically, if it falls
993 * within any of the render buffers, flush the buffer back to PVR2 ram.
994 */
995 gboolean pvr2_render_buffer_invalidate( sh4addr_t address, gboolean isWrite )
996 {
997 int i;
998 address = address & 0x1FFFFFFF;
999 for( i=0; i<render_buffer_count; i++ ) {
1000 uint32_t bufaddr = render_buffers[i]->address;
1001 if( bufaddr != -1 && bufaddr <= address &&
1002 (bufaddr + render_buffers[i]->size) > address ) {
1003 if( !render_buffers[i]->flushed ) {
1004 pvr2_render_buffer_copy_to_sh4( render_buffers[i] );
1005 render_buffers[i]->flushed = TRUE;
1006 }
1007 if( isWrite ) {
1008 render_buffers[i]->address = -1; /* Invalid */
1009 }
1010 return TRUE; /* should never have overlapping buffers */
1011 }
1012 }
1013 return FALSE;
1014 }
.