lxdream.org :: lxdream/src/pvr2/pvr2.c r433:a4f61551d79d

tree revision 433:a4f61551d79d

filename	src/pvr2/pvr2.c
changeset	433:a4f61551d79d
prev	373:0ac2ac96a4c5
next	441:0ff0093f3088
author	nkeynes
date	Tue Oct 09 08:48:28 2007 +0000 (16 years ago)
permissions	-rw-r--r--
last change	Fix compilation warnings

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     1 /**

     2  * $Id: pvr2.c,v 1.46 2007-10-09 08:48:28 nkeynes Exp $

     3  *

     4  * PVR2 (Video) Core module implementation and MMIO registers.

     5  *

     6  * Copyright (c) 2005 Nathan Keynes.

     7  *

     8  * This program is free software; you can redistribute it and/or modify

     9  * it under the terms of the GNU General Public License as published by

    10  * the Free Software Foundation; either version 2 of the License, or

    11  * (at your option) any later version.

    12  *

    13  * This program is distributed in the hope that it will be useful,

    14  * but WITHOUT ANY WARRANTY; without even the implied warranty of

    15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

    16  * GNU General Public License for more details.

    17  */

    18 #define MODULE pvr2_module

    20 #include "dream.h"

    21 #include "eventq.h"

    22 #include "display.h"

    23 #include "mem.h"

    24 #include "asic.h"

    25 #include "clock.h"

    26 #include "pvr2/pvr2.h"

    27 #include "sh4/sh4core.h"

    28 #define MMIO_IMPL

    29 #include "pvr2/pvr2mmio.h"

    31 char *video_base;

    33 #define MAX_RENDER_BUFFERS 4

    35 #define HPOS_PER_FRAME 0

    36 #define HPOS_PER_LINECOUNT 1

    38 static void pvr2_init( void );

    39 static void pvr2_reset( void );

    40 static uint32_t pvr2_run_slice( uint32_t );

    41 static void pvr2_save_state( FILE *f );

    42 static int pvr2_load_state( FILE *f );

    43 static void pvr2_update_raster_posn( uint32_t nanosecs );

    44 static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int line_time_ns );

    45 static render_buffer_t pvr2_get_render_buffer( frame_buffer_t frame );

    46 static render_buffer_t pvr2_next_render_buffer( );

    47 uint32_t pvr2_get_sync_status();

    49 void pvr2_display_frame( void );

    51 static int output_colour_formats[] = { COLFMT_ARGB1555, COLFMT_RGB565, COLFMT_RGB888, COLFMT_ARGB8888 };

    53 struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, pvr2_reset, NULL,

    54 					pvr2_run_slice, NULL,

    55 					pvr2_save_state, pvr2_load_state };

    58 display_driver_t display_driver = NULL;

    60 struct pvr2_state {

    61     uint32_t frame_count;

    62     uint32_t line_count;

    63     uint32_t line_remainder;

    64     uint32_t cycles_run; /* Cycles already executed prior to main time slice */

    65     uint32_t irq_hpos_line;

    66     uint32_t irq_hpos_line_count;

    67     uint32_t irq_hpos_mode;

    68     uint32_t irq_hpos_time_ns; /* Time within the line */

    69     uint32_t irq_vpos1;

    70     uint32_t irq_vpos2;

    71     uint32_t odd_even_field; /* 1 = odd, 0 = even */

    72     gboolean palette_changed; /* TRUE if palette has changed since last render */

    73     gchar *save_next_render_filename;

    74     /* timing */

    75     uint32_t dot_clock;

    76     uint32_t total_lines;

    77     uint32_t line_size;

    78     uint32_t line_time_ns;

    79     uint32_t vsync_lines;

    80     uint32_t hsync_width_ns;

    81     uint32_t front_porch_ns;

    82     uint32_t back_porch_ns;

    83     uint32_t retrace_start_line;

    84     uint32_t retrace_end_line;

    85     gboolean interlaced;

    86 } pvr2_state;

    88 render_buffer_t render_buffers[MAX_RENDER_BUFFERS];

    89 int render_buffer_count = 0;

    91 /**

    92  * Event handler for the hpos callback

    93  */

    94 static void pvr2_hpos_callback( int eventid ) {

    95     asic_event( eventid );

    96     pvr2_update_raster_posn(sh4r.slice_cycle);

    97     if( pvr2_state.irq_hpos_mode == HPOS_PER_LINECOUNT ) {

    98 	pvr2_state.irq_hpos_line += pvr2_state.irq_hpos_line_count;

    99 	while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {

   100 	    pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);

   101 	}

   102     }

   103     pvr2_schedule_scanline_event( eventid, pvr2_state.irq_hpos_line, 1,

   104 				  pvr2_state.irq_hpos_time_ns );

   105 }

   107 /**

   108  * Event handler for the scanline callbacks. Fires the corresponding

   109  * ASIC event, and resets the timer for the next field.

   110  */

   111 static void pvr2_scanline_callback( int eventid ) {

   112     asic_event( eventid );

   113     pvr2_update_raster_posn(sh4r.slice_cycle);

   114     if( eventid == EVENT_SCANLINE1 ) {

   115 	pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos1, 1, 0 );

   116     } else {

   117 	pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos2, 1, 0 );

   118     }

   119 }

   121 static void pvr2_init( void )

   122 {

   123     int i;

   124     register_io_region( &mmio_region_PVR2 );

   125     register_io_region( &mmio_region_PVR2PAL );

   126     register_io_region( &mmio_region_PVR2TA );

   127     register_event_callback( EVENT_HPOS, pvr2_hpos_callback );

   128     register_event_callback( EVENT_SCANLINE1, pvr2_scanline_callback );

   129     register_event_callback( EVENT_SCANLINE2, pvr2_scanline_callback );

   130     video_base = mem_get_region_by_name( MEM_REGION_VIDEO );

   131     texcache_init();

   132     pvr2_reset();

   133     pvr2_ta_reset();

   134     pvr2_state.save_next_render_filename = NULL;

   135     for( i=0; i<MAX_RENDER_BUFFERS; i++ ) {

   136 	render_buffers[i] = NULL;

   137     }

   138     render_buffer_count = 0;

   139 }

   141 static void pvr2_reset( void )

   142 {

   143     pvr2_state.line_count = 0;

   144     pvr2_state.line_remainder = 0;

   145     pvr2_state.cycles_run = 0;

   146     pvr2_state.irq_vpos1 = 0;

   147     pvr2_state.irq_vpos2 = 0;

   148     pvr2_state.dot_clock = PVR2_DOT_CLOCK;

   149     pvr2_state.back_porch_ns = 4000;

   150     pvr2_state.palette_changed = FALSE;

   151     mmio_region_PVR2_write( DISP_TOTAL, 0x0270035F );

   152     mmio_region_PVR2_write( DISP_SYNCTIME, 0x07D6A53F );

   153     mmio_region_PVR2_write( YUV_ADDR, 0 );

   154     mmio_region_PVR2_write( YUV_CFG, 0 );

   156     pvr2_ta_init();

   157     texcache_flush();

   158 }

   160 static void pvr2_save_state( FILE *f )

   161 {

   162     fwrite( &pvr2_state, sizeof(pvr2_state), 1, f );

   163     pvr2_ta_save_state( f );

   164     pvr2_yuv_save_state( f );

   165 }

   167 static int pvr2_load_state( FILE *f )

   168 {

   169     if( fread( &pvr2_state, sizeof(pvr2_state), 1, f ) != 1 )

   170 	return 1;

   171     if( pvr2_ta_load_state(f) ) {

   172 	return 1;

   173     }

   174     return pvr2_yuv_load_state(f);

   175 }

   177 /**

   178  * Update the current raster position to the given number of nanoseconds,

   179  * relative to the last time slice. (ie the raster will be adjusted forward

   180  * by nanosecs - nanosecs_already_run_this_timeslice)

   181  */

   182 static void pvr2_update_raster_posn( uint32_t nanosecs )

   183 {

   184     uint32_t old_line_count = pvr2_state.line_count;

   185     if( pvr2_state.line_time_ns == 0 ) {

   186 	return; /* do nothing */

   187     }

   188     pvr2_state.line_remainder += (nanosecs - pvr2_state.cycles_run);

   189     pvr2_state.cycles_run = nanosecs;

   190     while( pvr2_state.line_remainder >= pvr2_state.line_time_ns ) {

   191 	pvr2_state.line_count ++;

   192 	pvr2_state.line_remainder -= pvr2_state.line_time_ns;

   193     }

   195     if( pvr2_state.line_count >= pvr2_state.total_lines ) {

   196 	pvr2_state.line_count -= pvr2_state.total_lines;

   197 	if( pvr2_state.interlaced ) {

   198 	    pvr2_state.odd_even_field = !pvr2_state.odd_even_field;

   199 	}

   200     }

   201     if( pvr2_state.line_count >= pvr2_state.retrace_end_line &&

   202 	(old_line_count < pvr2_state.retrace_end_line ||

   203 	 old_line_count > pvr2_state.line_count) ) {

   204 	pvr2_state.frame_count++;

   205 	pvr2_display_frame();

   206     }

   207 }

   209 static uint32_t pvr2_run_slice( uint32_t nanosecs )

   210 {

   211     pvr2_update_raster_posn( nanosecs );

   212     pvr2_state.cycles_run = 0;

   213     return nanosecs;

   214 }

   216 int pvr2_get_frame_count()

   217 {

   218     return pvr2_state.frame_count;

   219 }

   221 gboolean pvr2_save_next_scene( const gchar *filename )

   222 {

   223     if( pvr2_state.save_next_render_filename != NULL ) {

   224 	g_free( pvr2_state.save_next_render_filename );

   225     }

   226     pvr2_state.save_next_render_filename = g_strdup(filename);

   227     return TRUE;

   228 }

   232 /**

   233  * Display the next frame, copying the current contents of video ram to

   234  * the window. If the video configuration has changed, first recompute the

   235  * new frame size/depth.

   236  */

   237 void pvr2_display_frame( void )

   238 {

   239     int dispmode = MMIO_READ( PVR2, DISP_MODE );

   240     int vidcfg = MMIO_READ( PVR2, DISP_SYNCCFG );

   241     gboolean bEnabled = (dispmode & DISPMODE_ENABLE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE;

   243     if( display_driver == NULL ) {

   244 	return; /* can't really do anything much */

   245     } else if( !bEnabled ) {

   246 	/* Output disabled == black */

   247 	display_driver->display_blank( 0 );

   248     } else if( MMIO_READ( PVR2, DISP_CFG2 ) & 0x08 ) {

   249 	/* Enabled but blanked - border colour */

   250 	uint32_t colour = MMIO_READ( PVR2, DISP_BORDER );

   251 	display_driver->display_blank( colour );

   252     } else {

   253 	/* Real output - determine dimensions etc */

   254 	struct frame_buffer fbuf;

   255 	uint32_t dispsize = MMIO_READ( PVR2, DISP_SIZE );

   256 	int vid_stride = (((dispsize & DISPSIZE_MODULO) >> 20) - 1);

   257 	int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;

   259 	fbuf.colour_format = output_colour_formats[(dispmode & DISPMODE_COLFMT) >> 2];

   260 	fbuf.width = vid_ppl << 2 / colour_formats[fbuf.colour_format].bpp;

   261 	fbuf.height = ((dispsize & DISPSIZE_LPF) >> 10) + 1;

   262 	fbuf.size = vid_ppl << 2 * fbuf.height;

   263 	fbuf.rowstride = (vid_ppl + vid_stride) << 2;

   265 	/* Determine the field to display, and deinterlace if possible */

   266 	if( pvr2_state.interlaced ) {

   267 	    if( vid_ppl == vid_stride ) { /* Magic deinterlace */

   268 		fbuf.height = fbuf.height << 1;

   269 		fbuf.rowstride = vid_ppl << 2;

   270 		fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );

   271 	    } else {

   272 		/* Just display the field as is, folks. This is slightly tricky -

   273 		 * we pick the field based on which frame is about to come through,

   274 		 * which may not be the same as the odd_even_field.

   275 		 */

   276 		gboolean oddfield = pvr2_state.odd_even_field;

   277 		if( pvr2_state.line_count >= pvr2_state.retrace_start_line ) {

   278 		    oddfield = !oddfield;

   279 		}

   280 		if( oddfield ) {

   281 		    fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );

   282 		} else {

   283 		    fbuf.address = MMIO_READ( PVR2, DISP_ADDR2 );

   284 		}

   285 	    }

   286 	} else {

   287 	    fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );

   288 	}

   289 	fbuf.address = (fbuf.address & 0x00FFFFFF) + PVR2_RAM_BASE;

   291 	render_buffer_t rbuf = pvr2_get_render_buffer( &fbuf );

   292 	if( rbuf != NULL ) {

   293 	    display_driver->display_render_buffer( rbuf );

   294 	} else {

   295 	    fbuf.data = video_base + (fbuf.address&0x00FFFFFF);

   296 	    display_driver->display_frame_buffer( &fbuf );

   297 	}

   298     }

   299 }

   301 /**

   302  * This has to handle every single register individually as they all get masked

   303  * off differently (and its easier to do it at write time)

   304  */

   305 void mmio_region_PVR2_write( uint32_t reg, uint32_t val )

   306 {

   307     if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */

   308         MMIO_WRITE( PVR2, reg, val );

   309         return;

   310     }

   312     switch(reg) {

   313     case PVRID:

   314     case PVRVER:

   315     case GUNPOS: /* Read only registers */

   316 	break;

   317     case PVRRESET:

   318 	val &= 0x00000007; /* Do stuff? */

   319 	MMIO_WRITE( PVR2, reg, val );

   320 	break;

   321     case RENDER_START: /* Don't really care what value */

   322 	if( pvr2_state.save_next_render_filename != NULL ) {

   323 	    if( pvr2_render_save_scene(pvr2_state.save_next_render_filename) == 0 ) {

   324 		INFO( "Saved scene to %s", pvr2_state.save_next_render_filename);

   325 	    }

   326 	    g_free( pvr2_state.save_next_render_filename );

   327 	    pvr2_state.save_next_render_filename = NULL;

   328 	}

   329 	render_buffer_t buffer = pvr2_next_render_buffer();

   330 	if( buffer != NULL ) {

   331 	    pvr2_render_scene( buffer );

   332 	}

   333 	asic_event( EVENT_PVR_RENDER_DONE );

   334 	break;

   335     case RENDER_POLYBASE:

   336     	MMIO_WRITE( PVR2, reg, val&0x00F00000 );

   337     	break;

   338     case RENDER_TSPCFG:

   339     	MMIO_WRITE( PVR2, reg, val&0x00010101 );

   340     	break;

   341     case DISP_BORDER:

   342     	MMIO_WRITE( PVR2, reg, val&0x01FFFFFF );

   343     	break;

   344     case DISP_MODE:

   345     	MMIO_WRITE( PVR2, reg, val&0x00FFFF7F );

   346     	break;

   347     case RENDER_MODE:

   348     	MMIO_WRITE( PVR2, reg, val&0x00FFFF0F );

   349     	break;

   350     case RENDER_SIZE:

   351     	MMIO_WRITE( PVR2, reg, val&0x000001FF );

   352     	break;

   353     case DISP_ADDR1:

   354 	val &= 0x00FFFFFC;

   355 	MMIO_WRITE( PVR2, reg, val );

   356 	pvr2_update_raster_posn(sh4r.slice_cycle);

   357 	break;

   358     case DISP_ADDR2:

   359     	MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );

   360 	pvr2_update_raster_posn(sh4r.slice_cycle);

   361     	break;

   362     case DISP_SIZE:

   363     	MMIO_WRITE( PVR2, reg, val&0x3FFFFFFF );

   364     	break;

   365     case RENDER_ADDR1:

   366     case RENDER_ADDR2:

   367     	MMIO_WRITE( PVR2, reg, val&0x01FFFFFC );

   368     	break;

   369     case RENDER_HCLIP:

   370 	MMIO_WRITE( PVR2, reg, val&0x07FF07FF );

   371 	break;

   372     case RENDER_VCLIP:

   373 	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );

   374 	break;

   375     case DISP_HPOSIRQ:

   376 	MMIO_WRITE( PVR2, reg, val&0x03FF33FF );

   377 	pvr2_state.irq_hpos_line = val & 0x03FF;

   378 	pvr2_state.irq_hpos_time_ns = 2000000*((val>>16)&0x03FF)/pvr2_state.dot_clock;

   379 	pvr2_state.irq_hpos_mode = (val >> 12) & 0x03;

   380 	switch( pvr2_state.irq_hpos_mode ) {

   381 	case 3: /* Reserved - treat as 0 */

   382 	case 0: /* Once per frame at specified line */

   383 	    pvr2_state.irq_hpos_mode = HPOS_PER_FRAME;

   384 	    break;

   385 	case 2: /* Once per line - as per-line-count */

   386 	    pvr2_state.irq_hpos_line = 1;

   387 	    pvr2_state.irq_hpos_mode = 1;

   388 	case 1: /* Once per N lines */

   389 	    pvr2_state.irq_hpos_line_count = pvr2_state.irq_hpos_line;

   390 	    pvr2_state.irq_hpos_line = (pvr2_state.line_count >> 1) +

   391 		pvr2_state.irq_hpos_line_count;

   392 	    while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {

   393 		pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);

   394 	    }

   395 	    pvr2_state.irq_hpos_mode = HPOS_PER_LINECOUNT;

   396 	}

   397 	pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0,

   398 					  pvr2_state.irq_hpos_time_ns );

   399 	break;

   400     case DISP_VPOSIRQ:

   401 	val = val & 0x03FF03FF;

   402 	pvr2_state.irq_vpos1 = (val >> 16);

   403 	pvr2_state.irq_vpos2 = val & 0x03FF;

   404 	pvr2_update_raster_posn(sh4r.slice_cycle);

   405 	pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );

   406 	pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );

   407 	MMIO_WRITE( PVR2, reg, val );

   408 	break;

   409     case RENDER_NEARCLIP:

   410 	MMIO_WRITE( PVR2, reg, val & 0x7FFFFFFF );

   411 	break;

   412     case RENDER_SHADOW:

   413 	MMIO_WRITE( PVR2, reg, val&0x000001FF );

   414 	break;

   415     case RENDER_OBJCFG:

   416     	MMIO_WRITE( PVR2, reg, val&0x003FFFFF );

   417     	break;

   418     case RENDER_TSPCLIP:

   419     	MMIO_WRITE( PVR2, reg, val&0x7FFFFFFF );

   420     	break;

   421     case RENDER_FARCLIP:

   422 	MMIO_WRITE( PVR2, reg, val&0xFFFFFFF0 );

   423 	break;

   424     case RENDER_BGPLANE:

   425     	MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );

   426     	break;

   427     case RENDER_ISPCFG:

   428     	MMIO_WRITE( PVR2, reg, val&0x00FFFFF9 );

   429     	break;

   430     case VRAM_CFG1:

   431 	MMIO_WRITE( PVR2, reg, val&0x000000FF );

   432 	break;

   433     case VRAM_CFG2:

   434 	MMIO_WRITE( PVR2, reg, val&0x003FFFFF );

   435 	break;

   436     case VRAM_CFG3:

   437 	MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );

   438 	break;

   439     case RENDER_FOGTBLCOL:

   440     case RENDER_FOGVRTCOL:

   441 	MMIO_WRITE( PVR2, reg, val&0x00FFFFFF );

   442 	break;

   443     case RENDER_FOGCOEFF:

   444 	MMIO_WRITE( PVR2, reg, val&0x0000FFFF );

   445 	break;

   446     case RENDER_CLAMPHI:

   447     case RENDER_CLAMPLO:

   448 	MMIO_WRITE( PVR2, reg, val );

   449 	break;

   450     case RENDER_TEXSIZE:

   451 	MMIO_WRITE( PVR2, reg, val&0x00031F1F );

   452 	break;

   453     case RENDER_PALETTE:

   454 	MMIO_WRITE( PVR2, reg, val&0x00000003 );

   455 	break;

   457 	/********** CRTC registers *************/

   458     case DISP_HBORDER:

   459     case DISP_VBORDER:

   460 	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );

   461 	break;

   462     case DISP_TOTAL:

   463 	val = val & 0x03FF03FF;

   464 	MMIO_WRITE( PVR2, reg, val );

   465 	pvr2_update_raster_posn(sh4r.slice_cycle);

   466 	pvr2_state.total_lines = (val >> 16) + 1;

   467 	pvr2_state.line_size = (val & 0x03FF) + 1;

   468 	pvr2_state.line_time_ns = 1000000 * pvr2_state.line_size / pvr2_state.dot_clock;

   469 	pvr2_state.retrace_end_line = 0x2A;

   470 	pvr2_state.retrace_start_line = pvr2_state.total_lines - 6;

   471 	pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );

   472 	pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );

   473 	pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0,

   474 					  pvr2_state.irq_hpos_time_ns );

   475 	break;

   476     case DISP_SYNCCFG:

   477 	MMIO_WRITE( PVR2, reg, val&0x000003FF );

   478 	pvr2_state.interlaced = (val & 0x0010) ? TRUE : FALSE;

   479 	break;

   480     case DISP_SYNCTIME:

   481 	pvr2_state.vsync_lines = (val >> 8) & 0x0F;

   482 	pvr2_state.hsync_width_ns = ((val & 0x7F) + 1) * 2000000 / pvr2_state.dot_clock;

   483 	MMIO_WRITE( PVR2, reg, val&0xFFFFFF7F );

   484 	break;

   485     case DISP_CFG2:

   486 	MMIO_WRITE( PVR2, reg, val&0x003F01FF );

   487 	break;

   488     case DISP_HPOS:

   489 	val = val & 0x03FF;

   490 	pvr2_state.front_porch_ns = (val + 1) * 1000000 / pvr2_state.dot_clock;

   491 	MMIO_WRITE( PVR2, reg, val );

   492 	break;

   493     case DISP_VPOS:

   494 	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );

   495 	break;

   497 	/*********** Tile accelerator registers ***********/

   498     case TA_POLYPOS:

   499     case TA_LISTPOS:

   500 	/* Readonly registers */

   501 	break;

   502     case TA_TILEBASE:

   503     case TA_LISTEND:

   504     case TA_LISTBASE:

   505 	MMIO_WRITE( PVR2, reg, val&0x00FFFFE0 );

   506 	break;

   507     case RENDER_TILEBASE:

   508     case TA_POLYBASE:

   509     case TA_POLYEND:

   510 	MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );

   511 	break;

   512     case TA_TILESIZE:

   513 	MMIO_WRITE( PVR2, reg, val&0x000F003F );

   514 	break;

   515     case TA_TILECFG:

   516 	MMIO_WRITE( PVR2, reg, val&0x00133333 );

   517 	break;

   518     case TA_INIT:

   519 	if( val & 0x80000000 )

   520 	    pvr2_ta_init();

   521 	break;

   522     case TA_REINIT:

   523 	break;

   524 	/**************** Scaler registers? ****************/

   525     case RENDER_SCALER:

   526 	MMIO_WRITE( PVR2, reg, val&0x0007FFFF );

   527 	break;

   529     case YUV_ADDR:

   530 	val = val & 0x00FFFFF8;

   531 	MMIO_WRITE( PVR2, reg, val );

   532 	pvr2_yuv_init( val );

   533 	break;

   534     case YUV_CFG:

   535 	MMIO_WRITE( PVR2, reg, val&0x01013F3F );

   536 	pvr2_yuv_set_config(val);

   537 	break;

   539 	/**************** Unknowns ***************/

   540     case PVRUNK1:

   541     	MMIO_WRITE( PVR2, reg, val&0x000007FF );

   542     	break;

   543     case PVRUNK2:

   544 	MMIO_WRITE( PVR2, reg, val&0x00000007 );

   545 	break;

   546     case PVRUNK3:

   547 	MMIO_WRITE( PVR2, reg, val&0x000FFF3F );

   548 	break;

   549     case PVRUNK5:

   550 	MMIO_WRITE( PVR2, reg, val&0x0000FFFF );

   551 	break;

   552     case PVRUNK6:

   553 	MMIO_WRITE( PVR2, reg, val&0x000000FF );

   554 	break;

   555     case PVRUNK7:

   556 	MMIO_WRITE( PVR2, reg, val&0x00000001 );

   557 	break;

   558     }

   559 }

   561 /**

   562  * Calculate the current read value of the syncstat register, using

   563  * the current SH4 clock time as an offset from the last timeslice.

   564  * The register reads (LSB to MSB) as:

   565  *     0..9  Current scan line

   566  *     10    Odd/even field (1 = odd, 0 = even)

   567  *     11    Display active (including border and overscan)

   568  *     12    Horizontal sync off

   569  *     13    Vertical sync off

   570  * Note this method is probably incorrect for anything other than straight

   571  * interlaced PAL/NTSC, and needs further testing.

   572  */

   573 uint32_t pvr2_get_sync_status()

   574 {

   575     pvr2_update_raster_posn(sh4r.slice_cycle);

   576     uint32_t result = pvr2_state.line_count;

   578     if( pvr2_state.odd_even_field ) {

   579 	result |= 0x0400;

   580     }

   581     if( (pvr2_state.line_count & 0x01) == pvr2_state.odd_even_field ) {

   582 	if( pvr2_state.line_remainder > pvr2_state.hsync_width_ns ) {

   583 	    result |= 0x1000; /* !HSYNC */

   584 	}

   585 	if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {

   586 	    if( pvr2_state.line_remainder > pvr2_state.front_porch_ns ) {

   587 		result |= 0x2800; /* Display active */

   588 	    } else {

   589 		result |= 0x2000; /* Front porch */

   590 	    }

   591 	}

   592     } else {

   593 	if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {

   594 	    if( pvr2_state.line_remainder < (pvr2_state.line_time_ns - pvr2_state.back_porch_ns)) {

   595 		result |= 0x3800; /* Display active */

   596 	    } else {

   597 		result |= 0x3000;

   598 	    }

   599 	} else {

   600 	    result |= 0x1000; /* Back porch */

   601 	}

   602     }

   603     return result;

   604 }

   606 /**

   607  * Schedule a "scanline" event. This actually goes off at

   608  * 2 * line in even fields and 2 * line + 1 in odd fields.

   609  * Otherwise this behaves as per pvr2_schedule_line_event().

   610  * The raster position should be updated before calling this

   611  * method.

   612  * @param eventid Event to fire at the specified time

   613  * @param line Line on which to fire the event (this is 2n/2n+1 for interlaced

   614  *  displays).

   615  * @param hpos_ns Nanoseconds into the line at which to fire.

   616  */

   617 static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int hpos_ns )

   618 {

   619     uint32_t field = pvr2_state.odd_even_field;

   620     if( line <= pvr2_state.line_count && pvr2_state.interlaced ) {

   621 	field = !field;

   622     }

   623     if( hpos_ns > pvr2_state.line_time_ns ) {

   624 	hpos_ns = pvr2_state.line_time_ns;

   625     }

   627     line <<= 1;

   628     if( field ) {

   629 	line += 1;

   630     }

   632     if( line < pvr2_state.total_lines ) {

   633 	uint32_t lines;

   634 	uint32_t time;

   635 	if( line <= pvr2_state.line_count ) {

   636 	    lines = (pvr2_state.total_lines - pvr2_state.line_count + line);

   637 	} else {

   638 	    lines = (line - pvr2_state.line_count);

   639 	}

   640 	if( lines <= minimum_lines ) {

   641 	    lines += pvr2_state.total_lines;

   642 	}

   643 	time = (lines * pvr2_state.line_time_ns) - pvr2_state.line_remainder + hpos_ns;

   644 	event_schedule( eventid, time );

   645     } else {

   646 	event_cancel( eventid );

   647     }

   648 }

   650 MMIO_REGION_READ_FN( PVR2, reg )

   651 {

   652     switch( reg ) {

   653         case DISP_SYNCSTAT:

   654             return pvr2_get_sync_status();

   655         default:

   656             return MMIO_READ( PVR2, reg );

   657     }

   658 }

   660 MMIO_REGION_WRITE_FN( PVR2PAL, reg, val )

   661 {

   662     MMIO_WRITE( PVR2PAL, reg, val );

   663     pvr2_state.palette_changed = TRUE;

   664 }

   666 void pvr2_check_palette_changed()

   667 {

   668     if( pvr2_state.palette_changed ) {

   669 	texcache_invalidate_palette();

   670 	pvr2_state.palette_changed = FALSE;

   671     }

   672 }

   674 MMIO_REGION_READ_DEFFN( PVR2PAL );

   676 void pvr2_set_base_address( uint32_t base )

   677 {

   678     mmio_region_PVR2_write( DISP_ADDR1, base );

   679 }

   684 int32_t mmio_region_PVR2TA_read( uint32_t reg )

   685 {

   686     return 0xFFFFFFFF;

   687 }

   689 void mmio_region_PVR2TA_write( uint32_t reg, uint32_t val )

   690 {

   691     pvr2_ta_write( (unsigned char *)&val, sizeof(uint32_t) );

   692 }

   694 /**

   695  * Find the render buffer corresponding to the requested output frame

   696  * (does not consider texture renders).

   697  * @return the render_buffer if found, or null if no such buffer.

   698  *

   699  * Note: Currently does not consider "partial matches", ie partial

   700  * frame overlap - it probably needs to do this.

   701  */

   702 render_buffer_t pvr2_get_render_buffer( frame_buffer_t frame )

   703 {

   704     int i;

   705     for( i=0; i<render_buffer_count; i++ ) {

   706 	if( render_buffers[i] != NULL && render_buffers[i]->address == frame->address ) {

   707 	    return render_buffers[i];

   708 	}

   709     }

   710     return NULL;

   711 }

   713 /**

   714  * Determine the next render buffer to write into. The order of preference is:

   715  *   1. An existing buffer with the same address. (not flushed unless the new

   716  * size is smaller than the old one).

   717  *   2. An existing buffer with the same size chosen by LRU order. Old buffer

   718  *       is flushed to vram.

   719  *   3. A new buffer if one can be created.

   720  *   4. The current display buff

   721  * Note: The current display field(s) will never be overwritten except as a last

   722  * resort.

   723  */

   724 render_buffer_t pvr2_next_render_buffer()

   725 {

   726     render_buffer_t result = NULL;

   727     uint32_t render_addr = MMIO_READ( PVR2, RENDER_ADDR1 );

   728     uint32_t render_mode = MMIO_READ( PVR2, RENDER_MODE );

   729     uint32_t render_scale = MMIO_READ( PVR2, RENDER_SCALER );

   730     uint32_t render_stride = MMIO_READ( PVR2, RENDER_SIZE ) << 3;

   732     if( render_addr & 0x01000000 ) { /* vram64 */

   733 	render_addr = (render_addr & 0x00FFFFFF) + PVR2_RAM_BASE_INT;

   734     } else { /* vram32 */

   735 	render_addr = (render_addr & 0x00FFFFFF) + PVR2_RAM_BASE;

   736     }

   738     int width, height, i;

   739     int colour_format = pvr2_render_colour_format[render_mode&0x07];

   740     pvr2_render_getsize( &width, &height );

   742     /* Check existing buffers for an available buffer */

   743     for( i=0; i<render_buffer_count; i++ ) {

   744 	if( render_buffers[i]->width == width && render_buffers[i]->height == height ) {

   745 	    /* needs to be the right dimensions */

   746 	    if( render_buffers[i]->address == render_addr ) {

   747 		/* perfect */

   748 		result = render_buffers[i];

   749 		break;

   750 	    } else if( render_buffers[i]->address == -1 && result == NULL ) {

   751 		result = render_buffers[i];

   752 	    }

   753 	} else if( render_buffers[i]->address == render_addr ) {

   754 	    /* right address, wrong size - if it's larger, flush it, otherwise

   755 	     * nuke it quietly */

   756 	    if( render_buffers[i]->width * render_buffers[i]->height >

   757 		width*height ) {

   758 		pvr2_render_buffer_copy_to_sh4( render_buffers[i] );

   759 	    }

   760 	    render_buffers[i]->address = -1;

   761 	}

   762     }

   764     /* Nothing available - make one */

   765     if( result == NULL ) {

   766 	if( render_buffer_count == MAX_RENDER_BUFFERS ) {

   767 	    /* maximum buffers reached - need to throw one away */

   768 	    uint32_t field1_addr = MMIO_READ( PVR2, DISP_ADDR1 );

   769 	    uint32_t field2_addr = MMIO_READ( PVR2, DISP_ADDR2 );

   770 	    for( i=0; i<render_buffer_count; i++ ) {

   771 		if( render_buffers[i]->address != field1_addr &&

   772 		    render_buffers[i]->address != field2_addr ) {

   773 		    /* Never throw away the current "front buffer(s)" */

   774 		    result = render_buffers[i];

   775 		    pvr2_render_buffer_copy_to_sh4( result );

   776 		    if( result->width != width || result->height != height ) {

   777 			display_driver->destroy_render_buffer(render_buffers[i]);

   778 			result = display_driver->create_render_buffer(width,height);

   779 			render_buffers[i] = result;

   780 		    }

   781 		    break;

   782 		}

   783 	    }

   784 	} else {

   785 	    result = display_driver->create_render_buffer(width,height);

   786 	    if( result != NULL ) {

   787 		render_buffers[render_buffer_count++] = result;

   788 	    } else {

   789 		//		ERROR( "Failed to obtain a render buffer!" );

   790 		return NULL;

   791 	    }

   792 	}

   793     }

   795     /* Setup the buffer */

   796     result->rowstride = render_stride;

   797     result->colour_format = colour_format;

   798     result->scale = render_scale;

   799     result->size = width * height * colour_formats[colour_format].bpp;

   800     result->address = render_addr;

   801     result->flushed = FALSE;

   802     return result;

   803 }

   805 /**

   806  * Invalidate any caching on the supplied address. Specifically, if it falls

   807  * within any of the render buffers, flush the buffer back to PVR2 ram.

   808  */

   809 gboolean pvr2_render_buffer_invalidate( sh4addr_t address, gboolean isWrite )

   810 {

   811     int i;

   812     address = address & 0x1FFFFFFF;

   813     for( i=0; i<render_buffer_count; i++ ) {

   814 	uint32_t bufaddr = render_buffers[i]->address;

   815 	if( bufaddr != -1 && bufaddr <= address &&

   816 	    (bufaddr + render_buffers[i]->size) > address ) {

   817 	    if( !render_buffers[i]->flushed ) {

   818 		pvr2_render_buffer_copy_to_sh4( render_buffers[i] );

   819 		render_buffers[i]->flushed = TRUE;

   820 	    }

   821 	    if( isWrite ) {

   822 		render_buffers[i]->address = -1; /* Invalid */

   823 	    }

   824 	    return TRUE; /* should never have overlapping buffers */

   825 	}

   826     }

   827     return FALSE;

   828 }