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lxdream.org :: lxdream/src/sh4/sh4core.in
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4core.in
changeset 671:a530ea88eebd
prev669:ab344e42bca9
next732:f05753bbe723
author nkeynes
date Thu May 15 10:22:39 2008 +0000 (12 years ago)
permissions -rw-r--r--
last change Permanently add SH4 instruction statistics tracking (enabled with --enable-sh4stats)
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     1 /**
     2  * $Id$
     3  * 
     4  * SH4 emulation core, and parent module for all the SH4 peripheral
     5  * modules.
     6  *
     7  * Copyright (c) 2005 Nathan Keynes.
     8  *
     9  * This program is free software; you can redistribute it and/or modify
    10  * it under the terms of the GNU General Public License as published by
    11  * the Free Software Foundation; either version 2 of the License, or
    12  * (at your option) any later version.
    13  *
    14  * This program is distributed in the hope that it will be useful,
    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17  * GNU General Public License for more details.
    18  */
    20 #define MODULE sh4_module
    21 #include <assert.h>
    22 #include <math.h>
    23 #include "dream.h"
    24 #include "dreamcast.h"
    25 #include "eventq.h"
    26 #include "mem.h"
    27 #include "clock.h"
    28 #include "syscall.h"
    29 #include "sh4/sh4core.h"
    30 #include "sh4/sh4mmio.h"
    31 #include "sh4/sh4stat.h"
    32 #include "sh4/intc.h"
    34 #define SH4_CALLTRACE 1
    36 #define MAX_INT 0x7FFFFFFF
    37 #define MIN_INT 0x80000000
    38 #define MAX_INTF 2147483647.0
    39 #define MIN_INTF -2147483648.0
    41 /********************** SH4 Module Definition ****************************/
    43 uint32_t sh4_run_slice( uint32_t nanosecs ) 
    44 {
    45     int i;
    46     sh4r.slice_cycle = 0;
    48     if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
    49 	sh4_sleep_run_slice(nanosecs);
    50     }
    52     if( sh4_breakpoint_count == 0 ) {
    53 	for( ; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
    54 	    if( SH4_EVENT_PENDING() ) {
    55 		if( sh4r.event_types & PENDING_EVENT ) {
    56 		    event_execute();
    57 		}
    58 		/* Eventq execute may (quite likely) deliver an immediate IRQ */
    59 		if( sh4r.event_types & PENDING_IRQ ) {
    60 		    sh4_accept_interrupt();
    61 		}
    62 	    }
    63 	    if( !sh4_execute_instruction() ) {
    64 		break;
    65 	    }
    66 	}
    67     } else {
    68 	for( ;sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
    69 	    if( SH4_EVENT_PENDING() ) {
    70 		if( sh4r.event_types & PENDING_EVENT ) {
    71 		    event_execute();
    72 		}
    73 		/* Eventq execute may (quite likely) deliver an immediate IRQ */
    74 		if( sh4r.event_types & PENDING_IRQ ) {
    75 		    sh4_accept_interrupt();
    76 		}
    77 	    }
    79 	    if( !sh4_execute_instruction() )
    80 		break;
    81 #ifdef ENABLE_DEBUG_MODE
    82 	    for( i=0; i<sh4_breakpoint_count; i++ ) {
    83 		if( sh4_breakpoints[i].address == sh4r.pc ) {
    84 		    break;
    85 		}
    86 	    }
    87 	    if( i != sh4_breakpoint_count ) {
    88 		dreamcast_stop();
    89 		if( sh4_breakpoints[i].type == BREAK_ONESHOT )
    90 		    sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );
    91 		break;
    92 	    }
    93 #endif	
    94 	}
    95     }
    97     /* If we aborted early, but the cpu is still technically running,
    98      * we're doing a hard abort - cut the timeslice back to what we
    99      * actually executed
   100      */
   101     if( sh4r.slice_cycle != nanosecs && sh4r.sh4_state == SH4_STATE_RUNNING ) {
   102 	nanosecs = sh4r.slice_cycle;
   103     }
   104     if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
   105 	TMU_run_slice( nanosecs );
   106 	SCIF_run_slice( nanosecs );
   107     }
   108     return nanosecs;
   109 }
   111 /********************** SH4 emulation core  ****************************/
   113 #define UNDEF(ir) return sh4_raise_slot_exception(EXC_ILLEGAL, EXC_SLOT_ILLEGAL)
   114 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)
   116 #if(SH4_CALLTRACE == 1)
   117 #define MAX_CALLSTACK 32
   118 static struct call_stack {
   119     sh4addr_t call_addr;
   120     sh4addr_t target_addr;
   121     sh4addr_t stack_pointer;
   122 } call_stack[MAX_CALLSTACK];
   124 static int call_stack_depth = 0;
   125 int sh4_call_trace_on = 0;
   127 static inline void trace_call( sh4addr_t source, sh4addr_t dest ) 
   128 {
   129     if( call_stack_depth < MAX_CALLSTACK ) {
   130 	call_stack[call_stack_depth].call_addr = source;
   131 	call_stack[call_stack_depth].target_addr = dest;
   132 	call_stack[call_stack_depth].stack_pointer = sh4r.r[15];
   133     }
   134     call_stack_depth++;
   135 }
   137 static inline void trace_return( sh4addr_t source, sh4addr_t dest )
   138 {
   139     if( call_stack_depth > 0 ) {
   140 	call_stack_depth--;
   141     }
   142 }
   144 void fprint_stack_trace( FILE *f )
   145 {
   146     int i = call_stack_depth -1;
   147     if( i >= MAX_CALLSTACK )
   148 	i = MAX_CALLSTACK - 1;
   149     for( ; i >= 0; i-- ) {
   150 	fprintf( f, "%d. Call from %08X => %08X, SP=%08X\n", 
   151 		 (call_stack_depth - i), call_stack[i].call_addr,
   152 		 call_stack[i].target_addr, call_stack[i].stack_pointer );
   153     }
   154 }
   156 #define TRACE_CALL( source, dest ) trace_call(source, dest)
   157 #define TRACE_RETURN( source, dest ) trace_return(source, dest)
   158 #else
   159 #define TRACE_CALL( dest, rts ) 
   160 #define TRACE_RETURN( source, dest )
   161 #endif
   163 #define MEM_READ_BYTE( addr, val ) memtmp = mmu_vma_to_phys_read(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { val = sh4_read_byte(memtmp); }
   164 #define MEM_READ_WORD( addr, val ) memtmp = mmu_vma_to_phys_read(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { val = sh4_read_word(memtmp); }
   165 #define MEM_READ_LONG( addr, val ) memtmp = mmu_vma_to_phys_read(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { val = sh4_read_long(memtmp); }
   166 #define MEM_WRITE_BYTE( addr, val ) memtmp = mmu_vma_to_phys_write(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { sh4_write_byte(memtmp, val); }
   167 #define MEM_WRITE_WORD( addr, val ) memtmp = mmu_vma_to_phys_write(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { sh4_write_word(memtmp, val); }
   168 #define MEM_WRITE_LONG( addr, val ) memtmp = mmu_vma_to_phys_write(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { sh4_write_long(memtmp, val); }
   170 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
   172 #define MEM_FP_READ( addr, reg ) sh4_read_float( addr, reg );
   173 #define MEM_FP_WRITE( addr, reg ) sh4_write_float( addr, reg );
   175 #define CHECKPRIV() if( !IS_SH4_PRIVMODE() ) return sh4_raise_slot_exception( EXC_ILLEGAL, EXC_SLOT_ILLEGAL )
   176 #define CHECKRALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )
   177 #define CHECKRALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )
   178 #define CHECKWALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )
   179 #define CHECKWALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )
   181 #define CHECKFPUEN() if( !IS_FPU_ENABLED() ) { if( ir == 0xFFFD ) { UNDEF(ir); } else { return sh4_raise_slot_exception( EXC_FPU_DISABLED, EXC_SLOT_FPU_DISABLED ); } }
   182 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); dreamcast_stop(); return FALSE; }
   183 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) return sh4_raise_exception(EXC_SLOT_ILLEGAL)
   185 static void sh4_write_float( uint32_t addr, int reg )
   186 {
   187     if( IS_FPU_DOUBLESIZE() ) {
   188 	if( reg & 1 ) {
   189 	    sh4_write_long( addr, *((uint32_t *)&XF((reg)&0x0E)) );
   190 	    sh4_write_long( addr+4, *((uint32_t *)&XF(reg)) );
   191 	} else {
   192 	    sh4_write_long( addr, *((uint32_t *)&FR(reg)) ); 
   193 	    sh4_write_long( addr+4, *((uint32_t *)&FR((reg)|0x01)) );
   194 	}
   195     } else {
   196 	sh4_write_long( addr, *((uint32_t *)&FR((reg))) );
   197     }
   198 }
   200 static void sh4_read_float( uint32_t addr, int reg )
   201 {
   202     if( IS_FPU_DOUBLESIZE() ) {
   203 	if( reg & 1 ) {
   204 	    *((uint32_t *)&XF((reg) & 0x0E)) = sh4_read_long(addr);
   205 	    *((uint32_t *)&XF(reg)) = sh4_read_long(addr+4);
   206 	} else {
   207 	    *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
   208 	    *((uint32_t *)&FR((reg) | 0x01)) = sh4_read_long(addr+4);
   209 	}
   210     } else {
   211 	*((uint32_t *)&FR(reg)) = sh4_read_long(addr);
   212     }
   213 }
   215 gboolean sh4_execute_instruction( void )
   216 {
   217     uint32_t pc;
   218     unsigned short ir;
   219     uint32_t tmp;
   220     float ftmp;
   221     double dtmp;
   222     int64_t memtmp; // temporary holder for memory reads
   224 #define R0 sh4r.r[0]
   225     pc = sh4r.pc;
   226     if( pc > 0xFFFFFF00 ) {
   227 	/* SYSCALL Magic */
   228 	syscall_invoke( pc );
   229 	sh4r.in_delay_slot = 0;
   230 	pc = sh4r.pc = sh4r.pr;
   231 	sh4r.new_pc = sh4r.pc + 2;
   232         return TRUE;
   233     }
   234     CHECKRALIGN16(pc);
   236 #ifdef ENABLE_SH4STATS
   237     sh4_stats_add_by_pc(sh4r.pc);
   238 #endif
   240     /* Read instruction */
   241     if( !IS_IN_ICACHE(pc) ) {
   242 	if( !mmu_update_icache(pc) ) {
   243 	    // Fault - look for the fault handler
   244 	    if( !mmu_update_icache(sh4r.pc) ) {
   245 		// double fault - halt
   246 		ERROR( "Double fault - halting" );
   247 		dreamcast_stop();
   248 		return FALSE;
   249 	    }
   250 	}
   251 	pc = sh4r.pc;
   252     }
   253     assert( IS_IN_ICACHE(pc) );
   254     ir = *(uint16_t *)GET_ICACHE_PTR(sh4r.pc);
   255 %%
   256 AND Rm, Rn {: sh4r.r[Rn] &= sh4r.r[Rm]; :}
   257 AND #imm, R0 {: R0 &= imm; :}
   258  AND.B #imm, @(R0, GBR) {: MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm & tmp ); :}
   259 NOT Rm, Rn {: sh4r.r[Rn] = ~sh4r.r[Rm]; :}
   260 OR Rm, Rn {: sh4r.r[Rn] |= sh4r.r[Rm]; :}
   261 OR #imm, R0  {: R0 |= imm; :}
   262  OR.B #imm, @(R0, GBR) {: MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm | tmp ); :}
   263 TAS.B @Rn {:
   264     MEM_READ_BYTE( sh4r.r[Rn], tmp );
   265     sh4r.t = ( tmp == 0 ? 1 : 0 );
   266     MEM_WRITE_BYTE( sh4r.r[Rn], tmp | 0x80 );
   267 :}
   268 TST Rm, Rn {: sh4r.t = (sh4r.r[Rn]&sh4r.r[Rm] ? 0 : 1); :}
   269 TST #imm, R0 {: sh4r.t = (R0 & imm ? 0 : 1); :}
   270  TST.B #imm, @(R0, GBR) {: MEM_READ_BYTE(R0+sh4r.gbr, tmp); sh4r.t = ( tmp & imm ? 0 : 1 ); :}
   271 XOR Rm, Rn {: sh4r.r[Rn] ^= sh4r.r[Rm]; :}
   272 XOR #imm, R0 {: R0 ^= imm; :}
   273  XOR.B #imm, @(R0, GBR) {: MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm ^ tmp ); :}
   274 XTRCT Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rn]>>16) | (sh4r.r[Rm]<<16); :}
   276 ROTL Rn {:
   277     sh4r.t = sh4r.r[Rn] >> 31;
   278     sh4r.r[Rn] <<= 1;
   279     sh4r.r[Rn] |= sh4r.t;
   280 :}
   281 ROTR Rn {:
   282     sh4r.t = sh4r.r[Rn] & 0x00000001;
   283     sh4r.r[Rn] >>= 1;
   284     sh4r.r[Rn] |= (sh4r.t << 31);
   285 :}
   286 ROTCL Rn {:
   287     tmp = sh4r.r[Rn] >> 31;
   288     sh4r.r[Rn] <<= 1;
   289     sh4r.r[Rn] |= sh4r.t;
   290     sh4r.t = tmp;
   291 :}
   292 ROTCR Rn {:
   293     tmp = sh4r.r[Rn] & 0x00000001;
   294     sh4r.r[Rn] >>= 1;
   295     sh4r.r[Rn] |= (sh4r.t << 31 );
   296     sh4r.t = tmp;
   297 :}
   298 SHAD Rm, Rn {:
   299     tmp = sh4r.r[Rm];
   300     if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
   301     else if( (tmp & 0x1F) == 0 )  
   302         sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 31;
   303     else 
   304 	sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> (((~sh4r.r[Rm]) & 0x1F)+1);
   305 :}
   306 SHLD Rm, Rn {:
   307     tmp = sh4r.r[Rm];
   308     if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
   309     else if( (tmp & 0x1F) == 0 ) sh4r.r[Rn] = 0;
   310     else sh4r.r[Rn] >>= (((~tmp) & 0x1F)+1);
   311 :}
   312 SHAL Rn {:
   313     sh4r.t = sh4r.r[Rn] >> 31;
   314     sh4r.r[Rn] <<= 1;
   315 :}
   316 SHAR Rn {:
   317     sh4r.t = sh4r.r[Rn] & 0x00000001;
   318     sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 1;
   319 :}
   320 SHLL Rn {: sh4r.t = sh4r.r[Rn] >> 31; sh4r.r[Rn] <<= 1; :}
   321 SHLR Rn {: sh4r.t = sh4r.r[Rn] & 0x00000001; sh4r.r[Rn] >>= 1; :}
   322 SHLL2 Rn {: sh4r.r[Rn] <<= 2; :}
   323 SHLR2 Rn {: sh4r.r[Rn] >>= 2; :}
   324 SHLL8 Rn {: sh4r.r[Rn] <<= 8; :}
   325 SHLR8 Rn {: sh4r.r[Rn] >>= 8; :}
   326 SHLL16 Rn {: sh4r.r[Rn] <<= 16; :}
   327 SHLR16 Rn {: sh4r.r[Rn] >>= 16; :}
   329 EXTU.B Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]&0x000000FF; :}
   330 EXTU.W Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]&0x0000FFFF; :}
   331 EXTS.B Rm, Rn {: sh4r.r[Rn] = SIGNEXT8( sh4r.r[Rm]&0x000000FF ); :}
   332 EXTS.W Rm, Rn {: sh4r.r[Rn] = SIGNEXT16( sh4r.r[Rm]&0x0000FFFF ); :}
   333 SWAP.B Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rm]&0xFFFF0000) | ((sh4r.r[Rm]&0x0000FF00)>>8) | ((sh4r.r[Rm]&0x000000FF)<<8); :}
   334 SWAP.W Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rm]>>16) | (sh4r.r[Rm]<<16); :}
   336 CLRT {: sh4r.t = 0; :}
   337 SETT {: sh4r.t = 1; :}
   338 CLRMAC {: sh4r.mac = 0; :}
   339 LDTLB {: MMU_ldtlb(); :}
   340 CLRS {: sh4r.s = 0; :}
   341 SETS {: sh4r.s = 1; :}
   342 MOVT Rn {: sh4r.r[Rn] = sh4r.t; :}
   343 NOP {: /* NOP */ :}
   345 PREF @Rn {:
   346      tmp = sh4r.r[Rn];
   347      if( (tmp & 0xFC000000) == 0xE0000000 ) {
   348 	 sh4_flush_store_queue(tmp);
   349      }
   350 :}
   351 OCBI @Rn {: :}
   352 OCBP @Rn {: :}
   353 OCBWB @Rn {: :}
   354 MOVCA.L R0, @Rn {:
   355     tmp = sh4r.r[Rn];
   356     CHECKWALIGN32(tmp);
   357     MEM_WRITE_LONG( tmp, R0 );
   358 :}
   359 MOV.B Rm, @(R0, Rn) {: MEM_WRITE_BYTE( R0 + sh4r.r[Rn], sh4r.r[Rm] ); :}
   360 MOV.W Rm, @(R0, Rn) {: 
   361     CHECKWALIGN16( R0 + sh4r.r[Rn] );
   362     MEM_WRITE_WORD( R0 + sh4r.r[Rn], sh4r.r[Rm] );
   363 :}
   364 MOV.L Rm, @(R0, Rn) {:
   365     CHECKWALIGN32( R0 + sh4r.r[Rn] );
   366     MEM_WRITE_LONG( R0 + sh4r.r[Rn], sh4r.r[Rm] );
   367 :}
   368 MOV.B @(R0, Rm), Rn {: MEM_READ_BYTE( R0 + sh4r.r[Rm], sh4r.r[Rn] ); :}
   369 MOV.W @(R0, Rm), Rn {: CHECKRALIGN16( R0 + sh4r.r[Rm] );
   370     MEM_READ_WORD( R0 + sh4r.r[Rm], sh4r.r[Rn] );
   371 :}
   372 MOV.L @(R0, Rm), Rn {: CHECKRALIGN32( R0 + sh4r.r[Rm] );
   373     MEM_READ_LONG( R0 + sh4r.r[Rm], sh4r.r[Rn] );
   374 :}
   375 MOV.L Rm, @(disp, Rn) {:
   376     tmp = sh4r.r[Rn] + disp;
   377     CHECKWALIGN32( tmp );
   378     MEM_WRITE_LONG( tmp, sh4r.r[Rm] );
   379 :}
   380 MOV.B Rm, @Rn {: MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] ); :}
   381 MOV.W Rm, @Rn {: CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] ); :}
   382 MOV.L Rm, @Rn {: CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] ); :}
   383  MOV.B Rm, @-Rn {: MEM_WRITE_BYTE( sh4r.r[Rn]-1, sh4r.r[Rm] ); sh4r.r[Rn]--; :}
   384  MOV.W Rm, @-Rn {: CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn]-2, sh4r.r[Rm] ); sh4r.r[Rn] -= 2; :}
   385  MOV.L Rm, @-Rn {: CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.r[Rm] ); sh4r.r[Rn] -= 4; :}
   386 MOV.L @(disp, Rm), Rn {:
   387     tmp = sh4r.r[Rm] + disp;
   388     CHECKRALIGN32( tmp );
   389     MEM_READ_LONG( tmp, sh4r.r[Rn] );
   390 :}
   391 MOV.B @Rm, Rn {: MEM_READ_BYTE( sh4r.r[Rm], sh4r.r[Rn] ); :}
   392  MOV.W @Rm, Rn {: CHECKRALIGN16( sh4r.r[Rm] ); MEM_READ_WORD( sh4r.r[Rm], sh4r.r[Rn] ); :}
   393  MOV.L @Rm, Rn {: CHECKRALIGN32( sh4r.r[Rm] ); MEM_READ_LONG( sh4r.r[Rm], sh4r.r[Rn] ); :}
   394 MOV Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]; :}
   395  MOV.B @Rm+, Rn {: MEM_READ_BYTE( sh4r.r[Rm], sh4r.r[Rn] ); sh4r.r[Rm] ++; :}
   396  MOV.W @Rm+, Rn {: CHECKRALIGN16( sh4r.r[Rm] ); MEM_READ_WORD( sh4r.r[Rm], sh4r.r[Rn] ); sh4r.r[Rm] += 2; :}
   397  MOV.L @Rm+, Rn {: CHECKRALIGN32( sh4r.r[Rm] ); MEM_READ_LONG( sh4r.r[Rm], sh4r.r[Rn] ); sh4r.r[Rm] += 4; :}
   398 MOV.L @(disp, PC), Rn {:
   399     CHECKSLOTILLEGAL();
   400     tmp = (pc&0xFFFFFFFC) + disp + 4;
   401     MEM_READ_LONG( tmp, sh4r.r[Rn] );
   402 :}
   403 MOV.B R0, @(disp, GBR) {: MEM_WRITE_BYTE( sh4r.gbr + disp, R0 ); :}
   404 MOV.W R0, @(disp, GBR) {:
   405     tmp = sh4r.gbr + disp;
   406     CHECKWALIGN16( tmp );
   407     MEM_WRITE_WORD( tmp, R0 );
   408 :}
   409 MOV.L R0, @(disp, GBR) {:
   410     tmp = sh4r.gbr + disp;
   411     CHECKWALIGN32( tmp );
   412     MEM_WRITE_LONG( tmp, R0 );
   413 :}
   414  MOV.B @(disp, GBR), R0 {: MEM_READ_BYTE( sh4r.gbr + disp, R0 ); :}
   415 MOV.W @(disp, GBR), R0 {: 
   416     tmp = sh4r.gbr + disp;
   417     CHECKRALIGN16( tmp );
   418     MEM_READ_WORD( tmp, R0 );
   419 :}
   420 MOV.L @(disp, GBR), R0 {:
   421     tmp = sh4r.gbr + disp;
   422     CHECKRALIGN32( tmp );
   423     MEM_READ_LONG( tmp, R0 );
   424 :}
   425 MOV.B R0, @(disp, Rn) {: MEM_WRITE_BYTE( sh4r.r[Rn] + disp, R0 ); :}
   426 MOV.W R0, @(disp, Rn) {: 
   427     tmp = sh4r.r[Rn] + disp;
   428     CHECKWALIGN16( tmp );
   429     MEM_WRITE_WORD( tmp, R0 );
   430 :}
   431  MOV.B @(disp, Rm), R0 {: MEM_READ_BYTE( sh4r.r[Rm] + disp, R0 ); :}
   432 MOV.W @(disp, Rm), R0 {: 
   433     tmp = sh4r.r[Rm] + disp;
   434     CHECKRALIGN16( tmp );
   435     MEM_READ_WORD( tmp, R0 );
   436 :}
   437 MOV.W @(disp, PC), Rn {:
   438     CHECKSLOTILLEGAL();
   439     tmp = pc + 4 + disp;
   440     MEM_READ_WORD( tmp, sh4r.r[Rn] );
   441 :}
   442 MOVA @(disp, PC), R0 {:
   443     CHECKSLOTILLEGAL();
   444     R0 = (pc&0xFFFFFFFC) + disp + 4;
   445 :}
   446 MOV #imm, Rn {:  sh4r.r[Rn] = imm; :}
   448 CMP/EQ #imm, R0 {: sh4r.t = ( R0 == imm ? 1 : 0 ); :}
   449 CMP/EQ Rm, Rn {: sh4r.t = ( sh4r.r[Rm] == sh4r.r[Rn] ? 1 : 0 ); :}
   450 CMP/GE Rm, Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= ((int32_t)sh4r.r[Rm]) ? 1 : 0 ); :}
   451 CMP/GT Rm, Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) > ((int32_t)sh4r.r[Rm]) ? 1 : 0 ); :}
   452 CMP/HI Rm, Rn {: sh4r.t = ( sh4r.r[Rn] > sh4r.r[Rm] ? 1 : 0 ); :}
   453 CMP/HS Rm, Rn {: sh4r.t = ( sh4r.r[Rn] >= sh4r.r[Rm] ? 1 : 0 ); :}
   454 CMP/PL Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) > 0 ? 1 : 0 ); :}
   455 CMP/PZ Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= 0 ? 1 : 0 ); :}
   456 CMP/STR Rm, Rn {: 
   457     /* set T = 1 if any byte in RM & RN is the same */
   458     tmp = sh4r.r[Rm] ^ sh4r.r[Rn];
   459     sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
   460              (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
   461 :}
   463 ADD Rm, Rn {: sh4r.r[Rn] += sh4r.r[Rm]; :}
   464 ADD #imm, Rn {: sh4r.r[Rn] += imm; :}
   465 ADDC Rm, Rn {:
   466     tmp = sh4r.r[Rn];
   467     sh4r.r[Rn] += sh4r.r[Rm] + sh4r.t;
   468     sh4r.t = ( sh4r.r[Rn] < tmp || (sh4r.r[Rn] == tmp && sh4r.t != 0) ? 1 : 0 );
   469 :}
   470 ADDV Rm, Rn {:
   471     tmp = sh4r.r[Rn] + sh4r.r[Rm];
   472     sh4r.t = ( (sh4r.r[Rn]>>31) == (sh4r.r[Rm]>>31) && ((sh4r.r[Rn]>>31) != (tmp>>31)) );
   473     sh4r.r[Rn] = tmp;
   474 :}
   475 DIV0U {: sh4r.m = sh4r.q = sh4r.t = 0; :}
   476 DIV0S Rm, Rn {: 
   477     sh4r.q = sh4r.r[Rn]>>31;
   478     sh4r.m = sh4r.r[Rm]>>31;
   479     sh4r.t = sh4r.q ^ sh4r.m;
   480 :}
   481 DIV1 Rm, Rn {:
   482     /* This is derived from the sh4 manual with some simplifications */
   483     uint32_t tmp0, tmp1, tmp2, dir;
   485     dir = sh4r.q ^ sh4r.m;
   486     sh4r.q = (sh4r.r[Rn] >> 31);
   487     tmp2 = sh4r.r[Rm];
   488     sh4r.r[Rn] = (sh4r.r[Rn] << 1) | sh4r.t;
   489     tmp0 = sh4r.r[Rn];
   490     if( dir ) {
   491          sh4r.r[Rn] += tmp2;
   492          tmp1 = (sh4r.r[Rn]<tmp0 ? 1 : 0 );
   493     } else {
   494          sh4r.r[Rn] -= tmp2;
   495          tmp1 = (sh4r.r[Rn]>tmp0 ? 1 : 0 );
   496     }
   497     sh4r.q ^= sh4r.m ^ tmp1;
   498     sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
   499 :}
   500 DMULS.L Rm, Rn {: sh4r.mac = SIGNEXT32(sh4r.r[Rm]) * SIGNEXT32(sh4r.r[Rn]); :}
   501 DMULU.L Rm, Rn {: sh4r.mac = ((uint64_t)sh4r.r[Rm]) * ((uint64_t)sh4r.r[Rn]); :}
   502 DT Rn {:
   503     sh4r.r[Rn] --;
   504     sh4r.t = ( sh4r.r[Rn] == 0 ? 1 : 0 );
   505 :}
   506 MAC.W @Rm+, @Rn+ {:
   507     int32_t stmp;
   508     if( Rm == Rn ) {
   509 	CHECKRALIGN16(sh4r.r[Rn]);
   510 	MEM_READ_WORD( sh4r.r[Rn], tmp );
   511 	stmp = SIGNEXT16(tmp);
   512 	MEM_READ_WORD( sh4r.r[Rn]+2, tmp );
   513 	stmp *= SIGNEXT16(tmp);
   514 	sh4r.r[Rn] += 4;
   515     } else {
   516 	CHECKRALIGN16( sh4r.r[Rn] );
   517 	CHECKRALIGN16( sh4r.r[Rm] );
   518 	MEM_READ_WORD(sh4r.r[Rn], tmp);
   519 	stmp = SIGNEXT16(tmp);
   520 	MEM_READ_WORD(sh4r.r[Rm], tmp);
   521 	stmp = stmp * SIGNEXT16(tmp);
   522 	sh4r.r[Rn] += 2;
   523 	sh4r.r[Rm] += 2;
   524     }
   525     if( sh4r.s ) {
   526 	int64_t tmpl = (int64_t)((int32_t)sh4r.mac) + (int64_t)stmp;
   527 	if( tmpl > (int64_t)0x000000007FFFFFFFLL ) {
   528 	    sh4r.mac = 0x000000017FFFFFFFLL;
   529 	} else if( tmpl < (int64_t)0xFFFFFFFF80000000LL ) {
   530 	    sh4r.mac = 0x0000000180000000LL;
   531 	} else {
   532 	    sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
   533 		((uint32_t)(sh4r.mac + stmp));
   534 	}
   535     } else {
   536 	sh4r.mac += SIGNEXT32(stmp);
   537     }
   538 :}
   539 MAC.L @Rm+, @Rn+ {:
   540     int64_t tmpl;
   541     if( Rm == Rn ) {
   542 	CHECKRALIGN32( sh4r.r[Rn] );
   543 	MEM_READ_LONG(sh4r.r[Rn], tmp);
   544 	tmpl = SIGNEXT32(tmp);
   545 	MEM_READ_LONG(sh4r.r[Rn]+4, tmp);
   546 	tmpl = tmpl * SIGNEXT32(tmp) + sh4r.mac;
   547 	sh4r.r[Rn] += 8;
   548     } else {
   549 	CHECKRALIGN32( sh4r.r[Rm] );
   550 	CHECKRALIGN32( sh4r.r[Rn] );
   551 	MEM_READ_LONG(sh4r.r[Rn], tmp);
   552 	tmpl = SIGNEXT32(tmp);
   553 	MEM_READ_LONG(sh4r.r[Rm], tmp);
   554 	tmpl = tmpl * SIGNEXT32(tmp) + sh4r.mac;
   555 	sh4r.r[Rn] += 4;
   556 	sh4r.r[Rm] += 4;
   557     }
   558     if( sh4r.s ) {
   559         /* 48-bit Saturation. Yuch */
   560         if( tmpl < (int64_t)0xFFFF800000000000LL )
   561             tmpl = 0xFFFF800000000000LL;
   562         else if( tmpl > (int64_t)0x00007FFFFFFFFFFFLL )
   563             tmpl = 0x00007FFFFFFFFFFFLL;
   564     }
   565     sh4r.mac = tmpl;
   566 :}
   567 MUL.L Rm, Rn {: sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   568                         (sh4r.r[Rm] * sh4r.r[Rn]); :}
   569 MULU.W Rm, Rn {:
   570     sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   571                (uint32_t)((sh4r.r[Rm]&0xFFFF) * (sh4r.r[Rn]&0xFFFF));
   572 :}
   573 MULS.W Rm, Rn {:
   574     sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   575                (uint32_t)(SIGNEXT32(sh4r.r[Rm]&0xFFFF) * SIGNEXT32(sh4r.r[Rn]&0xFFFF));
   576 :}
   577 NEGC Rm, Rn {:
   578     tmp = 0 - sh4r.r[Rm];
   579     sh4r.r[Rn] = tmp - sh4r.t;
   580     sh4r.t = ( 0<tmp || tmp<sh4r.r[Rn] ? 1 : 0 );
   581 :}
   582 NEG Rm, Rn {: sh4r.r[Rn] = 0 - sh4r.r[Rm]; :}
   583 SUB Rm, Rn {: sh4r.r[Rn] -= sh4r.r[Rm]; :}
   584 SUBC Rm, Rn {: 
   585     tmp = sh4r.r[Rn];
   586     sh4r.r[Rn] = sh4r.r[Rn] - sh4r.r[Rm] - sh4r.t;
   587     sh4r.t = (sh4r.r[Rn] > tmp || (sh4r.r[Rn] == tmp && sh4r.t == 1));
   588 :}
   590 BRAF Rn {:
   591      CHECKSLOTILLEGAL();
   592      CHECKDEST( pc + 4 + sh4r.r[Rn] );
   593      sh4r.in_delay_slot = 1;
   594      sh4r.pc = sh4r.new_pc;
   595      sh4r.new_pc = pc + 4 + sh4r.r[Rn];
   596      return TRUE;
   597 :}
   598 BSRF Rn {:
   599      CHECKSLOTILLEGAL();
   600      CHECKDEST( pc + 4 + sh4r.r[Rn] );
   601      sh4r.in_delay_slot = 1;
   602      sh4r.pr = sh4r.pc + 4;
   603      sh4r.pc = sh4r.new_pc;
   604      sh4r.new_pc = pc + 4 + sh4r.r[Rn];
   605      TRACE_CALL( pc, sh4r.new_pc );
   606      return TRUE;
   607 :}
   608 BT disp {:
   609     CHECKSLOTILLEGAL();
   610     if( sh4r.t ) {
   611         CHECKDEST( sh4r.pc + disp + 4 )
   612         sh4r.pc += disp + 4;
   613         sh4r.new_pc = sh4r.pc + 2;
   614         return TRUE;
   615     }
   616 :}
   617 BF disp {:
   618     CHECKSLOTILLEGAL();
   619     if( !sh4r.t ) {
   620         CHECKDEST( sh4r.pc + disp + 4 )
   621         sh4r.pc += disp + 4;
   622         sh4r.new_pc = sh4r.pc + 2;
   623         return TRUE;
   624     }
   625 :}
   626 BT/S disp {:
   627     CHECKSLOTILLEGAL();
   628     if( sh4r.t ) {
   629         CHECKDEST( sh4r.pc + disp + 4 )
   630         sh4r.in_delay_slot = 1;
   631         sh4r.pc = sh4r.new_pc;
   632         sh4r.new_pc = pc + disp + 4;
   633         sh4r.in_delay_slot = 1;
   634         return TRUE;
   635     }
   636 :}
   637 BF/S disp {:
   638     CHECKSLOTILLEGAL();
   639     if( !sh4r.t ) {
   640         CHECKDEST( sh4r.pc + disp + 4 )
   641         sh4r.in_delay_slot = 1;
   642         sh4r.pc = sh4r.new_pc;
   643         sh4r.new_pc = pc + disp + 4;
   644         return TRUE;
   645     }
   646 :}
   647 BRA disp {:
   648     CHECKSLOTILLEGAL();
   649     CHECKDEST( sh4r.pc + disp + 4 );
   650     sh4r.in_delay_slot = 1;
   651     sh4r.pc = sh4r.new_pc;
   652     sh4r.new_pc = pc + 4 + disp;
   653     return TRUE;
   654 :}
   655 BSR disp {:
   656     CHECKDEST( sh4r.pc + disp + 4 );
   657     CHECKSLOTILLEGAL();
   658     sh4r.in_delay_slot = 1;
   659     sh4r.pr = pc + 4;
   660     sh4r.pc = sh4r.new_pc;
   661     sh4r.new_pc = pc + 4 + disp;
   662     TRACE_CALL( pc, sh4r.new_pc );
   663     return TRUE;
   664 :}
   665 TRAPA #imm {:
   666     CHECKSLOTILLEGAL();
   667     sh4r.pc += 2;
   668     sh4_raise_trap( imm );
   669     return TRUE;
   670 :}
   671 RTS {: 
   672     CHECKSLOTILLEGAL();
   673     CHECKDEST( sh4r.pr );
   674     sh4r.in_delay_slot = 1;
   675     sh4r.pc = sh4r.new_pc;
   676     sh4r.new_pc = sh4r.pr;
   677     TRACE_RETURN( pc, sh4r.new_pc );
   678     return TRUE;
   679 :}
   680 SLEEP {:
   681     if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
   682 	sh4r.sh4_state = SH4_STATE_STANDBY;
   683     } else {
   684 	sh4r.sh4_state = SH4_STATE_SLEEP;
   685     }
   686     return FALSE; /* Halt CPU */
   687 :}
   688 RTE {:
   689     CHECKPRIV();
   690     CHECKDEST( sh4r.spc );
   691     CHECKSLOTILLEGAL();
   692     sh4r.in_delay_slot = 1;
   693     sh4r.pc = sh4r.new_pc;
   694     sh4r.new_pc = sh4r.spc;
   695     sh4_write_sr( sh4r.ssr );
   696     return TRUE;
   697 :}
   698 JMP @Rn {:
   699     CHECKDEST( sh4r.r[Rn] );
   700     CHECKSLOTILLEGAL();
   701     sh4r.in_delay_slot = 1;
   702     sh4r.pc = sh4r.new_pc;
   703     sh4r.new_pc = sh4r.r[Rn];
   704     return TRUE;
   705 :}
   706 JSR @Rn {:
   707     CHECKDEST( sh4r.r[Rn] );
   708     CHECKSLOTILLEGAL();
   709     sh4r.in_delay_slot = 1;
   710     sh4r.pc = sh4r.new_pc;
   711     sh4r.new_pc = sh4r.r[Rn];
   712     sh4r.pr = pc + 4;
   713     TRACE_CALL( pc, sh4r.new_pc );
   714     return TRUE;
   715 :}
   716 STS MACH, Rn {: sh4r.r[Rn] = (sh4r.mac>>32); :}
   717 STS.L MACH, @-Rn {:
   718     CHECKWALIGN32( sh4r.r[Rn] );
   719     MEM_WRITE_LONG( sh4r.r[Rn]-4, (sh4r.mac>>32) );
   720     sh4r.r[Rn] -= 4;
   721 :}
   722 STC.L SR, @-Rn {:
   723     CHECKPRIV();
   724     CHECKWALIGN32( sh4r.r[Rn] );
   725     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4_read_sr() );
   726     sh4r.r[Rn] -= 4;
   727 :}
   728 LDS.L @Rm+, MACH {:
   729     CHECKRALIGN32( sh4r.r[Rm] );
   730     MEM_READ_LONG(sh4r.r[Rm], tmp);
   731     sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
   732 	(((uint64_t)tmp)<<32);
   733     sh4r.r[Rm] += 4;
   734 :}
   735 LDC.L @Rm+, SR {:
   736     CHECKSLOTILLEGAL();
   737     CHECKPRIV();
   738     CHECKWALIGN32( sh4r.r[Rm] );
   739     MEM_READ_LONG(sh4r.r[Rm], tmp);
   740     sh4_write_sr( tmp );
   741     sh4r.r[Rm] +=4;
   742 :}
   743 LDS Rm, MACH {:
   744     sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
   745                (((uint64_t)sh4r.r[Rm])<<32);
   746 :}
   747 LDC Rm, SR {:
   748     CHECKSLOTILLEGAL();
   749     CHECKPRIV();
   750     sh4_write_sr( sh4r.r[Rm] );
   751 :}
   752 LDC Rm, SGR {:
   753     CHECKPRIV();
   754     sh4r.sgr = sh4r.r[Rm];
   755 :}
   756 LDC.L @Rm+, SGR {:
   757     CHECKPRIV();
   758     CHECKRALIGN32( sh4r.r[Rm] );
   759     MEM_READ_LONG(sh4r.r[Rm], sh4r.sgr);
   760     sh4r.r[Rm] +=4;
   761 :}
   762 STS MACL, Rn {: sh4r.r[Rn] = (uint32_t)sh4r.mac; :}
   763 STS.L MACL, @-Rn {:
   764     CHECKWALIGN32( sh4r.r[Rn] );
   765     MEM_WRITE_LONG( sh4r.r[Rn]-4, (uint32_t)sh4r.mac );
   766     sh4r.r[Rn] -= 4;
   767 :}
   768 STC.L GBR, @-Rn {:
   769     CHECKWALIGN32( sh4r.r[Rn] );
   770     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.gbr );
   771     sh4r.r[Rn] -= 4;
   772 :}
   773 LDS.L @Rm+, MACL {:
   774     CHECKRALIGN32( sh4r.r[Rm] );
   775     MEM_READ_LONG(sh4r.r[Rm], tmp);
   776     sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
   777                (uint64_t)((uint32_t)tmp);
   778     sh4r.r[Rm] += 4;
   779 :}
   780 LDC.L @Rm+, GBR {:
   781     CHECKRALIGN32( sh4r.r[Rm] );
   782     MEM_READ_LONG(sh4r.r[Rm], sh4r.gbr);
   783     sh4r.r[Rm] +=4;
   784 :}
   785 LDS Rm, MACL {:
   786     sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
   787                (uint64_t)((uint32_t)(sh4r.r[Rm]));
   788 :}
   789 LDC Rm, GBR {: sh4r.gbr = sh4r.r[Rm]; :}
   790 STS PR, Rn {: sh4r.r[Rn] = sh4r.pr; :}
   791 STS.L PR, @-Rn {:
   792     CHECKWALIGN32( sh4r.r[Rn] );
   793     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.pr );
   794     sh4r.r[Rn] -= 4;
   795 :}
   796 STC.L VBR, @-Rn {:
   797     CHECKPRIV();
   798     CHECKWALIGN32( sh4r.r[Rn] );
   799     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.vbr );
   800     sh4r.r[Rn] -= 4;
   801 :}
   802 LDS.L @Rm+, PR {:
   803     CHECKRALIGN32( sh4r.r[Rm] );
   804     MEM_READ_LONG( sh4r.r[Rm], sh4r.pr );
   805     sh4r.r[Rm] += 4;
   806 :}
   807 LDC.L @Rm+, VBR {:
   808     CHECKPRIV();
   809     CHECKRALIGN32( sh4r.r[Rm] );
   810     MEM_READ_LONG(sh4r.r[Rm], sh4r.vbr);
   811     sh4r.r[Rm] +=4;
   812 :}
   813 LDS Rm, PR {: sh4r.pr = sh4r.r[Rm]; :}
   814 LDC Rm, VBR {:
   815     CHECKPRIV();
   816     sh4r.vbr = sh4r.r[Rm];
   817 :}
   818 STC SGR, Rn {:
   819     CHECKPRIV();
   820     sh4r.r[Rn] = sh4r.sgr;
   821 :}
   822 STC.L SGR, @-Rn {:
   823     CHECKPRIV();
   824     CHECKWALIGN32( sh4r.r[Rn] );
   825     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.sgr );
   826     sh4r.r[Rn] -= 4;
   827 :}
   828 STC.L SSR, @-Rn {:
   829     CHECKPRIV();
   830     CHECKWALIGN32( sh4r.r[Rn] );
   831     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.ssr );
   832     sh4r.r[Rn] -= 4;
   833 :}
   834 LDC.L @Rm+, SSR {:
   835     CHECKPRIV();
   836     CHECKRALIGN32( sh4r.r[Rm] );
   837     MEM_READ_LONG(sh4r.r[Rm], sh4r.ssr);
   838     sh4r.r[Rm] +=4;
   839 :}
   840 LDC Rm, SSR {:
   841     CHECKPRIV();
   842     sh4r.ssr = sh4r.r[Rm];
   843 :}
   844 STC.L SPC, @-Rn {:
   845     CHECKPRIV();
   846     CHECKWALIGN32( sh4r.r[Rn] );
   847     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.spc );
   848     sh4r.r[Rn] -= 4;
   849 :}
   850 LDC.L @Rm+, SPC {:
   851     CHECKPRIV();
   852     CHECKRALIGN32( sh4r.r[Rm] );
   853     MEM_READ_LONG(sh4r.r[Rm], sh4r.spc);
   854     sh4r.r[Rm] +=4;
   855 :}
   856 LDC Rm, SPC {:
   857     CHECKPRIV();
   858     sh4r.spc = sh4r.r[Rm];
   859 :}
   860 STS FPUL, Rn {: 
   861     CHECKFPUEN();
   862     sh4r.r[Rn] = FPULi; 
   863 :}
   864 STS.L FPUL, @-Rn {:
   865     CHECKFPUEN();
   866     CHECKWALIGN32( sh4r.r[Rn] );
   867     MEM_WRITE_LONG( sh4r.r[Rn]-4, FPULi );
   868     sh4r.r[Rn] -= 4;
   869 :}
   870 LDS.L @Rm+, FPUL {:
   871     CHECKFPUEN();
   872     CHECKRALIGN32( sh4r.r[Rm] );
   873     MEM_READ_LONG(sh4r.r[Rm], FPULi);
   874     sh4r.r[Rm] +=4;
   875 :}
   876 LDS Rm, FPUL {:
   877     CHECKFPUEN();
   878     FPULi = sh4r.r[Rm]; 
   879 :}
   880 STS FPSCR, Rn {: 
   881     CHECKFPUEN();
   882     sh4r.r[Rn] = sh4r.fpscr; 
   883 :}
   884 STS.L FPSCR, @-Rn {:
   885     CHECKFPUEN();
   886     CHECKWALIGN32( sh4r.r[Rn] );
   887     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.fpscr );
   888     sh4r.r[Rn] -= 4;
   889 :}
   890 LDS.L @Rm+, FPSCR {:
   891     CHECKFPUEN();
   892     CHECKRALIGN32( sh4r.r[Rm] );
   893     MEM_READ_LONG(sh4r.r[Rm], tmp);
   894     sh4r.r[Rm] +=4;
   895     sh4_write_fpscr( tmp );
   896 :}
   897 LDS Rm, FPSCR {: 
   898     CHECKFPUEN();
   899     sh4_write_fpscr( sh4r.r[Rm] );
   900 :}
   901 STC DBR, Rn {: CHECKPRIV(); sh4r.r[Rn] = sh4r.dbr; :}
   902 STC.L DBR, @-Rn {:
   903     CHECKPRIV();
   904     CHECKWALIGN32( sh4r.r[Rn] );
   905     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.dbr );
   906     sh4r.r[Rn] -= 4;
   907 :}
   908 LDC.L @Rm+, DBR {:
   909     CHECKPRIV();
   910     CHECKRALIGN32( sh4r.r[Rm] );
   911     MEM_READ_LONG(sh4r.r[Rm], sh4r.dbr);
   912     sh4r.r[Rm] +=4;
   913 :}
   914 LDC Rm, DBR {:
   915     CHECKPRIV();
   916     sh4r.dbr = sh4r.r[Rm];
   917 :}
   918 STC.L Rm_BANK, @-Rn {:
   919     CHECKPRIV();
   920     CHECKWALIGN32( sh4r.r[Rn] );
   921     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.r_bank[Rm_BANK] );
   922     sh4r.r[Rn] -= 4;
   923 :}
   924 LDC.L @Rm+, Rn_BANK {:
   925     CHECKPRIV();
   926     CHECKRALIGN32( sh4r.r[Rm] );
   927     MEM_READ_LONG( sh4r.r[Rm], sh4r.r_bank[Rn_BANK] );
   928     sh4r.r[Rm] += 4;
   929 :}
   930 LDC Rm, Rn_BANK {:
   931     CHECKPRIV();
   932     sh4r.r_bank[Rn_BANK] = sh4r.r[Rm];
   933 :}
   934 STC SR, Rn {: 
   935     CHECKPRIV();
   936     sh4r.r[Rn] = sh4_read_sr();
   937 :}
   938 STC GBR, Rn {:
   939     sh4r.r[Rn] = sh4r.gbr;
   940 :}
   941 STC VBR, Rn {:
   942     CHECKPRIV();
   943     sh4r.r[Rn] = sh4r.vbr;
   944 :}
   945 STC SSR, Rn {:
   946     CHECKPRIV();
   947     sh4r.r[Rn] = sh4r.ssr;
   948 :}
   949 STC SPC, Rn {:
   950     CHECKPRIV();
   951     sh4r.r[Rn] = sh4r.spc;
   952 :}
   953 STC Rm_BANK, Rn {:
   954     CHECKPRIV();
   955     sh4r.r[Rn] = sh4r.r_bank[Rm_BANK];
   956 :}
   958 FADD FRm, FRn {:
   959     CHECKFPUEN();
   960     if( IS_FPU_DOUBLEPREC() ) {
   961 	DR(FRn) += DR(FRm);
   962     } else {
   963 	FR(FRn) += FR(FRm);
   964     }
   965 :}
   966 FSUB FRm, FRn {:
   967     CHECKFPUEN();
   968     if( IS_FPU_DOUBLEPREC() ) {
   969 	DR(FRn) -= DR(FRm);
   970     } else {
   971 	FR(FRn) -= FR(FRm);
   972     }
   973 :}
   975 FMUL FRm, FRn {:
   976     CHECKFPUEN();
   977     if( IS_FPU_DOUBLEPREC() ) {
   978 	DR(FRn) *= DR(FRm);
   979     } else {
   980 	FR(FRn) *= FR(FRm);
   981     }
   982 :}
   984 FDIV FRm, FRn {:
   985     CHECKFPUEN();
   986     if( IS_FPU_DOUBLEPREC() ) {
   987 	DR(FRn) /= DR(FRm);
   988     } else {
   989 	FR(FRn) /= FR(FRm);
   990     }
   991 :}
   993 FCMP/EQ FRm, FRn {:
   994     CHECKFPUEN();
   995     if( IS_FPU_DOUBLEPREC() ) {
   996 	sh4r.t = ( DR(FRn) == DR(FRm) ? 1 : 0 );
   997     } else {
   998 	sh4r.t = ( FR(FRn) == FR(FRm) ? 1 : 0 );
   999     }
  1000 :}
  1002 FCMP/GT FRm, FRn {:
  1003     CHECKFPUEN();
  1004     if( IS_FPU_DOUBLEPREC() ) {
  1005 	sh4r.t = ( DR(FRn) > DR(FRm) ? 1 : 0 );
  1006     } else {
  1007 	sh4r.t = ( FR(FRn) > FR(FRm) ? 1 : 0 );
  1009 :}
  1011 FMOV @(R0, Rm), FRn {: MEM_FP_READ( sh4r.r[Rm] + R0, FRn ); :}
  1012 FMOV FRm, @(R0, Rn) {: MEM_FP_WRITE( sh4r.r[Rn] + R0, FRm ); :}
  1013 FMOV @Rm, FRn {: MEM_FP_READ( sh4r.r[Rm], FRn ); :}
  1014 FMOV @Rm+, FRn {: MEM_FP_READ( sh4r.r[Rm], FRn ); sh4r.r[Rm] += FP_WIDTH; :}
  1015 FMOV FRm, @Rn {: MEM_FP_WRITE( sh4r.r[Rn], FRm ); :}
  1016  FMOV FRm, @-Rn {: MEM_FP_WRITE( sh4r.r[Rn] - FP_WIDTH, FRm ); sh4r.r[Rn] -= FP_WIDTH; :}
  1017 FMOV FRm, FRn {: 
  1018     if( IS_FPU_DOUBLESIZE() )
  1019 	DR(FRn) = DR(FRm);
  1020     else
  1021 	FR(FRn) = FR(FRm);
  1022 :}
  1023 FSTS FPUL, FRn {: CHECKFPUEN(); FR(FRn) = FPULf; :}
  1024 FLDS FRm, FPUL {: CHECKFPUEN(); FPULf = FR(FRm); :}
  1025 FLOAT FPUL, FRn {: 
  1026     CHECKFPUEN();
  1027     if( IS_FPU_DOUBLEPREC() ) {
  1028 	if( FRn&1 ) { // No, really...
  1029 	    dtmp = (double)FPULi;
  1030 	    FR(FRn) = *(((float *)&dtmp)+1);
  1031 	} else {
  1032 	    DRF(FRn>>1) = (double)FPULi;
  1034     } else {
  1035 	FR(FRn) = (float)FPULi;
  1037 :}
  1038 FTRC FRm, FPUL {:
  1039     CHECKFPUEN();
  1040     if( IS_FPU_DOUBLEPREC() ) {
  1041 	if( FRm&1 ) {
  1042 	    dtmp = 0;
  1043 	    *(((float *)&dtmp)+1) = FR(FRm);
  1044 	} else {
  1045 	    dtmp = DRF(FRm>>1);
  1047         if( dtmp >= MAX_INTF )
  1048             FPULi = MAX_INT;
  1049         else if( dtmp <= MIN_INTF )
  1050             FPULi = MIN_INT;
  1051         else 
  1052             FPULi = (int32_t)dtmp;
  1053     } else {
  1054 	ftmp = FR(FRm);
  1055 	if( ftmp >= MAX_INTF )
  1056 	    FPULi = MAX_INT;
  1057 	else if( ftmp <= MIN_INTF )
  1058 	    FPULi = MIN_INT;
  1059 	else
  1060 	    FPULi = (int32_t)ftmp;
  1062 :}
  1063 FNEG FRn {:
  1064     CHECKFPUEN();
  1065     if( IS_FPU_DOUBLEPREC() ) {
  1066 	DR(FRn) = -DR(FRn);
  1067     } else {
  1068         FR(FRn) = -FR(FRn);
  1070 :}
  1071 FABS FRn {:
  1072     CHECKFPUEN();
  1073     if( IS_FPU_DOUBLEPREC() ) {
  1074 	DR(FRn) = fabs(DR(FRn));
  1075     } else {
  1076         FR(FRn) = fabsf(FR(FRn));
  1078 :}
  1079 FSQRT FRn {:
  1080     CHECKFPUEN();
  1081     if( IS_FPU_DOUBLEPREC() ) {
  1082 	DR(FRn) = sqrt(DR(FRn));
  1083     } else {
  1084         FR(FRn) = sqrtf(FR(FRn));
  1086 :}
  1087 FLDI0 FRn {:
  1088     CHECKFPUEN();
  1089     if( IS_FPU_DOUBLEPREC() ) {
  1090 	DR(FRn) = 0.0;
  1091     } else {
  1092         FR(FRn) = 0.0;
  1094 :}
  1095 FLDI1 FRn {:
  1096     CHECKFPUEN();
  1097     if( IS_FPU_DOUBLEPREC() ) {
  1098 	DR(FRn) = 1.0;
  1099     } else {
  1100         FR(FRn) = 1.0;
  1102 :}
  1103 FMAC FR0, FRm, FRn {:
  1104     CHECKFPUEN();
  1105     if( IS_FPU_DOUBLEPREC() ) {
  1106         DR(FRn) += DR(FRm)*DR(0);
  1107     } else {
  1108 	FR(FRn) += FR(FRm)*FR(0);
  1110 :}
  1111 FRCHG {: 
  1112     CHECKFPUEN(); 
  1113     sh4r.fpscr ^= FPSCR_FR; 
  1114     sh4_switch_fr_banks();
  1115 :}
  1116 FSCHG {: CHECKFPUEN(); sh4r.fpscr ^= FPSCR_SZ; :}
  1117 FCNVSD FPUL, FRn {:
  1118     CHECKFPUEN();
  1119     if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
  1120 	DR(FRn) = (double)FPULf;
  1122 :}
  1123 FCNVDS FRm, FPUL {:
  1124     CHECKFPUEN();
  1125     if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
  1126 	FPULf = (float)DR(FRm);
  1128 :}
  1130 FSRRA FRn {:
  1131     CHECKFPUEN();
  1132     if( !IS_FPU_DOUBLEPREC() ) {
  1133 	FR(FRn) = 1.0/sqrtf(FR(FRn));
  1135 :}
  1136 FIPR FVm, FVn {:
  1137     CHECKFPUEN();
  1138     if( !IS_FPU_DOUBLEPREC() ) {
  1139         int tmp2 = FVn<<2;
  1140         tmp = FVm<<2;
  1141         FR(tmp2+3) = FR(tmp)*FR(tmp2) +
  1142             FR(tmp+1)*FR(tmp2+1) +
  1143             FR(tmp+2)*FR(tmp2+2) +
  1144             FR(tmp+3)*FR(tmp2+3);
  1146 :}
  1147 FSCA FPUL, FRn {:
  1148     CHECKFPUEN();
  1149     if( !IS_FPU_DOUBLEPREC() ) {
  1150 	sh4_fsca( FPULi, &(DRF(FRn>>1)) );
  1151 	/*
  1152         float angle = (((float)(FPULi&0xFFFF))/65536.0) * 2 * M_PI;
  1153         FR(FRn) = sinf(angle);
  1154         FR((FRn)+1) = cosf(angle);
  1155 	*/
  1157 :}
  1158 FTRV XMTRX, FVn {:
  1159     CHECKFPUEN();
  1160     if( !IS_FPU_DOUBLEPREC() ) {
  1161 	sh4_ftrv(&(DRF(FVn<<1)) );
  1163 :}
  1164 UNDEF {:
  1165     UNDEF(ir);
  1166 :}
  1167 %%
  1168     sh4r.pc = sh4r.new_pc;
  1169     sh4r.new_pc += 2;
  1170     sh4r.in_delay_slot = 0;
  1171     return TRUE;
.