4 * SH4 emulation core, and parent module for all the SH4 peripheral
7 * Copyright (c) 2005 Nathan Keynes.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
20 #define MODULE sh4_module
24 #include "dreamcast.h"
29 #include "sh4/sh4core.h"
30 #include "sh4/sh4mmio.h"
31 #include "sh4/sh4stat.h"
34 #define SH4_CALLTRACE 1
36 #define MAX_INT 0x7FFFFFFF
37 #define MIN_INT 0x80000000
38 #define MAX_INTF 2147483647.0
39 #define MIN_INTF -2147483648.0
41 /********************** SH4 Module Definition ****************************/
43 uint32_t sh4_run_slice( uint32_t nanosecs )
48 if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
49 sh4_sleep_run_slice(nanosecs);
52 if( sh4_breakpoint_count == 0 ) {
53 for( ; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
54 if( SH4_EVENT_PENDING() ) {
55 if( sh4r.event_types & PENDING_EVENT ) {
58 /* Eventq execute may (quite likely) deliver an immediate IRQ */
59 if( sh4r.event_types & PENDING_IRQ ) {
60 sh4_accept_interrupt();
63 if( !sh4_execute_instruction() ) {
68 for( ;sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
69 if( SH4_EVENT_PENDING() ) {
70 if( sh4r.event_types & PENDING_EVENT ) {
73 /* Eventq execute may (quite likely) deliver an immediate IRQ */
74 if( sh4r.event_types & PENDING_IRQ ) {
75 sh4_accept_interrupt();
79 if( !sh4_execute_instruction() )
81 #ifdef ENABLE_DEBUG_MODE
82 for( i=0; i<sh4_breakpoint_count; i++ ) {
83 if( sh4_breakpoints[i].address == sh4r.pc ) {
87 if( i != sh4_breakpoint_count ) {
89 if( sh4_breakpoints[i].type == BREAK_ONESHOT )
90 sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );
97 /* If we aborted early, but the cpu is still technically running,
98 * we're doing a hard abort - cut the timeslice back to what we
101 if( sh4r.slice_cycle != nanosecs && sh4r.sh4_state == SH4_STATE_RUNNING ) {
102 nanosecs = sh4r.slice_cycle;
104 if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
105 TMU_run_slice( nanosecs );
106 SCIF_run_slice( nanosecs );
111 /********************** SH4 emulation core ****************************/
113 #define UNDEF(ir) return sh4_raise_slot_exception(EXC_ILLEGAL, EXC_SLOT_ILLEGAL)
114 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)
116 #if(SH4_CALLTRACE == 1)
117 #define MAX_CALLSTACK 32
118 static struct call_stack {
120 sh4addr_t target_addr;
121 sh4addr_t stack_pointer;
122 } call_stack[MAX_CALLSTACK];
124 static int call_stack_depth = 0;
125 int sh4_call_trace_on = 0;
127 static inline void trace_call( sh4addr_t source, sh4addr_t dest )
129 if( call_stack_depth < MAX_CALLSTACK ) {
130 call_stack[call_stack_depth].call_addr = source;
131 call_stack[call_stack_depth].target_addr = dest;
132 call_stack[call_stack_depth].stack_pointer = sh4r.r[15];
137 static inline void trace_return( sh4addr_t source, sh4addr_t dest )
139 if( call_stack_depth > 0 ) {
144 void fprint_stack_trace( FILE *f )
146 int i = call_stack_depth -1;
147 if( i >= MAX_CALLSTACK )
148 i = MAX_CALLSTACK - 1;
149 for( ; i >= 0; i-- ) {
150 fprintf( f, "%d. Call from %08X => %08X, SP=%08X\n",
151 (call_stack_depth - i), call_stack[i].call_addr,
152 call_stack[i].target_addr, call_stack[i].stack_pointer );
156 #define TRACE_CALL( source, dest ) trace_call(source, dest)
157 #define TRACE_RETURN( source, dest ) trace_return(source, dest)
159 #define TRACE_CALL( dest, rts )
160 #define TRACE_RETURN( source, dest )
163 #define MEM_READ_BYTE( addr, val ) memtmp = mmu_vma_to_phys_read(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { val = sh4_read_byte(memtmp); }
164 #define MEM_READ_WORD( addr, val ) memtmp = mmu_vma_to_phys_read(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { val = sh4_read_word(memtmp); }
165 #define MEM_READ_LONG( addr, val ) memtmp = mmu_vma_to_phys_read(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { val = sh4_read_long(memtmp); }
166 #define MEM_WRITE_BYTE( addr, val ) memtmp = mmu_vma_to_phys_write(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { sh4_write_byte(memtmp, val); }
167 #define MEM_WRITE_WORD( addr, val ) memtmp = mmu_vma_to_phys_write(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { sh4_write_word(memtmp, val); }
168 #define MEM_WRITE_LONG( addr, val ) memtmp = mmu_vma_to_phys_write(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { sh4_write_long(memtmp, val); }
170 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
172 #define MEM_FP_READ( addr, reg ) sh4_read_float( addr, reg );
173 #define MEM_FP_WRITE( addr, reg ) sh4_write_float( addr, reg );
175 #define CHECKPRIV() if( !IS_SH4_PRIVMODE() ) return sh4_raise_slot_exception( EXC_ILLEGAL, EXC_SLOT_ILLEGAL )
176 #define CHECKRALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )
177 #define CHECKRALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )
178 #define CHECKWALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )
179 #define CHECKWALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )
181 #define CHECKFPUEN() if( !IS_FPU_ENABLED() ) { if( ir == 0xFFFD ) { UNDEF(ir); } else { return sh4_raise_slot_exception( EXC_FPU_DISABLED, EXC_SLOT_FPU_DISABLED ); } }
182 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); dreamcast_stop(); return FALSE; }
183 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) return sh4_raise_exception(EXC_SLOT_ILLEGAL)
185 static void sh4_write_float( uint32_t addr, int reg )
187 if( IS_FPU_DOUBLESIZE() ) {
189 sh4_write_long( addr, *((uint32_t *)&XF((reg)&0x0E)) );
190 sh4_write_long( addr+4, *((uint32_t *)&XF(reg)) );
192 sh4_write_long( addr, *((uint32_t *)&FR(reg)) );
193 sh4_write_long( addr+4, *((uint32_t *)&FR((reg)|0x01)) );
196 sh4_write_long( addr, *((uint32_t *)&FR((reg))) );
200 static void sh4_read_float( uint32_t addr, int reg )
202 if( IS_FPU_DOUBLESIZE() ) {
204 *((uint32_t *)&XF((reg) & 0x0E)) = sh4_read_long(addr);
205 *((uint32_t *)&XF(reg)) = sh4_read_long(addr+4);
207 *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
208 *((uint32_t *)&FR((reg) | 0x01)) = sh4_read_long(addr+4);
211 *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
215 gboolean sh4_execute_instruction( void )
222 int64_t memtmp; // temporary holder for memory reads
226 if( pc > 0xFFFFFF00 ) {
228 syscall_invoke( pc );
229 sh4r.in_delay_slot = 0;
230 pc = sh4r.pc = sh4r.pr;
231 sh4r.new_pc = sh4r.pc + 2;
236 #ifdef ENABLE_SH4STATS
237 sh4_stats_add_by_pc(sh4r.pc);
240 /* Read instruction */
241 if( !IS_IN_ICACHE(pc) ) {
242 if( !mmu_update_icache(pc) ) {
243 // Fault - look for the fault handler
244 if( !mmu_update_icache(sh4r.pc) ) {
245 // double fault - halt
246 ERROR( "Double fault - halting" );
253 assert( IS_IN_ICACHE(pc) );
254 ir = *(uint16_t *)GET_ICACHE_PTR(sh4r.pc);
256 AND Rm, Rn {: sh4r.r[Rn] &= sh4r.r[Rm]; :}
257 AND #imm, R0 {: R0 &= imm; :}
258 AND.B #imm, @(R0, GBR) {: MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm & tmp ); :}
259 NOT Rm, Rn {: sh4r.r[Rn] = ~sh4r.r[Rm]; :}
260 OR Rm, Rn {: sh4r.r[Rn] |= sh4r.r[Rm]; :}
261 OR #imm, R0 {: R0 |= imm; :}
262 OR.B #imm, @(R0, GBR) {: MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm | tmp ); :}
264 MEM_READ_BYTE( sh4r.r[Rn], tmp );
265 sh4r.t = ( tmp == 0 ? 1 : 0 );
266 MEM_WRITE_BYTE( sh4r.r[Rn], tmp | 0x80 );
268 TST Rm, Rn {: sh4r.t = (sh4r.r[Rn]&sh4r.r[Rm] ? 0 : 1); :}
269 TST #imm, R0 {: sh4r.t = (R0 & imm ? 0 : 1); :}
270 TST.B #imm, @(R0, GBR) {: MEM_READ_BYTE(R0+sh4r.gbr, tmp); sh4r.t = ( tmp & imm ? 0 : 1 ); :}
271 XOR Rm, Rn {: sh4r.r[Rn] ^= sh4r.r[Rm]; :}
272 XOR #imm, R0 {: R0 ^= imm; :}
273 XOR.B #imm, @(R0, GBR) {: MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm ^ tmp ); :}
274 XTRCT Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rn]>>16) | (sh4r.r[Rm]<<16); :}
277 sh4r.t = sh4r.r[Rn] >> 31;
279 sh4r.r[Rn] |= sh4r.t;
282 sh4r.t = sh4r.r[Rn] & 0x00000001;
284 sh4r.r[Rn] |= (sh4r.t << 31);
287 tmp = sh4r.r[Rn] >> 31;
289 sh4r.r[Rn] |= sh4r.t;
293 tmp = sh4r.r[Rn] & 0x00000001;
295 sh4r.r[Rn] |= (sh4r.t << 31 );
300 if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
301 else if( (tmp & 0x1F) == 0 )
302 sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 31;
304 sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> (((~sh4r.r[Rm]) & 0x1F)+1);
308 if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
309 else if( (tmp & 0x1F) == 0 ) sh4r.r[Rn] = 0;
310 else sh4r.r[Rn] >>= (((~tmp) & 0x1F)+1);
313 sh4r.t = sh4r.r[Rn] >> 31;
317 sh4r.t = sh4r.r[Rn] & 0x00000001;
318 sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 1;
320 SHLL Rn {: sh4r.t = sh4r.r[Rn] >> 31; sh4r.r[Rn] <<= 1; :}
321 SHLR Rn {: sh4r.t = sh4r.r[Rn] & 0x00000001; sh4r.r[Rn] >>= 1; :}
322 SHLL2 Rn {: sh4r.r[Rn] <<= 2; :}
323 SHLR2 Rn {: sh4r.r[Rn] >>= 2; :}
324 SHLL8 Rn {: sh4r.r[Rn] <<= 8; :}
325 SHLR8 Rn {: sh4r.r[Rn] >>= 8; :}
326 SHLL16 Rn {: sh4r.r[Rn] <<= 16; :}
327 SHLR16 Rn {: sh4r.r[Rn] >>= 16; :}
329 EXTU.B Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]&0x000000FF; :}
330 EXTU.W Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]&0x0000FFFF; :}
331 EXTS.B Rm, Rn {: sh4r.r[Rn] = SIGNEXT8( sh4r.r[Rm]&0x000000FF ); :}
332 EXTS.W Rm, Rn {: sh4r.r[Rn] = SIGNEXT16( sh4r.r[Rm]&0x0000FFFF ); :}
333 SWAP.B Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rm]&0xFFFF0000) | ((sh4r.r[Rm]&0x0000FF00)>>8) | ((sh4r.r[Rm]&0x000000FF)<<8); :}
334 SWAP.W Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rm]>>16) | (sh4r.r[Rm]<<16); :}
336 CLRT {: sh4r.t = 0; :}
337 SETT {: sh4r.t = 1; :}
338 CLRMAC {: sh4r.mac = 0; :}
339 LDTLB {: MMU_ldtlb(); :}
340 CLRS {: sh4r.s = 0; :}
341 SETS {: sh4r.s = 1; :}
342 MOVT Rn {: sh4r.r[Rn] = sh4r.t; :}
347 if( (tmp & 0xFC000000) == 0xE0000000 ) {
348 sh4_flush_store_queue(tmp);
357 MEM_WRITE_LONG( tmp, R0 );
359 MOV.B Rm, @(R0, Rn) {: MEM_WRITE_BYTE( R0 + sh4r.r[Rn], sh4r.r[Rm] ); :}
360 MOV.W Rm, @(R0, Rn) {:
361 CHECKWALIGN16( R0 + sh4r.r[Rn] );
362 MEM_WRITE_WORD( R0 + sh4r.r[Rn], sh4r.r[Rm] );
364 MOV.L Rm, @(R0, Rn) {:
365 CHECKWALIGN32( R0 + sh4r.r[Rn] );
366 MEM_WRITE_LONG( R0 + sh4r.r[Rn], sh4r.r[Rm] );
368 MOV.B @(R0, Rm), Rn {: MEM_READ_BYTE( R0 + sh4r.r[Rm], sh4r.r[Rn] ); :}
369 MOV.W @(R0, Rm), Rn {: CHECKRALIGN16( R0 + sh4r.r[Rm] );
370 MEM_READ_WORD( R0 + sh4r.r[Rm], sh4r.r[Rn] );
372 MOV.L @(R0, Rm), Rn {: CHECKRALIGN32( R0 + sh4r.r[Rm] );
373 MEM_READ_LONG( R0 + sh4r.r[Rm], sh4r.r[Rn] );
375 MOV.L Rm, @(disp, Rn) {:
376 tmp = sh4r.r[Rn] + disp;
377 CHECKWALIGN32( tmp );
378 MEM_WRITE_LONG( tmp, sh4r.r[Rm] );
380 MOV.B Rm, @Rn {: MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] ); :}
381 MOV.W Rm, @Rn {: CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] ); :}
382 MOV.L Rm, @Rn {: CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] ); :}
383 MOV.B Rm, @-Rn {: MEM_WRITE_BYTE( sh4r.r[Rn]-1, sh4r.r[Rm] ); sh4r.r[Rn]--; :}
384 MOV.W Rm, @-Rn {: CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn]-2, sh4r.r[Rm] ); sh4r.r[Rn] -= 2; :}
385 MOV.L Rm, @-Rn {: CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.r[Rm] ); sh4r.r[Rn] -= 4; :}
386 MOV.L @(disp, Rm), Rn {:
387 tmp = sh4r.r[Rm] + disp;
388 CHECKRALIGN32( tmp );
389 MEM_READ_LONG( tmp, sh4r.r[Rn] );
391 MOV.B @Rm, Rn {: MEM_READ_BYTE( sh4r.r[Rm], sh4r.r[Rn] ); :}
392 MOV.W @Rm, Rn {: CHECKRALIGN16( sh4r.r[Rm] ); MEM_READ_WORD( sh4r.r[Rm], sh4r.r[Rn] ); :}
393 MOV.L @Rm, Rn {: CHECKRALIGN32( sh4r.r[Rm] ); MEM_READ_LONG( sh4r.r[Rm], sh4r.r[Rn] ); :}
394 MOV Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]; :}
395 MOV.B @Rm+, Rn {: MEM_READ_BYTE( sh4r.r[Rm], sh4r.r[Rn] ); sh4r.r[Rm] ++; :}
396 MOV.W @Rm+, Rn {: CHECKRALIGN16( sh4r.r[Rm] ); MEM_READ_WORD( sh4r.r[Rm], sh4r.r[Rn] ); sh4r.r[Rm] += 2; :}
397 MOV.L @Rm+, Rn {: CHECKRALIGN32( sh4r.r[Rm] ); MEM_READ_LONG( sh4r.r[Rm], sh4r.r[Rn] ); sh4r.r[Rm] += 4; :}
398 MOV.L @(disp, PC), Rn {:
400 tmp = (pc&0xFFFFFFFC) + disp + 4;
401 MEM_READ_LONG( tmp, sh4r.r[Rn] );
403 MOV.B R0, @(disp, GBR) {: MEM_WRITE_BYTE( sh4r.gbr + disp, R0 ); :}
404 MOV.W R0, @(disp, GBR) {:
405 tmp = sh4r.gbr + disp;
406 CHECKWALIGN16( tmp );
407 MEM_WRITE_WORD( tmp, R0 );
409 MOV.L R0, @(disp, GBR) {:
410 tmp = sh4r.gbr + disp;
411 CHECKWALIGN32( tmp );
412 MEM_WRITE_LONG( tmp, R0 );
414 MOV.B @(disp, GBR), R0 {: MEM_READ_BYTE( sh4r.gbr + disp, R0 ); :}
415 MOV.W @(disp, GBR), R0 {:
416 tmp = sh4r.gbr + disp;
417 CHECKRALIGN16( tmp );
418 MEM_READ_WORD( tmp, R0 );
420 MOV.L @(disp, GBR), R0 {:
421 tmp = sh4r.gbr + disp;
422 CHECKRALIGN32( tmp );
423 MEM_READ_LONG( tmp, R0 );
425 MOV.B R0, @(disp, Rn) {: MEM_WRITE_BYTE( sh4r.r[Rn] + disp, R0 ); :}
426 MOV.W R0, @(disp, Rn) {:
427 tmp = sh4r.r[Rn] + disp;
428 CHECKWALIGN16( tmp );
429 MEM_WRITE_WORD( tmp, R0 );
431 MOV.B @(disp, Rm), R0 {: MEM_READ_BYTE( sh4r.r[Rm] + disp, R0 ); :}
432 MOV.W @(disp, Rm), R0 {:
433 tmp = sh4r.r[Rm] + disp;
434 CHECKRALIGN16( tmp );
435 MEM_READ_WORD( tmp, R0 );
437 MOV.W @(disp, PC), Rn {:
440 MEM_READ_WORD( tmp, sh4r.r[Rn] );
442 MOVA @(disp, PC), R0 {:
444 R0 = (pc&0xFFFFFFFC) + disp + 4;
446 MOV #imm, Rn {: sh4r.r[Rn] = imm; :}
448 CMP/EQ #imm, R0 {: sh4r.t = ( R0 == imm ? 1 : 0 ); :}
449 CMP/EQ Rm, Rn {: sh4r.t = ( sh4r.r[Rm] == sh4r.r[Rn] ? 1 : 0 ); :}
450 CMP/GE Rm, Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= ((int32_t)sh4r.r[Rm]) ? 1 : 0 ); :}
451 CMP/GT Rm, Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) > ((int32_t)sh4r.r[Rm]) ? 1 : 0 ); :}
452 CMP/HI Rm, Rn {: sh4r.t = ( sh4r.r[Rn] > sh4r.r[Rm] ? 1 : 0 ); :}
453 CMP/HS Rm, Rn {: sh4r.t = ( sh4r.r[Rn] >= sh4r.r[Rm] ? 1 : 0 ); :}
454 CMP/PL Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) > 0 ? 1 : 0 ); :}
455 CMP/PZ Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= 0 ? 1 : 0 ); :}
457 /* set T = 1 if any byte in RM & RN is the same */
458 tmp = sh4r.r[Rm] ^ sh4r.r[Rn];
459 sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
460 (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
463 ADD Rm, Rn {: sh4r.r[Rn] += sh4r.r[Rm]; :}
464 ADD #imm, Rn {: sh4r.r[Rn] += imm; :}
467 sh4r.r[Rn] += sh4r.r[Rm] + sh4r.t;
468 sh4r.t = ( sh4r.r[Rn] < tmp || (sh4r.r[Rn] == tmp && sh4r.t != 0) ? 1 : 0 );
471 tmp = sh4r.r[Rn] + sh4r.r[Rm];
472 sh4r.t = ( (sh4r.r[Rn]>>31) == (sh4r.r[Rm]>>31) && ((sh4r.r[Rn]>>31) != (tmp>>31)) );
475 DIV0U {: sh4r.m = sh4r.q = sh4r.t = 0; :}
477 sh4r.q = sh4r.r[Rn]>>31;
478 sh4r.m = sh4r.r[Rm]>>31;
479 sh4r.t = sh4r.q ^ sh4r.m;
482 /* This is derived from the sh4 manual with some simplifications */
483 uint32_t tmp0, tmp1, tmp2, dir;
485 dir = sh4r.q ^ sh4r.m;
486 sh4r.q = (sh4r.r[Rn] >> 31);
488 sh4r.r[Rn] = (sh4r.r[Rn] << 1) | sh4r.t;
492 tmp1 = (sh4r.r[Rn]<tmp0 ? 1 : 0 );
495 tmp1 = (sh4r.r[Rn]>tmp0 ? 1 : 0 );
497 sh4r.q ^= sh4r.m ^ tmp1;
498 sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
500 DMULS.L Rm, Rn {: sh4r.mac = SIGNEXT32(sh4r.r[Rm]) * SIGNEXT32(sh4r.r[Rn]); :}
501 DMULU.L Rm, Rn {: sh4r.mac = ((uint64_t)sh4r.r[Rm]) * ((uint64_t)sh4r.r[Rn]); :}
504 sh4r.t = ( sh4r.r[Rn] == 0 ? 1 : 0 );
509 CHECKRALIGN16(sh4r.r[Rn]);
510 MEM_READ_WORD( sh4r.r[Rn], tmp );
511 stmp = SIGNEXT16(tmp);
512 MEM_READ_WORD( sh4r.r[Rn]+2, tmp );
513 stmp *= SIGNEXT16(tmp);
516 CHECKRALIGN16( sh4r.r[Rn] );
517 CHECKRALIGN16( sh4r.r[Rm] );
518 MEM_READ_WORD(sh4r.r[Rn], tmp);
519 stmp = SIGNEXT16(tmp);
520 MEM_READ_WORD(sh4r.r[Rm], tmp);
521 stmp = stmp * SIGNEXT16(tmp);
526 int64_t tmpl = (int64_t)((int32_t)sh4r.mac) + (int64_t)stmp;
527 if( tmpl > (int64_t)0x000000007FFFFFFFLL ) {
528 sh4r.mac = 0x000000017FFFFFFFLL;
529 } else if( tmpl < (int64_t)0xFFFFFFFF80000000LL ) {
530 sh4r.mac = 0x0000000180000000LL;
532 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
533 ((uint32_t)(sh4r.mac + stmp));
536 sh4r.mac += SIGNEXT32(stmp);
542 CHECKRALIGN32( sh4r.r[Rn] );
543 MEM_READ_LONG(sh4r.r[Rn], tmp);
544 tmpl = SIGNEXT32(tmp);
545 MEM_READ_LONG(sh4r.r[Rn]+4, tmp);
546 tmpl = tmpl * SIGNEXT32(tmp) + sh4r.mac;
549 CHECKRALIGN32( sh4r.r[Rm] );
550 CHECKRALIGN32( sh4r.r[Rn] );
551 MEM_READ_LONG(sh4r.r[Rn], tmp);
552 tmpl = SIGNEXT32(tmp);
553 MEM_READ_LONG(sh4r.r[Rm], tmp);
554 tmpl = tmpl * SIGNEXT32(tmp) + sh4r.mac;
559 /* 48-bit Saturation. Yuch */
560 if( tmpl < (int64_t)0xFFFF800000000000LL )
561 tmpl = 0xFFFF800000000000LL;
562 else if( tmpl > (int64_t)0x00007FFFFFFFFFFFLL )
563 tmpl = 0x00007FFFFFFFFFFFLL;
567 MUL.L Rm, Rn {: sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
568 (sh4r.r[Rm] * sh4r.r[Rn]); :}
570 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
571 (uint32_t)((sh4r.r[Rm]&0xFFFF) * (sh4r.r[Rn]&0xFFFF));
574 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
575 (uint32_t)(SIGNEXT32(sh4r.r[Rm]&0xFFFF) * SIGNEXT32(sh4r.r[Rn]&0xFFFF));
578 tmp = 0 - sh4r.r[Rm];
579 sh4r.r[Rn] = tmp - sh4r.t;
580 sh4r.t = ( 0<tmp || tmp<sh4r.r[Rn] ? 1 : 0 );
582 NEG Rm, Rn {: sh4r.r[Rn] = 0 - sh4r.r[Rm]; :}
583 SUB Rm, Rn {: sh4r.r[Rn] -= sh4r.r[Rm]; :}
586 sh4r.r[Rn] = sh4r.r[Rn] - sh4r.r[Rm] - sh4r.t;
587 sh4r.t = (sh4r.r[Rn] > tmp || (sh4r.r[Rn] == tmp && sh4r.t == 1));
592 CHECKDEST( pc + 4 + sh4r.r[Rn] );
593 sh4r.in_delay_slot = 1;
594 sh4r.pc = sh4r.new_pc;
595 sh4r.new_pc = pc + 4 + sh4r.r[Rn];
600 CHECKDEST( pc + 4 + sh4r.r[Rn] );
601 sh4r.in_delay_slot = 1;
602 sh4r.pr = sh4r.pc + 4;
603 sh4r.pc = sh4r.new_pc;
604 sh4r.new_pc = pc + 4 + sh4r.r[Rn];
605 TRACE_CALL( pc, sh4r.new_pc );
611 CHECKDEST( sh4r.pc + disp + 4 )
613 sh4r.new_pc = sh4r.pc + 2;
620 CHECKDEST( sh4r.pc + disp + 4 )
622 sh4r.new_pc = sh4r.pc + 2;
629 CHECKDEST( sh4r.pc + disp + 4 )
630 sh4r.in_delay_slot = 1;
631 sh4r.pc = sh4r.new_pc;
632 sh4r.new_pc = pc + disp + 4;
633 sh4r.in_delay_slot = 1;
640 CHECKDEST( sh4r.pc + disp + 4 )
641 sh4r.in_delay_slot = 1;
642 sh4r.pc = sh4r.new_pc;
643 sh4r.new_pc = pc + disp + 4;
649 CHECKDEST( sh4r.pc + disp + 4 );
650 sh4r.in_delay_slot = 1;
651 sh4r.pc = sh4r.new_pc;
652 sh4r.new_pc = pc + 4 + disp;
656 CHECKDEST( sh4r.pc + disp + 4 );
658 sh4r.in_delay_slot = 1;
660 sh4r.pc = sh4r.new_pc;
661 sh4r.new_pc = pc + 4 + disp;
662 TRACE_CALL( pc, sh4r.new_pc );
668 sh4_raise_trap( imm );
673 CHECKDEST( sh4r.pr );
674 sh4r.in_delay_slot = 1;
675 sh4r.pc = sh4r.new_pc;
676 sh4r.new_pc = sh4r.pr;
677 TRACE_RETURN( pc, sh4r.new_pc );
681 if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
682 sh4r.sh4_state = SH4_STATE_STANDBY;
684 sh4r.sh4_state = SH4_STATE_SLEEP;
686 return FALSE; /* Halt CPU */
690 CHECKDEST( sh4r.spc );
692 sh4r.in_delay_slot = 1;
693 sh4r.pc = sh4r.new_pc;
694 sh4r.new_pc = sh4r.spc;
695 sh4_write_sr( sh4r.ssr );
699 CHECKDEST( sh4r.r[Rn] );
701 sh4r.in_delay_slot = 1;
702 sh4r.pc = sh4r.new_pc;
703 sh4r.new_pc = sh4r.r[Rn];
707 CHECKDEST( sh4r.r[Rn] );
709 sh4r.in_delay_slot = 1;
710 sh4r.pc = sh4r.new_pc;
711 sh4r.new_pc = sh4r.r[Rn];
713 TRACE_CALL( pc, sh4r.new_pc );
716 STS MACH, Rn {: sh4r.r[Rn] = (sh4r.mac>>32); :}
718 CHECKWALIGN32( sh4r.r[Rn] );
719 MEM_WRITE_LONG( sh4r.r[Rn]-4, (sh4r.mac>>32) );
724 CHECKWALIGN32( sh4r.r[Rn] );
725 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4_read_sr() );
729 CHECKRALIGN32( sh4r.r[Rm] );
730 MEM_READ_LONG(sh4r.r[Rm], tmp);
731 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
732 (((uint64_t)tmp)<<32);
738 CHECKWALIGN32( sh4r.r[Rm] );
739 MEM_READ_LONG(sh4r.r[Rm], tmp);
744 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
745 (((uint64_t)sh4r.r[Rm])<<32);
750 sh4_write_sr( sh4r.r[Rm] );
754 sh4r.sgr = sh4r.r[Rm];
758 CHECKRALIGN32( sh4r.r[Rm] );
759 MEM_READ_LONG(sh4r.r[Rm], sh4r.sgr);
762 STS MACL, Rn {: sh4r.r[Rn] = (uint32_t)sh4r.mac; :}
764 CHECKWALIGN32( sh4r.r[Rn] );
765 MEM_WRITE_LONG( sh4r.r[Rn]-4, (uint32_t)sh4r.mac );
769 CHECKWALIGN32( sh4r.r[Rn] );
770 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.gbr );
774 CHECKRALIGN32( sh4r.r[Rm] );
775 MEM_READ_LONG(sh4r.r[Rm], tmp);
776 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
777 (uint64_t)((uint32_t)tmp);
781 CHECKRALIGN32( sh4r.r[Rm] );
782 MEM_READ_LONG(sh4r.r[Rm], sh4r.gbr);
786 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
787 (uint64_t)((uint32_t)(sh4r.r[Rm]));
789 LDC Rm, GBR {: sh4r.gbr = sh4r.r[Rm]; :}
790 STS PR, Rn {: sh4r.r[Rn] = sh4r.pr; :}
792 CHECKWALIGN32( sh4r.r[Rn] );
793 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.pr );
798 CHECKWALIGN32( sh4r.r[Rn] );
799 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.vbr );
803 CHECKRALIGN32( sh4r.r[Rm] );
804 MEM_READ_LONG( sh4r.r[Rm], sh4r.pr );
809 CHECKRALIGN32( sh4r.r[Rm] );
810 MEM_READ_LONG(sh4r.r[Rm], sh4r.vbr);
813 LDS Rm, PR {: sh4r.pr = sh4r.r[Rm]; :}
816 sh4r.vbr = sh4r.r[Rm];
820 sh4r.r[Rn] = sh4r.sgr;
824 CHECKWALIGN32( sh4r.r[Rn] );
825 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.sgr );
830 CHECKWALIGN32( sh4r.r[Rn] );
831 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.ssr );
836 CHECKRALIGN32( sh4r.r[Rm] );
837 MEM_READ_LONG(sh4r.r[Rm], sh4r.ssr);
842 sh4r.ssr = sh4r.r[Rm];
846 CHECKWALIGN32( sh4r.r[Rn] );
847 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.spc );
852 CHECKRALIGN32( sh4r.r[Rm] );
853 MEM_READ_LONG(sh4r.r[Rm], sh4r.spc);
858 sh4r.spc = sh4r.r[Rm];
866 CHECKWALIGN32( sh4r.r[Rn] );
867 MEM_WRITE_LONG( sh4r.r[Rn]-4, FPULi );
872 CHECKRALIGN32( sh4r.r[Rm] );
873 MEM_READ_LONG(sh4r.r[Rm], FPULi);
882 sh4r.r[Rn] = sh4r.fpscr;
886 CHECKWALIGN32( sh4r.r[Rn] );
887 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.fpscr );
892 CHECKRALIGN32( sh4r.r[Rm] );
893 MEM_READ_LONG(sh4r.r[Rm], tmp);
895 sh4_write_fpscr( tmp );
899 sh4_write_fpscr( sh4r.r[Rm] );
901 STC DBR, Rn {: CHECKPRIV(); sh4r.r[Rn] = sh4r.dbr; :}
904 CHECKWALIGN32( sh4r.r[Rn] );
905 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.dbr );
910 CHECKRALIGN32( sh4r.r[Rm] );
911 MEM_READ_LONG(sh4r.r[Rm], sh4r.dbr);
916 sh4r.dbr = sh4r.r[Rm];
918 STC.L Rm_BANK, @-Rn {:
920 CHECKWALIGN32( sh4r.r[Rn] );
921 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.r_bank[Rm_BANK] );
924 LDC.L @Rm+, Rn_BANK {:
926 CHECKRALIGN32( sh4r.r[Rm] );
927 MEM_READ_LONG( sh4r.r[Rm], sh4r.r_bank[Rn_BANK] );
932 sh4r.r_bank[Rn_BANK] = sh4r.r[Rm];
936 sh4r.r[Rn] = sh4_read_sr();
939 sh4r.r[Rn] = sh4r.gbr;
943 sh4r.r[Rn] = sh4r.vbr;
947 sh4r.r[Rn] = sh4r.ssr;
951 sh4r.r[Rn] = sh4r.spc;
955 sh4r.r[Rn] = sh4r.r_bank[Rm_BANK];
960 if( IS_FPU_DOUBLEPREC() ) {
968 if( IS_FPU_DOUBLEPREC() ) {
977 if( IS_FPU_DOUBLEPREC() ) {
986 if( IS_FPU_DOUBLEPREC() ) {
995 if( IS_FPU_DOUBLEPREC() ) {
996 sh4r.t = ( DR(FRn) == DR(FRm) ? 1 : 0 );
998 sh4r.t = ( FR(FRn) == FR(FRm) ? 1 : 0 );
1004 if( IS_FPU_DOUBLEPREC() ) {
1005 sh4r.t = ( DR(FRn) > DR(FRm) ? 1 : 0 );
1007 sh4r.t = ( FR(FRn) > FR(FRm) ? 1 : 0 );
1011 FMOV @(R0, Rm), FRn {: MEM_FP_READ( sh4r.r[Rm] + R0, FRn ); :}
1012 FMOV FRm, @(R0, Rn) {: MEM_FP_WRITE( sh4r.r[Rn] + R0, FRm ); :}
1013 FMOV @Rm, FRn {: MEM_FP_READ( sh4r.r[Rm], FRn ); :}
1014 FMOV @Rm+, FRn {: MEM_FP_READ( sh4r.r[Rm], FRn ); sh4r.r[Rm] += FP_WIDTH; :}
1015 FMOV FRm, @Rn {: MEM_FP_WRITE( sh4r.r[Rn], FRm ); :}
1016 FMOV FRm, @-Rn {: MEM_FP_WRITE( sh4r.r[Rn] - FP_WIDTH, FRm ); sh4r.r[Rn] -= FP_WIDTH; :}
1018 if( IS_FPU_DOUBLESIZE() )
1023 FSTS FPUL, FRn {: CHECKFPUEN(); FR(FRn) = FPULf; :}
1024 FLDS FRm, FPUL {: CHECKFPUEN(); FPULf = FR(FRm); :}
1027 if( IS_FPU_DOUBLEPREC() ) {
1028 if( FRn&1 ) { // No, really...
1029 dtmp = (double)FPULi;
1030 FR(FRn) = *(((float *)&dtmp)+1);
1032 DRF(FRn>>1) = (double)FPULi;
1035 FR(FRn) = (float)FPULi;
1040 if( IS_FPU_DOUBLEPREC() ) {
1043 *(((float *)&dtmp)+1) = FR(FRm);
1047 if( dtmp >= MAX_INTF )
1049 else if( dtmp <= MIN_INTF )
1052 FPULi = (int32_t)dtmp;
1055 if( ftmp >= MAX_INTF )
1057 else if( ftmp <= MIN_INTF )
1060 FPULi = (int32_t)ftmp;
1065 if( IS_FPU_DOUBLEPREC() ) {
1073 if( IS_FPU_DOUBLEPREC() ) {
1074 DR(FRn) = fabs(DR(FRn));
1076 FR(FRn) = fabsf(FR(FRn));
1081 if( IS_FPU_DOUBLEPREC() ) {
1082 DR(FRn) = sqrt(DR(FRn));
1084 FR(FRn) = sqrtf(FR(FRn));
1089 if( IS_FPU_DOUBLEPREC() ) {
1097 if( IS_FPU_DOUBLEPREC() ) {
1103 FMAC FR0, FRm, FRn {:
1105 if( IS_FPU_DOUBLEPREC() ) {
1106 DR(FRn) += DR(FRm)*DR(0);
1108 FR(FRn) += FR(FRm)*FR(0);
1113 sh4r.fpscr ^= FPSCR_FR;
1114 sh4_switch_fr_banks();
1116 FSCHG {: CHECKFPUEN(); sh4r.fpscr ^= FPSCR_SZ; :}
1119 if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
1120 DR(FRn) = (double)FPULf;
1125 if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
1126 FPULf = (float)DR(FRm);
1132 if( !IS_FPU_DOUBLEPREC() ) {
1133 FR(FRn) = 1.0/sqrtf(FR(FRn));
1138 if( !IS_FPU_DOUBLEPREC() ) {
1141 FR(tmp2+3) = FR(tmp)*FR(tmp2) +
1142 FR(tmp+1)*FR(tmp2+1) +
1143 FR(tmp+2)*FR(tmp2+2) +
1144 FR(tmp+3)*FR(tmp2+3);
1149 if( !IS_FPU_DOUBLEPREC() ) {
1150 sh4_fsca( FPULi, &(DRF(FRn>>1)) );
1152 float angle = (((float)(FPULi&0xFFFF))/65536.0) * 2 * M_PI;
1153 FR(FRn) = sinf(angle);
1154 FR((FRn)+1) = cosf(angle);
1160 if( !IS_FPU_DOUBLEPREC() ) {
1161 sh4_ftrv(&(DRF(FVn<<1)) );
1168 sh4r.pc = sh4r.new_pc;
1170 sh4r.in_delay_slot = 0;
.