filename | src/pvr2/pvr2.c |
changeset | 856:02ac5f37bfc9 |
prev | 851:41e8ae2c114b |
next | 867:3af8840d5d8c |
author | nkeynes |
date | Sun Sep 28 01:09:51 2008 +0000 (15 years ago) |
permissions | -rw-r--r-- |
last change | Initial shadow volume implementation for opaque polygons (stencil isn't quite right, but we get some kind of shadows now) |
view | annotate | diff | log | raw |
1 /**
2 * $Id$
3 *
4 * PVR2 (Video) Core module implementation and MMIO registers.
5 *
6 * Copyright (c) 2005 Nathan Keynes.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18 #define MODULE pvr2_module
20 #include <assert.h>
21 #include "dream.h"
22 #include "eventq.h"
23 #include "display.h"
24 #include "mem.h"
25 #include "asic.h"
26 #include "clock.h"
27 #include "pvr2/pvr2.h"
28 #include "pvr2/pvr2mmio.h"
29 #include "pvr2/scene.h"
30 #include "sh4/sh4.h"
31 #define MMIO_IMPL
32 #include "pvr2/pvr2mmio.h"
34 unsigned char *video_base;
36 #define MAX_RENDER_BUFFERS 4
38 #define HPOS_PER_FRAME 0
39 #define HPOS_PER_LINECOUNT 1
41 static void pvr2_init( void );
42 static void pvr2_reset( void );
43 static uint32_t pvr2_run_slice( uint32_t );
44 static void pvr2_save_state( FILE *f );
45 static int pvr2_load_state( FILE *f );
46 static void pvr2_update_raster_posn( uint32_t nanosecs );
47 static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int line_time_ns );
48 static render_buffer_t pvr2_get_render_buffer( frame_buffer_t frame );
49 static render_buffer_t pvr2_next_render_buffer( );
50 static render_buffer_t pvr2_frame_buffer_to_render_buffer( frame_buffer_t frame );
51 uint32_t pvr2_get_sync_status();
53 void pvr2_display_frame( void );
55 static int output_colour_formats[] = { COLFMT_BGRA1555, COLFMT_RGB565, COLFMT_BGR888, COLFMT_BGRA8888 };
56 static int render_colour_formats[8] = {
57 COLFMT_BGRA1555, COLFMT_RGB565, COLFMT_BGRA4444, COLFMT_BGRA1555,
58 COLFMT_BGR888, COLFMT_BGRA8888, COLFMT_BGRA8888, COLFMT_BGRA4444 };
61 struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, pvr2_reset, NULL,
62 pvr2_run_slice, NULL,
63 pvr2_save_state, pvr2_load_state };
66 display_driver_t display_driver = NULL;
68 struct pvr2_state {
69 uint32_t frame_count;
70 uint32_t line_count;
71 uint32_t line_remainder;
72 uint32_t cycles_run; /* Cycles already executed prior to main time slice */
73 uint32_t irq_hpos_line;
74 uint32_t irq_hpos_line_count;
75 uint32_t irq_hpos_mode;
76 uint32_t irq_hpos_time_ns; /* Time within the line */
77 uint32_t irq_vpos1;
78 uint32_t irq_vpos2;
79 uint32_t odd_even_field; /* 1 = odd, 0 = even */
80 int32_t palette_changed; /* TRUE if palette has changed since last render */
81 /* timing */
82 uint32_t dot_clock;
83 uint32_t total_lines;
84 uint32_t line_size;
85 uint32_t line_time_ns;
86 uint32_t vsync_lines;
87 uint32_t hsync_width_ns;
88 uint32_t front_porch_ns;
89 uint32_t back_porch_ns;
90 uint32_t retrace_start_line;
91 uint32_t retrace_end_line;
92 int32_t interlaced;
93 } pvr2_state;
95 static gchar *save_next_render_filename;
96 static render_buffer_t render_buffers[MAX_RENDER_BUFFERS];
97 static uint32_t render_buffer_count = 0;
98 static render_buffer_t displayed_render_buffer = NULL;
99 static uint32_t displayed_border_colour = 0;
101 /**
102 * Event handler for the hpos callback
103 */
104 static void pvr2_hpos_callback( int eventid ) {
105 asic_event( eventid );
106 pvr2_update_raster_posn(sh4r.slice_cycle);
107 if( pvr2_state.irq_hpos_mode == HPOS_PER_LINECOUNT ) {
108 pvr2_state.irq_hpos_line += pvr2_state.irq_hpos_line_count;
109 while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {
110 pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);
111 }
112 }
113 pvr2_schedule_scanline_event( eventid, pvr2_state.irq_hpos_line, 1,
114 pvr2_state.irq_hpos_time_ns );
115 }
117 /**
118 * Event handler for the scanline callbacks. Fires the corresponding
119 * ASIC event, and resets the timer for the next field.
120 */
121 static void pvr2_scanline_callback( int eventid )
122 {
123 asic_event( eventid );
124 pvr2_update_raster_posn(sh4r.slice_cycle);
125 if( eventid == EVENT_SCANLINE1 ) {
126 pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos1, 1, 0 );
127 } else {
128 pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos2, 1, 0 );
129 }
130 }
132 static void pvr2_gunpos_callback( int eventid )
133 {
134 pvr2_update_raster_posn(sh4r.slice_cycle);
135 int hpos = pvr2_state.line_remainder * pvr2_state.dot_clock / 1000000;
136 MMIO_WRITE( PVR2, GUNPOS, ((pvr2_state.line_count<<16)|(hpos&0x3FF)) );
137 asic_event( EVENT_MAPLE_DMA );
138 }
140 static void pvr2_init( void )
141 {
142 int i;
143 register_io_region( &mmio_region_PVR2 );
144 register_io_region( &mmio_region_PVR2PAL );
145 register_io_region( &mmio_region_PVR2TA );
146 register_event_callback( EVENT_HPOS, pvr2_hpos_callback );
147 register_event_callback( EVENT_SCANLINE1, pvr2_scanline_callback );
148 register_event_callback( EVENT_SCANLINE2, pvr2_scanline_callback );
149 register_event_callback( EVENT_GUNPOS, pvr2_gunpos_callback );
150 video_base = mem_get_region_by_name( MEM_REGION_VIDEO );
151 texcache_init();
152 pvr2_reset();
153 pvr2_ta_reset();
154 save_next_render_filename = NULL;
155 for( i=0; i<MAX_RENDER_BUFFERS; i++ ) {
156 render_buffers[i] = NULL;
157 }
158 render_buffer_count = 0;
159 displayed_render_buffer = NULL;
160 displayed_border_colour = 0;
161 }
163 static void pvr2_reset( void )
164 {
165 int i;
166 pvr2_state.line_count = 0;
167 pvr2_state.line_remainder = 0;
168 pvr2_state.cycles_run = 0;
169 pvr2_state.irq_vpos1 = 0;
170 pvr2_state.irq_vpos2 = 0;
171 pvr2_state.dot_clock = PVR2_DOT_CLOCK;
172 pvr2_state.back_porch_ns = 4000;
173 pvr2_state.palette_changed = FALSE;
174 mmio_region_PVR2_write( DISP_TOTAL, 0x0270035F );
175 mmio_region_PVR2_write( DISP_SYNCTIME, 0x07D6A53F );
176 mmio_region_PVR2_write( YUV_ADDR, 0 );
177 mmio_region_PVR2_write( YUV_CFG, 0 );
179 pvr2_ta_init();
180 texcache_flush();
181 if( display_driver ) {
182 display_driver->display_blank(0);
183 for( i=0; i<render_buffer_count; i++ ) {
184 display_driver->destroy_render_buffer(render_buffers[i]);
185 render_buffers[i] = NULL;
186 }
187 render_buffer_count = 0;
188 }
189 }
191 void pvr2_save_render_buffer( FILE *f, render_buffer_t buffer )
192 {
193 struct frame_buffer fbuf;
195 fbuf.width = buffer->width;
196 fbuf.height = buffer->height;
197 fbuf.rowstride = fbuf.width*3;
198 fbuf.colour_format = COLFMT_BGR888;
199 fbuf.inverted = buffer->inverted;
200 fbuf.data = g_malloc0( buffer->width * buffer->height * 3 );
202 display_driver->read_render_buffer( fbuf.data, buffer, fbuf.rowstride, COLFMT_BGR888 );
203 write_png_to_stream( f, &fbuf );
204 g_free( fbuf.data );
206 fwrite( &buffer->rowstride, sizeof(buffer->rowstride), 1, f );
207 fwrite( &buffer->colour_format, sizeof(buffer->colour_format), 1, f );
208 fwrite( &buffer->address, sizeof(buffer->address), 1, f );
209 fwrite( &buffer->scale, sizeof(buffer->scale), 1, f );
210 int32_t flushed = (int32_t)buffer->flushed; // Force to 32-bits for save-file consistency
211 fwrite( &flushed, sizeof(flushed), 1, f );
213 }
215 render_buffer_t pvr2_load_render_buffer( FILE *f )
216 {
217 frame_buffer_t frame = read_png_from_stream( f );
218 if( frame == NULL ) {
219 return NULL;
220 }
222 render_buffer_t buffer = pvr2_frame_buffer_to_render_buffer(frame);
223 if( buffer != NULL ) {
224 int32_t flushed;
225 fread( &buffer->rowstride, sizeof(buffer->rowstride), 1, f );
226 fread( &buffer->colour_format, sizeof(buffer->colour_format), 1, f );
227 fread( &buffer->address, sizeof(buffer->address), 1, f );
228 fread( &buffer->scale, sizeof(buffer->scale), 1, f );
229 fread( &flushed, sizeof(flushed), 1, f );
230 buffer->flushed = (gboolean)flushed;
231 } else {
232 fseek( f, sizeof(buffer->rowstride)+sizeof(buffer->colour_format)+
233 sizeof(buffer->address)+sizeof(buffer->scale)+
234 sizeof(int32_t), SEEK_CUR );
235 }
236 return buffer;
237 }
242 void pvr2_save_render_buffers( FILE *f )
243 {
244 int i;
245 uint32_t has_frontbuffer;
246 fwrite( &render_buffer_count, sizeof(render_buffer_count), 1, f );
247 if( displayed_render_buffer != NULL ) {
248 has_frontbuffer = 1;
249 fwrite( &has_frontbuffer, sizeof(has_frontbuffer), 1, f );
250 pvr2_save_render_buffer( f, displayed_render_buffer );
251 } else {
252 has_frontbuffer = 0;
253 fwrite( &has_frontbuffer, sizeof(has_frontbuffer), 1, f );
254 }
256 for( i=0; i<render_buffer_count; i++ ) {
257 if( render_buffers[i] != displayed_render_buffer && render_buffers[i] != NULL ) {
258 pvr2_save_render_buffer( f, render_buffers[i] );
259 }
260 }
261 }
263 gboolean pvr2_load_render_buffers( FILE *f )
264 {
265 uint32_t count, has_frontbuffer;
266 int i;
268 fread( &count, sizeof(count), 1, f );
269 if( count > MAX_RENDER_BUFFERS ) {
270 return FALSE;
271 }
272 fread( &has_frontbuffer, sizeof(has_frontbuffer), 1, f );
273 for( i=0; i<render_buffer_count; i++ ) {
274 display_driver->destroy_render_buffer(render_buffers[i]);
275 render_buffers[i] = NULL;
276 }
277 render_buffer_count = 0;
279 if( has_frontbuffer ) {
280 displayed_render_buffer = pvr2_load_render_buffer(f);
281 display_driver->display_render_buffer( displayed_render_buffer );
282 count--;
283 }
285 for( i=0; i<count; i++ ) {
286 pvr2_load_render_buffer( f );
287 }
288 return TRUE;
289 }
292 static void pvr2_save_state( FILE *f )
293 {
294 pvr2_save_render_buffers( f );
295 fwrite( &pvr2_state, sizeof(pvr2_state), 1, f );
296 pvr2_ta_save_state( f );
297 pvr2_yuv_save_state( f );
298 }
300 static int pvr2_load_state( FILE *f )
301 {
302 if( !pvr2_load_render_buffers(f) )
303 return 1;
304 if( fread( &pvr2_state, sizeof(pvr2_state), 1, f ) != 1 )
305 return 1;
306 if( pvr2_ta_load_state(f) ) {
307 return 1;
308 }
309 return pvr2_yuv_load_state(f);
310 }
312 /**
313 * Update the current raster position to the given number of nanoseconds,
314 * relative to the last time slice. (ie the raster will be adjusted forward
315 * by nanosecs - nanosecs_already_run_this_timeslice)
316 */
317 static void pvr2_update_raster_posn( uint32_t nanosecs )
318 {
319 uint32_t old_line_count = pvr2_state.line_count;
320 if( pvr2_state.line_time_ns == 0 ) {
321 return; /* do nothing */
322 }
323 pvr2_state.line_remainder += (nanosecs - pvr2_state.cycles_run);
324 pvr2_state.cycles_run = nanosecs;
325 while( pvr2_state.line_remainder >= pvr2_state.line_time_ns ) {
326 pvr2_state.line_count ++;
327 pvr2_state.line_remainder -= pvr2_state.line_time_ns;
328 }
330 if( pvr2_state.line_count >= pvr2_state.total_lines ) {
331 pvr2_state.line_count -= pvr2_state.total_lines;
332 if( pvr2_state.interlaced ) {
333 pvr2_state.odd_even_field = !pvr2_state.odd_even_field;
334 }
335 }
336 if( pvr2_state.line_count >= pvr2_state.retrace_end_line &&
337 (old_line_count < pvr2_state.retrace_end_line ||
338 old_line_count > pvr2_state.line_count) ) {
339 pvr2_state.frame_count++;
340 pvr2_display_frame();
341 }
342 }
344 static uint32_t pvr2_run_slice( uint32_t nanosecs )
345 {
346 pvr2_update_raster_posn( nanosecs );
347 pvr2_state.cycles_run = 0;
348 return nanosecs;
349 }
351 int pvr2_get_frame_count()
352 {
353 return pvr2_state.frame_count;
354 }
356 void pvr2_redraw_display()
357 {
358 if( display_driver != NULL ) {
359 if( displayed_render_buffer == NULL ) {
360 display_driver->display_blank(displayed_border_colour);
361 } else {
362 display_driver->display_render_buffer(displayed_render_buffer);
363 }
364 }
365 }
367 gboolean pvr2_save_next_scene( const gchar *filename )
368 {
369 if( save_next_render_filename != NULL ) {
370 g_free( save_next_render_filename );
371 }
372 save_next_render_filename = g_strdup(filename);
373 return TRUE;
374 }
378 /**
379 * Display the next frame, copying the current contents of video ram to
380 * the window. If the video configuration has changed, first recompute the
381 * new frame size/depth.
382 */
383 void pvr2_display_frame( void )
384 {
385 int dispmode = MMIO_READ( PVR2, DISP_MODE );
386 int vidcfg = MMIO_READ( PVR2, DISP_SYNCCFG );
387 gboolean bEnabled = (dispmode & DISPMODE_ENABLE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE;
389 if( display_driver == NULL ) {
390 return; /* can't really do anything much */
391 } else if( !bEnabled ) {
392 /* Output disabled == black */
393 displayed_render_buffer = NULL;
394 displayed_border_colour = 0;
395 display_driver->display_blank( 0 );
396 } else if( MMIO_READ( PVR2, DISP_CFG2 ) & 0x08 ) {
397 /* Enabled but blanked - border colour */
398 displayed_border_colour = MMIO_READ( PVR2, DISP_BORDER );
399 displayed_render_buffer = NULL;
400 display_driver->display_blank( displayed_border_colour );
401 } else {
402 /* Real output - determine dimensions etc */
403 struct frame_buffer fbuf;
404 uint32_t dispsize = MMIO_READ( PVR2, DISP_SIZE );
405 int vid_stride = (((dispsize & DISPSIZE_MODULO) >> 20) - 1);
406 int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
408 fbuf.colour_format = output_colour_formats[(dispmode & DISPMODE_COLFMT) >> 2];
409 fbuf.width = vid_ppl << 2 / colour_formats[fbuf.colour_format].bpp;
410 fbuf.height = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
411 fbuf.size = vid_ppl << 2 * fbuf.height;
412 fbuf.rowstride = (vid_ppl + vid_stride) << 2;
414 /* Determine the field to display, and deinterlace if possible */
415 if( pvr2_state.interlaced ) {
416 if( vid_ppl == vid_stride ) { /* Magic deinterlace */
417 fbuf.height = fbuf.height << 1;
418 fbuf.rowstride = vid_ppl << 2;
419 fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
420 } else {
421 /* Just display the field as is, folks. This is slightly tricky -
422 * we pick the field based on which frame is about to come through,
423 * which may not be the same as the odd_even_field.
424 */
425 gboolean oddfield = pvr2_state.odd_even_field;
426 if( pvr2_state.line_count >= pvr2_state.retrace_start_line ) {
427 oddfield = !oddfield;
428 }
429 if( oddfield ) {
430 fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
431 } else {
432 fbuf.address = MMIO_READ( PVR2, DISP_ADDR2 );
433 }
434 }
435 } else {
436 fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
437 }
438 fbuf.address = (fbuf.address & 0x00FFFFFF) + PVR2_RAM_BASE;
439 fbuf.inverted = FALSE;
440 fbuf.data = video_base + (fbuf.address&0x00FFFFFF);
442 render_buffer_t rbuf = pvr2_get_render_buffer( &fbuf );
443 if( rbuf == NULL ) {
444 rbuf = pvr2_frame_buffer_to_render_buffer( &fbuf );
445 }
446 displayed_render_buffer = rbuf;
447 if( rbuf != NULL ) {
448 display_driver->display_render_buffer( rbuf );
449 }
450 }
451 }
453 /**
454 * This has to handle every single register individually as they all get masked
455 * off differently (and its easier to do it at write time)
456 */
457 void mmio_region_PVR2_write( uint32_t reg, uint32_t val )
458 {
459 if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
460 MMIO_WRITE( PVR2, reg, val );
461 return;
462 }
464 switch(reg) {
465 case PVRID:
466 case PVRVER:
467 case GUNPOS: /* Read only registers */
468 break;
469 case PVRRESET:
470 val &= 0x00000007; /* Do stuff? */
471 MMIO_WRITE( PVR2, reg, val );
472 break;
473 case RENDER_START: /* Don't really care what value */
474 if( save_next_render_filename != NULL ) {
475 if( pvr2_render_save_scene(save_next_render_filename) == 0 ) {
476 INFO( "Saved scene to %s", save_next_render_filename);
477 }
478 g_free( save_next_render_filename );
479 save_next_render_filename = NULL;
480 }
481 pvr2_scene_read();
482 render_buffer_t buffer = pvr2_next_render_buffer();
483 if( buffer != NULL ) {
484 pvr2_scene_render( buffer );
485 pvr2_finish_render_buffer( buffer );
486 }
487 asic_event( EVENT_PVR_RENDER_DONE );
488 break;
489 case RENDER_POLYBASE:
490 MMIO_WRITE( PVR2, reg, val&0x00F00000 );
491 break;
492 case RENDER_TSPCFG:
493 MMIO_WRITE( PVR2, reg, val&0x00010101 );
494 break;
495 case DISP_BORDER:
496 MMIO_WRITE( PVR2, reg, val&0x01FFFFFF );
497 break;
498 case DISP_MODE:
499 MMIO_WRITE( PVR2, reg, val&0x00FFFF7F );
500 break;
501 case RENDER_MODE:
502 MMIO_WRITE( PVR2, reg, val&0x00FFFF0F );
503 break;
504 case RENDER_SIZE:
505 MMIO_WRITE( PVR2, reg, val&0x000001FF );
506 break;
507 case DISP_ADDR1:
508 val &= 0x00FFFFFC;
509 MMIO_WRITE( PVR2, reg, val );
510 pvr2_update_raster_posn(sh4r.slice_cycle);
511 break;
512 case DISP_ADDR2:
513 MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
514 pvr2_update_raster_posn(sh4r.slice_cycle);
515 break;
516 case DISP_SIZE:
517 MMIO_WRITE( PVR2, reg, val&0x3FFFFFFF );
518 break;
519 case RENDER_ADDR1:
520 case RENDER_ADDR2:
521 MMIO_WRITE( PVR2, reg, val&0x01FFFFFC );
522 break;
523 case RENDER_HCLIP:
524 MMIO_WRITE( PVR2, reg, val&0x07FF07FF );
525 break;
526 case RENDER_VCLIP:
527 MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
528 break;
529 case DISP_HPOSIRQ:
530 MMIO_WRITE( PVR2, reg, val&0x03FF33FF );
531 pvr2_state.irq_hpos_line = val & 0x03FF;
532 pvr2_state.irq_hpos_time_ns = 2000000*((val>>16)&0x03FF)/pvr2_state.dot_clock;
533 pvr2_state.irq_hpos_mode = (val >> 12) & 0x03;
534 switch( pvr2_state.irq_hpos_mode ) {
535 case 3: /* Reserved - treat as 0 */
536 case 0: /* Once per frame at specified line */
537 pvr2_state.irq_hpos_mode = HPOS_PER_FRAME;
538 break;
539 case 2: /* Once per line - as per-line-count */
540 pvr2_state.irq_hpos_line = 1;
541 pvr2_state.irq_hpos_mode = 1;
542 case 1: /* Once per N lines */
543 pvr2_state.irq_hpos_line_count = pvr2_state.irq_hpos_line;
544 pvr2_state.irq_hpos_line = (pvr2_state.line_count >> 1) +
545 pvr2_state.irq_hpos_line_count;
546 while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {
547 pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);
548 }
549 pvr2_state.irq_hpos_mode = HPOS_PER_LINECOUNT;
550 }
551 pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0,
552 pvr2_state.irq_hpos_time_ns );
553 break;
554 case DISP_VPOSIRQ:
555 val = val & 0x03FF03FF;
556 pvr2_state.irq_vpos1 = (val >> 16);
557 pvr2_state.irq_vpos2 = val & 0x03FF;
558 pvr2_update_raster_posn(sh4r.slice_cycle);
559 pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );
560 pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );
561 MMIO_WRITE( PVR2, reg, val );
562 break;
563 case RENDER_NEARCLIP:
564 MMIO_WRITE( PVR2, reg, val & 0x7FFFFFFF );
565 break;
566 case RENDER_SHADOW:
567 MMIO_WRITE( PVR2, reg, val&0x000001FF );
568 break;
569 case RENDER_OBJCFG:
570 MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
571 break;
572 case RENDER_TSPCLIP:
573 MMIO_WRITE( PVR2, reg, val&0x7FFFFFFF );
574 break;
575 case RENDER_FARCLIP:
576 MMIO_WRITE( PVR2, reg, val&0xFFFFFFF0 );
577 break;
578 case RENDER_BGPLANE:
579 MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
580 break;
581 case RENDER_ISPCFG:
582 MMIO_WRITE( PVR2, reg, val&0x00FFFFF9 );
583 break;
584 case VRAM_CFG1:
585 MMIO_WRITE( PVR2, reg, val&0x000000FF );
586 break;
587 case VRAM_CFG2:
588 MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
589 break;
590 case VRAM_CFG3:
591 MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
592 break;
593 case RENDER_FOGTBLCOL:
594 case RENDER_FOGVRTCOL:
595 MMIO_WRITE( PVR2, reg, val&0x00FFFFFF );
596 break;
597 case RENDER_FOGCOEFF:
598 MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
599 break;
600 case RENDER_CLAMPHI:
601 case RENDER_CLAMPLO:
602 MMIO_WRITE( PVR2, reg, val );
603 break;
604 case RENDER_TEXSIZE:
605 MMIO_WRITE( PVR2, reg, val&0x00031F1F );
606 break;
607 case RENDER_PALETTE:
608 MMIO_WRITE( PVR2, reg, val&0x00000003 );
609 break;
610 case RENDER_ALPHA_REF:
611 MMIO_WRITE( PVR2, reg, val&0x000000FF );
612 break;
613 /********** CRTC registers *************/
614 case DISP_HBORDER:
615 case DISP_VBORDER:
616 MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
617 break;
618 case DISP_TOTAL:
619 val = val & 0x03FF03FF;
620 MMIO_WRITE( PVR2, reg, val );
621 pvr2_update_raster_posn(sh4r.slice_cycle);
622 pvr2_state.total_lines = (val >> 16) + 1;
623 pvr2_state.line_size = (val & 0x03FF) + 1;
624 pvr2_state.line_time_ns = 1000000 * pvr2_state.line_size / pvr2_state.dot_clock;
625 pvr2_state.retrace_end_line = 0x2A;
626 pvr2_state.retrace_start_line = pvr2_state.total_lines - 6;
627 pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );
628 pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );
629 pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0,
630 pvr2_state.irq_hpos_time_ns );
631 break;
632 case DISP_SYNCCFG:
633 MMIO_WRITE( PVR2, reg, val&0x000003FF );
634 pvr2_state.interlaced = (val & 0x0010) ? TRUE : FALSE;
635 break;
636 case DISP_SYNCTIME:
637 pvr2_state.vsync_lines = (val >> 8) & 0x0F;
638 pvr2_state.hsync_width_ns = ((val & 0x7F) + 1) * 2000000 / pvr2_state.dot_clock;
639 MMIO_WRITE( PVR2, reg, val&0xFFFFFF7F );
640 break;
641 case DISP_CFG2:
642 MMIO_WRITE( PVR2, reg, val&0x003F01FF );
643 break;
644 case DISP_HPOS:
645 val = val & 0x03FF;
646 pvr2_state.front_porch_ns = (val + 1) * 1000000 / pvr2_state.dot_clock;
647 MMIO_WRITE( PVR2, reg, val );
648 break;
649 case DISP_VPOS:
650 MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
651 break;
653 /*********** Tile accelerator registers ***********/
654 case TA_POLYPOS:
655 case TA_LISTPOS:
656 /* Readonly registers */
657 break;
658 case TA_TILEBASE:
659 case TA_LISTEND:
660 case TA_LISTBASE:
661 MMIO_WRITE( PVR2, reg, val&0x00FFFFE0 );
662 break;
663 case RENDER_TILEBASE:
664 case TA_POLYBASE:
665 case TA_POLYEND:
666 MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
667 break;
668 case TA_TILESIZE:
669 MMIO_WRITE( PVR2, reg, val&0x000F003F );
670 break;
671 case TA_TILECFG:
672 MMIO_WRITE( PVR2, reg, val&0x00133333 );
673 break;
674 case TA_INIT:
675 if( val & 0x80000000 )
676 pvr2_ta_init();
677 break;
678 case TA_REINIT:
679 break;
680 /**************** Scaler registers? ****************/
681 case RENDER_SCALER:
682 MMIO_WRITE( PVR2, reg, val&0x0007FFFF );
683 break;
685 case YUV_ADDR:
686 val = val & 0x00FFFFF8;
687 MMIO_WRITE( PVR2, reg, val );
688 pvr2_yuv_init( val );
689 break;
690 case YUV_CFG:
691 MMIO_WRITE( PVR2, reg, val&0x01013F3F );
692 pvr2_yuv_set_config(val);
693 break;
695 /**************** Unknowns ***************/
696 case PVRUNK1:
697 MMIO_WRITE( PVR2, reg, val&0x000007FF );
698 break;
699 case PVRUNK2:
700 MMIO_WRITE( PVR2, reg, val&0x00000007 );
701 break;
702 case PVRUNK3:
703 MMIO_WRITE( PVR2, reg, val&0x000FFF3F );
704 break;
705 case PVRUNK5:
706 MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
707 break;
708 case PVRUNK7:
709 MMIO_WRITE( PVR2, reg, val&0x00000001 );
710 break;
711 case PVRUNK8:
712 MMIO_WRITE( PVR2, reg, val&0x0300FFFF );
713 break;
714 }
715 }
717 /**
718 * Calculate the current read value of the syncstat register, using
719 * the current SH4 clock time as an offset from the last timeslice.
720 * The register reads (LSB to MSB) as:
721 * 0..9 Current scan line
722 * 10 Odd/even field (1 = odd, 0 = even)
723 * 11 Display active (including border and overscan)
724 * 12 Horizontal sync off
725 * 13 Vertical sync off
726 * Note this method is probably incorrect for anything other than straight
727 * interlaced PAL/NTSC, and needs further testing.
728 */
729 uint32_t pvr2_get_sync_status()
730 {
731 pvr2_update_raster_posn(sh4r.slice_cycle);
732 uint32_t result = pvr2_state.line_count;
734 if( pvr2_state.odd_even_field ) {
735 result |= 0x0400;
736 }
737 if( (pvr2_state.line_count & 0x01) == pvr2_state.odd_even_field ) {
738 if( pvr2_state.line_remainder > pvr2_state.hsync_width_ns ) {
739 result |= 0x1000; /* !HSYNC */
740 }
741 if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
742 if( pvr2_state.line_remainder > pvr2_state.front_porch_ns ) {
743 result |= 0x2800; /* Display active */
744 } else {
745 result |= 0x2000; /* Front porch */
746 }
747 }
748 } else {
749 if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
750 if( pvr2_state.line_remainder < (pvr2_state.line_time_ns - pvr2_state.back_porch_ns)) {
751 result |= 0x3800; /* Display active */
752 } else {
753 result |= 0x3000;
754 }
755 } else {
756 result |= 0x1000; /* Back porch */
757 }
758 }
759 return result;
760 }
762 /**
763 * Schedule a "scanline" event. This actually goes off at
764 * 2 * line in even fields and 2 * line + 1 in odd fields.
765 * Otherwise this behaves as per pvr2_schedule_line_event().
766 * The raster position should be updated before calling this
767 * method.
768 * @param eventid Event to fire at the specified time
769 * @param line Line on which to fire the event (this is 2n/2n+1 for interlaced
770 * displays).
771 * @param hpos_ns Nanoseconds into the line at which to fire.
772 */
773 static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int hpos_ns )
774 {
775 uint32_t field = pvr2_state.odd_even_field;
776 if( line <= pvr2_state.line_count && pvr2_state.interlaced ) {
777 field = !field;
778 }
779 if( hpos_ns > pvr2_state.line_time_ns ) {
780 hpos_ns = pvr2_state.line_time_ns;
781 }
783 line <<= 1;
784 if( field ) {
785 line += 1;
786 }
788 if( line < pvr2_state.total_lines ) {
789 uint32_t lines;
790 uint32_t time;
791 if( line <= pvr2_state.line_count ) {
792 lines = (pvr2_state.total_lines - pvr2_state.line_count + line);
793 } else {
794 lines = (line - pvr2_state.line_count);
795 }
796 if( lines <= minimum_lines ) {
797 lines += pvr2_state.total_lines;
798 }
799 time = (lines * pvr2_state.line_time_ns) - pvr2_state.line_remainder + hpos_ns;
800 event_schedule( eventid, time );
801 } else {
802 event_cancel( eventid );
803 }
804 }
806 void pvr2_queue_gun_event( int xpos, int ypos )
807 {
808 pvr2_update_raster_posn(sh4r.slice_cycle);
809 pvr2_schedule_scanline_event( EVENT_GUNPOS, (ypos >> 1) + pvr2_state.vsync_lines, 0,
810 (1000000 * xpos / pvr2_state.dot_clock) + pvr2_state.hsync_width_ns );
811 }
813 MMIO_REGION_READ_FN( PVR2, reg )
814 {
815 switch( reg ) {
816 case DISP_SYNCSTAT:
817 return pvr2_get_sync_status();
818 default:
819 return MMIO_READ( PVR2, reg );
820 }
821 }
823 MMIO_REGION_WRITE_FN( PVR2PAL, reg, val )
824 {
825 MMIO_WRITE( PVR2PAL, reg, val );
826 pvr2_state.palette_changed = TRUE;
827 }
829 void pvr2_check_palette_changed()
830 {
831 if( pvr2_state.palette_changed ) {
832 texcache_invalidate_palette();
833 pvr2_state.palette_changed = FALSE;
834 }
835 }
837 MMIO_REGION_READ_DEFFN( PVR2PAL );
839 void pvr2_set_base_address( uint32_t base )
840 {
841 mmio_region_PVR2_write( DISP_ADDR1, base );
842 }
847 int32_t mmio_region_PVR2TA_read( uint32_t reg )
848 {
849 return 0xFFFFFFFF;
850 }
852 void mmio_region_PVR2TA_write( uint32_t reg, uint32_t val )
853 {
854 pvr2_ta_write( (unsigned char *)&val, sizeof(uint32_t) );
855 }
857 render_buffer_t pvr2_create_render_buffer( sh4addr_t addr, int width, int height, GLuint tex_id )
858 {
859 if( display_driver != NULL && display_driver->create_render_buffer != NULL ) {
860 render_buffer_t buffer = display_driver->create_render_buffer(width,height,tex_id);
861 buffer->address = addr;
862 return buffer;
863 }
864 return NULL;
865 }
867 void pvr2_destroy_render_buffer( render_buffer_t buffer )
868 {
869 if( !buffer->flushed )
870 pvr2_render_buffer_copy_to_sh4( buffer );
871 display_driver->destroy_render_buffer( buffer );
872 }
874 void pvr2_finish_render_buffer( render_buffer_t buffer )
875 {
876 display_driver->finish_render( buffer );
877 }
879 /**
880 * Find the render buffer corresponding to the requested output frame
881 * (does not consider texture renders).
882 * @return the render_buffer if found, or null if no such buffer.
883 *
884 * Note: Currently does not consider "partial matches", ie partial
885 * frame overlap - it probably needs to do this.
886 */
887 render_buffer_t pvr2_get_render_buffer( frame_buffer_t frame )
888 {
889 int i;
890 for( i=0; i<render_buffer_count; i++ ) {
891 if( render_buffers[i] != NULL && render_buffers[i]->address == frame->address ) {
892 return render_buffers[i];
893 }
894 }
895 return NULL;
896 }
898 /**
899 * Allocate a render buffer with the requested parameters.
900 * The order of preference is:
901 * 1. An existing buffer with the same address. (not flushed unless the new
902 * size is smaller than the old one).
903 * 2. An existing buffer with the same size chosen by LRU order. Old buffer
904 * is flushed to vram.
905 * 3. A new buffer if one can be created.
906 * 4. The current display buff
907 * Note: The current display field(s) will never be overwritten except as a last
908 * resort.
909 */
910 render_buffer_t pvr2_alloc_render_buffer( sh4addr_t render_addr, int width, int height )
911 {
912 int i;
913 render_buffer_t result = NULL;
915 /* Check existing buffers for an available buffer */
916 for( i=0; i<render_buffer_count; i++ ) {
917 if( render_buffers[i]->width == width && render_buffers[i]->height == height ) {
918 /* needs to be the right dimensions */
919 if( render_buffers[i]->address == render_addr ) {
920 if( displayed_render_buffer == render_buffers[i] ) {
921 /* Same address, but we can't use it because the
922 * display has it. Mark it as unaddressed for later.
923 */
924 render_buffers[i]->address = -1;
925 } else {
926 /* perfect */
927 result = render_buffers[i];
928 break;
929 }
930 } else if( render_buffers[i]->address == -1 && result == NULL &&
931 displayed_render_buffer != render_buffers[i] ) {
932 result = render_buffers[i];
933 }
935 } else if( render_buffers[i]->address == render_addr ) {
936 /* right address, wrong size - if it's larger, flush it, otherwise
937 * nuke it quietly */
938 if( render_buffers[i]->width * render_buffers[i]->height >
939 width*height ) {
940 pvr2_render_buffer_copy_to_sh4( render_buffers[i] );
941 }
942 render_buffers[i]->address = -1;
943 }
944 }
946 /* Nothing available - make one */
947 if( result == NULL ) {
948 if( render_buffer_count == MAX_RENDER_BUFFERS ) {
949 /* maximum buffers reached - need to throw one away */
950 uint32_t field1_addr = MMIO_READ( PVR2, DISP_ADDR1 );
951 uint32_t field2_addr = MMIO_READ( PVR2, DISP_ADDR2 );
952 for( i=0; i<render_buffer_count; i++ ) {
953 if( render_buffers[i]->address != field1_addr &&
954 render_buffers[i]->address != field2_addr &&
955 render_buffers[i] != displayed_render_buffer ) {
956 /* Never throw away the current "front buffer(s)" */
957 result = render_buffers[i];
958 if( !result->flushed ) {
959 pvr2_render_buffer_copy_to_sh4( result );
960 }
961 if( result->width != width || result->height != height ) {
962 display_driver->destroy_render_buffer(render_buffers[i]);
963 result = display_driver->create_render_buffer(width,height,0);
964 render_buffers[i] = result;
965 }
966 break;
967 }
968 }
969 } else {
970 result = display_driver->create_render_buffer(width,height,0);
971 if( result != NULL ) {
972 render_buffers[render_buffer_count++] = result;
973 }
974 }
975 }
977 if( result != NULL ) {
978 result->address = render_addr;
979 }
980 return result;
981 }
983 /**
984 * Allocate a render buffer based on the current rendering settings
985 */
986 render_buffer_t pvr2_next_render_buffer()
987 {
988 render_buffer_t result = NULL;
989 uint32_t render_addr = MMIO_READ( PVR2, RENDER_ADDR1 );
990 uint32_t render_mode = MMIO_READ( PVR2, RENDER_MODE );
991 uint32_t render_scale = MMIO_READ( PVR2, RENDER_SCALER );
992 uint32_t render_stride = MMIO_READ( PVR2, RENDER_SIZE ) << 3;
994 int width = pvr2_scene_buffer_width();
995 int height = pvr2_scene_buffer_height();
996 int colour_format = render_colour_formats[render_mode&0x07];
998 if( render_addr & 0x01000000 ) { /* vram64 */
999 render_addr = (render_addr & 0x00FFFFFF) + PVR2_RAM_BASE_INT;
1000 result = texcache_get_render_buffer( render_addr, colour_format, width, height );
1001 } else { /* vram32 */
1002 render_addr = (render_addr & 0x00FFFFFF) + PVR2_RAM_BASE;
1003 result = pvr2_alloc_render_buffer( render_addr, width, height );
1004 }
1006 /* Setup the buffer */
1007 if( result != NULL ) {
1008 result->rowstride = render_stride;
1009 result->colour_format = colour_format;
1010 result->scale = render_scale;
1011 result->size = width * height * colour_formats[colour_format].bpp;
1012 result->flushed = FALSE;
1013 result->inverted = TRUE; // render buffers are inverted normally
1014 }
1015 return result;
1016 }
1018 static render_buffer_t pvr2_frame_buffer_to_render_buffer( frame_buffer_t frame )
1019 {
1020 render_buffer_t result = pvr2_alloc_render_buffer( frame->address, frame->width, frame->height );
1021 if( result != NULL ) {
1022 int bpp = colour_formats[frame->colour_format].bpp;
1023 result->rowstride = frame->rowstride;
1024 result->colour_format = frame->colour_format;
1025 result->scale = 0x400;
1026 result->size = frame->width * frame->height * bpp;
1027 result->flushed = TRUE;
1028 result->inverted = frame->inverted;
1029 display_driver->load_frame_buffer( frame, result );
1030 }
1031 return result;
1032 }
1035 /**
1036 * Invalidate any caching on the supplied address. Specifically, if it falls
1037 * within any of the render buffers, flush the buffer back to PVR2 ram.
1038 */
1039 gboolean pvr2_render_buffer_invalidate( sh4addr_t address, gboolean isWrite )
1040 {
1041 int i;
1042 address = address & 0x1FFFFFFF;
1043 for( i=0; i<render_buffer_count; i++ ) {
1044 uint32_t bufaddr = render_buffers[i]->address;
1045 if( bufaddr != -1 && bufaddr <= address &&
1046 (bufaddr + render_buffers[i]->size) > address ) {
1047 if( !render_buffers[i]->flushed ) {
1048 pvr2_render_buffer_copy_to_sh4( render_buffers[i] );
1049 }
1050 if( isWrite ) {
1051 render_buffers[i]->address = -1; /* Invalid */
1052 }
1053 return TRUE; /* should never have overlapping buffers */
1054 }
1055 }
1056 return FALSE;
1057 }
.