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lxdream.org :: lxdream/test/testspu.c
lxdream 0.9.1
released Jun 29
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filename test/testspu.c
changeset 278:a66aaa522d31
next812:8cc61d5ea1f8
author nkeynes
date Sun Jan 14 02:53:11 2007 +0000 (13 years ago)
permissions -rw-r--r--
last change Initial (non-working) spu dma test case
view annotate diff log raw
     2 #include <stdlib.h>
     3 #include "asic.h"
     4 #include "lib.h"
     5 #include "testdata.h"
     7 #define SPUBASE 0xA05F7800
     8 #define SPUBASERAM 0x00800000
     9 #define SPUWAIT  (SPUBASE+0x90)
    10 #define SPUMAGIC (SPUBASE+0xBC)
    13 #define SPUDMAEXT(x) (SPUBASE+(0x20*(x)))
    14 #define SPUDMAHOST(x) (SPUBASE+(0x20*(x))+0x04)
    15 #define SPUDMASIZE(x) (SPUBASE+(0x20*(x))+0x08)
    16 #define SPUDMADIR(x) (SPUBASE+(0x20*(x))+0x0C)
    17 #define SPUDMAMODE(x) (SPUBASE+(0x20*(x))+0x10)
    18 #define SPUDMACTL1(x) (SPUBASE+(0x20*(x))+0x14)
    19 #define SPUDMACTL2(x) (SPUBASE+(0x20*(x))+0x18)
    20 #define SPUDMASTOP(x) (SPUBASE+(0x20*(x))+0x1C)
    22 void dump_spu_regs()
    23 {
    24     fwrite_dump( stderr, (char *)(0xA05F7800), 0x100 );
    25 }    
    27 int dma_to_spu( int chan, uint32_t target, char *data, uint32_t size )
    28 {
    29     long_write( SPUWAIT, 0 );
    30     long_write( SPUMAGIC, 0x4659404f );
    31     long_write( SPUDMACTL1(chan), 0 );
    32     long_write( SPUDMACTL2(chan), 0 );
    33     long_write( SPUDMAHOST(chan), ((uint32_t)data)&0x1FFFFFE0 );
    34     long_write( SPUDMASIZE(chan), size | 0x80000000 );
    35     long_write( SPUDMAEXT(chan), target );
    36     long_write( SPUDMADIR(chan), 0 );
    37     long_write( SPUDMAMODE(chan), 0 );
    39     long_write( SPUDMACTL1(chan), 1 );
    40     long_write( SPUDMACTL2(chan), 1 );
    41     if( asic_wait( EVENT_SPU_DMA0 + chan ) != 0 ) {
    42 	fprintf( stderr, "Timeout waiting for DMA event\n" );
    43 	dump_spu_regs();
    44 	return -1;
    45     }
    46     return 0;
    47 }
    49 int dma_from_spu( int chan, char *data, uint32_t src, uint32_t size )
    50 {
    51     long_write( SPUWAIT, 0 );
    52     long_write( SPUMAGIC, 0x4659404f );
    53     long_write( SPUDMACTL1(chan), 0 );
    54     long_write( SPUDMACTL2(chan), 0 );
    55     long_write( SPUDMAHOST(chan), ((uint32_t)data)&0x1FFFFFE0 );
    56     long_write( SPUDMASIZE(chan), size | 0x80000000 );
    57     long_write( SPUDMAEXT(chan), src );
    58     long_write( SPUDMADIR(chan), 1 );
    59     long_write( SPUDMAMODE(chan), 5 );
    61     long_write( SPUDMACTL1(chan), 1 );
    62     long_write( SPUDMACTL2(chan), 1 );
    63     if( asic_wait( EVENT_SPU_DMA0 + chan ) != 0 ) {
    64 	fprintf( stderr, "Timeout waiting for DMA event\n" );
    65 	dump_spu_regs();
    66 	return -1;
    67     }
    68     return 0;
    69 }
    71 #define SPUTARGETADDR (SPUBASERAM+0x10000)
    72 #define SPUTARGET ((char *)(SPUTARGETADDR))
    74 int test_spu_dma_channel( int chan )
    75 {
    76     char sampledata1[256+32];
    77     char sampledata2[256+32];
    78     char resultdata[256+32];
    80     int i;
    81     char *p1 = DMA_ALIGN(sampledata1), *p2 = DMA_ALIGN(sampledata2);
    82     char *r = DMA_ALIGN(resultdata);
    84     for( i=0; i<256; i++ ) {
    85 	p1[i] = (char)(i*i);
    86 	p2[i] = 256 - i;
    87     }
    89     if( dma_to_spu( chan, SPUTARGETADDR, p1, 256 ) != 0 ) {
    90 	return -1;
    91     }
    93     if( memcmp( p1, SPUTARGET, 256 ) != 0 ) {
    94 	fprintf( stderr, "First data mismatch:\n" );
    95 	fwrite_diff( stderr, p1, 256, SPUTARGET, 256 );
    96 	return -1;
    97     }
    99     if( dma_to_spu( chan, SPUTARGETADDR, p2, 256 ) != 0 ) {
   100 	return -1;
   101     }
   103     if( memcmp( p2, SPUTARGET, 256 ) != 0 ) {
   104 	fprintf( stderr, "Second data mismatch:\n" );
   105 	fwrite_diff( stderr, p2, 256, SPUTARGET, 256 );
   106 	return -1;
   107     }
   109     memset( r, 0, 256 );
   110     if( dma_from_spu( chan, r, SPUTARGETADDR, 256 ) != 0 ) {
   111 	return -1;
   112     }
   114     if( memcmp( p2, r, 256 ) != 0 ) {
   115 	fprintf( stderr, "Read data mismatch:\n" );
   116 	fwrite_diff( stderr, p2, 256, r, 256 );
   117 	return -1;
   118     }
   119 }
   122 int test_spu_dma()
   123 {
   124     int i; 
   125     for( i=0; i<4; i++ ) {
   126 	if( test_spu_dma_channel(i) != 0 ) {
   127 	    return -1;
   128 	}
   129     }
   130 }
   132 test_func_t tests[] = { test_spu_dma, NULL };
   134 int main()
   135 {
   136     return run_tests(tests);
   137 }
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