filename | test/sh4/inc.s |
changeset | 231:a9e61a96a885 |
prev | 228:70adc8ffa8d1 |
next | 233:f8333b94f503 |
author | nkeynes |
date | Tue Sep 26 11:05:38 2006 +0000 (14 years ago) |
permissions | -rw-r--r-- |
last change | Add BT, BT/S, CMP/EQ, CMP/GE, CMP/GT, CMP/HI, CMP/HS tests Add general slot-illegal exception test |
view | annotate | diff | log | raw |
1 .altmacro
2 .macro fail name
3 LOCAL LC1
4 LOCAL LC2
5 add #1, r13
6 mov.l LC1, r3
7 mov r12, r5
8 mov.l \name, r4
9 xor r6, r6
10 jsr @r3
11 nop
12 bra LC2
13 nop
14 .align 4
15 LC1:
16 .long _test_print_failure
17 LC2:
18 .endm
20 .macro failm name msg
21 LOCAL LC1
22 LOCAL LC2
23 add #1, r13
24 mov.l LC1, r3
25 mov r12, r5
26 mov.l \name, r4
27 mov.l \msg, r6
28 jsr @r3
29 nop
30 bra LC2
31 nop
32 .align 4
33 LC1:
34 .long _test_print_failure
35 LC2:
36 .endm
39 .macro start_test
40 mov.l r14, @-r15
41 sts.l pr, @-r15
42 mov.l r12, @-r15
43 mov.l r13, @-r15
44 mov r15, r14
45 xor r12,r12
46 xor r13,r13
47 ! r12 is the test counter
48 ! r13 is the failed-test counter
49 .endm
51 .macro end_test name
52 LOCAL test_print_result_k
53 mov.l \name, r4
54 mov r13, r5
55 mov r12, r6
56 mov.l test_print_result_k, r3
57 jsr @r3
58 nop
59 mov r14, r15
60 mov.l @r15+, r13
61 mov.l @r15+, r12
62 lds.l @r15+, pr
63 mov.l @r15+, r14
64 rts
65 nop
66 .align 4
67 test_print_result_k:
68 .long _test_print_result
69 .endm
72 .macro assert_t_set testname
73 LOCAL LC1
74 LOCAL LC2
75 LOCAL LCM
76 stc sr, r1
77 mov.l r1, @-r15
78 xor r0, r0
79 add #1, r0
80 and r0, r1
81 cmp/eq r0, r1
82 bt LC2
83 add #1, r13
84 mov.l LC1, r3
85 mov r12, r5
86 mov.l \testname, r4
87 mov.l LCM, r6
88 jsr @r3
89 nop
90 bra LC2
91 nop
92 .align 4
93 LC1:
94 .long _test_print_failure
95 LCM: .long assert_t_clear_message
96 LC2:
97 mov.l @r15+, r1
98 ldc r1, sr
99 .endm
101 .macro assert_t_clear testname
102 LOCAL LC1
103 LOCAL LC2
104 LOCAL LCM
105 stc sr, r1
106 mov.l r1, @-r15
107 xor r0, r0
108 add #1, r0
109 and r0, r1
110 cmp/eq r0, r1
111 bf LC2
112 add #1, r13
113 mov.l LC1, r3
114 mov r12, r5
115 mov.l \testname, r4
116 mov.l LCM, r6
117 jsr @r3
118 nop
119 bra LC2
120 nop
121 .align 4
122 LC1:
123 .long _test_print_failure
124 LCM: .long assert_t_clear_message
125 LC2:
126 mov.l @r15+, r1
127 ldc r1, sr
128 .endm
130 ! Note that yes there is a perfectly good clrt instruction, but we try to
131 ! minimize the number of instructions we depend on here.
133 .macro clc
134 xor r0, r0
135 addc r0, r0
136 .endm
137 .macro setc
138 xor r0, r0
139 not r0, r0
140 addc r0, r0
141 .endm
143 .macro clearbl
144 LOCAL L1
145 LOCAL L2
146 mov.l L1, r0
147 stc sr, r1
148 and r0, r1
149 ldc r1, sr
150 bra L2
151 nop
152 .align 4
153 L1: .long 0xEFFFFFFF
154 L2:
155 .endm
157 .macro setbl
158 LOCAL L1
159 LOCAL L2
160 xor r0, r0
161 add #1, r0
162 shll r0, 28
163 stc sr, r1
164 or r0, r1
165 ldc r1, sr
166 bra L2
167 nop
168 .align 4
169 L1: .long 0x10000000
170 L2:
171 .endm
173 .macro expect_exc code
174 LOCAL L1, L2, L3
175 mov.l L1, r3
176 mov.l L2, r4
177 jsr @r3
178 nop
179 bra L3
180 nop
181 .align 4
182 L1: .long _expect_exception
183 L2: .long \code
184 L3:
186 .endm
188 .macro assert_exc_caught testname, expectpc
189 LOCAL L1, L2, L3
190 mov.l L1, r3
191 mov.l \testname, r4
192 mov r12, r5
193 mov.l L2, r6
194 jsr @r3
195 nop
196 add r0, r13
197 bra L3
198 nop
199 .align 4
200 L1: .long _assert_exception_caught
201 L2: .long \expectpc
202 L3:
203 .endm
205 .align 2
206 assert_t_set_message:
207 .string "Expected T=1 but was 0"
209 assert_t_clear_message:
210 .string "Expected T=0 but was 1"
.