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lxdream.org :: lxdream/src/pvr2/pvr2.c
lxdream 0.9.1
released Jun 29
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filename src/pvr2/pvr2.c
changeset 669:ab344e42bca9
prev653:3202ff01d48e
next674:377d987db8f2
author nkeynes
date Mon May 12 10:00:13 2008 +0000 (11 years ago)
permissions -rw-r--r--
last change Cleanup most of the -Wall warnings (getting a bit sloppy...)
Convert FP code to use fixed banks rather than indirect pointer
(3-4% faster this way now)
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     1 /**
     2  * $Id$
     3  *
     4  * PVR2 (Video) Core module implementation and MMIO registers.
     5  *
     6  * Copyright (c) 2005 Nathan Keynes.
     7  *
     8  * This program is free software; you can redistribute it and/or modify
     9  * it under the terms of the GNU General Public License as published by
    10  * the Free Software Foundation; either version 2 of the License, or
    11  * (at your option) any later version.
    12  *
    13  * This program is distributed in the hope that it will be useful,
    14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    16  * GNU General Public License for more details.
    17  */
    18 #define MODULE pvr2_module
    20 #include <assert.h>
    21 #include "dream.h"
    22 #include "eventq.h"
    23 #include "display.h"
    24 #include "mem.h"
    25 #include "asic.h"
    26 #include "clock.h"
    27 #include "pvr2/pvr2.h"
    28 #include "pvr2/scene.h"
    29 #include "sh4/sh4.h"
    30 #define MMIO_IMPL
    31 #include "pvr2/pvr2mmio.h"
    33 unsigned char *video_base;
    35 #define MAX_RENDER_BUFFERS 4
    37 #define HPOS_PER_FRAME 0
    38 #define HPOS_PER_LINECOUNT 1
    40 static void pvr2_init( void );
    41 static void pvr2_reset( void );
    42 static uint32_t pvr2_run_slice( uint32_t );
    43 static void pvr2_save_state( FILE *f );
    44 static int pvr2_load_state( FILE *f );
    45 static void pvr2_update_raster_posn( uint32_t nanosecs );
    46 static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int line_time_ns );
    47 static render_buffer_t pvr2_get_render_buffer( frame_buffer_t frame );
    48 static render_buffer_t pvr2_next_render_buffer( );
    49 static render_buffer_t pvr2_frame_buffer_to_render_buffer( frame_buffer_t frame );
    50 uint32_t pvr2_get_sync_status();
    52 void pvr2_display_frame( void );
    54 static int output_colour_formats[] = { COLFMT_BGRA1555, COLFMT_RGB565, COLFMT_BGR888, COLFMT_BGRA8888 };
    56 struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, pvr2_reset, NULL, 
    57 					pvr2_run_slice, NULL,
    58 					pvr2_save_state, pvr2_load_state };
    61 display_driver_t display_driver = NULL;
    63 struct pvr2_state {
    64     uint32_t frame_count;
    65     uint32_t line_count;
    66     uint32_t line_remainder;
    67     uint32_t cycles_run; /* Cycles already executed prior to main time slice */
    68     uint32_t irq_hpos_line;
    69     uint32_t irq_hpos_line_count;
    70     uint32_t irq_hpos_mode;
    71     uint32_t irq_hpos_time_ns; /* Time within the line */
    72     uint32_t irq_vpos1;
    73     uint32_t irq_vpos2;
    74     uint32_t odd_even_field; /* 1 = odd, 0 = even */
    75     gboolean palette_changed; /* TRUE if palette has changed since last render */
    76     gchar *save_next_render_filename;
    77     /* timing */
    78     uint32_t dot_clock;
    79     uint32_t total_lines;
    80     uint32_t line_size;
    81     uint32_t line_time_ns;
    82     uint32_t vsync_lines;
    83     uint32_t hsync_width_ns;
    84     uint32_t front_porch_ns;
    85     uint32_t back_porch_ns;
    86     uint32_t retrace_start_line;
    87     uint32_t retrace_end_line;
    88     gboolean interlaced;
    89 } pvr2_state;
    91 static render_buffer_t render_buffers[MAX_RENDER_BUFFERS];
    92 static int render_buffer_count = 0;
    93 static render_buffer_t displayed_render_buffer = NULL;
    94 static uint32_t displayed_border_colour = 0;
    96 /**
    97  * Event handler for the hpos callback
    98  */
    99 static void pvr2_hpos_callback( int eventid ) {
   100     asic_event( eventid );
   101     pvr2_update_raster_posn(sh4r.slice_cycle);
   102     if( pvr2_state.irq_hpos_mode == HPOS_PER_LINECOUNT ) {
   103 	pvr2_state.irq_hpos_line += pvr2_state.irq_hpos_line_count;
   104 	while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {
   105 	    pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);
   106 	}
   107     }
   108     pvr2_schedule_scanline_event( eventid, pvr2_state.irq_hpos_line, 1, 
   109 				  pvr2_state.irq_hpos_time_ns );
   110 }
   112 /**
   113  * Event handler for the scanline callbacks. Fires the corresponding
   114  * ASIC event, and resets the timer for the next field.
   115  */
   116 static void pvr2_scanline_callback( int eventid ) {
   117     asic_event( eventid );
   118     pvr2_update_raster_posn(sh4r.slice_cycle);
   119     if( eventid == EVENT_SCANLINE1 ) {
   120 	pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos1, 1, 0 );
   121     } else {
   122 	pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos2, 1, 0 );
   123     }
   124 }
   126 static void pvr2_init( void )
   127 {
   128     int i;
   129     register_io_region( &mmio_region_PVR2 );
   130     register_io_region( &mmio_region_PVR2PAL );
   131     register_io_region( &mmio_region_PVR2TA );
   132     register_event_callback( EVENT_HPOS, pvr2_hpos_callback );
   133     register_event_callback( EVENT_SCANLINE1, pvr2_scanline_callback );
   134     register_event_callback( EVENT_SCANLINE2, pvr2_scanline_callback );
   135     video_base = mem_get_region_by_name( MEM_REGION_VIDEO );
   136     texcache_init();
   137     pvr2_reset();
   138     pvr2_ta_reset();
   139     pvr2_state.save_next_render_filename = NULL;
   140     for( i=0; i<MAX_RENDER_BUFFERS; i++ ) {
   141 	render_buffers[i] = NULL;
   142     }
   143     render_buffer_count = 0;
   144     displayed_render_buffer = NULL;
   145     displayed_border_colour = 0;
   146 }
   148 static void pvr2_reset( void )
   149 {
   150     int i;
   151     pvr2_state.line_count = 0;
   152     pvr2_state.line_remainder = 0;
   153     pvr2_state.cycles_run = 0;
   154     pvr2_state.irq_vpos1 = 0;
   155     pvr2_state.irq_vpos2 = 0;
   156     pvr2_state.dot_clock = PVR2_DOT_CLOCK;
   157     pvr2_state.back_porch_ns = 4000;
   158     pvr2_state.palette_changed = FALSE;
   159     mmio_region_PVR2_write( DISP_TOTAL, 0x0270035F );
   160     mmio_region_PVR2_write( DISP_SYNCTIME, 0x07D6A53F );
   161     mmio_region_PVR2_write( YUV_ADDR, 0 );
   162     mmio_region_PVR2_write( YUV_CFG, 0 );
   164     pvr2_ta_init();
   165     texcache_flush();
   166     if( display_driver ) {
   167 	display_driver->display_blank(0);
   168 	for( i=0; i<render_buffer_count; i++ ) {
   169 	    display_driver->destroy_render_buffer(render_buffers[i]);
   170 	    render_buffers[i] = NULL;
   171 	}
   172 	render_buffer_count = 0;
   173     }
   174 }
   176 void pvr2_save_render_buffer( FILE *f, render_buffer_t buffer )
   177 {
   178     struct frame_buffer fbuf;
   180     fbuf.width = buffer->width;
   181     fbuf.height = buffer->height;
   182     fbuf.rowstride = fbuf.width*3;
   183     fbuf.colour_format = COLFMT_BGR888;
   184     fbuf.inverted = buffer->inverted;
   185     fbuf.data = g_malloc0( buffer->width * buffer->height * 3 );
   187     display_driver->read_render_buffer( fbuf.data, buffer, fbuf.rowstride, COLFMT_BGR888 );
   188     write_png_to_stream( f, &fbuf );
   189     g_free( fbuf.data );
   191     fwrite( &buffer->rowstride, sizeof(buffer->rowstride), 1, f );
   192     fwrite( &buffer->colour_format, sizeof(buffer->colour_format), 1, f );
   193     fwrite( &buffer->address, sizeof(buffer->address), 1, f );
   194     fwrite( &buffer->scale, sizeof(buffer->scale), 1, f );
   195     fwrite( &buffer->flushed, sizeof(buffer->flushed), 1, f );
   197 }
   199 render_buffer_t pvr2_load_render_buffer( FILE *f )
   200 {
   201     frame_buffer_t frame = read_png_from_stream( f );
   202     if( frame == NULL ) {
   203 	return NULL;
   204     }
   206     render_buffer_t buffer = pvr2_frame_buffer_to_render_buffer(frame);
   207     if( buffer != NULL ) {
   208 	fread( &buffer->rowstride, sizeof(buffer->rowstride), 1, f );
   209 	fread( &buffer->colour_format, sizeof(buffer->colour_format), 1, f );
   210 	fread( &buffer->address, sizeof(buffer->address), 1, f );
   211 	fread( &buffer->scale, sizeof(buffer->scale), 1, f );
   212 	fread( &buffer->flushed, sizeof(buffer->flushed), 1, f );
   213     } else {
   214 	fseek( f, sizeof(buffer->rowstride)+sizeof(buffer->colour_format)+
   215 	       sizeof(buffer->address)+sizeof(buffer->scale)+
   216 	       sizeof(buffer->flushed), SEEK_CUR );
   217     }
   218     return buffer;
   219 }
   224 void pvr2_save_render_buffers( FILE *f )
   225 {
   226     int i;
   227     fwrite( &render_buffer_count, sizeof(render_buffer_count), 1, f );
   228     if( displayed_render_buffer != NULL ) {
   229 	i = 1;
   230 	fwrite( &i, sizeof(i), 1, f );
   231 	pvr2_save_render_buffer( f, displayed_render_buffer );
   232     } else {
   233 	i = 0;
   234 	fwrite( &i, sizeof(i), 1, f );
   235     }
   237     for( i=0; i<render_buffer_count; i++ ) {
   238 	if( render_buffers[i] != displayed_render_buffer && render_buffers[i] != NULL ) {
   239 	    pvr2_save_render_buffer( f, render_buffers[i] );
   240 	}
   241     }
   242 }
   244 gboolean pvr2_load_render_buffers( FILE *f )
   245 {
   246     uint32_t count;
   247     int i, has_frontbuffer;
   249     fread( &count, sizeof(count), 1, f );
   250     if( count > MAX_RENDER_BUFFERS ) {
   251 	return FALSE;
   252     }
   253     fread( &has_frontbuffer, sizeof(has_frontbuffer), 1, f );
   254     for( i=0; i<render_buffer_count; i++ ) {
   255 	display_driver->destroy_render_buffer(render_buffers[i]);
   256 	render_buffers[i] = NULL;
   257     }
   258     render_buffer_count = 0;
   260     if( has_frontbuffer ) {
   261 	displayed_render_buffer = pvr2_load_render_buffer(f);
   262 	display_driver->display_render_buffer( displayed_render_buffer );
   263 	count--;
   264     }
   266     for( i=0; i<count; i++ ) {
   267 	pvr2_load_render_buffer( f );
   268     }
   269     return TRUE;
   270 }
   273 static void pvr2_save_state( FILE *f )
   274 {
   275     pvr2_save_render_buffers( f );
   276     fwrite( &pvr2_state, sizeof(pvr2_state), 1, f );
   277     pvr2_ta_save_state( f );
   278     pvr2_yuv_save_state( f );
   279 }
   281 static int pvr2_load_state( FILE *f )
   282 {
   283     if( !pvr2_load_render_buffers(f) )
   284 	return 1;
   285     if( fread( &pvr2_state, sizeof(pvr2_state), 1, f ) != 1 )
   286 	return 1;
   287     if( pvr2_ta_load_state(f) ) {
   288 	return 1;
   289     }
   290     return pvr2_yuv_load_state(f);
   291 }
   293 /**
   294  * Update the current raster position to the given number of nanoseconds,
   295  * relative to the last time slice. (ie the raster will be adjusted forward
   296  * by nanosecs - nanosecs_already_run_this_timeslice)
   297  */
   298 static void pvr2_update_raster_posn( uint32_t nanosecs )
   299 {
   300     uint32_t old_line_count = pvr2_state.line_count;
   301     if( pvr2_state.line_time_ns == 0 ) {
   302 	return; /* do nothing */
   303     }
   304     pvr2_state.line_remainder += (nanosecs - pvr2_state.cycles_run);
   305     pvr2_state.cycles_run = nanosecs;
   306     while( pvr2_state.line_remainder >= pvr2_state.line_time_ns ) {
   307 	pvr2_state.line_count ++;
   308 	pvr2_state.line_remainder -= pvr2_state.line_time_ns;
   309     }
   311     if( pvr2_state.line_count >= pvr2_state.total_lines ) {
   312 	pvr2_state.line_count -= pvr2_state.total_lines;
   313 	if( pvr2_state.interlaced ) {
   314 	    pvr2_state.odd_even_field = !pvr2_state.odd_even_field;
   315 	}
   316     }
   317     if( pvr2_state.line_count >= pvr2_state.retrace_end_line &&
   318 	(old_line_count < pvr2_state.retrace_end_line ||
   319 	 old_line_count > pvr2_state.line_count) ) {
   320 	pvr2_state.frame_count++;
   321 	pvr2_display_frame();
   322     }
   323 }
   325 static uint32_t pvr2_run_slice( uint32_t nanosecs ) 
   326 {
   327     pvr2_update_raster_posn( nanosecs );
   328     pvr2_state.cycles_run = 0;
   329     return nanosecs;
   330 }
   332 int pvr2_get_frame_count() 
   333 {
   334     return pvr2_state.frame_count;
   335 }
   337 render_buffer_t pvr2_get_front_buffer()
   338 {
   339     return displayed_render_buffer;
   340 }
   342 uint32_t pvr2_get_border_colour()
   343 {
   344     return displayed_border_colour;
   345 }
   347 gboolean pvr2_save_next_scene( const gchar *filename )
   348 {
   349     if( pvr2_state.save_next_render_filename != NULL ) {
   350 	g_free( pvr2_state.save_next_render_filename );
   351     } 
   352     pvr2_state.save_next_render_filename = g_strdup(filename);
   353     return TRUE;
   354 }
   358 /**
   359  * Display the next frame, copying the current contents of video ram to
   360  * the window. If the video configuration has changed, first recompute the
   361  * new frame size/depth.
   362  */
   363 void pvr2_display_frame( void )
   364 {
   365     int dispmode = MMIO_READ( PVR2, DISP_MODE );
   366     int vidcfg = MMIO_READ( PVR2, DISP_SYNCCFG );
   367     gboolean bEnabled = (dispmode & DISPMODE_ENABLE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE;
   369     if( display_driver == NULL ) {
   370 	return; /* can't really do anything much */
   371     } else if( !bEnabled ) {
   372 	/* Output disabled == black */
   373 	displayed_render_buffer = NULL;
   374 	displayed_border_colour = 0;
   375 	display_driver->display_blank( 0 ); 
   376     } else if( MMIO_READ( PVR2, DISP_CFG2 ) & 0x08 ) { 
   377 	/* Enabled but blanked - border colour */
   378 	displayed_border_colour = MMIO_READ( PVR2, DISP_BORDER );
   379 	displayed_render_buffer = NULL;
   380 	display_driver->display_blank( displayed_border_colour );
   381     } else {
   382 	/* Real output - determine dimensions etc */
   383 	struct frame_buffer fbuf;
   384 	uint32_t dispsize = MMIO_READ( PVR2, DISP_SIZE );
   385 	int vid_stride = (((dispsize & DISPSIZE_MODULO) >> 20) - 1);
   386 	int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
   388 	fbuf.colour_format = output_colour_formats[(dispmode & DISPMODE_COLFMT) >> 2];
   389 	fbuf.width = vid_ppl << 2 / colour_formats[fbuf.colour_format].bpp;
   390 	fbuf.height = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
   391 	fbuf.size = vid_ppl << 2 * fbuf.height;
   392 	fbuf.rowstride = (vid_ppl + vid_stride) << 2;
   394 	/* Determine the field to display, and deinterlace if possible */
   395 	if( pvr2_state.interlaced ) {
   396 	    if( vid_ppl == vid_stride ) { /* Magic deinterlace */
   397 		fbuf.height = fbuf.height << 1;
   398 		fbuf.rowstride = vid_ppl << 2;
   399 		fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
   400 	    } else { 
   401 		/* Just display the field as is, folks. This is slightly tricky -
   402 		 * we pick the field based on which frame is about to come through,
   403 		 * which may not be the same as the odd_even_field.
   404 		 */
   405 		gboolean oddfield = pvr2_state.odd_even_field;
   406 		if( pvr2_state.line_count >= pvr2_state.retrace_start_line ) {
   407 		    oddfield = !oddfield;
   408 		}
   409 		if( oddfield ) {
   410 		    fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
   411 		} else {
   412 		    fbuf.address = MMIO_READ( PVR2, DISP_ADDR2 );
   413 		}
   414 	    }
   415 	} else {
   416 	    fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
   417 	}
   418 	fbuf.address = (fbuf.address & 0x00FFFFFF) + PVR2_RAM_BASE;
   419 	fbuf.inverted = FALSE;
   420 	fbuf.data = video_base + (fbuf.address&0x00FFFFFF);
   422 	render_buffer_t rbuf = pvr2_get_render_buffer( &fbuf );
   423 	if( rbuf == NULL ) {
   424 	    rbuf = pvr2_frame_buffer_to_render_buffer( &fbuf );
   425 	}
   426 	displayed_render_buffer = rbuf;
   427 	if( rbuf != NULL ) {
   428 	    display_driver->display_render_buffer( rbuf );
   429 	}
   430     }
   431 }
   433 /**
   434  * This has to handle every single register individually as they all get masked 
   435  * off differently (and its easier to do it at write time)
   436  */
   437 void mmio_region_PVR2_write( uint32_t reg, uint32_t val )
   438 {
   439     if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
   440         MMIO_WRITE( PVR2, reg, val );
   441         return;
   442     }
   444     switch(reg) {
   445     case PVRID:
   446     case PVRVER:
   447     case GUNPOS: /* Read only registers */
   448 	break;
   449     case PVRRESET:
   450 	val &= 0x00000007; /* Do stuff? */
   451 	MMIO_WRITE( PVR2, reg, val );
   452 	break;
   453     case RENDER_START: /* Don't really care what value */
   454 	if( pvr2_state.save_next_render_filename != NULL ) {
   455 	    if( pvr2_render_save_scene(pvr2_state.save_next_render_filename) == 0 ) {
   456 		INFO( "Saved scene to %s", pvr2_state.save_next_render_filename);
   457 	    }
   458 	    g_free( pvr2_state.save_next_render_filename );
   459 	    pvr2_state.save_next_render_filename = NULL;
   460 	}
   461 	pvr2_scene_read();
   462 	render_buffer_t buffer = pvr2_next_render_buffer();
   463 	if( buffer != NULL ) {
   464 	    pvr2_scene_render( buffer );
   465 	}
   466 	asic_event( EVENT_PVR_RENDER_DONE );
   467 	break;
   468     case RENDER_POLYBASE:
   469     	MMIO_WRITE( PVR2, reg, val&0x00F00000 );
   470     	break;
   471     case RENDER_TSPCFG:
   472     	MMIO_WRITE( PVR2, reg, val&0x00010101 );
   473     	break;
   474     case DISP_BORDER:
   475     	MMIO_WRITE( PVR2, reg, val&0x01FFFFFF );
   476     	break;
   477     case DISP_MODE:
   478     	MMIO_WRITE( PVR2, reg, val&0x00FFFF7F );
   479     	break;
   480     case RENDER_MODE:
   481     	MMIO_WRITE( PVR2, reg, val&0x00FFFF0F );
   482     	break;
   483     case RENDER_SIZE:
   484     	MMIO_WRITE( PVR2, reg, val&0x000001FF );
   485     	break;
   486     case DISP_ADDR1:
   487 	val &= 0x00FFFFFC;
   488 	MMIO_WRITE( PVR2, reg, val );
   489 	pvr2_update_raster_posn(sh4r.slice_cycle);
   490 	break;
   491     case DISP_ADDR2:
   492     	MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
   493 	pvr2_update_raster_posn(sh4r.slice_cycle);
   494     	break;
   495     case DISP_SIZE:
   496     	MMIO_WRITE( PVR2, reg, val&0x3FFFFFFF );
   497     	break;
   498     case RENDER_ADDR1:
   499     case RENDER_ADDR2:
   500     	MMIO_WRITE( PVR2, reg, val&0x01FFFFFC );
   501     	break;
   502     case RENDER_HCLIP:
   503 	MMIO_WRITE( PVR2, reg, val&0x07FF07FF );
   504 	break;
   505     case RENDER_VCLIP:
   506 	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
   507 	break;
   508     case DISP_HPOSIRQ:
   509 	MMIO_WRITE( PVR2, reg, val&0x03FF33FF );
   510 	pvr2_state.irq_hpos_line = val & 0x03FF;
   511 	pvr2_state.irq_hpos_time_ns = 2000000*((val>>16)&0x03FF)/pvr2_state.dot_clock;
   512 	pvr2_state.irq_hpos_mode = (val >> 12) & 0x03;
   513 	switch( pvr2_state.irq_hpos_mode ) {
   514 	case 3: /* Reserved - treat as 0 */
   515 	case 0: /* Once per frame at specified line */
   516 	    pvr2_state.irq_hpos_mode = HPOS_PER_FRAME;
   517 	    break;
   518 	case 2: /* Once per line - as per-line-count */
   519 	    pvr2_state.irq_hpos_line = 1;
   520 	    pvr2_state.irq_hpos_mode = 1;
   521 	case 1: /* Once per N lines */
   522 	    pvr2_state.irq_hpos_line_count = pvr2_state.irq_hpos_line;
   523 	    pvr2_state.irq_hpos_line = (pvr2_state.line_count >> 1) + 
   524 		pvr2_state.irq_hpos_line_count;
   525 	    while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {
   526 		pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);
   527 	    }
   528 	    pvr2_state.irq_hpos_mode = HPOS_PER_LINECOUNT;
   529 	}
   530 	pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0,
   531 					  pvr2_state.irq_hpos_time_ns );
   532 	break;
   533     case DISP_VPOSIRQ:
   534 	val = val & 0x03FF03FF;
   535 	pvr2_state.irq_vpos1 = (val >> 16);
   536 	pvr2_state.irq_vpos2 = val & 0x03FF;
   537 	pvr2_update_raster_posn(sh4r.slice_cycle);
   538 	pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );
   539 	pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );
   540 	MMIO_WRITE( PVR2, reg, val );
   541 	break;
   542     case RENDER_NEARCLIP:
   543 	MMIO_WRITE( PVR2, reg, val & 0x7FFFFFFF );
   544 	break;
   545     case RENDER_SHADOW:
   546 	MMIO_WRITE( PVR2, reg, val&0x000001FF );
   547 	break;
   548     case RENDER_OBJCFG:
   549     	MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
   550     	break;
   551     case RENDER_TSPCLIP:
   552     	MMIO_WRITE( PVR2, reg, val&0x7FFFFFFF );
   553     	break;
   554     case RENDER_FARCLIP:
   555 	MMIO_WRITE( PVR2, reg, val&0xFFFFFFF0 );
   556 	break;
   557     case RENDER_BGPLANE:
   558     	MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
   559     	break;
   560     case RENDER_ISPCFG:
   561     	MMIO_WRITE( PVR2, reg, val&0x00FFFFF9 );
   562     	break;
   563     case VRAM_CFG1:
   564 	MMIO_WRITE( PVR2, reg, val&0x000000FF );
   565 	break;
   566     case VRAM_CFG2:
   567 	MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
   568 	break;
   569     case VRAM_CFG3:
   570 	MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
   571 	break;
   572     case RENDER_FOGTBLCOL:
   573     case RENDER_FOGVRTCOL:
   574 	MMIO_WRITE( PVR2, reg, val&0x00FFFFFF );
   575 	break;
   576     case RENDER_FOGCOEFF:
   577 	MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
   578 	break;
   579     case RENDER_CLAMPHI:
   580     case RENDER_CLAMPLO:
   581 	MMIO_WRITE( PVR2, reg, val );
   582 	break;
   583     case RENDER_TEXSIZE:
   584 	MMIO_WRITE( PVR2, reg, val&0x00031F1F );
   585 	break;
   586     case RENDER_PALETTE:
   587 	MMIO_WRITE( PVR2, reg, val&0x00000003 );
   588 	break;
   589     case RENDER_ALPHA_REF:
   590 	MMIO_WRITE( PVR2, reg, val&0x000000FF );
   591 	break;
   592 	/********** CRTC registers *************/
   593     case DISP_HBORDER:
   594     case DISP_VBORDER:
   595 	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
   596 	break;
   597     case DISP_TOTAL:
   598 	val = val & 0x03FF03FF;
   599 	MMIO_WRITE( PVR2, reg, val );
   600 	pvr2_update_raster_posn(sh4r.slice_cycle);
   601 	pvr2_state.total_lines = (val >> 16) + 1;
   602 	pvr2_state.line_size = (val & 0x03FF) + 1;
   603 	pvr2_state.line_time_ns = 1000000 * pvr2_state.line_size / pvr2_state.dot_clock;
   604 	pvr2_state.retrace_end_line = 0x2A;
   605 	pvr2_state.retrace_start_line = pvr2_state.total_lines - 6;
   606 	pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );
   607 	pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );
   608 	pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0, 
   609 					  pvr2_state.irq_hpos_time_ns );
   610 	break;
   611     case DISP_SYNCCFG:
   612 	MMIO_WRITE( PVR2, reg, val&0x000003FF );
   613 	pvr2_state.interlaced = (val & 0x0010) ? TRUE : FALSE;
   614 	break;
   615     case DISP_SYNCTIME:
   616 	pvr2_state.vsync_lines = (val >> 8) & 0x0F;
   617 	pvr2_state.hsync_width_ns = ((val & 0x7F) + 1) * 2000000 / pvr2_state.dot_clock;
   618 	MMIO_WRITE( PVR2, reg, val&0xFFFFFF7F );
   619 	break;
   620     case DISP_CFG2:
   621 	MMIO_WRITE( PVR2, reg, val&0x003F01FF );
   622 	break;
   623     case DISP_HPOS:
   624 	val = val & 0x03FF;
   625 	pvr2_state.front_porch_ns = (val + 1) * 1000000 / pvr2_state.dot_clock;
   626 	MMIO_WRITE( PVR2, reg, val );
   627 	break;
   628     case DISP_VPOS:
   629 	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
   630 	break;
   632 	/*********** Tile accelerator registers ***********/
   633     case TA_POLYPOS:
   634     case TA_LISTPOS:
   635 	/* Readonly registers */
   636 	break;
   637     case TA_TILEBASE:
   638     case TA_LISTEND:
   639     case TA_LISTBASE:
   640 	MMIO_WRITE( PVR2, reg, val&0x00FFFFE0 );
   641 	break;
   642     case RENDER_TILEBASE:
   643     case TA_POLYBASE:
   644     case TA_POLYEND:
   645 	MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
   646 	break;
   647     case TA_TILESIZE:
   648 	MMIO_WRITE( PVR2, reg, val&0x000F003F );
   649 	break;
   650     case TA_TILECFG:
   651 	MMIO_WRITE( PVR2, reg, val&0x00133333 );
   652 	break;
   653     case TA_INIT:
   654 	if( val & 0x80000000 )
   655 	    pvr2_ta_init();
   656 	break;
   657     case TA_REINIT:
   658 	break;
   659 	/**************** Scaler registers? ****************/
   660     case RENDER_SCALER:
   661 	MMIO_WRITE( PVR2, reg, val&0x0007FFFF );
   662 	break;
   664     case YUV_ADDR:
   665 	val = val & 0x00FFFFF8;
   666 	MMIO_WRITE( PVR2, reg, val );
   667 	pvr2_yuv_init( val );
   668 	break;
   669     case YUV_CFG:
   670 	MMIO_WRITE( PVR2, reg, val&0x01013F3F );
   671 	pvr2_yuv_set_config(val);
   672 	break;
   674 	/**************** Unknowns ***************/
   675     case PVRUNK1:
   676     	MMIO_WRITE( PVR2, reg, val&0x000007FF );
   677     	break;
   678     case PVRUNK2:
   679 	MMIO_WRITE( PVR2, reg, val&0x00000007 );
   680 	break;
   681     case PVRUNK3:
   682 	MMIO_WRITE( PVR2, reg, val&0x000FFF3F );
   683 	break;
   684     case PVRUNK5:
   685 	MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
   686 	break;
   687     case PVRUNK7:
   688 	MMIO_WRITE( PVR2, reg, val&0x00000001 );
   689 	break;
   690     }
   691 }
   693 /**
   694  * Calculate the current read value of the syncstat register, using
   695  * the current SH4 clock time as an offset from the last timeslice.
   696  * The register reads (LSB to MSB) as:
   697  *     0..9  Current scan line
   698  *     10    Odd/even field (1 = odd, 0 = even)
   699  *     11    Display active (including border and overscan)
   700  *     12    Horizontal sync off
   701  *     13    Vertical sync off
   702  * Note this method is probably incorrect for anything other than straight
   703  * interlaced PAL/NTSC, and needs further testing. 
   704  */
   705 uint32_t pvr2_get_sync_status()
   706 {
   707     pvr2_update_raster_posn(sh4r.slice_cycle);
   708     uint32_t result = pvr2_state.line_count;
   710     if( pvr2_state.odd_even_field ) {
   711 	result |= 0x0400;
   712     }
   713     if( (pvr2_state.line_count & 0x01) == pvr2_state.odd_even_field ) {
   714 	if( pvr2_state.line_remainder > pvr2_state.hsync_width_ns ) {
   715 	    result |= 0x1000; /* !HSYNC */
   716 	}
   717 	if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
   718 	    if( pvr2_state.line_remainder > pvr2_state.front_porch_ns ) {
   719 		result |= 0x2800; /* Display active */
   720 	    } else {
   721 		result |= 0x2000; /* Front porch */
   722 	    }
   723 	}
   724     } else {
   725 	if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
   726 	    if( pvr2_state.line_remainder < (pvr2_state.line_time_ns - pvr2_state.back_porch_ns)) {
   727 		result |= 0x3800; /* Display active */
   728 	    } else {
   729 		result |= 0x3000;
   730 	    }
   731 	} else {
   732 	    result |= 0x1000; /* Back porch */
   733 	}
   734     }
   735     return result;
   736 }
   738 /**
   739  * Schedule a "scanline" event. This actually goes off at
   740  * 2 * line in even fields and 2 * line + 1 in odd fields.
   741  * Otherwise this behaves as per pvr2_schedule_line_event().
   742  * The raster position should be updated before calling this
   743  * method.
   744  * @param eventid Event to fire at the specified time
   745  * @param line Line on which to fire the event (this is 2n/2n+1 for interlaced
   746  *  displays). 
   747  * @param hpos_ns Nanoseconds into the line at which to fire.
   748  */
   749 static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int hpos_ns )
   750 {
   751     uint32_t field = pvr2_state.odd_even_field;
   752     if( line <= pvr2_state.line_count && pvr2_state.interlaced ) {
   753 	field = !field;
   754     }
   755     if( hpos_ns > pvr2_state.line_time_ns ) {
   756 	hpos_ns = pvr2_state.line_time_ns;
   757     }
   759     line <<= 1;
   760     if( field ) {
   761 	line += 1;
   762     }
   764     if( line < pvr2_state.total_lines ) {
   765 	uint32_t lines;
   766 	uint32_t time;
   767 	if( line <= pvr2_state.line_count ) {
   768 	    lines = (pvr2_state.total_lines - pvr2_state.line_count + line);
   769 	} else {
   770 	    lines = (line - pvr2_state.line_count);
   771 	}
   772 	if( lines <= minimum_lines ) {
   773 	    lines += pvr2_state.total_lines;
   774 	}
   775 	time = (lines * pvr2_state.line_time_ns) - pvr2_state.line_remainder + hpos_ns;
   776 	event_schedule( eventid, time );
   777     } else {
   778 	event_cancel( eventid );
   779     }
   780 }
   782 MMIO_REGION_READ_FN( PVR2, reg )
   783 {
   784     switch( reg ) {
   785         case DISP_SYNCSTAT:
   786             return pvr2_get_sync_status();
   787         default:
   788             return MMIO_READ( PVR2, reg );
   789     }
   790 }
   792 MMIO_REGION_WRITE_FN( PVR2PAL, reg, val )
   793 {
   794     MMIO_WRITE( PVR2PAL, reg, val );
   795     pvr2_state.palette_changed = TRUE;
   796 }
   798 void pvr2_check_palette_changed()
   799 {
   800     if( pvr2_state.palette_changed ) {
   801 	texcache_invalidate_palette();
   802 	pvr2_state.palette_changed = FALSE;
   803     }
   804 }
   806 MMIO_REGION_READ_DEFFN( PVR2PAL );
   808 void pvr2_set_base_address( uint32_t base ) 
   809 {
   810     mmio_region_PVR2_write( DISP_ADDR1, base );
   811 }
   816 int32_t mmio_region_PVR2TA_read( uint32_t reg )
   817 {
   818     return 0xFFFFFFFF;
   819 }
   821 void mmio_region_PVR2TA_write( uint32_t reg, uint32_t val )
   822 {
   823     pvr2_ta_write( (unsigned char *)&val, sizeof(uint32_t) );
   824 }
   826 /**
   827  * Find the render buffer corresponding to the requested output frame
   828  * (does not consider texture renders). 
   829  * @return the render_buffer if found, or null if no such buffer.
   830  *
   831  * Note: Currently does not consider "partial matches", ie partial
   832  * frame overlap - it probably needs to do this.
   833  */
   834 render_buffer_t pvr2_get_render_buffer( frame_buffer_t frame )
   835 {
   836     int i;
   837     for( i=0; i<render_buffer_count; i++ ) {
   838 	if( render_buffers[i] != NULL && render_buffers[i]->address == frame->address ) {
   839 	    return render_buffers[i];
   840 	}
   841     }
   842     return NULL;
   843 }
   845 /**
   846  * Allocate a render buffer with the requested parameters.
   847  * The order of preference is:
   848  *   1. An existing buffer with the same address. (not flushed unless the new
   849  * size is smaller than the old one).
   850  *   2. An existing buffer with the same size chosen by LRU order. Old buffer
   851  *       is flushed to vram.
   852  *   3. A new buffer if one can be created.
   853  *   4. The current display buff
   854  * Note: The current display field(s) will never be overwritten except as a last
   855  * resort.
   856  */
   857 render_buffer_t pvr2_alloc_render_buffer( sh4addr_t render_addr, int width, int height )
   858 {
   859     int i;
   860     render_buffer_t result = NULL;
   862     /* Check existing buffers for an available buffer */
   863     for( i=0; i<render_buffer_count; i++ ) {
   864 	if( render_buffers[i]->width == width && render_buffers[i]->height == height ) {
   865 	    /* needs to be the right dimensions */
   866 	    if( render_buffers[i]->address == render_addr ) {
   867 		if( displayed_render_buffer == render_buffers[i] ) {
   868 		    /* Same address, but we can't use it because the
   869 		     * display has it. Mark it as unaddressed for later.
   870 		     */
   871 		    render_buffers[i]->address = -1;
   872 		} else {
   873 		    /* perfect */
   874 		    result = render_buffers[i];
   875 		    break;
   876 		}
   877 	    } else if( render_buffers[i]->address == -1 && result == NULL && 
   878 		       displayed_render_buffer != render_buffers[i] ) {
   879 		result = render_buffers[i];
   880 	    }
   882 	} else if( render_buffers[i]->address == render_addr ) {
   883 	    /* right address, wrong size - if it's larger, flush it, otherwise 
   884 	     * nuke it quietly */
   885 	    if( render_buffers[i]->width * render_buffers[i]->height >
   886 		width*height ) {
   887 		pvr2_render_buffer_copy_to_sh4( render_buffers[i] );
   888 	    }
   889 	    render_buffers[i]->address = -1;
   890 	}
   891     }
   893     /* Nothing available - make one */
   894     if( result == NULL ) {
   895 	if( render_buffer_count == MAX_RENDER_BUFFERS ) {
   896 	    /* maximum buffers reached - need to throw one away */
   897 	    uint32_t field1_addr = MMIO_READ( PVR2, DISP_ADDR1 );
   898 	    uint32_t field2_addr = MMIO_READ( PVR2, DISP_ADDR2 );
   899 	    for( i=0; i<render_buffer_count; i++ ) {
   900 		if( render_buffers[i]->address != field1_addr &&
   901 		    render_buffers[i]->address != field2_addr &&
   902 		    render_buffers[i] != displayed_render_buffer ) {
   903 		    /* Never throw away the current "front buffer(s)" */
   904 		    result = render_buffers[i];
   905 		    if( !result->flushed ) {
   906 			pvr2_render_buffer_copy_to_sh4( result );
   907 		    }
   908 		    if( result->width != width || result->height != height ) {
   909 			display_driver->destroy_render_buffer(render_buffers[i]);
   910 			result = display_driver->create_render_buffer(width,height);
   911 			render_buffers[i] = result;
   912 		    }
   913 		    break;
   914 		}
   915 	    }
   916 	} else {
   917 	    result = display_driver->create_render_buffer(width,height);
   918 	    if( result != NULL ) { 
   919 		render_buffers[render_buffer_count++] = result;
   920 	    }
   921 	}
   922     }
   924     if( result != NULL ) {
   925 	result->address = render_addr;
   926     }
   927     return result;
   928 }
   930 /**
   931  * Allocate a render buffer based on the current rendering settings
   932  */
   933 render_buffer_t pvr2_next_render_buffer()
   934 {
   935     render_buffer_t result = NULL;
   936     uint32_t render_addr = MMIO_READ( PVR2, RENDER_ADDR1 );
   937     uint32_t render_mode = MMIO_READ( PVR2, RENDER_MODE );
   938     uint32_t render_scale = MMIO_READ( PVR2, RENDER_SCALER );
   939     uint32_t render_stride = MMIO_READ( PVR2, RENDER_SIZE ) << 3;
   941     if( render_addr & 0x01000000 ) { /* vram64 */
   942 	render_addr = (render_addr & 0x00FFFFFF) + PVR2_RAM_BASE_INT;
   943     } else { /* vram32 */
   944 	render_addr = (render_addr & 0x00FFFFFF) + PVR2_RAM_BASE;
   945     }
   947     int width = pvr2_scene_buffer_width();
   948     int height = pvr2_scene_buffer_height();
   949     int colour_format = pvr2_render_colour_format[render_mode&0x07];
   951     result = pvr2_alloc_render_buffer( render_addr, width, height );
   952     /* Setup the buffer */
   953     if( result != NULL ) {
   954 	result->rowstride = render_stride;
   955 	result->colour_format = colour_format;
   956 	result->scale = render_scale;
   957 	result->size = width * height * colour_formats[colour_format].bpp;
   958 	result->flushed = FALSE;
   959 	result->inverted = TRUE; // render buffers are inverted normally
   960     }
   961     return result;
   962 }
   964 static render_buffer_t pvr2_frame_buffer_to_render_buffer( frame_buffer_t frame )
   965 {
   966     render_buffer_t result = pvr2_alloc_render_buffer( frame->address, frame->width, frame->height );
   967     if( result != NULL ) {
   968 	int bpp = colour_formats[frame->colour_format].bpp;
   969 	result->rowstride = frame->rowstride;
   970 	result->colour_format = frame->colour_format;
   971 	result->scale = 0x400;
   972 	result->size = frame->width * frame->height * bpp;
   973 	result->flushed = TRUE;
   974 	result->inverted = frame->inverted;
   975 	display_driver->load_frame_buffer( frame, result );
   976     }
   977     return result;
   978 }
   981 /**
   982  * Invalidate any caching on the supplied address. Specifically, if it falls
   983  * within any of the render buffers, flush the buffer back to PVR2 ram.
   984  */
   985 gboolean pvr2_render_buffer_invalidate( sh4addr_t address, gboolean isWrite )
   986 {
   987     int i;
   988     address = address & 0x1FFFFFFF;
   989     for( i=0; i<render_buffer_count; i++ ) {
   990 	uint32_t bufaddr = render_buffers[i]->address;
   991 	if( bufaddr != -1 && bufaddr <= address && 
   992 	    (bufaddr + render_buffers[i]->size) > address ) {
   993 	    if( !render_buffers[i]->flushed ) {
   994 		pvr2_render_buffer_copy_to_sh4( render_buffers[i] );
   995 		render_buffers[i]->flushed = TRUE;
   996 	    }
   997 	    if( isWrite ) {
   998 		render_buffers[i]->address = -1; /* Invalid */
   999 	    }
  1000 	    return TRUE; /* should never have overlapping buffers */
  1003     return FALSE;
.