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lxdream.org :: lxdream/src/sh4/sh4.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4.c
changeset 669:ab344e42bca9
prev638:d6dc39e935af
next671:a530ea88eebd
author nkeynes
date Mon May 12 10:00:13 2008 +0000 (13 years ago)
permissions -rw-r--r--
last change Cleanup most of the -Wall warnings (getting a bit sloppy...)
Convert FP code to use fixed banks rather than indirect pointer
(3-4% faster this way now)
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     1 /**
     2  * $Id$
     3  * 
     4  * SH4 parent module for all CPU modes and SH4 peripheral
     5  * modules.
     6  *
     7  * Copyright (c) 2005 Nathan Keynes.
     8  *
     9  * This program is free software; you can redistribute it and/or modify
    10  * it under the terms of the GNU General Public License as published by
    11  * the Free Software Foundation; either version 2 of the License, or
    12  * (at your option) any later version.
    13  *
    14  * This program is distributed in the hope that it will be useful,
    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17  * GNU General Public License for more details.
    18  */
    20 #define MODULE sh4_module
    21 #include <math.h>
    22 #include <assert.h>
    23 #include "dream.h"
    24 #include "dreamcast.h"
    25 #include "mem.h"
    26 #include "clock.h"
    27 #include "eventq.h"
    28 #include "syscall.h"
    29 #include "sh4/intc.h"
    30 #include "sh4/sh4core.h"
    31 #include "sh4/sh4mmio.h"
    32 #include "sh4/sh4stat.h"
    33 #include "sh4/sh4trans.h"
    34 #include "sh4/xltcache.h"
    36 void sh4_init( void );
    37 void sh4_xlat_init( void );
    38 void sh4_reset( void );
    39 void sh4_start( void );
    40 void sh4_stop( void );
    41 void sh4_save_state( FILE *f );
    42 int sh4_load_state( FILE *f );
    44 uint32_t sh4_run_slice( uint32_t );
    45 uint32_t sh4_xlat_run_slice( uint32_t );
    47 struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset, 
    48 				       sh4_start, sh4_run_slice, sh4_stop,
    49 				       sh4_save_state, sh4_load_state };
    51 struct sh4_registers sh4r;
    52 struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
    53 int sh4_breakpoint_count = 0;
    54 sh4ptr_t sh4_main_ram;
    55 gboolean sh4_starting = FALSE;
    56 static gboolean sh4_use_translator = FALSE;
    57 struct sh4_icache_struct sh4_icache = { NULL, -1, -1, 0 };
    59 void sh4_set_use_xlat( gboolean use )
    60 {
    61 // No-op if the translator was not built
    62 #ifdef SH4_TRANSLATOR
    63     if( use ) {
    64 	xlat_cache_init();
    65 	sh4_translate_init();
    66 	sh4_module.run_time_slice = sh4_xlat_run_slice;
    67     } else {
    68 	sh4_module.run_time_slice = sh4_run_slice;
    69     }
    70     sh4_use_translator = use;
    71 #endif
    72 }
    74 gboolean sh4_is_using_xlat()
    75 {
    76     return sh4_use_translator;
    77 }
    79 void sh4_init(void)
    80 {
    81     register_io_regions( mmio_list_sh4mmio );
    82     sh4_main_ram = mem_get_region_by_name(MEM_REGION_MAIN);
    83     MMU_init();
    84     TMU_init();
    85     sh4_reset();
    86 }
    88 void sh4_start(void)
    89 {
    90     sh4_starting = TRUE;
    91 }
    93 void sh4_reset(void)
    94 {
    95     if(	sh4_use_translator ) {
    96 	xlat_flush_cache();
    97     }
    99     /* zero everything out, for the sake of having a consistent state. */
   100     memset( &sh4r, 0, sizeof(sh4r) );
   102     /* Resume running if we were halted */
   103     sh4r.sh4_state = SH4_STATE_RUNNING;
   105     sh4r.pc    = 0xA0000000;
   106     sh4r.new_pc= 0xA0000002;
   107     sh4r.vbr   = 0x00000000;
   108     sh4r.fpscr = 0x00040001;
   109     sh4r.sr    = 0x700000F0;
   111     /* Mem reset will do this, but if we want to reset _just_ the SH4... */
   112     MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
   114     /* Peripheral modules */
   115     CPG_reset();
   116     INTC_reset();
   117     MMU_reset();
   118     TMU_reset();
   119     SCIF_reset();
   120     sh4_stats_reset();
   121 }
   123 void sh4_stop(void)
   124 {
   125     if(	sh4_use_translator ) {
   126 	/* If we were running with the translator, update new_pc and in_delay_slot */
   127 	sh4r.new_pc = sh4r.pc+2;
   128 	sh4r.in_delay_slot = FALSE;
   129     }
   131 }
   133 void sh4_save_state( FILE *f )
   134 {
   135     if(	sh4_use_translator ) {
   136 	/* If we were running with the translator, update new_pc and in_delay_slot */
   137 	sh4r.new_pc = sh4r.pc+2;
   138 	sh4r.in_delay_slot = FALSE;
   139     }
   141     fwrite( &sh4r, sizeof(sh4r), 1, f );
   142     MMU_save_state( f );
   143     INTC_save_state( f );
   144     TMU_save_state( f );
   145     SCIF_save_state( f );
   146 }
   148 int sh4_load_state( FILE * f )
   149 {
   150     if(	sh4_use_translator ) {
   151 	xlat_flush_cache();
   152     }
   153     fread( &sh4r, sizeof(sh4r), 1, f );
   154     MMU_load_state( f );
   155     INTC_load_state( f );
   156     TMU_load_state( f );
   157     return SCIF_load_state( f );
   158 }
   161 void sh4_set_breakpoint( uint32_t pc, breakpoint_type_t type )
   162 {
   163     sh4_breakpoints[sh4_breakpoint_count].address = pc;
   164     sh4_breakpoints[sh4_breakpoint_count].type = type;
   165     if( sh4_use_translator ) {
   166 	xlat_invalidate_word( pc );
   167     }
   168     sh4_breakpoint_count++;
   169 }
   171 gboolean sh4_clear_breakpoint( uint32_t pc, breakpoint_type_t type )
   172 {
   173     int i;
   175     for( i=0; i<sh4_breakpoint_count; i++ ) {
   176 	if( sh4_breakpoints[i].address == pc && 
   177 	    sh4_breakpoints[i].type == type ) {
   178 	    while( ++i < sh4_breakpoint_count ) {
   179 		sh4_breakpoints[i-1].address = sh4_breakpoints[i].address;
   180 		sh4_breakpoints[i-1].type = sh4_breakpoints[i].type;
   181 	    }
   182 	    if( sh4_use_translator ) {
   183 		xlat_invalidate_word( pc );
   184 	    }
   185 	    sh4_breakpoint_count--;
   186 	    return TRUE;
   187 	}
   188     }
   189     return FALSE;
   190 }
   192 int sh4_get_breakpoint( uint32_t pc )
   193 {
   194     int i;
   195     for( i=0; i<sh4_breakpoint_count; i++ ) {
   196 	if( sh4_breakpoints[i].address == pc )
   197 	    return sh4_breakpoints[i].type;
   198     }
   199     return 0;
   200 }
   202 void sh4_set_pc( int pc )
   203 {
   204     sh4r.pc = pc;
   205     sh4r.new_pc = pc+2;
   206 }
   209 /******************************* Support methods ***************************/
   211 static void sh4_switch_banks( )
   212 {
   213     uint32_t tmp[8];
   215     memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
   216     memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
   217     memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
   218 }
   220 void sh4_switch_fr_banks()
   221 {
   222     int i;
   223     for( i=0; i<16; i++ ) {
   224 	float tmp = sh4r.fr[0][i];
   225 	sh4r.fr[0][i] = sh4r.fr[1][i];
   226 	sh4r.fr[1][i] = tmp;
   227     }
   228 }
   230 void sh4_write_sr( uint32_t newval )
   231 {
   232     int oldbank = (sh4r.sr&SR_MDRB) == SR_MDRB;
   233     int newbank = (newval&SR_MDRB) == SR_MDRB;
   234     if( oldbank != newbank )
   235         sh4_switch_banks();
   236     sh4r.sr = newval;
   237     sh4r.t = (newval&SR_T) ? 1 : 0;
   238     sh4r.s = (newval&SR_S) ? 1 : 0;
   239     sh4r.m = (newval&SR_M) ? 1 : 0;
   240     sh4r.q = (newval&SR_Q) ? 1 : 0;
   241     intc_mask_changed();
   242 }
   244 void sh4_write_fpscr( uint32_t newval )
   245 {
   246     if( (sh4r.fpscr ^ newval) & FPSCR_FR ) {
   247 	sh4_switch_fr_banks();
   248     }
   249     sh4r.fpscr = newval;
   250 }
   252 uint32_t sh4_read_sr( void )
   253 {
   254     /* synchronize sh4r.sr with the various bitflags */
   255     sh4r.sr &= SR_MQSTMASK;
   256     if( sh4r.t ) sh4r.sr |= SR_T;
   257     if( sh4r.s ) sh4r.sr |= SR_S;
   258     if( sh4r.m ) sh4r.sr |= SR_M;
   259     if( sh4r.q ) sh4r.sr |= SR_Q;
   260     return sh4r.sr;
   261 }
   265 #define RAISE( x, v ) do{			\
   266     if( sh4r.vbr == 0 ) { \
   267         ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
   268         dreamcast_stop(); return FALSE;	\
   269     } else { \
   270         sh4r.spc = sh4r.pc;	\
   271         sh4r.ssr = sh4_read_sr(); \
   272         sh4r.sgr = sh4r.r[15]; \
   273         MMIO_WRITE(MMU,EXPEVT,x); \
   274         sh4r.pc = sh4r.vbr + v; \
   275         sh4r.new_pc = sh4r.pc + 2; \
   276         sh4_write_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
   277 	if( sh4r.in_delay_slot ) { \
   278 	    sh4r.in_delay_slot = 0; \
   279 	    sh4r.spc -= 2; \
   280 	} \
   281     } \
   282     return TRUE; } while(0)
   284 /**
   285  * Raise a general CPU exception for the specified exception code.
   286  * (NOT for TRAPA or TLB exceptions)
   287  */
   288 gboolean sh4_raise_exception( int code )
   289 {
   290     RAISE( code, EXV_EXCEPTION );
   291 }
   293 /**
   294  * Raise a CPU reset exception with the specified exception code.
   295  */
   296 gboolean sh4_raise_reset( int code )
   297 {
   298     // FIXME: reset modules as per "manual reset"
   299     sh4_reset();
   300     MMIO_WRITE(MMU,EXPEVT,code);
   301     sh4r.vbr = 0;
   302     sh4r.pc = 0xA0000000;
   303     sh4r.new_pc = sh4r.pc + 2;
   304     sh4_write_sr( (sh4r.sr|SR_MD|SR_BL|SR_RB|SR_IMASK)
   305 		  &(~SR_FD) );
   306     return TRUE;
   307 }
   309 gboolean sh4_raise_trap( int trap )
   310 {
   311     MMIO_WRITE( MMU, TRA, trap<<2 );
   312     RAISE( EXC_TRAP, EXV_EXCEPTION );
   313 }
   315 gboolean sh4_raise_slot_exception( int normal_code, int slot_code ) {
   316     if( sh4r.in_delay_slot ) {
   317 	return sh4_raise_exception(slot_code);
   318     } else {
   319 	return sh4_raise_exception(normal_code);
   320     }
   321 }
   323 gboolean sh4_raise_tlb_exception( int code )
   324 {
   325     RAISE( code, EXV_TLBMISS );
   326 }
   328 void sh4_accept_interrupt( void )
   329 {
   330     uint32_t code = intc_accept_interrupt();
   331     sh4r.ssr = sh4_read_sr();
   332     sh4r.spc = sh4r.pc;
   333     sh4r.sgr = sh4r.r[15];
   334     sh4_write_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
   335     MMIO_WRITE( MMU, INTEVT, code );
   336     sh4r.pc = sh4r.vbr + 0x600;
   337     sh4r.new_pc = sh4r.pc + 2;
   338     //    WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
   339 }
   341 void signsat48( void )
   342 {
   343     if( ((int64_t)sh4r.mac) < (int64_t)0xFFFF800000000000LL )
   344 	sh4r.mac = 0xFFFF800000000000LL;
   345     else if( ((int64_t)sh4r.mac) > (int64_t)0x00007FFFFFFFFFFFLL )
   346 	sh4r.mac = 0x00007FFFFFFFFFFFLL;
   347 }
   349 void sh4_fsca( uint32_t anglei, float *fr )
   350 {
   351     float angle = (((float)(anglei&0xFFFF))/65536.0) * 2 * M_PI;
   352     *fr++ = cosf(angle);
   353     *fr = sinf(angle);
   354 }
   356 /**
   357  * Enter sleep mode (eg by executing a SLEEP instruction).
   358  * Sets sh4_state appropriately and ensures any stopping peripheral modules
   359  * are up to date.
   360  */
   361 void sh4_sleep(void)
   362 {
   363     if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
   364 	sh4r.sh4_state = SH4_STATE_STANDBY;
   365 	/* Bring all running peripheral modules up to date, and then halt them. */
   366 	TMU_run_slice( sh4r.slice_cycle );
   367 	SCIF_run_slice( sh4r.slice_cycle );
   368     } else {
   369 	if( MMIO_READ( CPG, STBCR2 ) & 0x80 ) {
   370 	    sh4r.sh4_state = SH4_STATE_DEEP_SLEEP;
   371 	    /* Halt DMAC but other peripherals still running */
   373 	} else {
   374 	    sh4r.sh4_state = SH4_STATE_SLEEP;
   375 	}
   376     }
   377     if( sh4_xlat_is_running() ) {
   378 	sh4_translate_exit( XLAT_EXIT_SLEEP );
   379     }
   380 }
   382 /**
   383  * Wakeup following sleep mode (IRQ or reset). Sets state back to running,
   384  * and restarts any peripheral devices that were stopped.
   385  */
   386 void sh4_wakeup(void)
   387 {
   388     switch( sh4r.sh4_state ) {
   389     case SH4_STATE_STANDBY:
   390 	break;
   391     case SH4_STATE_DEEP_SLEEP:
   392 	break;
   393     case SH4_STATE_SLEEP:
   394 	break;
   395     }
   396     sh4r.sh4_state = SH4_STATE_RUNNING;
   397 }
   399 /**
   400  * Run a time slice (or portion of a timeslice) while the SH4 is sleeping.
   401  * Returns when either the SH4 wakes up (interrupt received) or the end of
   402  * the slice is reached. Updates sh4.slice_cycle with the exit time and
   403  * returns the same value.
   404  */
   405 uint32_t sh4_sleep_run_slice( uint32_t nanosecs )
   406 {
   407     int sleep_state = sh4r.sh4_state;
   408     assert( sleep_state != SH4_STATE_RUNNING );
   410     while( sh4r.event_pending < nanosecs ) {
   411 	sh4r.slice_cycle = sh4r.event_pending;
   412 	if( sh4r.event_types & PENDING_EVENT ) {
   413 	    event_execute();
   414 	}
   415 	if( sh4r.event_types & PENDING_IRQ ) {
   416 	    sh4_wakeup();
   417 	    return sh4r.slice_cycle;
   418 	}
   419     }
   420     sh4r.slice_cycle = nanosecs;
   421     return sh4r.slice_cycle;
   422 }
   425 /**
   426  * Compute the matrix tranform of fv given the matrix xf.
   427  * Both fv and xf are word-swapped as per the sh4r.fr banks
   428  */
   429 void sh4_ftrv( float *target )
   430 {
   431     float fv[4] = { target[1], target[0], target[3], target[2] };
   432     target[1] = sh4r.fr[1][1] * fv[0] + sh4r.fr[1][5]*fv[1] +
   433 	sh4r.fr[1][9]*fv[2] + sh4r.fr[1][13]*fv[3];
   434     target[0] = sh4r.fr[1][0] * fv[0] + sh4r.fr[1][4]*fv[1] +
   435 	sh4r.fr[1][8]*fv[2] + sh4r.fr[1][12]*fv[3];
   436     target[3] = sh4r.fr[1][3] * fv[0] + sh4r.fr[1][7]*fv[1] +
   437 	sh4r.fr[1][11]*fv[2] + sh4r.fr[1][15]*fv[3];
   438     target[2] = sh4r.fr[1][2] * fv[0] + sh4r.fr[1][6]*fv[1] +
   439 	sh4r.fr[1][10]*fv[2] + sh4r.fr[1][14]*fv[3];
   440 }
   442 gboolean sh4_has_page( sh4vma_t vma )
   443 {
   444     sh4addr_t addr = mmu_vma_to_phys_disasm(vma);
   445     return addr != MMU_VMA_ERROR && mem_has_page(addr);
   446 }
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