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lxdream.org :: lxdream/src/sh4/sh4core.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4core.c
changeset 669:ab344e42bca9
prev641:afb9a42c61c6
next671:a530ea88eebd
author nkeynes
date Mon May 12 10:00:13 2008 +0000 (13 years ago)
permissions -rw-r--r--
last change Cleanup most of the -Wall warnings (getting a bit sloppy...)
Convert FP code to use fixed banks rather than indirect pointer
(3-4% faster this way now)
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     1 /**
     2  * $Id$
     3  * 
     4  * SH4 emulation core, and parent module for all the SH4 peripheral
     5  * modules.
     6  *
     7  * Copyright (c) 2005 Nathan Keynes.
     8  *
     9  * This program is free software; you can redistribute it and/or modify
    10  * it under the terms of the GNU General Public License as published by
    11  * the Free Software Foundation; either version 2 of the License, or
    12  * (at your option) any later version.
    13  *
    14  * This program is distributed in the hope that it will be useful,
    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17  * GNU General Public License for more details.
    18  */
    20 #define MODULE sh4_module
    21 #include <assert.h>
    22 #include <math.h>
    23 #include "dream.h"
    24 #include "dreamcast.h"
    25 #include "eventq.h"
    26 #include "mem.h"
    27 #include "clock.h"
    28 #include "syscall.h"
    29 #include "sh4/sh4core.h"
    30 #include "sh4/sh4mmio.h"
    31 #include "sh4/intc.h"
    33 #define SH4_CALLTRACE 1
    35 #define MAX_INT 0x7FFFFFFF
    36 #define MIN_INT 0x80000000
    37 #define MAX_INTF 2147483647.0
    38 #define MIN_INTF -2147483648.0
    40 /********************** SH4 Module Definition ****************************/
    42 uint32_t sh4_run_slice( uint32_t nanosecs ) 
    43 {
    44     int i;
    45     sh4r.slice_cycle = 0;
    47     if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
    48 	sh4_sleep_run_slice(nanosecs);
    49     }
    51     if( sh4_breakpoint_count == 0 ) {
    52 	for( ; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
    53 	    if( SH4_EVENT_PENDING() ) {
    54 		if( sh4r.event_types & PENDING_EVENT ) {
    55 		    event_execute();
    56 		}
    57 		/* Eventq execute may (quite likely) deliver an immediate IRQ */
    58 		if( sh4r.event_types & PENDING_IRQ ) {
    59 		    sh4_accept_interrupt();
    60 		}
    61 	    }
    62 	    if( !sh4_execute_instruction() ) {
    63 		break;
    64 	    }
    65 	}
    66     } else {
    67 	for( ;sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
    68 	    if( SH4_EVENT_PENDING() ) {
    69 		if( sh4r.event_types & PENDING_EVENT ) {
    70 		    event_execute();
    71 		}
    72 		/* Eventq execute may (quite likely) deliver an immediate IRQ */
    73 		if( sh4r.event_types & PENDING_IRQ ) {
    74 		    sh4_accept_interrupt();
    75 		}
    76 	    }
    78 	    if( !sh4_execute_instruction() )
    79 		break;
    80 #ifdef ENABLE_DEBUG_MODE
    81 	    for( i=0; i<sh4_breakpoint_count; i++ ) {
    82 		if( sh4_breakpoints[i].address == sh4r.pc ) {
    83 		    break;
    84 		}
    85 	    }
    86 	    if( i != sh4_breakpoint_count ) {
    87 		dreamcast_stop();
    88 		if( sh4_breakpoints[i].type == BREAK_ONESHOT )
    89 		    sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );
    90 		break;
    91 	    }
    92 #endif	
    93 	}
    94     }
    96     /* If we aborted early, but the cpu is still technically running,
    97      * we're doing a hard abort - cut the timeslice back to what we
    98      * actually executed
    99      */
   100     if( sh4r.slice_cycle != nanosecs && sh4r.sh4_state == SH4_STATE_RUNNING ) {
   101 	nanosecs = sh4r.slice_cycle;
   102     }
   103     if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
   104 	TMU_run_slice( nanosecs );
   105 	SCIF_run_slice( nanosecs );
   106     }
   107     return nanosecs;
   108 }
   110 /********************** SH4 emulation core  ****************************/
   112 #define UNDEF(ir) return sh4_raise_slot_exception(EXC_ILLEGAL, EXC_SLOT_ILLEGAL)
   113 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)
   115 #if(SH4_CALLTRACE == 1)
   116 #define MAX_CALLSTACK 32
   117 static struct call_stack {
   118     sh4addr_t call_addr;
   119     sh4addr_t target_addr;
   120     sh4addr_t stack_pointer;
   121 } call_stack[MAX_CALLSTACK];
   123 static int call_stack_depth = 0;
   124 int sh4_call_trace_on = 0;
   126 static inline void trace_call( sh4addr_t source, sh4addr_t dest ) 
   127 {
   128     if( call_stack_depth < MAX_CALLSTACK ) {
   129 	call_stack[call_stack_depth].call_addr = source;
   130 	call_stack[call_stack_depth].target_addr = dest;
   131 	call_stack[call_stack_depth].stack_pointer = sh4r.r[15];
   132     }
   133     call_stack_depth++;
   134 }
   136 static inline void trace_return( sh4addr_t source, sh4addr_t dest )
   137 {
   138     if( call_stack_depth > 0 ) {
   139 	call_stack_depth--;
   140     }
   141 }
   143 void fprint_stack_trace( FILE *f )
   144 {
   145     int i = call_stack_depth -1;
   146     if( i >= MAX_CALLSTACK )
   147 	i = MAX_CALLSTACK - 1;
   148     for( ; i >= 0; i-- ) {
   149 	fprintf( f, "%d. Call from %08X => %08X, SP=%08X\n", 
   150 		 (call_stack_depth - i), call_stack[i].call_addr,
   151 		 call_stack[i].target_addr, call_stack[i].stack_pointer );
   152     }
   153 }
   155 #define TRACE_CALL( source, dest ) trace_call(source, dest)
   156 #define TRACE_RETURN( source, dest ) trace_return(source, dest)
   157 #else
   158 #define TRACE_CALL( dest, rts ) 
   159 #define TRACE_RETURN( source, dest )
   160 #endif
   162 #define MEM_READ_BYTE( addr, val ) memtmp = mmu_vma_to_phys_read(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { val = sh4_read_byte(memtmp); }
   163 #define MEM_READ_WORD( addr, val ) memtmp = mmu_vma_to_phys_read(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { val = sh4_read_word(memtmp); }
   164 #define MEM_READ_LONG( addr, val ) memtmp = mmu_vma_to_phys_read(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { val = sh4_read_long(memtmp); }
   165 #define MEM_WRITE_BYTE( addr, val ) memtmp = mmu_vma_to_phys_write(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { sh4_write_byte(memtmp, val); }
   166 #define MEM_WRITE_WORD( addr, val ) memtmp = mmu_vma_to_phys_write(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { sh4_write_word(memtmp, val); }
   167 #define MEM_WRITE_LONG( addr, val ) memtmp = mmu_vma_to_phys_write(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { sh4_write_long(memtmp, val); }
   169 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
   171 #define MEM_FP_READ( addr, reg ) sh4_read_float( addr, reg );
   172 #define MEM_FP_WRITE( addr, reg ) sh4_write_float( addr, reg );
   174 #define CHECKPRIV() if( !IS_SH4_PRIVMODE() ) return sh4_raise_slot_exception( EXC_ILLEGAL, EXC_SLOT_ILLEGAL )
   175 #define CHECKRALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )
   176 #define CHECKRALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )
   177 #define CHECKWALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )
   178 #define CHECKWALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )
   180 #define CHECKFPUEN() if( !IS_FPU_ENABLED() ) { if( ir == 0xFFFD ) { UNDEF(ir); } else { return sh4_raise_slot_exception( EXC_FPU_DISABLED, EXC_SLOT_FPU_DISABLED ); } }
   181 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); dreamcast_stop(); return FALSE; }
   182 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) return sh4_raise_exception(EXC_SLOT_ILLEGAL)
   184 static void sh4_write_float( uint32_t addr, int reg )
   185 {
   186     if( IS_FPU_DOUBLESIZE() ) {
   187 	if( reg & 1 ) {
   188 	    sh4_write_long( addr, *((uint32_t *)&XF((reg)&0x0E)) );
   189 	    sh4_write_long( addr+4, *((uint32_t *)&XF(reg)) );
   190 	} else {
   191 	    sh4_write_long( addr, *((uint32_t *)&FR(reg)) ); 
   192 	    sh4_write_long( addr+4, *((uint32_t *)&FR((reg)|0x01)) );
   193 	}
   194     } else {
   195 	sh4_write_long( addr, *((uint32_t *)&FR((reg))) );
   196     }
   197 }
   199 static void sh4_read_float( uint32_t addr, int reg )
   200 {
   201     if( IS_FPU_DOUBLESIZE() ) {
   202 	if( reg & 1 ) {
   203 	    *((uint32_t *)&XF((reg) & 0x0E)) = sh4_read_long(addr);
   204 	    *((uint32_t *)&XF(reg)) = sh4_read_long(addr+4);
   205 	} else {
   206 	    *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
   207 	    *((uint32_t *)&FR((reg) | 0x01)) = sh4_read_long(addr+4);
   208 	}
   209     } else {
   210 	*((uint32_t *)&FR(reg)) = sh4_read_long(addr);
   211     }
   212 }
   214 gboolean sh4_execute_instruction( void )
   215 {
   216     uint32_t pc;
   217     unsigned short ir;
   218     uint32_t tmp;
   219     float ftmp;
   220     double dtmp;
   221     int64_t memtmp; // temporary holder for memory reads
   223 #define R0 sh4r.r[0]
   224     pc = sh4r.pc;
   225     if( pc > 0xFFFFFF00 ) {
   226 	/* SYSCALL Magic */
   227 	syscall_invoke( pc );
   228 	sh4r.in_delay_slot = 0;
   229 	pc = sh4r.pc = sh4r.pr;
   230 	sh4r.new_pc = sh4r.pc + 2;
   231     }
   232     CHECKRALIGN16(pc);
   234     /* Read instruction */
   235     if( !IS_IN_ICACHE(pc) ) {
   236 	if( !mmu_update_icache(pc) ) {
   237 	    // Fault - look for the fault handler
   238 	    if( !mmu_update_icache(sh4r.pc) ) {
   239 		// double fault - halt
   240 		ERROR( "Double fault - halting" );
   241 		dreamcast_stop();
   242 		return FALSE;
   243 	    }
   244 	}
   245 	pc = sh4r.pc;
   246     }
   247     assert( IS_IN_ICACHE(pc) );
   248     ir = *(uint16_t *)GET_ICACHE_PTR(sh4r.pc);
   249         switch( (ir&0xF000) >> 12 ) {
   250             case 0x0:
   251                 switch( ir&0xF ) {
   252                     case 0x2:
   253                         switch( (ir&0x80) >> 7 ) {
   254                             case 0x0:
   255                                 switch( (ir&0x70) >> 4 ) {
   256                                     case 0x0:
   257                                         { /* STC SR, Rn */
   258                                         uint32_t Rn = ((ir>>8)&0xF); 
   259                                         CHECKPRIV();
   260                                         sh4r.r[Rn] = sh4_read_sr();
   261                                         }
   262                                         break;
   263                                     case 0x1:
   264                                         { /* STC GBR, Rn */
   265                                         uint32_t Rn = ((ir>>8)&0xF); 
   266                                         sh4r.r[Rn] = sh4r.gbr;
   267                                         }
   268                                         break;
   269                                     case 0x2:
   270                                         { /* STC VBR, Rn */
   271                                         uint32_t Rn = ((ir>>8)&0xF); 
   272                                         CHECKPRIV();
   273                                         sh4r.r[Rn] = sh4r.vbr;
   274                                         }
   275                                         break;
   276                                     case 0x3:
   277                                         { /* STC SSR, Rn */
   278                                         uint32_t Rn = ((ir>>8)&0xF); 
   279                                         CHECKPRIV();
   280                                         sh4r.r[Rn] = sh4r.ssr;
   281                                         }
   282                                         break;
   283                                     case 0x4:
   284                                         { /* STC SPC, Rn */
   285                                         uint32_t Rn = ((ir>>8)&0xF); 
   286                                         CHECKPRIV();
   287                                         sh4r.r[Rn] = sh4r.spc;
   288                                         }
   289                                         break;
   290                                     default:
   291                                         UNDEF();
   292                                         break;
   293                                 }
   294                                 break;
   295                             case 0x1:
   296                                 { /* STC Rm_BANK, Rn */
   297                                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
   298                                 CHECKPRIV();
   299                                 sh4r.r[Rn] = sh4r.r_bank[Rm_BANK];
   300                                 }
   301                                 break;
   302                         }
   303                         break;
   304                     case 0x3:
   305                         switch( (ir&0xF0) >> 4 ) {
   306                             case 0x0:
   307                                 { /* BSRF Rn */
   308                                 uint32_t Rn = ((ir>>8)&0xF); 
   309                                 CHECKSLOTILLEGAL();
   310                                 CHECKDEST( pc + 4 + sh4r.r[Rn] );
   311                                 sh4r.in_delay_slot = 1;
   312                                 sh4r.pr = sh4r.pc + 4;
   313                                 sh4r.pc = sh4r.new_pc;
   314                                 sh4r.new_pc = pc + 4 + sh4r.r[Rn];
   315                                 TRACE_CALL( pc, sh4r.new_pc );
   316                                 return TRUE;
   317                                 }
   318                                 break;
   319                             case 0x2:
   320                                 { /* BRAF Rn */
   321                                 uint32_t Rn = ((ir>>8)&0xF); 
   322                                 CHECKSLOTILLEGAL();
   323                                 CHECKDEST( pc + 4 + sh4r.r[Rn] );
   324                                 sh4r.in_delay_slot = 1;
   325                                 sh4r.pc = sh4r.new_pc;
   326                                 sh4r.new_pc = pc + 4 + sh4r.r[Rn];
   327                                 return TRUE;
   328                                 }
   329                                 break;
   330                             case 0x8:
   331                                 { /* PREF @Rn */
   332                                 uint32_t Rn = ((ir>>8)&0xF); 
   333                                 tmp = sh4r.r[Rn];
   334                                 if( (tmp & 0xFC000000) == 0xE0000000 ) {
   335                            	 sh4_flush_store_queue(tmp);
   336                                 }
   337                                 }
   338                                 break;
   339                             case 0x9:
   340                                 { /* OCBI @Rn */
   341                                 uint32_t Rn = ((ir>>8)&0xF); 
   342                                 }
   343                                 break;
   344                             case 0xA:
   345                                 { /* OCBP @Rn */
   346                                 uint32_t Rn = ((ir>>8)&0xF); 
   347                                 }
   348                                 break;
   349                             case 0xB:
   350                                 { /* OCBWB @Rn */
   351                                 uint32_t Rn = ((ir>>8)&0xF); 
   352                                 }
   353                                 break;
   354                             case 0xC:
   355                                 { /* MOVCA.L R0, @Rn */
   356                                 uint32_t Rn = ((ir>>8)&0xF); 
   357                                 tmp = sh4r.r[Rn];
   358                                 CHECKWALIGN32(tmp);
   359                                 MEM_WRITE_LONG( tmp, R0 );
   360                                 }
   361                                 break;
   362                             default:
   363                                 UNDEF();
   364                                 break;
   365                         }
   366                         break;
   367                     case 0x4:
   368                         { /* MOV.B Rm, @(R0, Rn) */
   369                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   370                         MEM_WRITE_BYTE( R0 + sh4r.r[Rn], sh4r.r[Rm] );
   371                         }
   372                         break;
   373                     case 0x5:
   374                         { /* MOV.W Rm, @(R0, Rn) */
   375                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   376                         CHECKWALIGN16( R0 + sh4r.r[Rn] );
   377                         MEM_WRITE_WORD( R0 + sh4r.r[Rn], sh4r.r[Rm] );
   378                         }
   379                         break;
   380                     case 0x6:
   381                         { /* MOV.L Rm, @(R0, Rn) */
   382                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   383                         CHECKWALIGN32( R0 + sh4r.r[Rn] );
   384                         MEM_WRITE_LONG( R0 + sh4r.r[Rn], sh4r.r[Rm] );
   385                         }
   386                         break;
   387                     case 0x7:
   388                         { /* MUL.L Rm, Rn */
   389                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   390                         sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   391                                                (sh4r.r[Rm] * sh4r.r[Rn]);
   392                         }
   393                         break;
   394                     case 0x8:
   395                         switch( (ir&0xFF0) >> 4 ) {
   396                             case 0x0:
   397                                 { /* CLRT */
   398                                 sh4r.t = 0;
   399                                 }
   400                                 break;
   401                             case 0x1:
   402                                 { /* SETT */
   403                                 sh4r.t = 1;
   404                                 }
   405                                 break;
   406                             case 0x2:
   407                                 { /* CLRMAC */
   408                                 sh4r.mac = 0;
   409                                 }
   410                                 break;
   411                             case 0x3:
   412                                 { /* LDTLB */
   413                                 MMU_ldtlb();
   414                                 }
   415                                 break;
   416                             case 0x4:
   417                                 { /* CLRS */
   418                                 sh4r.s = 0;
   419                                 }
   420                                 break;
   421                             case 0x5:
   422                                 { /* SETS */
   423                                 sh4r.s = 1;
   424                                 }
   425                                 break;
   426                             default:
   427                                 UNDEF();
   428                                 break;
   429                         }
   430                         break;
   431                     case 0x9:
   432                         switch( (ir&0xF0) >> 4 ) {
   433                             case 0x0:
   434                                 { /* NOP */
   435                                 /* NOP */
   436                                 }
   437                                 break;
   438                             case 0x1:
   439                                 { /* DIV0U */
   440                                 sh4r.m = sh4r.q = sh4r.t = 0;
   441                                 }
   442                                 break;
   443                             case 0x2:
   444                                 { /* MOVT Rn */
   445                                 uint32_t Rn = ((ir>>8)&0xF); 
   446                                 sh4r.r[Rn] = sh4r.t;
   447                                 }
   448                                 break;
   449                             default:
   450                                 UNDEF();
   451                                 break;
   452                         }
   453                         break;
   454                     case 0xA:
   455                         switch( (ir&0xF0) >> 4 ) {
   456                             case 0x0:
   457                                 { /* STS MACH, Rn */
   458                                 uint32_t Rn = ((ir>>8)&0xF); 
   459                                 sh4r.r[Rn] = (sh4r.mac>>32);
   460                                 }
   461                                 break;
   462                             case 0x1:
   463                                 { /* STS MACL, Rn */
   464                                 uint32_t Rn = ((ir>>8)&0xF); 
   465                                 sh4r.r[Rn] = (uint32_t)sh4r.mac;
   466                                 }
   467                                 break;
   468                             case 0x2:
   469                                 { /* STS PR, Rn */
   470                                 uint32_t Rn = ((ir>>8)&0xF); 
   471                                 sh4r.r[Rn] = sh4r.pr;
   472                                 }
   473                                 break;
   474                             case 0x3:
   475                                 { /* STC SGR, Rn */
   476                                 uint32_t Rn = ((ir>>8)&0xF); 
   477                                 CHECKPRIV();
   478                                 sh4r.r[Rn] = sh4r.sgr;
   479                                 }
   480                                 break;
   481                             case 0x5:
   482                                 { /* STS FPUL, Rn */
   483                                 uint32_t Rn = ((ir>>8)&0xF); 
   484                                 CHECKFPUEN();
   485                                 sh4r.r[Rn] = FPULi;
   486                                 }
   487                                 break;
   488                             case 0x6:
   489                                 { /* STS FPSCR, Rn */
   490                                 uint32_t Rn = ((ir>>8)&0xF); 
   491                                 CHECKFPUEN();
   492                                 sh4r.r[Rn] = sh4r.fpscr;
   493                                 }
   494                                 break;
   495                             case 0xF:
   496                                 { /* STC DBR, Rn */
   497                                 uint32_t Rn = ((ir>>8)&0xF); 
   498                                 CHECKPRIV(); sh4r.r[Rn] = sh4r.dbr;
   499                                 }
   500                                 break;
   501                             default:
   502                                 UNDEF();
   503                                 break;
   504                         }
   505                         break;
   506                     case 0xB:
   507                         switch( (ir&0xFF0) >> 4 ) {
   508                             case 0x0:
   509                                 { /* RTS */
   510                                 CHECKSLOTILLEGAL();
   511                                 CHECKDEST( sh4r.pr );
   512                                 sh4r.in_delay_slot = 1;
   513                                 sh4r.pc = sh4r.new_pc;
   514                                 sh4r.new_pc = sh4r.pr;
   515                                 TRACE_RETURN( pc, sh4r.new_pc );
   516                                 return TRUE;
   517                                 }
   518                                 break;
   519                             case 0x1:
   520                                 { /* SLEEP */
   521                                 if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
   522                             	sh4r.sh4_state = SH4_STATE_STANDBY;
   523                                 } else {
   524                             	sh4r.sh4_state = SH4_STATE_SLEEP;
   525                                 }
   526                                 return FALSE; /* Halt CPU */
   527                                 }
   528                                 break;
   529                             case 0x2:
   530                                 { /* RTE */
   531                                 CHECKPRIV();
   532                                 CHECKDEST( sh4r.spc );
   533                                 CHECKSLOTILLEGAL();
   534                                 sh4r.in_delay_slot = 1;
   535                                 sh4r.pc = sh4r.new_pc;
   536                                 sh4r.new_pc = sh4r.spc;
   537                                 sh4_write_sr( sh4r.ssr );
   538                                 return TRUE;
   539                                 }
   540                                 break;
   541                             default:
   542                                 UNDEF();
   543                                 break;
   544                         }
   545                         break;
   546                     case 0xC:
   547                         { /* MOV.B @(R0, Rm), Rn */
   548                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   549                         MEM_READ_BYTE( R0 + sh4r.r[Rm], sh4r.r[Rn] );
   550                         }
   551                         break;
   552                     case 0xD:
   553                         { /* MOV.W @(R0, Rm), Rn */
   554                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   555                         CHECKRALIGN16( R0 + sh4r.r[Rm] );
   556                            MEM_READ_WORD( R0 + sh4r.r[Rm], sh4r.r[Rn] );
   557                         }
   558                         break;
   559                     case 0xE:
   560                         { /* MOV.L @(R0, Rm), Rn */
   561                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   562                         CHECKRALIGN32( R0 + sh4r.r[Rm] );
   563                            MEM_READ_LONG( R0 + sh4r.r[Rm], sh4r.r[Rn] );
   564                         }
   565                         break;
   566                     case 0xF:
   567                         { /* MAC.L @Rm+, @Rn+ */
   568                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   569                         int64_t tmpl;
   570                         if( Rm == Rn ) {
   571                     	CHECKRALIGN32( sh4r.r[Rn] );
   572                     	MEM_READ_LONG(sh4r.r[Rn], tmp);
   573                     	tmpl = SIGNEXT32(tmp);
   574                     	MEM_READ_LONG(sh4r.r[Rn]+4, tmp);
   575                     	tmpl = tmpl * SIGNEXT32(tmp) + sh4r.mac;
   576                     	sh4r.r[Rn] += 8;
   577                         } else {
   578                     	CHECKRALIGN32( sh4r.r[Rm] );
   579                     	CHECKRALIGN32( sh4r.r[Rn] );
   580                     	MEM_READ_LONG(sh4r.r[Rn], tmp);
   581                     	tmpl = SIGNEXT32(tmp);
   582                     	MEM_READ_LONG(sh4r.r[Rm], tmp);
   583                     	tmpl = tmpl * SIGNEXT32(tmp) + sh4r.mac;
   584                     	sh4r.r[Rn] += 4;
   585                     	sh4r.r[Rm] += 4;
   586                         }
   587                         if( sh4r.s ) {
   588                             /* 48-bit Saturation. Yuch */
   589                             if( tmpl < (int64_t)0xFFFF800000000000LL )
   590                                 tmpl = 0xFFFF800000000000LL;
   591                             else if( tmpl > (int64_t)0x00007FFFFFFFFFFFLL )
   592                                 tmpl = 0x00007FFFFFFFFFFFLL;
   593                         }
   594                         sh4r.mac = tmpl;
   595                         }
   596                         break;
   597                     default:
   598                         UNDEF();
   599                         break;
   600                 }
   601                 break;
   602             case 0x1:
   603                 { /* MOV.L Rm, @(disp, Rn) */
   604                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
   605                 tmp = sh4r.r[Rn] + disp;
   606                 CHECKWALIGN32( tmp );
   607                 MEM_WRITE_LONG( tmp, sh4r.r[Rm] );
   608                 }
   609                 break;
   610             case 0x2:
   611                 switch( ir&0xF ) {
   612                     case 0x0:
   613                         { /* MOV.B Rm, @Rn */
   614                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   615                         MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] );
   616                         }
   617                         break;
   618                     case 0x1:
   619                         { /* MOV.W Rm, @Rn */
   620                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   621                         CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] );
   622                         }
   623                         break;
   624                     case 0x2:
   625                         { /* MOV.L Rm, @Rn */
   626                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   627                         CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] );
   628                         }
   629                         break;
   630                     case 0x4:
   631                         { /* MOV.B Rm, @-Rn */
   632                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   633                         MEM_WRITE_BYTE( sh4r.r[Rn]-1, sh4r.r[Rm] ); sh4r.r[Rn]--;
   634                         }
   635                         break;
   636                     case 0x5:
   637                         { /* MOV.W Rm, @-Rn */
   638                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   639                         CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn]-2, sh4r.r[Rm] ); sh4r.r[Rn] -= 2;
   640                         }
   641                         break;
   642                     case 0x6:
   643                         { /* MOV.L Rm, @-Rn */
   644                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   645                         CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.r[Rm] ); sh4r.r[Rn] -= 4;
   646                         }
   647                         break;
   648                     case 0x7:
   649                         { /* DIV0S Rm, Rn */
   650                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   651                         sh4r.q = sh4r.r[Rn]>>31;
   652                         sh4r.m = sh4r.r[Rm]>>31;
   653                         sh4r.t = sh4r.q ^ sh4r.m;
   654                         }
   655                         break;
   656                     case 0x8:
   657                         { /* TST Rm, Rn */
   658                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   659                         sh4r.t = (sh4r.r[Rn]&sh4r.r[Rm] ? 0 : 1);
   660                         }
   661                         break;
   662                     case 0x9:
   663                         { /* AND Rm, Rn */
   664                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   665                         sh4r.r[Rn] &= sh4r.r[Rm];
   666                         }
   667                         break;
   668                     case 0xA:
   669                         { /* XOR Rm, Rn */
   670                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   671                         sh4r.r[Rn] ^= sh4r.r[Rm];
   672                         }
   673                         break;
   674                     case 0xB:
   675                         { /* OR Rm, Rn */
   676                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   677                         sh4r.r[Rn] |= sh4r.r[Rm];
   678                         }
   679                         break;
   680                     case 0xC:
   681                         { /* CMP/STR Rm, Rn */
   682                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   683                         /* set T = 1 if any byte in RM & RN is the same */
   684                         tmp = sh4r.r[Rm] ^ sh4r.r[Rn];
   685                         sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
   686                                  (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
   687                         }
   688                         break;
   689                     case 0xD:
   690                         { /* XTRCT Rm, Rn */
   691                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   692                         sh4r.r[Rn] = (sh4r.r[Rn]>>16) | (sh4r.r[Rm]<<16);
   693                         }
   694                         break;
   695                     case 0xE:
   696                         { /* MULU.W Rm, Rn */
   697                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   698                         sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   699                                    (uint32_t)((sh4r.r[Rm]&0xFFFF) * (sh4r.r[Rn]&0xFFFF));
   700                         }
   701                         break;
   702                     case 0xF:
   703                         { /* MULS.W Rm, Rn */
   704                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   705                         sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   706                                    (uint32_t)(SIGNEXT32(sh4r.r[Rm]&0xFFFF) * SIGNEXT32(sh4r.r[Rn]&0xFFFF));
   707                         }
   708                         break;
   709                     default:
   710                         UNDEF();
   711                         break;
   712                 }
   713                 break;
   714             case 0x3:
   715                 switch( ir&0xF ) {
   716                     case 0x0:
   717                         { /* CMP/EQ Rm, Rn */
   718                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   719                         sh4r.t = ( sh4r.r[Rm] == sh4r.r[Rn] ? 1 : 0 );
   720                         }
   721                         break;
   722                     case 0x2:
   723                         { /* CMP/HS Rm, Rn */
   724                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   725                         sh4r.t = ( sh4r.r[Rn] >= sh4r.r[Rm] ? 1 : 0 );
   726                         }
   727                         break;
   728                     case 0x3:
   729                         { /* CMP/GE Rm, Rn */
   730                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   731                         sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= ((int32_t)sh4r.r[Rm]) ? 1 : 0 );
   732                         }
   733                         break;
   734                     case 0x4:
   735                         { /* DIV1 Rm, Rn */
   736                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   737                         /* This is derived from the sh4 manual with some simplifications */
   738                         uint32_t tmp0, tmp1, tmp2, dir;
   740                         dir = sh4r.q ^ sh4r.m;
   741                         sh4r.q = (sh4r.r[Rn] >> 31);
   742                         tmp2 = sh4r.r[Rm];
   743                         sh4r.r[Rn] = (sh4r.r[Rn] << 1) | sh4r.t;
   744                         tmp0 = sh4r.r[Rn];
   745                         if( dir ) {
   746                              sh4r.r[Rn] += tmp2;
   747                              tmp1 = (sh4r.r[Rn]<tmp0 ? 1 : 0 );
   748                         } else {
   749                              sh4r.r[Rn] -= tmp2;
   750                              tmp1 = (sh4r.r[Rn]>tmp0 ? 1 : 0 );
   751                         }
   752                         sh4r.q ^= sh4r.m ^ tmp1;
   753                         sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
   754                         }
   755                         break;
   756                     case 0x5:
   757                         { /* DMULU.L Rm, Rn */
   758                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   759                         sh4r.mac = ((uint64_t)sh4r.r[Rm]) * ((uint64_t)sh4r.r[Rn]);
   760                         }
   761                         break;
   762                     case 0x6:
   763                         { /* CMP/HI Rm, Rn */
   764                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   765                         sh4r.t = ( sh4r.r[Rn] > sh4r.r[Rm] ? 1 : 0 );
   766                         }
   767                         break;
   768                     case 0x7:
   769                         { /* CMP/GT Rm, Rn */
   770                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   771                         sh4r.t = ( ((int32_t)sh4r.r[Rn]) > ((int32_t)sh4r.r[Rm]) ? 1 : 0 );
   772                         }
   773                         break;
   774                     case 0x8:
   775                         { /* SUB Rm, Rn */
   776                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   777                         sh4r.r[Rn] -= sh4r.r[Rm];
   778                         }
   779                         break;
   780                     case 0xA:
   781                         { /* SUBC Rm, Rn */
   782                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   783                         tmp = sh4r.r[Rn];
   784                         sh4r.r[Rn] = sh4r.r[Rn] - sh4r.r[Rm] - sh4r.t;
   785                         sh4r.t = (sh4r.r[Rn] > tmp || (sh4r.r[Rn] == tmp && sh4r.t == 1));
   786                         }
   787                         break;
   788                     case 0xB:
   789                         UNIMP(ir); /* SUBV Rm, Rn */
   790                         break;
   791                     case 0xC:
   792                         { /* ADD Rm, Rn */
   793                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   794                         sh4r.r[Rn] += sh4r.r[Rm];
   795                         }
   796                         break;
   797                     case 0xD:
   798                         { /* DMULS.L Rm, Rn */
   799                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   800                         sh4r.mac = SIGNEXT32(sh4r.r[Rm]) * SIGNEXT32(sh4r.r[Rn]);
   801                         }
   802                         break;
   803                     case 0xE:
   804                         { /* ADDC Rm, Rn */
   805                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   806                         tmp = sh4r.r[Rn];
   807                         sh4r.r[Rn] += sh4r.r[Rm] + sh4r.t;
   808                         sh4r.t = ( sh4r.r[Rn] < tmp || (sh4r.r[Rn] == tmp && sh4r.t != 0) ? 1 : 0 );
   809                         }
   810                         break;
   811                     case 0xF:
   812                         { /* ADDV Rm, Rn */
   813                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   814                         tmp = sh4r.r[Rn] + sh4r.r[Rm];
   815                         sh4r.t = ( (sh4r.r[Rn]>>31) == (sh4r.r[Rm]>>31) && ((sh4r.r[Rn]>>31) != (tmp>>31)) );
   816                         sh4r.r[Rn] = tmp;
   817                         }
   818                         break;
   819                     default:
   820                         UNDEF();
   821                         break;
   822                 }
   823                 break;
   824             case 0x4:
   825                 switch( ir&0xF ) {
   826                     case 0x0:
   827                         switch( (ir&0xF0) >> 4 ) {
   828                             case 0x0:
   829                                 { /* SHLL Rn */
   830                                 uint32_t Rn = ((ir>>8)&0xF); 
   831                                 sh4r.t = sh4r.r[Rn] >> 31; sh4r.r[Rn] <<= 1;
   832                                 }
   833                                 break;
   834                             case 0x1:
   835                                 { /* DT Rn */
   836                                 uint32_t Rn = ((ir>>8)&0xF); 
   837                                 sh4r.r[Rn] --;
   838                                 sh4r.t = ( sh4r.r[Rn] == 0 ? 1 : 0 );
   839                                 }
   840                                 break;
   841                             case 0x2:
   842                                 { /* SHAL Rn */
   843                                 uint32_t Rn = ((ir>>8)&0xF); 
   844                                 sh4r.t = sh4r.r[Rn] >> 31;
   845                                 sh4r.r[Rn] <<= 1;
   846                                 }
   847                                 break;
   848                             default:
   849                                 UNDEF();
   850                                 break;
   851                         }
   852                         break;
   853                     case 0x1:
   854                         switch( (ir&0xF0) >> 4 ) {
   855                             case 0x0:
   856                                 { /* SHLR Rn */
   857                                 uint32_t Rn = ((ir>>8)&0xF); 
   858                                 sh4r.t = sh4r.r[Rn] & 0x00000001; sh4r.r[Rn] >>= 1;
   859                                 }
   860                                 break;
   861                             case 0x1:
   862                                 { /* CMP/PZ Rn */
   863                                 uint32_t Rn = ((ir>>8)&0xF); 
   864                                 sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= 0 ? 1 : 0 );
   865                                 }
   866                                 break;
   867                             case 0x2:
   868                                 { /* SHAR Rn */
   869                                 uint32_t Rn = ((ir>>8)&0xF); 
   870                                 sh4r.t = sh4r.r[Rn] & 0x00000001;
   871                                 sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 1;
   872                                 }
   873                                 break;
   874                             default:
   875                                 UNDEF();
   876                                 break;
   877                         }
   878                         break;
   879                     case 0x2:
   880                         switch( (ir&0xF0) >> 4 ) {
   881                             case 0x0:
   882                                 { /* STS.L MACH, @-Rn */
   883                                 uint32_t Rn = ((ir>>8)&0xF); 
   884                                 CHECKWALIGN32( sh4r.r[Rn] );
   885                                 MEM_WRITE_LONG( sh4r.r[Rn]-4, (sh4r.mac>>32) );
   886                                 sh4r.r[Rn] -= 4;
   887                                 }
   888                                 break;
   889                             case 0x1:
   890                                 { /* STS.L MACL, @-Rn */
   891                                 uint32_t Rn = ((ir>>8)&0xF); 
   892                                 CHECKWALIGN32( sh4r.r[Rn] );
   893                                 MEM_WRITE_LONG( sh4r.r[Rn]-4, (uint32_t)sh4r.mac );
   894                                 sh4r.r[Rn] -= 4;
   895                                 }
   896                                 break;
   897                             case 0x2:
   898                                 { /* STS.L PR, @-Rn */
   899                                 uint32_t Rn = ((ir>>8)&0xF); 
   900                                 CHECKWALIGN32( sh4r.r[Rn] );
   901                                 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.pr );
   902                                 sh4r.r[Rn] -= 4;
   903                                 }
   904                                 break;
   905                             case 0x3:
   906                                 { /* STC.L SGR, @-Rn */
   907                                 uint32_t Rn = ((ir>>8)&0xF); 
   908                                 CHECKPRIV();
   909                                 CHECKWALIGN32( sh4r.r[Rn] );
   910                                 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.sgr );
   911                                 sh4r.r[Rn] -= 4;
   912                                 }
   913                                 break;
   914                             case 0x5:
   915                                 { /* STS.L FPUL, @-Rn */
   916                                 uint32_t Rn = ((ir>>8)&0xF); 
   917                                 CHECKFPUEN();
   918                                 CHECKWALIGN32( sh4r.r[Rn] );
   919                                 MEM_WRITE_LONG( sh4r.r[Rn]-4, FPULi );
   920                                 sh4r.r[Rn] -= 4;
   921                                 }
   922                                 break;
   923                             case 0x6:
   924                                 { /* STS.L FPSCR, @-Rn */
   925                                 uint32_t Rn = ((ir>>8)&0xF); 
   926                                 CHECKFPUEN();
   927                                 CHECKWALIGN32( sh4r.r[Rn] );
   928                                 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.fpscr );
   929                                 sh4r.r[Rn] -= 4;
   930                                 }
   931                                 break;
   932                             case 0xF:
   933                                 { /* STC.L DBR, @-Rn */
   934                                 uint32_t Rn = ((ir>>8)&0xF); 
   935                                 CHECKPRIV();
   936                                 CHECKWALIGN32( sh4r.r[Rn] );
   937                                 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.dbr );
   938                                 sh4r.r[Rn] -= 4;
   939                                 }
   940                                 break;
   941                             default:
   942                                 UNDEF();
   943                                 break;
   944                         }
   945                         break;
   946                     case 0x3:
   947                         switch( (ir&0x80) >> 7 ) {
   948                             case 0x0:
   949                                 switch( (ir&0x70) >> 4 ) {
   950                                     case 0x0:
   951                                         { /* STC.L SR, @-Rn */
   952                                         uint32_t Rn = ((ir>>8)&0xF); 
   953                                         CHECKPRIV();
   954                                         CHECKWALIGN32( sh4r.r[Rn] );
   955                                         MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4_read_sr() );
   956                                         sh4r.r[Rn] -= 4;
   957                                         }
   958                                         break;
   959                                     case 0x1:
   960                                         { /* STC.L GBR, @-Rn */
   961                                         uint32_t Rn = ((ir>>8)&0xF); 
   962                                         CHECKWALIGN32( sh4r.r[Rn] );
   963                                         MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.gbr );
   964                                         sh4r.r[Rn] -= 4;
   965                                         }
   966                                         break;
   967                                     case 0x2:
   968                                         { /* STC.L VBR, @-Rn */
   969                                         uint32_t Rn = ((ir>>8)&0xF); 
   970                                         CHECKPRIV();
   971                                         CHECKWALIGN32( sh4r.r[Rn] );
   972                                         MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.vbr );
   973                                         sh4r.r[Rn] -= 4;
   974                                         }
   975                                         break;
   976                                     case 0x3:
   977                                         { /* STC.L SSR, @-Rn */
   978                                         uint32_t Rn = ((ir>>8)&0xF); 
   979                                         CHECKPRIV();
   980                                         CHECKWALIGN32( sh4r.r[Rn] );
   981                                         MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.ssr );
   982                                         sh4r.r[Rn] -= 4;
   983                                         }
   984                                         break;
   985                                     case 0x4:
   986                                         { /* STC.L SPC, @-Rn */
   987                                         uint32_t Rn = ((ir>>8)&0xF); 
   988                                         CHECKPRIV();
   989                                         CHECKWALIGN32( sh4r.r[Rn] );
   990                                         MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.spc );
   991                                         sh4r.r[Rn] -= 4;
   992                                         }
   993                                         break;
   994                                     default:
   995                                         UNDEF();
   996                                         break;
   997                                 }
   998                                 break;
   999                             case 0x1:
  1000                                 { /* STC.L Rm_BANK, @-Rn */
  1001                                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
  1002                                 CHECKPRIV();
  1003                                 CHECKWALIGN32( sh4r.r[Rn] );
  1004                                 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.r_bank[Rm_BANK] );
  1005                                 sh4r.r[Rn] -= 4;
  1007                                 break;
  1009                         break;
  1010                     case 0x4:
  1011                         switch( (ir&0xF0) >> 4 ) {
  1012                             case 0x0:
  1013                                 { /* ROTL Rn */
  1014                                 uint32_t Rn = ((ir>>8)&0xF); 
  1015                                 sh4r.t = sh4r.r[Rn] >> 31;
  1016                                 sh4r.r[Rn] <<= 1;
  1017                                 sh4r.r[Rn] |= sh4r.t;
  1019                                 break;
  1020                             case 0x2:
  1021                                 { /* ROTCL Rn */
  1022                                 uint32_t Rn = ((ir>>8)&0xF); 
  1023                                 tmp = sh4r.r[Rn] >> 31;
  1024                                 sh4r.r[Rn] <<= 1;
  1025                                 sh4r.r[Rn] |= sh4r.t;
  1026                                 sh4r.t = tmp;
  1028                                 break;
  1029                             default:
  1030                                 UNDEF();
  1031                                 break;
  1033                         break;
  1034                     case 0x5:
  1035                         switch( (ir&0xF0) >> 4 ) {
  1036                             case 0x0:
  1037                                 { /* ROTR Rn */
  1038                                 uint32_t Rn = ((ir>>8)&0xF); 
  1039                                 sh4r.t = sh4r.r[Rn] & 0x00000001;
  1040                                 sh4r.r[Rn] >>= 1;
  1041                                 sh4r.r[Rn] |= (sh4r.t << 31);
  1043                                 break;
  1044                             case 0x1:
  1045                                 { /* CMP/PL Rn */
  1046                                 uint32_t Rn = ((ir>>8)&0xF); 
  1047                                 sh4r.t = ( ((int32_t)sh4r.r[Rn]) > 0 ? 1 : 0 );
  1049                                 break;
  1050                             case 0x2:
  1051                                 { /* ROTCR Rn */
  1052                                 uint32_t Rn = ((ir>>8)&0xF); 
  1053                                 tmp = sh4r.r[Rn] & 0x00000001;
  1054                                 sh4r.r[Rn] >>= 1;
  1055                                 sh4r.r[Rn] |= (sh4r.t << 31 );
  1056                                 sh4r.t = tmp;
  1058                                 break;
  1059                             default:
  1060                                 UNDEF();
  1061                                 break;
  1063                         break;
  1064                     case 0x6:
  1065                         switch( (ir&0xF0) >> 4 ) {
  1066                             case 0x0:
  1067                                 { /* LDS.L @Rm+, MACH */
  1068                                 uint32_t Rm = ((ir>>8)&0xF); 
  1069                                 CHECKRALIGN32( sh4r.r[Rm] );
  1070                                 MEM_READ_LONG(sh4r.r[Rm], tmp);
  1071                                 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
  1072                             	(((uint64_t)tmp)<<32);
  1073                                 sh4r.r[Rm] += 4;
  1075                                 break;
  1076                             case 0x1:
  1077                                 { /* LDS.L @Rm+, MACL */
  1078                                 uint32_t Rm = ((ir>>8)&0xF); 
  1079                                 CHECKRALIGN32( sh4r.r[Rm] );
  1080                                 MEM_READ_LONG(sh4r.r[Rm], tmp);
  1081                                 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
  1082                                            (uint64_t)((uint32_t)tmp);
  1083                                 sh4r.r[Rm] += 4;
  1085                                 break;
  1086                             case 0x2:
  1087                                 { /* LDS.L @Rm+, PR */
  1088                                 uint32_t Rm = ((ir>>8)&0xF); 
  1089                                 CHECKRALIGN32( sh4r.r[Rm] );
  1090                                 MEM_READ_LONG( sh4r.r[Rm], sh4r.pr );
  1091                                 sh4r.r[Rm] += 4;
  1093                                 break;
  1094                             case 0x3:
  1095                                 { /* LDC.L @Rm+, SGR */
  1096                                 uint32_t Rm = ((ir>>8)&0xF); 
  1097                                 CHECKPRIV();
  1098                                 CHECKRALIGN32( sh4r.r[Rm] );
  1099                                 MEM_READ_LONG(sh4r.r[Rm], sh4r.sgr);
  1100                                 sh4r.r[Rm] +=4;
  1102                                 break;
  1103                             case 0x5:
  1104                                 { /* LDS.L @Rm+, FPUL */
  1105                                 uint32_t Rm = ((ir>>8)&0xF); 
  1106                                 CHECKFPUEN();
  1107                                 CHECKRALIGN32( sh4r.r[Rm] );
  1108                                 MEM_READ_LONG(sh4r.r[Rm], FPULi);
  1109                                 sh4r.r[Rm] +=4;
  1111                                 break;
  1112                             case 0x6:
  1113                                 { /* LDS.L @Rm+, FPSCR */
  1114                                 uint32_t Rm = ((ir>>8)&0xF); 
  1115                                 CHECKFPUEN();
  1116                                 CHECKRALIGN32( sh4r.r[Rm] );
  1117                                 MEM_READ_LONG(sh4r.r[Rm], tmp);
  1118                                 sh4r.r[Rm] +=4;
  1119                                 sh4_write_fpscr( tmp );
  1121                                 break;
  1122                             case 0xF:
  1123                                 { /* LDC.L @Rm+, DBR */
  1124                                 uint32_t Rm = ((ir>>8)&0xF); 
  1125                                 CHECKPRIV();
  1126                                 CHECKRALIGN32( sh4r.r[Rm] );
  1127                                 MEM_READ_LONG(sh4r.r[Rm], sh4r.dbr);
  1128                                 sh4r.r[Rm] +=4;
  1130                                 break;
  1131                             default:
  1132                                 UNDEF();
  1133                                 break;
  1135                         break;
  1136                     case 0x7:
  1137                         switch( (ir&0x80) >> 7 ) {
  1138                             case 0x0:
  1139                                 switch( (ir&0x70) >> 4 ) {
  1140                                     case 0x0:
  1141                                         { /* LDC.L @Rm+, SR */
  1142                                         uint32_t Rm = ((ir>>8)&0xF); 
  1143                                         CHECKSLOTILLEGAL();
  1144                                         CHECKPRIV();
  1145                                         CHECKWALIGN32( sh4r.r[Rm] );
  1146                                         MEM_READ_LONG(sh4r.r[Rm], tmp);
  1147                                         sh4_write_sr( tmp );
  1148                                         sh4r.r[Rm] +=4;
  1150                                         break;
  1151                                     case 0x1:
  1152                                         { /* LDC.L @Rm+, GBR */
  1153                                         uint32_t Rm = ((ir>>8)&0xF); 
  1154                                         CHECKRALIGN32( sh4r.r[Rm] );
  1155                                         MEM_READ_LONG(sh4r.r[Rm], sh4r.gbr);
  1156                                         sh4r.r[Rm] +=4;
  1158                                         break;
  1159                                     case 0x2:
  1160                                         { /* LDC.L @Rm+, VBR */
  1161                                         uint32_t Rm = ((ir>>8)&0xF); 
  1162                                         CHECKPRIV();
  1163                                         CHECKRALIGN32( sh4r.r[Rm] );
  1164                                         MEM_READ_LONG(sh4r.r[Rm], sh4r.vbr);
  1165                                         sh4r.r[Rm] +=4;
  1167                                         break;
  1168                                     case 0x3:
  1169                                         { /* LDC.L @Rm+, SSR */
  1170                                         uint32_t Rm = ((ir>>8)&0xF); 
  1171                                         CHECKPRIV();
  1172                                         CHECKRALIGN32( sh4r.r[Rm] );
  1173                                         MEM_READ_LONG(sh4r.r[Rm], sh4r.ssr);
  1174                                         sh4r.r[Rm] +=4;
  1176                                         break;
  1177                                     case 0x4:
  1178                                         { /* LDC.L @Rm+, SPC */
  1179                                         uint32_t Rm = ((ir>>8)&0xF); 
  1180                                         CHECKPRIV();
  1181                                         CHECKRALIGN32( sh4r.r[Rm] );
  1182                                         MEM_READ_LONG(sh4r.r[Rm], sh4r.spc);
  1183                                         sh4r.r[Rm] +=4;
  1185                                         break;
  1186                                     default:
  1187                                         UNDEF();
  1188                                         break;
  1190                                 break;
  1191                             case 0x1:
  1192                                 { /* LDC.L @Rm+, Rn_BANK */
  1193                                 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
  1194                                 CHECKPRIV();
  1195                                 CHECKRALIGN32( sh4r.r[Rm] );
  1196                                 MEM_READ_LONG( sh4r.r[Rm], sh4r.r_bank[Rn_BANK] );
  1197                                 sh4r.r[Rm] += 4;
  1199                                 break;
  1201                         break;
  1202                     case 0x8:
  1203                         switch( (ir&0xF0) >> 4 ) {
  1204                             case 0x0:
  1205                                 { /* SHLL2 Rn */
  1206                                 uint32_t Rn = ((ir>>8)&0xF); 
  1207                                 sh4r.r[Rn] <<= 2;
  1209                                 break;
  1210                             case 0x1:
  1211                                 { /* SHLL8 Rn */
  1212                                 uint32_t Rn = ((ir>>8)&0xF); 
  1213                                 sh4r.r[Rn] <<= 8;
  1215                                 break;
  1216                             case 0x2:
  1217                                 { /* SHLL16 Rn */
  1218                                 uint32_t Rn = ((ir>>8)&0xF); 
  1219                                 sh4r.r[Rn] <<= 16;
  1221                                 break;
  1222                             default:
  1223                                 UNDEF();
  1224                                 break;
  1226                         break;
  1227                     case 0x9:
  1228                         switch( (ir&0xF0) >> 4 ) {
  1229                             case 0x0:
  1230                                 { /* SHLR2 Rn */
  1231                                 uint32_t Rn = ((ir>>8)&0xF); 
  1232                                 sh4r.r[Rn] >>= 2;
  1234                                 break;
  1235                             case 0x1:
  1236                                 { /* SHLR8 Rn */
  1237                                 uint32_t Rn = ((ir>>8)&0xF); 
  1238                                 sh4r.r[Rn] >>= 8;
  1240                                 break;
  1241                             case 0x2:
  1242                                 { /* SHLR16 Rn */
  1243                                 uint32_t Rn = ((ir>>8)&0xF); 
  1244                                 sh4r.r[Rn] >>= 16;
  1246                                 break;
  1247                             default:
  1248                                 UNDEF();
  1249                                 break;
  1251                         break;
  1252                     case 0xA:
  1253                         switch( (ir&0xF0) >> 4 ) {
  1254                             case 0x0:
  1255                                 { /* LDS Rm, MACH */
  1256                                 uint32_t Rm = ((ir>>8)&0xF); 
  1257                                 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
  1258                                            (((uint64_t)sh4r.r[Rm])<<32);
  1260                                 break;
  1261                             case 0x1:
  1262                                 { /* LDS Rm, MACL */
  1263                                 uint32_t Rm = ((ir>>8)&0xF); 
  1264                                 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
  1265                                            (uint64_t)((uint32_t)(sh4r.r[Rm]));
  1267                                 break;
  1268                             case 0x2:
  1269                                 { /* LDS Rm, PR */
  1270                                 uint32_t Rm = ((ir>>8)&0xF); 
  1271                                 sh4r.pr = sh4r.r[Rm];
  1273                                 break;
  1274                             case 0x3:
  1275                                 { /* LDC Rm, SGR */
  1276                                 uint32_t Rm = ((ir>>8)&0xF); 
  1277                                 CHECKPRIV();
  1278                                 sh4r.sgr = sh4r.r[Rm];
  1280                                 break;
  1281                             case 0x5:
  1282                                 { /* LDS Rm, FPUL */
  1283                                 uint32_t Rm = ((ir>>8)&0xF); 
  1284                                 CHECKFPUEN();
  1285                                 FPULi = sh4r.r[Rm];
  1287                                 break;
  1288                             case 0x6:
  1289                                 { /* LDS Rm, FPSCR */
  1290                                 uint32_t Rm = ((ir>>8)&0xF); 
  1291                                 CHECKFPUEN();
  1292                                 sh4_write_fpscr( sh4r.r[Rm] );
  1294                                 break;
  1295                             case 0xF:
  1296                                 { /* LDC Rm, DBR */
  1297                                 uint32_t Rm = ((ir>>8)&0xF); 
  1298                                 CHECKPRIV();
  1299                                 sh4r.dbr = sh4r.r[Rm];
  1301                                 break;
  1302                             default:
  1303                                 UNDEF();
  1304                                 break;
  1306                         break;
  1307                     case 0xB:
  1308                         switch( (ir&0xF0) >> 4 ) {
  1309                             case 0x0:
  1310                                 { /* JSR @Rn */
  1311                                 uint32_t Rn = ((ir>>8)&0xF); 
  1312                                 CHECKDEST( sh4r.r[Rn] );
  1313                                 CHECKSLOTILLEGAL();
  1314                                 sh4r.in_delay_slot = 1;
  1315                                 sh4r.pc = sh4r.new_pc;
  1316                                 sh4r.new_pc = sh4r.r[Rn];
  1317                                 sh4r.pr = pc + 4;
  1318                                 TRACE_CALL( pc, sh4r.new_pc );
  1319                                 return TRUE;
  1321                                 break;
  1322                             case 0x1:
  1323                                 { /* TAS.B @Rn */
  1324                                 uint32_t Rn = ((ir>>8)&0xF); 
  1325                                 MEM_READ_BYTE( sh4r.r[Rn], tmp );
  1326                                 sh4r.t = ( tmp == 0 ? 1 : 0 );
  1327                                 MEM_WRITE_BYTE( sh4r.r[Rn], tmp | 0x80 );
  1329                                 break;
  1330                             case 0x2:
  1331                                 { /* JMP @Rn */
  1332                                 uint32_t Rn = ((ir>>8)&0xF); 
  1333                                 CHECKDEST( sh4r.r[Rn] );
  1334                                 CHECKSLOTILLEGAL();
  1335                                 sh4r.in_delay_slot = 1;
  1336                                 sh4r.pc = sh4r.new_pc;
  1337                                 sh4r.new_pc = sh4r.r[Rn];
  1338                                 return TRUE;
  1340                                 break;
  1341                             default:
  1342                                 UNDEF();
  1343                                 break;
  1345                         break;
  1346                     case 0xC:
  1347                         { /* SHAD Rm, Rn */
  1348                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1349                         tmp = sh4r.r[Rm];
  1350                         if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
  1351                         else if( (tmp & 0x1F) == 0 )  
  1352                             sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 31;
  1353                         else 
  1354                     	sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> (((~sh4r.r[Rm]) & 0x1F)+1);
  1356                         break;
  1357                     case 0xD:
  1358                         { /* SHLD Rm, Rn */
  1359                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1360                         tmp = sh4r.r[Rm];
  1361                         if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
  1362                         else if( (tmp & 0x1F) == 0 ) sh4r.r[Rn] = 0;
  1363                         else sh4r.r[Rn] >>= (((~tmp) & 0x1F)+1);
  1365                         break;
  1366                     case 0xE:
  1367                         switch( (ir&0x80) >> 7 ) {
  1368                             case 0x0:
  1369                                 switch( (ir&0x70) >> 4 ) {
  1370                                     case 0x0:
  1371                                         { /* LDC Rm, SR */
  1372                                         uint32_t Rm = ((ir>>8)&0xF); 
  1373                                         CHECKSLOTILLEGAL();
  1374                                         CHECKPRIV();
  1375                                         sh4_write_sr( sh4r.r[Rm] );
  1377                                         break;
  1378                                     case 0x1:
  1379                                         { /* LDC Rm, GBR */
  1380                                         uint32_t Rm = ((ir>>8)&0xF); 
  1381                                         sh4r.gbr = sh4r.r[Rm];
  1383                                         break;
  1384                                     case 0x2:
  1385                                         { /* LDC Rm, VBR */
  1386                                         uint32_t Rm = ((ir>>8)&0xF); 
  1387                                         CHECKPRIV();
  1388                                         sh4r.vbr = sh4r.r[Rm];
  1390                                         break;
  1391                                     case 0x3:
  1392                                         { /* LDC Rm, SSR */
  1393                                         uint32_t Rm = ((ir>>8)&0xF); 
  1394                                         CHECKPRIV();
  1395                                         sh4r.ssr = sh4r.r[Rm];
  1397                                         break;
  1398                                     case 0x4:
  1399                                         { /* LDC Rm, SPC */
  1400                                         uint32_t Rm = ((ir>>8)&0xF); 
  1401                                         CHECKPRIV();
  1402                                         sh4r.spc = sh4r.r[Rm];
  1404                                         break;
  1405                                     default:
  1406                                         UNDEF();
  1407                                         break;
  1409                                 break;
  1410                             case 0x1:
  1411                                 { /* LDC Rm, Rn_BANK */
  1412                                 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
  1413                                 CHECKPRIV();
  1414                                 sh4r.r_bank[Rn_BANK] = sh4r.r[Rm];
  1416                                 break;
  1418                         break;
  1419                     case 0xF:
  1420                         { /* MAC.W @Rm+, @Rn+ */
  1421                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1422                         int32_t stmp;
  1423                         if( Rm == Rn ) {
  1424                     	CHECKRALIGN16(sh4r.r[Rn]);
  1425                     	MEM_READ_WORD( sh4r.r[Rn], tmp );
  1426                     	stmp = SIGNEXT16(tmp);
  1427                     	MEM_READ_WORD( sh4r.r[Rn]+2, tmp );
  1428                     	stmp *= SIGNEXT16(tmp);
  1429                     	sh4r.r[Rn] += 4;
  1430                         } else {
  1431                     	CHECKRALIGN16( sh4r.r[Rn] );
  1432                     	CHECKRALIGN16( sh4r.r[Rm] );
  1433                     	MEM_READ_WORD(sh4r.r[Rn], tmp);
  1434                     	stmp = SIGNEXT16(tmp);
  1435                     	MEM_READ_WORD(sh4r.r[Rm], tmp);
  1436                     	stmp = stmp * SIGNEXT16(tmp);
  1437                     	sh4r.r[Rn] += 2;
  1438                     	sh4r.r[Rm] += 2;
  1440                         if( sh4r.s ) {
  1441                     	int64_t tmpl = (int64_t)((int32_t)sh4r.mac) + (int64_t)stmp;
  1442                     	if( tmpl > (int64_t)0x000000007FFFFFFFLL ) {
  1443                     	    sh4r.mac = 0x000000017FFFFFFFLL;
  1444                     	} else if( tmpl < (int64_t)0xFFFFFFFF80000000LL ) {
  1445                     	    sh4r.mac = 0x0000000180000000LL;
  1446                     	} else {
  1447                     	    sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
  1448                     		((uint32_t)(sh4r.mac + stmp));
  1450                         } else {
  1451                     	sh4r.mac += SIGNEXT32(stmp);
  1454                         break;
  1456                 break;
  1457             case 0x5:
  1458                 { /* MOV.L @(disp, Rm), Rn */
  1459                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
  1460                 tmp = sh4r.r[Rm] + disp;
  1461                 CHECKRALIGN32( tmp );
  1462                 MEM_READ_LONG( tmp, sh4r.r[Rn] );
  1464                 break;
  1465             case 0x6:
  1466                 switch( ir&0xF ) {
  1467                     case 0x0:
  1468                         { /* MOV.B @Rm, Rn */
  1469                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1470                         MEM_READ_BYTE( sh4r.r[Rm], sh4r.r[Rn] );
  1472                         break;
  1473                     case 0x1:
  1474                         { /* MOV.W @Rm, Rn */
  1475                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1476                         CHECKRALIGN16( sh4r.r[Rm] ); MEM_READ_WORD( sh4r.r[Rm], sh4r.r[Rn] );
  1478                         break;
  1479                     case 0x2:
  1480                         { /* MOV.L @Rm, Rn */
  1481                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1482                         CHECKRALIGN32( sh4r.r[Rm] ); MEM_READ_LONG( sh4r.r[Rm], sh4r.r[Rn] );
  1484                         break;
  1485                     case 0x3:
  1486                         { /* MOV Rm, Rn */
  1487                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1488                         sh4r.r[Rn] = sh4r.r[Rm];
  1490                         break;
  1491                     case 0x4:
  1492                         { /* MOV.B @Rm+, Rn */
  1493                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1494                         MEM_READ_BYTE( sh4r.r[Rm], sh4r.r[Rn] ); sh4r.r[Rm] ++;
  1496                         break;
  1497                     case 0x5:
  1498                         { /* MOV.W @Rm+, Rn */
  1499                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1500                         CHECKRALIGN16( sh4r.r[Rm] ); MEM_READ_WORD( sh4r.r[Rm], sh4r.r[Rn] ); sh4r.r[Rm] += 2;
  1502                         break;
  1503                     case 0x6:
  1504                         { /* MOV.L @Rm+, Rn */
  1505                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1506                         CHECKRALIGN32( sh4r.r[Rm] ); MEM_READ_LONG( sh4r.r[Rm], sh4r.r[Rn] ); sh4r.r[Rm] += 4;
  1508                         break;
  1509                     case 0x7:
  1510                         { /* NOT Rm, Rn */
  1511                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1512                         sh4r.r[Rn] = ~sh4r.r[Rm];
  1514                         break;
  1515                     case 0x8:
  1516                         { /* SWAP.B Rm, Rn */
  1517                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1518                         sh4r.r[Rn] = (sh4r.r[Rm]&0xFFFF0000) | ((sh4r.r[Rm]&0x0000FF00)>>8) | ((sh4r.r[Rm]&0x000000FF)<<8);
  1520                         break;
  1521                     case 0x9:
  1522                         { /* SWAP.W Rm, Rn */
  1523                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1524                         sh4r.r[Rn] = (sh4r.r[Rm]>>16) | (sh4r.r[Rm]<<16);
  1526                         break;
  1527                     case 0xA:
  1528                         { /* NEGC Rm, Rn */
  1529                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1530                         tmp = 0 - sh4r.r[Rm];
  1531                         sh4r.r[Rn] = tmp - sh4r.t;
  1532                         sh4r.t = ( 0<tmp || tmp<sh4r.r[Rn] ? 1 : 0 );
  1534                         break;
  1535                     case 0xB:
  1536                         { /* NEG Rm, Rn */
  1537                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1538                         sh4r.r[Rn] = 0 - sh4r.r[Rm];
  1540                         break;
  1541                     case 0xC:
  1542                         { /* EXTU.B Rm, Rn */
  1543                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1544                         sh4r.r[Rn] = sh4r.r[Rm]&0x000000FF;
  1546                         break;
  1547                     case 0xD:
  1548                         { /* EXTU.W Rm, Rn */
  1549                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1550                         sh4r.r[Rn] = sh4r.r[Rm]&0x0000FFFF;
  1552                         break;
  1553                     case 0xE:
  1554                         { /* EXTS.B Rm, Rn */
  1555                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1556                         sh4r.r[Rn] = SIGNEXT8( sh4r.r[Rm]&0x000000FF );
  1558                         break;
  1559                     case 0xF:
  1560                         { /* EXTS.W Rm, Rn */
  1561                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1562                         sh4r.r[Rn] = SIGNEXT16( sh4r.r[Rm]&0x0000FFFF );
  1564                         break;
  1566                 break;
  1567             case 0x7:
  1568                 { /* ADD #imm, Rn */
  1569                 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
  1570                 sh4r.r[Rn] += imm;
  1572                 break;
  1573             case 0x8:
  1574                 switch( (ir&0xF00) >> 8 ) {
  1575                     case 0x0:
  1576                         { /* MOV.B R0, @(disp, Rn) */
  1577                         uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
  1578                         MEM_WRITE_BYTE( sh4r.r[Rn] + disp, R0 );
  1580                         break;
  1581                     case 0x1:
  1582                         { /* MOV.W R0, @(disp, Rn) */
  1583                         uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
  1584                         tmp = sh4r.r[Rn] + disp;
  1585                         CHECKWALIGN16( tmp );
  1586                         MEM_WRITE_WORD( tmp, R0 );
  1588                         break;
  1589                     case 0x4:
  1590                         { /* MOV.B @(disp, Rm), R0 */
  1591                         uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
  1592                         MEM_READ_BYTE( sh4r.r[Rm] + disp, R0 );
  1594                         break;
  1595                     case 0x5:
  1596                         { /* MOV.W @(disp, Rm), R0 */
  1597                         uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
  1598                         tmp = sh4r.r[Rm] + disp;
  1599                         CHECKRALIGN16( tmp );
  1600                         MEM_READ_WORD( tmp, R0 );
  1602                         break;
  1603                     case 0x8:
  1604                         { /* CMP/EQ #imm, R0 */
  1605                         int32_t imm = SIGNEXT8(ir&0xFF); 
  1606                         sh4r.t = ( R0 == imm ? 1 : 0 );
  1608                         break;
  1609                     case 0x9:
  1610                         { /* BT disp */
  1611                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  1612                         CHECKSLOTILLEGAL();
  1613                         if( sh4r.t ) {
  1614                             CHECKDEST( sh4r.pc + disp + 4 )
  1615                             sh4r.pc += disp + 4;
  1616                             sh4r.new_pc = sh4r.pc + 2;
  1617                             return TRUE;
  1620                         break;
  1621                     case 0xB:
  1622                         { /* BF disp */
  1623                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  1624                         CHECKSLOTILLEGAL();
  1625                         if( !sh4r.t ) {
  1626                             CHECKDEST( sh4r.pc + disp + 4 )
  1627                             sh4r.pc += disp + 4;
  1628                             sh4r.new_pc = sh4r.pc + 2;
  1629                             return TRUE;
  1632                         break;
  1633                     case 0xD:
  1634                         { /* BT/S disp */
  1635                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  1636                         CHECKSLOTILLEGAL();
  1637                         if( sh4r.t ) {
  1638                             CHECKDEST( sh4r.pc + disp + 4 )
  1639                             sh4r.in_delay_slot = 1;
  1640                             sh4r.pc = sh4r.new_pc;
  1641                             sh4r.new_pc = pc + disp + 4;
  1642                             sh4r.in_delay_slot = 1;
  1643                             return TRUE;
  1646                         break;
  1647                     case 0xF:
  1648                         { /* BF/S disp */
  1649                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  1650                         CHECKSLOTILLEGAL();
  1651                         if( !sh4r.t ) {
  1652                             CHECKDEST( sh4r.pc + disp + 4 )
  1653                             sh4r.in_delay_slot = 1;
  1654                             sh4r.pc = sh4r.new_pc;
  1655                             sh4r.new_pc = pc + disp + 4;
  1656                             return TRUE;
  1659                         break;
  1660                     default:
  1661                         UNDEF();
  1662                         break;
  1664                 break;
  1665             case 0x9:
  1666                 { /* MOV.W @(disp, PC), Rn */
  1667                 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1; 
  1668                 CHECKSLOTILLEGAL();
  1669                 tmp = pc + 4 + disp;
  1670                 MEM_READ_WORD( tmp, sh4r.r[Rn] );
  1672                 break;
  1673             case 0xA:
  1674                 { /* BRA disp */
  1675                 int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
  1676                 CHECKSLOTILLEGAL();
  1677                 CHECKDEST( sh4r.pc + disp + 4 );
  1678                 sh4r.in_delay_slot = 1;
  1679                 sh4r.pc = sh4r.new_pc;
  1680                 sh4r.new_pc = pc + 4 + disp;
  1681                 return TRUE;
  1683                 break;
  1684             case 0xB:
  1685                 { /* BSR disp */
  1686                 int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
  1687                 CHECKDEST( sh4r.pc + disp + 4 );
  1688                 CHECKSLOTILLEGAL();
  1689                 sh4r.in_delay_slot = 1;
  1690                 sh4r.pr = pc + 4;
  1691                 sh4r.pc = sh4r.new_pc;
  1692                 sh4r.new_pc = pc + 4 + disp;
  1693                 TRACE_CALL( pc, sh4r.new_pc );
  1694                 return TRUE;
  1696                 break;
  1697             case 0xC:
  1698                 switch( (ir&0xF00) >> 8 ) {
  1699                     case 0x0:
  1700                         { /* MOV.B R0, @(disp, GBR) */
  1701                         uint32_t disp = (ir&0xFF); 
  1702                         MEM_WRITE_BYTE( sh4r.gbr + disp, R0 );
  1704                         break;
  1705                     case 0x1:
  1706                         { /* MOV.W R0, @(disp, GBR) */
  1707                         uint32_t disp = (ir&0xFF)<<1; 
  1708                         tmp = sh4r.gbr + disp;
  1709                         CHECKWALIGN16( tmp );
  1710                         MEM_WRITE_WORD( tmp, R0 );
  1712                         break;
  1713                     case 0x2:
  1714                         { /* MOV.L R0, @(disp, GBR) */
  1715                         uint32_t disp = (ir&0xFF)<<2; 
  1716                         tmp = sh4r.gbr + disp;
  1717                         CHECKWALIGN32( tmp );
  1718                         MEM_WRITE_LONG( tmp, R0 );
  1720                         break;
  1721                     case 0x3:
  1722                         { /* TRAPA #imm */
  1723                         uint32_t imm = (ir&0xFF); 
  1724                         CHECKSLOTILLEGAL();
  1725                         sh4r.pc += 2;
  1726                         sh4_raise_trap( imm );
  1727                         return TRUE;
  1729                         break;
  1730                     case 0x4:
  1731                         { /* MOV.B @(disp, GBR), R0 */
  1732                         uint32_t disp = (ir&0xFF); 
  1733                         MEM_READ_BYTE( sh4r.gbr + disp, R0 );
  1735                         break;
  1736                     case 0x5:
  1737                         { /* MOV.W @(disp, GBR), R0 */
  1738                         uint32_t disp = (ir&0xFF)<<1; 
  1739                         tmp = sh4r.gbr + disp;
  1740                         CHECKRALIGN16( tmp );
  1741                         MEM_READ_WORD( tmp, R0 );
  1743                         break;
  1744                     case 0x6:
  1745                         { /* MOV.L @(disp, GBR), R0 */
  1746                         uint32_t disp = (ir&0xFF)<<2; 
  1747                         tmp = sh4r.gbr + disp;
  1748                         CHECKRALIGN32( tmp );
  1749                         MEM_READ_LONG( tmp, R0 );
  1751                         break;
  1752                     case 0x7:
  1753                         { /* MOVA @(disp, PC), R0 */
  1754                         uint32_t disp = (ir&0xFF)<<2; 
  1755                         CHECKSLOTILLEGAL();
  1756                         R0 = (pc&0xFFFFFFFC) + disp + 4;
  1758                         break;
  1759                     case 0x8:
  1760                         { /* TST #imm, R0 */
  1761                         uint32_t imm = (ir&0xFF); 
  1762                         sh4r.t = (R0 & imm ? 0 : 1);
  1764                         break;
  1765                     case 0x9:
  1766                         { /* AND #imm, R0 */
  1767                         uint32_t imm = (ir&0xFF); 
  1768                         R0 &= imm;
  1770                         break;
  1771                     case 0xA:
  1772                         { /* XOR #imm, R0 */
  1773                         uint32_t imm = (ir&0xFF); 
  1774                         R0 ^= imm;
  1776                         break;
  1777                     case 0xB:
  1778                         { /* OR #imm, R0 */
  1779                         uint32_t imm = (ir&0xFF); 
  1780                         R0 |= imm;
  1782                         break;
  1783                     case 0xC:
  1784                         { /* TST.B #imm, @(R0, GBR) */
  1785                         uint32_t imm = (ir&0xFF); 
  1786                         MEM_READ_BYTE(R0+sh4r.gbr, tmp); sh4r.t = ( tmp & imm ? 0 : 1 );
  1788                         break;
  1789                     case 0xD:
  1790                         { /* AND.B #imm, @(R0, GBR) */
  1791                         uint32_t imm = (ir&0xFF); 
  1792                         MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm & tmp );
  1794                         break;
  1795                     case 0xE:
  1796                         { /* XOR.B #imm, @(R0, GBR) */
  1797                         uint32_t imm = (ir&0xFF); 
  1798                         MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm ^ tmp );
  1800                         break;
  1801                     case 0xF:
  1802                         { /* OR.B #imm, @(R0, GBR) */
  1803                         uint32_t imm = (ir&0xFF); 
  1804                         MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm | tmp );
  1806                         break;
  1808                 break;
  1809             case 0xD:
  1810                 { /* MOV.L @(disp, PC), Rn */
  1811                 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<2; 
  1812                 CHECKSLOTILLEGAL();
  1813                 tmp = (pc&0xFFFFFFFC) + disp + 4;
  1814                 MEM_READ_LONG( tmp, sh4r.r[Rn] );
  1816                 break;
  1817             case 0xE:
  1818                 { /* MOV #imm, Rn */
  1819                 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
  1820                 sh4r.r[Rn] = imm;
  1822                 break;
  1823             case 0xF:
  1824                 switch( ir&0xF ) {
  1825                     case 0x0:
  1826                         { /* FADD FRm, FRn */
  1827                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  1828                         CHECKFPUEN();
  1829                         if( IS_FPU_DOUBLEPREC() ) {
  1830                     	DR(FRn) += DR(FRm);
  1831                         } else {
  1832                     	FR(FRn) += FR(FRm);
  1835                         break;
  1836                     case 0x1:
  1837                         { /* FSUB FRm, FRn */
  1838                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  1839                         CHECKFPUEN();
  1840                         if( IS_FPU_DOUBLEPREC() ) {
  1841                     	DR(FRn) -= DR(FRm);
  1842                         } else {
  1843                     	FR(FRn) -= FR(FRm);
  1846                         break;
  1847                     case 0x2:
  1848                         { /* FMUL FRm, FRn */
  1849                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  1850                         CHECKFPUEN();
  1851                         if( IS_FPU_DOUBLEPREC() ) {
  1852                     	DR(FRn) *= DR(FRm);
  1853                         } else {
  1854                     	FR(FRn) *= FR(FRm);
  1857                         break;
  1858                     case 0x3:
  1859                         { /* FDIV FRm, FRn */
  1860                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  1861                         CHECKFPUEN();
  1862                         if( IS_FPU_DOUBLEPREC() ) {
  1863                     	DR(FRn) /= DR(FRm);
  1864                         } else {
  1865                     	FR(FRn) /= FR(FRm);
  1868                         break;
  1869                     case 0x4:
  1870                         { /* FCMP/EQ FRm, FRn */
  1871                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  1872                         CHECKFPUEN();
  1873                         if( IS_FPU_DOUBLEPREC() ) {
  1874                     	sh4r.t = ( DR(FRn) == DR(FRm) ? 1 : 0 );
  1875                         } else {
  1876                     	sh4r.t = ( FR(FRn) == FR(FRm) ? 1 : 0 );
  1879                         break;
  1880                     case 0x5:
  1881                         { /* FCMP/GT FRm, FRn */
  1882                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  1883                         CHECKFPUEN();
  1884                         if( IS_FPU_DOUBLEPREC() ) {
  1885                     	sh4r.t = ( DR(FRn) > DR(FRm) ? 1 : 0 );
  1886                         } else {
  1887                     	sh4r.t = ( FR(FRn) > FR(FRm) ? 1 : 0 );
  1890                         break;
  1891                     case 0x6:
  1892                         { /* FMOV @(R0, Rm), FRn */
  1893                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1894                         MEM_FP_READ( sh4r.r[Rm] + R0, FRn );
  1896                         break;
  1897                     case 0x7:
  1898                         { /* FMOV FRm, @(R0, Rn) */
  1899                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  1900                         MEM_FP_WRITE( sh4r.r[Rn] + R0, FRm );
  1902                         break;
  1903                     case 0x8:
  1904                         { /* FMOV @Rm, FRn */
  1905                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1906                         MEM_FP_READ( sh4r.r[Rm], FRn );
  1908                         break;
  1909                     case 0x9:
  1910                         { /* FMOV @Rm+, FRn */
  1911                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1912                         MEM_FP_READ( sh4r.r[Rm], FRn ); sh4r.r[Rm] += FP_WIDTH;
  1914                         break;
  1915                     case 0xA:
  1916                         { /* FMOV FRm, @Rn */
  1917                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  1918                         MEM_FP_WRITE( sh4r.r[Rn], FRm );
  1920                         break;
  1921                     case 0xB:
  1922                         { /* FMOV FRm, @-Rn */
  1923                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  1924                         MEM_FP_WRITE( sh4r.r[Rn] - FP_WIDTH, FRm ); sh4r.r[Rn] -= FP_WIDTH;
  1926                         break;
  1927                     case 0xC:
  1928                         { /* FMOV FRm, FRn */
  1929                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  1930                         if( IS_FPU_DOUBLESIZE() )
  1931                     	DR(FRn) = DR(FRm);
  1932                         else
  1933                     	FR(FRn) = FR(FRm);
  1935                         break;
  1936                     case 0xD:
  1937                         switch( (ir&0xF0) >> 4 ) {
  1938                             case 0x0:
  1939                                 { /* FSTS FPUL, FRn */
  1940                                 uint32_t FRn = ((ir>>8)&0xF); 
  1941                                 CHECKFPUEN(); FR(FRn) = FPULf;
  1943                                 break;
  1944                             case 0x1:
  1945                                 { /* FLDS FRm, FPUL */
  1946                                 uint32_t FRm = ((ir>>8)&0xF); 
  1947                                 CHECKFPUEN(); FPULf = FR(FRm);
  1949                                 break;
  1950                             case 0x2:
  1951                                 { /* FLOAT FPUL, FRn */
  1952                                 uint32_t FRn = ((ir>>8)&0xF); 
  1953                                 CHECKFPUEN();
  1954                                 if( IS_FPU_DOUBLEPREC() ) {
  1955                             	if( FRn&1 ) { // No, really...
  1956                             	    dtmp = (double)FPULi;
  1957                             	    FR(FRn) = *(((float *)&dtmp)+1);
  1958                             	} else {
  1959                             	    DRF(FRn>>1) = (double)FPULi;
  1961                                 } else {
  1962                             	FR(FRn) = (float)FPULi;
  1965                                 break;
  1966                             case 0x3:
  1967                                 { /* FTRC FRm, FPUL */
  1968                                 uint32_t FRm = ((ir>>8)&0xF); 
  1969                                 CHECKFPUEN();
  1970                                 if( IS_FPU_DOUBLEPREC() ) {
  1971                             	if( FRm&1 ) {
  1972                             	    dtmp = 0;
  1973                             	    *(((float *)&dtmp)+1) = FR(FRm);
  1974                             	} else {
  1975                             	    dtmp = DRF(FRm>>1);
  1977                                     if( dtmp >= MAX_INTF )
  1978                                         FPULi = MAX_INT;
  1979                                     else if( dtmp <= MIN_INTF )
  1980                                         FPULi = MIN_INT;
  1981                                     else 
  1982                                         FPULi = (int32_t)dtmp;
  1983                                 } else {
  1984                             	ftmp = FR(FRm);
  1985                             	if( ftmp >= MAX_INTF )
  1986                             	    FPULi = MAX_INT;
  1987                             	else if( ftmp <= MIN_INTF )
  1988                             	    FPULi = MIN_INT;
  1989                             	else
  1990                             	    FPULi = (int32_t)ftmp;
  1993                                 break;
  1994                             case 0x4:
  1995                                 { /* FNEG FRn */
  1996                                 uint32_t FRn = ((ir>>8)&0xF); 
  1997                                 CHECKFPUEN();
  1998                                 if( IS_FPU_DOUBLEPREC() ) {
  1999                             	DR(FRn) = -DR(FRn);
  2000                                 } else {
  2001                                     FR(FRn) = -FR(FRn);
  2004                                 break;
  2005                             case 0x5:
  2006                                 { /* FABS FRn */
  2007                                 uint32_t FRn = ((ir>>8)&0xF); 
  2008                                 CHECKFPUEN();
  2009                                 if( IS_FPU_DOUBLEPREC() ) {
  2010                             	DR(FRn) = fabs(DR(FRn));
  2011                                 } else {
  2012                                     FR(FRn) = fabsf(FR(FRn));
  2015                                 break;
  2016                             case 0x6:
  2017                                 { /* FSQRT FRn */
  2018                                 uint32_t FRn = ((ir>>8)&0xF); 
  2019                                 CHECKFPUEN();
  2020                                 if( IS_FPU_DOUBLEPREC() ) {
  2021                             	DR(FRn) = sqrt(DR(FRn));
  2022                                 } else {
  2023                                     FR(FRn) = sqrtf(FR(FRn));
  2026                                 break;
  2027                             case 0x7:
  2028                                 { /* FSRRA FRn */
  2029                                 uint32_t FRn = ((ir>>8)&0xF); 
  2030                                 CHECKFPUEN();
  2031                                 if( !IS_FPU_DOUBLEPREC() ) {
  2032                             	FR(FRn) = 1.0/sqrtf(FR(FRn));
  2035                                 break;
  2036                             case 0x8:
  2037                                 { /* FLDI0 FRn */
  2038                                 uint32_t FRn = ((ir>>8)&0xF); 
  2039                                 CHECKFPUEN();
  2040                                 if( IS_FPU_DOUBLEPREC() ) {
  2041                             	DR(FRn) = 0.0;
  2042                                 } else {
  2043                                     FR(FRn) = 0.0;
  2046                                 break;
  2047                             case 0x9:
  2048                                 { /* FLDI1 FRn */
  2049                                 uint32_t FRn = ((ir>>8)&0xF); 
  2050                                 CHECKFPUEN();
  2051                                 if( IS_FPU_DOUBLEPREC() ) {
  2052                             	DR(FRn) = 1.0;
  2053                                 } else {
  2054                                     FR(FRn) = 1.0;
  2057                                 break;
  2058                             case 0xA:
  2059                                 { /* FCNVSD FPUL, FRn */
  2060                                 uint32_t FRn = ((ir>>8)&0xF); 
  2061                                 CHECKFPUEN();
  2062                                 if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
  2063                             	DR(FRn) = (double)FPULf;
  2066                                 break;
  2067                             case 0xB:
  2068                                 { /* FCNVDS FRm, FPUL */
  2069                                 uint32_t FRm = ((ir>>8)&0xF); 
  2070                                 CHECKFPUEN();
  2071                                 if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
  2072                             	FPULf = (float)DR(FRm);
  2075                                 break;
  2076                             case 0xE:
  2077                                 { /* FIPR FVm, FVn */
  2078                                 uint32_t FVn = ((ir>>10)&0x3); uint32_t FVm = ((ir>>8)&0x3); 
  2079                                 CHECKFPUEN();
  2080                                 if( !IS_FPU_DOUBLEPREC() ) {
  2081                                     int tmp2 = FVn<<2;
  2082                                     tmp = FVm<<2;
  2083                                     FR(tmp2+3) = FR(tmp)*FR(tmp2) +
  2084                                         FR(tmp+1)*FR(tmp2+1) +
  2085                                         FR(tmp+2)*FR(tmp2+2) +
  2086                                         FR(tmp+3)*FR(tmp2+3);
  2089                                 break;
  2090                             case 0xF:
  2091                                 switch( (ir&0x100) >> 8 ) {
  2092                                     case 0x0:
  2093                                         { /* FSCA FPUL, FRn */
  2094                                         uint32_t FRn = ((ir>>9)&0x7)<<1; 
  2095                                         CHECKFPUEN();
  2096                                         if( !IS_FPU_DOUBLEPREC() ) {
  2097                                     	sh4_fsca( FPULi, &(DRF(FRn>>1)) );
  2098                                     	/*
  2099                                             float angle = (((float)(FPULi&0xFFFF))/65536.0) * 2 * M_PI;
  2100                                             FR(FRn) = sinf(angle);
  2101                                             FR((FRn)+1) = cosf(angle);
  2102                                     	*/
  2105                                         break;
  2106                                     case 0x1:
  2107                                         switch( (ir&0x200) >> 9 ) {
  2108                                             case 0x0:
  2109                                                 { /* FTRV XMTRX, FVn */
  2110                                                 uint32_t FVn = ((ir>>10)&0x3); 
  2111                                                 CHECKFPUEN();
  2112                                                 if( !IS_FPU_DOUBLEPREC() ) {
  2113                                             	sh4_ftrv(&(DRF(FVn<<1)) );
  2116                                                 break;
  2117                                             case 0x1:
  2118                                                 switch( (ir&0xC00) >> 10 ) {
  2119                                                     case 0x0:
  2120                                                         { /* FSCHG */
  2121                                                         CHECKFPUEN(); sh4r.fpscr ^= FPSCR_SZ;
  2123                                                         break;
  2124                                                     case 0x2:
  2125                                                         { /* FRCHG */
  2126                                                         CHECKFPUEN(); 
  2127                                                         sh4r.fpscr ^= FPSCR_FR; 
  2128                                                         sh4_switch_fr_banks();
  2130                                                         break;
  2131                                                     case 0x3:
  2132                                                         { /* UNDEF */
  2133                                                         UNDEF(ir);
  2135                                                         break;
  2136                                                     default:
  2137                                                         UNDEF();
  2138                                                         break;
  2140                                                 break;
  2142                                         break;
  2144                                 break;
  2145                             default:
  2146                                 UNDEF();
  2147                                 break;
  2149                         break;
  2150                     case 0xE:
  2151                         { /* FMAC FR0, FRm, FRn */
  2152                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2153                         CHECKFPUEN();
  2154                         if( IS_FPU_DOUBLEPREC() ) {
  2155                             DR(FRn) += DR(FRm)*DR(0);
  2156                         } else {
  2157                     	FR(FRn) += FR(FRm)*FR(0);
  2160                         break;
  2161                     default:
  2162                         UNDEF();
  2163                         break;
  2165                 break;
  2168     sh4r.pc = sh4r.new_pc;
  2169     sh4r.new_pc += 2;
  2170     sh4r.in_delay_slot = 0;
  2171     return TRUE;
.