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lxdream.org :: lxdream/src/sh4/sh4x86.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.c
changeset 669:ab344e42bca9
prev626:a010e30a30e9
next671:a530ea88eebd
author nkeynes
date Mon May 12 10:00:13 2008 +0000 (13 years ago)
permissions -rw-r--r--
last change Cleanup most of the -Wall warnings (getting a bit sloppy...)
Convert FP code to use fixed banks rather than indirect pointer
(3-4% faster this way now)
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     1 /**
     2  * $Id$
     3  * 
     4  * SH4 => x86 translation. This version does no real optimization, it just
     5  * outputs straight-line x86 code - it mainly exists to provide a baseline
     6  * to test the optimizing versions against.
     7  *
     8  * Copyright (c) 2007 Nathan Keynes.
     9  *
    10  * This program is free software; you can redistribute it and/or modify
    11  * it under the terms of the GNU General Public License as published by
    12  * the Free Software Foundation; either version 2 of the License, or
    13  * (at your option) any later version.
    14  *
    15  * This program is distributed in the hope that it will be useful,
    16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    18  * GNU General Public License for more details.
    19  */
    21 #include <assert.h>
    22 #include <math.h>
    24 #ifndef NDEBUG
    25 #define DEBUG_JUMPS 1
    26 #endif
    28 #include "sh4/xltcache.h"
    29 #include "sh4/sh4core.h"
    30 #include "sh4/sh4trans.h"
    31 #include "sh4/sh4mmio.h"
    32 #include "sh4/x86op.h"
    33 #include "clock.h"
    35 #define DEFAULT_BACKPATCH_SIZE 4096
    37 struct backpatch_record {
    38     uint32_t fixup_offset;
    39     uint32_t fixup_icount;
    40     int32_t exc_code;
    41 };
    43 #define MAX_RECOVERY_SIZE 2048
    45 #define DELAY_NONE 0
    46 #define DELAY_PC 1
    47 #define DELAY_PC_PR 2
    49 /** 
    50  * Struct to manage internal translation state. This state is not saved -
    51  * it is only valid between calls to sh4_translate_begin_block() and
    52  * sh4_translate_end_block()
    53  */
    54 struct sh4_x86_state {
    55     int in_delay_slot;
    56     gboolean priv_checked; /* true if we've already checked the cpu mode. */
    57     gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
    58     gboolean branch_taken; /* true if we branched unconditionally */
    59     uint32_t block_start_pc;
    60     uint32_t stack_posn;   /* Trace stack height for alignment purposes */
    61     int tstate;
    63     /* mode flags */
    64     gboolean tlb_on; /* True if tlb translation is active */
    66     /* Allocated memory for the (block-wide) back-patch list */
    67     struct backpatch_record *backpatch_list;
    68     uint32_t backpatch_posn;
    69     uint32_t backpatch_size;
    70 };
    72 #define TSTATE_NONE -1
    73 #define TSTATE_O    0
    74 #define TSTATE_C    2
    75 #define TSTATE_E    4
    76 #define TSTATE_NE   5
    77 #define TSTATE_G    0xF
    78 #define TSTATE_GE   0xD
    79 #define TSTATE_A    7
    80 #define TSTATE_AE   3
    82 /** Branch if T is set (either in the current cflags, or in sh4r.t) */
    83 #define JT_rel8(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
    84 	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
    85     OP(0x70+sh4_x86.tstate); MARK_JMP8(label); OP(-1)
    87 /** Branch if T is clear (either in the current cflags or in sh4r.t) */
    88 #define JF_rel8(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
    89 	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
    90     OP(0x70+ (sh4_x86.tstate^1)); MARK_JMP8(label); OP(-1)
    92 static struct sh4_x86_state sh4_x86;
    94 static uint32_t max_int = 0x7FFFFFFF;
    95 static uint32_t min_int = 0x80000000;
    96 static uint32_t save_fcw; /* save value for fpu control word */
    97 static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
    99 void sh4_translate_init(void)
   100 {
   101     sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
   102     sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(struct backpatch_record);
   103 }
   106 static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code )
   107 {
   108     if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
   109 	sh4_x86.backpatch_size <<= 1;
   110 	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, 
   111 					  sh4_x86.backpatch_size * sizeof(struct backpatch_record));
   112 	assert( sh4_x86.backpatch_list != NULL );
   113     }
   114     if( sh4_x86.in_delay_slot ) {
   115 	fixup_pc -= 2;
   116     }
   117     sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_offset = 
   118 	((uint8_t *)fixup_addr) - ((uint8_t *)xlat_current_block->code);
   119     sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1;
   120     sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code;
   121     sh4_x86.backpatch_posn++;
   122 }
   124 /**
   125  * Emit an instruction to load an SH4 reg into a real register
   126  */
   127 static inline void load_reg( int x86reg, int sh4reg ) 
   128 {
   129     /* mov [bp+n], reg */
   130     OP(0x8B);
   131     OP(0x45 + (x86reg<<3));
   132     OP(REG_OFFSET(r[sh4reg]));
   133 }
   135 static inline void load_reg16s( int x86reg, int sh4reg )
   136 {
   137     OP(0x0F);
   138     OP(0xBF);
   139     MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
   140 }
   142 static inline void load_reg16u( int x86reg, int sh4reg )
   143 {
   144     OP(0x0F);
   145     OP(0xB7);
   146     MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
   148 }
   150 #define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
   151 #define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
   152 /**
   153  * Emit an instruction to load an immediate value into a register
   154  */
   155 static inline void load_imm32( int x86reg, uint32_t value ) {
   156     /* mov #value, reg */
   157     OP(0xB8 + x86reg);
   158     OP32(value);
   159 }
   161 /**
   162  * Load an immediate 64-bit quantity (note: x86-64 only)
   163  */
   164 static inline void load_imm64( int x86reg, uint32_t value ) {
   165     /* mov #value, reg */
   166     REXW();
   167     OP(0xB8 + x86reg);
   168     OP64(value);
   169 }
   171 /**
   172  * Emit an instruction to store an SH4 reg (RN)
   173  */
   174 void static inline store_reg( int x86reg, int sh4reg ) {
   175     /* mov reg, [bp+n] */
   176     OP(0x89);
   177     OP(0x45 + (x86reg<<3));
   178     OP(REG_OFFSET(r[sh4reg]));
   179 }
   181 /**
   182  * Load an FR register (single-precision floating point) into an integer x86
   183  * register (eg for register-to-register moves)
   184  */
   185 #define load_fr(reg,frm)  OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[0][(frm)^1]) )
   186 #define load_xf(reg,frm)  OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[1][(frm)^1]) )
   188 /**
   189  * Load the low half of a DR register (DR or XD) into an integer x86 register 
   190  */
   191 #define load_dr0(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[frm&1][frm|0x01]) )
   192 #define load_dr1(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )
   194 /**
   195  * Store an FR register (single-precision floating point) from an integer x86+
   196  * register (eg for register-to-register moves)
   197  */
   198 #define store_fr(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[0][(frm)^1]) )
   199 #define store_xf(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[1][(frm)^1]) )
   201 #define store_dr0(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[frm&1][frm|0x01]) )
   202 #define store_dr1(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )
   205 #define push_fpul()  FLDF_sh4r(R_FPUL)
   206 #define pop_fpul()   FSTPF_sh4r(R_FPUL)
   207 #define push_fr(frm) FLDF_sh4r( REG_OFFSET(fr[0][(frm)^1]) )
   208 #define pop_fr(frm)  FSTPF_sh4r( REG_OFFSET(fr[0][(frm)^1]) )
   209 #define push_xf(frm) FLDF_sh4r( REG_OFFSET(fr[1][(frm)^1]) )
   210 #define pop_xf(frm)  FSTPF_sh4r( REG_OFFSET(fr[1][(frm)^1]) )
   211 #define push_dr(frm) FLDD_sh4r( REG_OFFSET(fr[0][(frm)&0x0E]) )
   212 #define pop_dr(frm)  FSTPD_sh4r( REG_OFFSET(fr[0][(frm)&0x0E]) )
   213 #define push_xdr(frm) FLDD_sh4r( REG_OFFSET(fr[1][(frm)&0x0E]) )
   214 #define pop_xdr(frm)  FSTPD_sh4r( REG_OFFSET(fr[1][(frm)&0x0E]) )
   218 /* Exception checks - Note that all exception checks will clobber EAX */
   220 #define check_priv( ) \
   221     if( !sh4_x86.priv_checked ) { \
   222 	sh4_x86.priv_checked = TRUE;\
   223 	load_spreg( R_EAX, R_SR );\
   224 	AND_imm32_r32( SR_MD, R_EAX );\
   225 	if( sh4_x86.in_delay_slot ) {\
   226 	    JE_exc( EXC_SLOT_ILLEGAL );\
   227 	} else {\
   228 	    JE_exc( EXC_ILLEGAL );\
   229 	}\
   230     }\
   232 #define check_fpuen( ) \
   233     if( !sh4_x86.fpuen_checked ) {\
   234 	sh4_x86.fpuen_checked = TRUE;\
   235 	load_spreg( R_EAX, R_SR );\
   236 	AND_imm32_r32( SR_FD, R_EAX );\
   237 	if( sh4_x86.in_delay_slot ) {\
   238 	    JNE_exc(EXC_SLOT_FPU_DISABLED);\
   239 	} else {\
   240 	    JNE_exc(EXC_FPU_DISABLED);\
   241 	}\
   242     }
   244 #define check_ralign16( x86reg ) \
   245     TEST_imm32_r32( 0x00000001, x86reg ); \
   246     JNE_exc(EXC_DATA_ADDR_READ)
   248 #define check_walign16( x86reg ) \
   249     TEST_imm32_r32( 0x00000001, x86reg ); \
   250     JNE_exc(EXC_DATA_ADDR_WRITE);
   252 #define check_ralign32( x86reg ) \
   253     TEST_imm32_r32( 0x00000003, x86reg ); \
   254     JNE_exc(EXC_DATA_ADDR_READ)
   256 #define check_walign32( x86reg ) \
   257     TEST_imm32_r32( 0x00000003, x86reg ); \
   258     JNE_exc(EXC_DATA_ADDR_WRITE);
   260 #define UNDEF()
   261 #define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
   262 #define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
   263 #define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
   264 #define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
   265 #define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
   266 #define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
   267 #define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
   269 /**
   270  * Perform MMU translation on the address in addr_reg for a read operation, iff the TLB is turned 
   271  * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.
   272  */
   273 #define MMU_TRANSLATE_READ( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
   275 #define MMU_TRANSLATE_READ_EXC( addr_reg, exc_code ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(exc_code); MEM_RESULT(addr_reg) }
   276 /**
   277  * Perform MMU translation on the address in addr_reg for a write operation, iff the TLB is turned 
   278  * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.
   279  */
   280 #define MMU_TRANSLATE_WRITE( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_write, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
   282 #define MEM_READ_SIZE (CALL_FUNC1_SIZE)
   283 #define MEM_WRITE_SIZE (CALL_FUNC2_SIZE)
   284 #define MMU_TRANSLATE_SIZE (sh4_x86.tlb_on ? (CALL_FUNC1_SIZE + 12) : 0 )
   286 #define SLOTILLEGAL() JMP_exc(EXC_SLOT_ILLEGAL); sh4_x86.in_delay_slot = DELAY_NONE; return 1;
   288 /****** Import appropriate calling conventions ******/
   289 #if SH4_TRANSLATOR == TARGET_X86_64
   290 #include "sh4/ia64abi.h"
   291 #else /* SH4_TRANSLATOR == TARGET_X86 */
   292 #ifdef APPLE_BUILD
   293 #include "sh4/ia32mac.h"
   294 #else
   295 #include "sh4/ia32abi.h"
   296 #endif
   297 #endif
   299 uint32_t sh4_translate_end_block_size()
   300 {
   301     if( sh4_x86.backpatch_posn <= 3 ) {
   302 	return EPILOGUE_SIZE + (sh4_x86.backpatch_posn*12);
   303     } else {
   304 	return EPILOGUE_SIZE + 48 + (sh4_x86.backpatch_posn-3)*15;
   305     }
   306 }
   309 /**
   310  * Embed a breakpoint into the generated code
   311  */
   312 void sh4_translate_emit_breakpoint( sh4vma_t pc )
   313 {
   314     load_imm32( R_EAX, pc );
   315     call_func1( sh4_translate_breakpoint_hit, R_EAX );
   316 }
   319 #define UNTRANSLATABLE(pc) !IS_IN_ICACHE(pc)
   321 /**
   322  * Embed a call to sh4_execute_instruction for situations that we
   323  * can't translate (just page-crossing delay slots at the moment).
   324  * Caller is responsible for setting new_pc before calling this function.
   325  *
   326  * Performs:
   327  *   Set PC = endpc
   328  *   Set sh4r.in_delay_slot = sh4_x86.in_delay_slot
   329  *   Update slice_cycle for endpc+2 (single step doesn't update slice_cycle)
   330  *   Call sh4_execute_instruction
   331  *   Call xlat_get_code_by_vma / xlat_get_code as for normal exit
   332  */
   333 void exit_block_emu( sh4vma_t endpc )
   334 {
   335     load_imm32( R_ECX, endpc - sh4_x86.block_start_pc );   // 5
   336     ADD_r32_sh4r( R_ECX, R_PC );
   338     load_imm32( R_ECX, (((endpc - sh4_x86.block_start_pc)>>1)+1)*sh4_cpu_period ); // 5
   339     ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );     // 6
   340     load_imm32( R_ECX, sh4_x86.in_delay_slot ? 1 : 0 );
   341     store_spreg( R_ECX, REG_OFFSET(in_delay_slot) );
   343     call_func0( sh4_execute_instruction );    
   344     load_spreg( R_EAX, R_PC );
   345     if( sh4_x86.tlb_on ) {
   346 	call_func1(xlat_get_code_by_vma,R_EAX);
   347     } else {
   348 	call_func1(xlat_get_code,R_EAX);
   349     }
   350     AND_imm8s_rptr( 0xFC, R_EAX );
   351     POP_r32(R_EBP);
   352     RET();
   353 } 
   355 /**
   356  * Translate a single instruction. Delayed branches are handled specially
   357  * by translating both branch and delayed instruction as a single unit (as
   358  * 
   359  * The instruction MUST be in the icache (assert check)
   360  *
   361  * @return true if the instruction marks the end of a basic block
   362  * (eg a branch or 
   363  */
   364 uint32_t sh4_translate_instruction( sh4vma_t pc )
   365 {
   366     uint32_t ir;
   367     /* Read instruction from icache */
   368     assert( IS_IN_ICACHE(pc) );
   369     ir = *(uint16_t *)GET_ICACHE_PTR(pc);
   371 	/* PC is not in the current icache - this usually means we're running
   372 	 * with MMU on, and we've gone past the end of the page. And since 
   373 	 * sh4_translate_block is pretty careful about this, it means we're
   374 	 * almost certainly in a delay slot.
   375 	 *
   376 	 * Since we can't assume the page is present (and we can't fault it in
   377 	 * at this point, inline a call to sh4_execute_instruction (with a few
   378 	 * small repairs to cope with the different environment).
   379 	 */
   381     if( !sh4_x86.in_delay_slot ) {
   382 	sh4_translate_add_recovery( (pc - sh4_x86.block_start_pc)>>1 );
   383     }
   384         switch( (ir&0xF000) >> 12 ) {
   385             case 0x0:
   386                 switch( ir&0xF ) {
   387                     case 0x2:
   388                         switch( (ir&0x80) >> 7 ) {
   389                             case 0x0:
   390                                 switch( (ir&0x70) >> 4 ) {
   391                                     case 0x0:
   392                                         { /* STC SR, Rn */
   393                                         uint32_t Rn = ((ir>>8)&0xF); 
   394                                         check_priv();
   395                                         call_func0(sh4_read_sr);
   396                                         store_reg( R_EAX, Rn );
   397                                         sh4_x86.tstate = TSTATE_NONE;
   398                                         }
   399                                         break;
   400                                     case 0x1:
   401                                         { /* STC GBR, Rn */
   402                                         uint32_t Rn = ((ir>>8)&0xF); 
   403                                         load_spreg( R_EAX, R_GBR );
   404                                         store_reg( R_EAX, Rn );
   405                                         }
   406                                         break;
   407                                     case 0x2:
   408                                         { /* STC VBR, Rn */
   409                                         uint32_t Rn = ((ir>>8)&0xF); 
   410                                         check_priv();
   411                                         load_spreg( R_EAX, R_VBR );
   412                                         store_reg( R_EAX, Rn );
   413                                         sh4_x86.tstate = TSTATE_NONE;
   414                                         }
   415                                         break;
   416                                     case 0x3:
   417                                         { /* STC SSR, Rn */
   418                                         uint32_t Rn = ((ir>>8)&0xF); 
   419                                         check_priv();
   420                                         load_spreg( R_EAX, R_SSR );
   421                                         store_reg( R_EAX, Rn );
   422                                         sh4_x86.tstate = TSTATE_NONE;
   423                                         }
   424                                         break;
   425                                     case 0x4:
   426                                         { /* STC SPC, Rn */
   427                                         uint32_t Rn = ((ir>>8)&0xF); 
   428                                         check_priv();
   429                                         load_spreg( R_EAX, R_SPC );
   430                                         store_reg( R_EAX, Rn );
   431                                         sh4_x86.tstate = TSTATE_NONE;
   432                                         }
   433                                         break;
   434                                     default:
   435                                         UNDEF();
   436                                         break;
   437                                 }
   438                                 break;
   439                             case 0x1:
   440                                 { /* STC Rm_BANK, Rn */
   441                                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
   442                                 check_priv();
   443                                 load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
   444                                 store_reg( R_EAX, Rn );
   445                                 sh4_x86.tstate = TSTATE_NONE;
   446                                 }
   447                                 break;
   448                         }
   449                         break;
   450                     case 0x3:
   451                         switch( (ir&0xF0) >> 4 ) {
   452                             case 0x0:
   453                                 { /* BSRF Rn */
   454                                 uint32_t Rn = ((ir>>8)&0xF); 
   455                                 if( sh4_x86.in_delay_slot ) {
   456                             	SLOTILLEGAL();
   457                                 } else {
   458                             	load_spreg( R_EAX, R_PC );
   459                             	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
   460                             	store_spreg( R_EAX, R_PR );
   461                             	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
   462                             	store_spreg( R_EAX, R_NEW_PC );
   464                             	sh4_x86.in_delay_slot = DELAY_PC;
   465                             	sh4_x86.tstate = TSTATE_NONE;
   466                             	sh4_x86.branch_taken = TRUE;
   467                             	if( UNTRANSLATABLE(pc+2) ) {
   468                             	    exit_block_emu(pc+2);
   469                             	    return 2;
   470                             	} else {
   471                             	    sh4_translate_instruction( pc + 2 );
   472                             	    exit_block_newpcset(pc+2);
   473                             	    return 4;
   474                             	}
   475                                 }
   476                                 }
   477                                 break;
   478                             case 0x2:
   479                                 { /* BRAF Rn */
   480                                 uint32_t Rn = ((ir>>8)&0xF); 
   481                                 if( sh4_x86.in_delay_slot ) {
   482                             	SLOTILLEGAL();
   483                                 } else {
   484                             	load_spreg( R_EAX, R_PC );
   485                             	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
   486                             	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
   487                             	store_spreg( R_EAX, R_NEW_PC );
   488                             	sh4_x86.in_delay_slot = DELAY_PC;
   489                             	sh4_x86.tstate = TSTATE_NONE;
   490                             	sh4_x86.branch_taken = TRUE;
   491                             	if( UNTRANSLATABLE(pc+2) ) {
   492                             	    exit_block_emu(pc+2);
   493                             	    return 2;
   494                             	} else {
   495                             	    sh4_translate_instruction( pc + 2 );
   496                             	    exit_block_newpcset(pc+2);
   497                             	    return 4;
   498                             	}
   499                                 }
   500                                 }
   501                                 break;
   502                             case 0x8:
   503                                 { /* PREF @Rn */
   504                                 uint32_t Rn = ((ir>>8)&0xF); 
   505                                 load_reg( R_EAX, Rn );
   506                                 MOV_r32_r32( R_EAX, R_ECX );
   507                                 AND_imm32_r32( 0xFC000000, R_EAX );
   508                                 CMP_imm32_r32( 0xE0000000, R_EAX );
   509                                 JNE_rel8(end);
   510                                 call_func1( sh4_flush_store_queue, R_ECX );
   511                                 TEST_r32_r32( R_EAX, R_EAX );
   512                                 JE_exc(-1);
   513                                 JMP_TARGET(end);
   514                                 sh4_x86.tstate = TSTATE_NONE;
   515                                 }
   516                                 break;
   517                             case 0x9:
   518                                 { /* OCBI @Rn */
   519                                 uint32_t Rn = ((ir>>8)&0xF); 
   520                                 }
   521                                 break;
   522                             case 0xA:
   523                                 { /* OCBP @Rn */
   524                                 uint32_t Rn = ((ir>>8)&0xF); 
   525                                 }
   526                                 break;
   527                             case 0xB:
   528                                 { /* OCBWB @Rn */
   529                                 uint32_t Rn = ((ir>>8)&0xF); 
   530                                 }
   531                                 break;
   532                             case 0xC:
   533                                 { /* MOVCA.L R0, @Rn */
   534                                 uint32_t Rn = ((ir>>8)&0xF); 
   535                                 load_reg( R_EAX, Rn );
   536                                 check_walign32( R_EAX );
   537                                 MMU_TRANSLATE_WRITE( R_EAX );
   538                                 load_reg( R_EDX, 0 );
   539                                 MEM_WRITE_LONG( R_EAX, R_EDX );
   540                                 sh4_x86.tstate = TSTATE_NONE;
   541                                 }
   542                                 break;
   543                             default:
   544                                 UNDEF();
   545                                 break;
   546                         }
   547                         break;
   548                     case 0x4:
   549                         { /* MOV.B Rm, @(R0, Rn) */
   550                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   551                         load_reg( R_EAX, 0 );
   552                         load_reg( R_ECX, Rn );
   553                         ADD_r32_r32( R_ECX, R_EAX );
   554                         MMU_TRANSLATE_WRITE( R_EAX );
   555                         load_reg( R_EDX, Rm );
   556                         MEM_WRITE_BYTE( R_EAX, R_EDX );
   557                         sh4_x86.tstate = TSTATE_NONE;
   558                         }
   559                         break;
   560                     case 0x5:
   561                         { /* MOV.W Rm, @(R0, Rn) */
   562                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   563                         load_reg( R_EAX, 0 );
   564                         load_reg( R_ECX, Rn );
   565                         ADD_r32_r32( R_ECX, R_EAX );
   566                         check_walign16( R_EAX );
   567                         MMU_TRANSLATE_WRITE( R_EAX );
   568                         load_reg( R_EDX, Rm );
   569                         MEM_WRITE_WORD( R_EAX, R_EDX );
   570                         sh4_x86.tstate = TSTATE_NONE;
   571                         }
   572                         break;
   573                     case 0x6:
   574                         { /* MOV.L Rm, @(R0, Rn) */
   575                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   576                         load_reg( R_EAX, 0 );
   577                         load_reg( R_ECX, Rn );
   578                         ADD_r32_r32( R_ECX, R_EAX );
   579                         check_walign32( R_EAX );
   580                         MMU_TRANSLATE_WRITE( R_EAX );
   581                         load_reg( R_EDX, Rm );
   582                         MEM_WRITE_LONG( R_EAX, R_EDX );
   583                         sh4_x86.tstate = TSTATE_NONE;
   584                         }
   585                         break;
   586                     case 0x7:
   587                         { /* MUL.L Rm, Rn */
   588                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   589                         load_reg( R_EAX, Rm );
   590                         load_reg( R_ECX, Rn );
   591                         MUL_r32( R_ECX );
   592                         store_spreg( R_EAX, R_MACL );
   593                         sh4_x86.tstate = TSTATE_NONE;
   594                         }
   595                         break;
   596                     case 0x8:
   597                         switch( (ir&0xFF0) >> 4 ) {
   598                             case 0x0:
   599                                 { /* CLRT */
   600                                 CLC();
   601                                 SETC_t();
   602                                 sh4_x86.tstate = TSTATE_C;
   603                                 }
   604                                 break;
   605                             case 0x1:
   606                                 { /* SETT */
   607                                 STC();
   608                                 SETC_t();
   609                                 sh4_x86.tstate = TSTATE_C;
   610                                 }
   611                                 break;
   612                             case 0x2:
   613                                 { /* CLRMAC */
   614                                 XOR_r32_r32(R_EAX, R_EAX);
   615                                 store_spreg( R_EAX, R_MACL );
   616                                 store_spreg( R_EAX, R_MACH );
   617                                 sh4_x86.tstate = TSTATE_NONE;
   618                                 }
   619                                 break;
   620                             case 0x3:
   621                                 { /* LDTLB */
   622                                 call_func0( MMU_ldtlb );
   623                                 }
   624                                 break;
   625                             case 0x4:
   626                                 { /* CLRS */
   627                                 CLC();
   628                                 SETC_sh4r(R_S);
   629                                 sh4_x86.tstate = TSTATE_C;
   630                                 }
   631                                 break;
   632                             case 0x5:
   633                                 { /* SETS */
   634                                 STC();
   635                                 SETC_sh4r(R_S);
   636                                 sh4_x86.tstate = TSTATE_C;
   637                                 }
   638                                 break;
   639                             default:
   640                                 UNDEF();
   641                                 break;
   642                         }
   643                         break;
   644                     case 0x9:
   645                         switch( (ir&0xF0) >> 4 ) {
   646                             case 0x0:
   647                                 { /* NOP */
   648                                 /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */
   649                                 }
   650                                 break;
   651                             case 0x1:
   652                                 { /* DIV0U */
   653                                 XOR_r32_r32( R_EAX, R_EAX );
   654                                 store_spreg( R_EAX, R_Q );
   655                                 store_spreg( R_EAX, R_M );
   656                                 store_spreg( R_EAX, R_T );
   657                                 sh4_x86.tstate = TSTATE_C; // works for DIV1
   658                                 }
   659                                 break;
   660                             case 0x2:
   661                                 { /* MOVT Rn */
   662                                 uint32_t Rn = ((ir>>8)&0xF); 
   663                                 load_spreg( R_EAX, R_T );
   664                                 store_reg( R_EAX, Rn );
   665                                 }
   666                                 break;
   667                             default:
   668                                 UNDEF();
   669                                 break;
   670                         }
   671                         break;
   672                     case 0xA:
   673                         switch( (ir&0xF0) >> 4 ) {
   674                             case 0x0:
   675                                 { /* STS MACH, Rn */
   676                                 uint32_t Rn = ((ir>>8)&0xF); 
   677                                 load_spreg( R_EAX, R_MACH );
   678                                 store_reg( R_EAX, Rn );
   679                                 }
   680                                 break;
   681                             case 0x1:
   682                                 { /* STS MACL, Rn */
   683                                 uint32_t Rn = ((ir>>8)&0xF); 
   684                                 load_spreg( R_EAX, R_MACL );
   685                                 store_reg( R_EAX, Rn );
   686                                 }
   687                                 break;
   688                             case 0x2:
   689                                 { /* STS PR, Rn */
   690                                 uint32_t Rn = ((ir>>8)&0xF); 
   691                                 load_spreg( R_EAX, R_PR );
   692                                 store_reg( R_EAX, Rn );
   693                                 }
   694                                 break;
   695                             case 0x3:
   696                                 { /* STC SGR, Rn */
   697                                 uint32_t Rn = ((ir>>8)&0xF); 
   698                                 check_priv();
   699                                 load_spreg( R_EAX, R_SGR );
   700                                 store_reg( R_EAX, Rn );
   701                                 sh4_x86.tstate = TSTATE_NONE;
   702                                 }
   703                                 break;
   704                             case 0x5:
   705                                 { /* STS FPUL, Rn */
   706                                 uint32_t Rn = ((ir>>8)&0xF); 
   707                                 check_fpuen();
   708                                 load_spreg( R_EAX, R_FPUL );
   709                                 store_reg( R_EAX, Rn );
   710                                 }
   711                                 break;
   712                             case 0x6:
   713                                 { /* STS FPSCR, Rn */
   714                                 uint32_t Rn = ((ir>>8)&0xF); 
   715                                 check_fpuen();
   716                                 load_spreg( R_EAX, R_FPSCR );
   717                                 store_reg( R_EAX, Rn );
   718                                 }
   719                                 break;
   720                             case 0xF:
   721                                 { /* STC DBR, Rn */
   722                                 uint32_t Rn = ((ir>>8)&0xF); 
   723                                 check_priv();
   724                                 load_spreg( R_EAX, R_DBR );
   725                                 store_reg( R_EAX, Rn );
   726                                 sh4_x86.tstate = TSTATE_NONE;
   727                                 }
   728                                 break;
   729                             default:
   730                                 UNDEF();
   731                                 break;
   732                         }
   733                         break;
   734                     case 0xB:
   735                         switch( (ir&0xFF0) >> 4 ) {
   736                             case 0x0:
   737                                 { /* RTS */
   738                                 if( sh4_x86.in_delay_slot ) {
   739                             	SLOTILLEGAL();
   740                                 } else {
   741                             	load_spreg( R_ECX, R_PR );
   742                             	store_spreg( R_ECX, R_NEW_PC );
   743                             	sh4_x86.in_delay_slot = DELAY_PC;
   744                             	sh4_x86.branch_taken = TRUE;
   745                             	if( UNTRANSLATABLE(pc+2) ) {
   746                             	    exit_block_emu(pc+2);
   747                             	    return 2;
   748                             	} else {
   749                             	    sh4_translate_instruction(pc+2);
   750                             	    exit_block_newpcset(pc+2);
   751                             	    return 4;
   752                             	}
   753                                 }
   754                                 }
   755                                 break;
   756                             case 0x1:
   757                                 { /* SLEEP */
   758                                 check_priv();
   759                                 call_func0( sh4_sleep );
   760                                 sh4_x86.tstate = TSTATE_NONE;
   761                                 sh4_x86.in_delay_slot = DELAY_NONE;
   762                                 return 2;
   763                                 }
   764                                 break;
   765                             case 0x2:
   766                                 { /* RTE */
   767                                 if( sh4_x86.in_delay_slot ) {
   768                             	SLOTILLEGAL();
   769                                 } else {
   770                             	check_priv();
   771                             	load_spreg( R_ECX, R_SPC );
   772                             	store_spreg( R_ECX, R_NEW_PC );
   773                             	load_spreg( R_EAX, R_SSR );
   774                             	call_func1( sh4_write_sr, R_EAX );
   775                             	sh4_x86.in_delay_slot = DELAY_PC;
   776                             	sh4_x86.priv_checked = FALSE;
   777                             	sh4_x86.fpuen_checked = FALSE;
   778                             	sh4_x86.tstate = TSTATE_NONE;
   779                             	sh4_x86.branch_taken = TRUE;
   780                             	if( UNTRANSLATABLE(pc+2) ) {
   781                             	    exit_block_emu(pc+2);
   782                             	    return 2;
   783                             	} else {
   784                             	    sh4_translate_instruction(pc+2);
   785                             	    exit_block_newpcset(pc+2);
   786                             	    return 4;
   787                             	}
   788                                 }
   789                                 }
   790                                 break;
   791                             default:
   792                                 UNDEF();
   793                                 break;
   794                         }
   795                         break;
   796                     case 0xC:
   797                         { /* MOV.B @(R0, Rm), Rn */
   798                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   799                         load_reg( R_EAX, 0 );
   800                         load_reg( R_ECX, Rm );
   801                         ADD_r32_r32( R_ECX, R_EAX );
   802                         MMU_TRANSLATE_READ( R_EAX )
   803                         MEM_READ_BYTE( R_EAX, R_EAX );
   804                         store_reg( R_EAX, Rn );
   805                         sh4_x86.tstate = TSTATE_NONE;
   806                         }
   807                         break;
   808                     case 0xD:
   809                         { /* MOV.W @(R0, Rm), Rn */
   810                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   811                         load_reg( R_EAX, 0 );
   812                         load_reg( R_ECX, Rm );
   813                         ADD_r32_r32( R_ECX, R_EAX );
   814                         check_ralign16( R_EAX );
   815                         MMU_TRANSLATE_READ( R_EAX );
   816                         MEM_READ_WORD( R_EAX, R_EAX );
   817                         store_reg( R_EAX, Rn );
   818                         sh4_x86.tstate = TSTATE_NONE;
   819                         }
   820                         break;
   821                     case 0xE:
   822                         { /* MOV.L @(R0, Rm), Rn */
   823                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   824                         load_reg( R_EAX, 0 );
   825                         load_reg( R_ECX, Rm );
   826                         ADD_r32_r32( R_ECX, R_EAX );
   827                         check_ralign32( R_EAX );
   828                         MMU_TRANSLATE_READ( R_EAX );
   829                         MEM_READ_LONG( R_EAX, R_EAX );
   830                         store_reg( R_EAX, Rn );
   831                         sh4_x86.tstate = TSTATE_NONE;
   832                         }
   833                         break;
   834                     case 0xF:
   835                         { /* MAC.L @Rm+, @Rn+ */
   836                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   837                         if( Rm == Rn ) {
   838                     	load_reg( R_EAX, Rm );
   839                     	check_ralign32( R_EAX );
   840                     	MMU_TRANSLATE_READ( R_EAX );
   841                     	PUSH_realigned_r32( R_EAX );
   842                     	load_reg( R_EAX, Rn );
   843                     	ADD_imm8s_r32( 4, R_EAX );
   844                     	MMU_TRANSLATE_READ_EXC( R_EAX, -5 );
   845                     	ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rn]) );
   846                     	// Note translate twice in case of page boundaries. Maybe worth
   847                     	// adding a page-boundary check to skip the second translation
   848                         } else {
   849                     	load_reg( R_EAX, Rm );
   850                     	check_ralign32( R_EAX );
   851                     	MMU_TRANSLATE_READ( R_EAX );
   852                     	load_reg( R_ECX, Rn );
   853                     	check_ralign32( R_ECX );
   854                     	PUSH_realigned_r32( R_EAX );
   855                     	MMU_TRANSLATE_READ_EXC( R_ECX, -5 );
   856                     	MOV_r32_r32( R_ECX, R_EAX );
   857                     	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
   858                     	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
   859                         }
   860                         MEM_READ_LONG( R_EAX, R_EAX );
   861                         POP_r32( R_ECX );
   862                         PUSH_r32( R_EAX );
   863                         MEM_READ_LONG( R_ECX, R_EAX );
   864                         POP_realigned_r32( R_ECX );
   866                         IMUL_r32( R_ECX );
   867                         ADD_r32_sh4r( R_EAX, R_MACL );
   868                         ADC_r32_sh4r( R_EDX, R_MACH );
   870                         load_spreg( R_ECX, R_S );
   871                         TEST_r32_r32(R_ECX, R_ECX);
   872                         JE_rel8( nosat );
   873                         call_func0( signsat48 );
   874                         JMP_TARGET( nosat );
   875                         sh4_x86.tstate = TSTATE_NONE;
   876                         }
   877                         break;
   878                     default:
   879                         UNDEF();
   880                         break;
   881                 }
   882                 break;
   883             case 0x1:
   884                 { /* MOV.L Rm, @(disp, Rn) */
   885                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
   886                 load_reg( R_EAX, Rn );
   887                 ADD_imm32_r32( disp, R_EAX );
   888                 check_walign32( R_EAX );
   889                 MMU_TRANSLATE_WRITE( R_EAX );
   890                 load_reg( R_EDX, Rm );
   891                 MEM_WRITE_LONG( R_EAX, R_EDX );
   892                 sh4_x86.tstate = TSTATE_NONE;
   893                 }
   894                 break;
   895             case 0x2:
   896                 switch( ir&0xF ) {
   897                     case 0x0:
   898                         { /* MOV.B Rm, @Rn */
   899                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   900                         load_reg( R_EAX, Rn );
   901                         MMU_TRANSLATE_WRITE( R_EAX );
   902                         load_reg( R_EDX, Rm );
   903                         MEM_WRITE_BYTE( R_EAX, R_EDX );
   904                         sh4_x86.tstate = TSTATE_NONE;
   905                         }
   906                         break;
   907                     case 0x1:
   908                         { /* MOV.W Rm, @Rn */
   909                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   910                         load_reg( R_EAX, Rn );
   911                         check_walign16( R_EAX );
   912                         MMU_TRANSLATE_WRITE( R_EAX )
   913                         load_reg( R_EDX, Rm );
   914                         MEM_WRITE_WORD( R_EAX, R_EDX );
   915                         sh4_x86.tstate = TSTATE_NONE;
   916                         }
   917                         break;
   918                     case 0x2:
   919                         { /* MOV.L Rm, @Rn */
   920                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   921                         load_reg( R_EAX, Rn );
   922                         check_walign32(R_EAX);
   923                         MMU_TRANSLATE_WRITE( R_EAX );
   924                         load_reg( R_EDX, Rm );
   925                         MEM_WRITE_LONG( R_EAX, R_EDX );
   926                         sh4_x86.tstate = TSTATE_NONE;
   927                         }
   928                         break;
   929                     case 0x4:
   930                         { /* MOV.B Rm, @-Rn */
   931                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   932                         load_reg( R_EAX, Rn );
   933                         ADD_imm8s_r32( -1, R_EAX );
   934                         MMU_TRANSLATE_WRITE( R_EAX );
   935                         load_reg( R_EDX, Rm );
   936                         ADD_imm8s_sh4r( -1, REG_OFFSET(r[Rn]) );
   937                         MEM_WRITE_BYTE( R_EAX, R_EDX );
   938                         sh4_x86.tstate = TSTATE_NONE;
   939                         }
   940                         break;
   941                     case 0x5:
   942                         { /* MOV.W Rm, @-Rn */
   943                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   944                         load_reg( R_EAX, Rn );
   945                         ADD_imm8s_r32( -2, R_EAX );
   946                         check_walign16( R_EAX );
   947                         MMU_TRANSLATE_WRITE( R_EAX );
   948                         load_reg( R_EDX, Rm );
   949                         ADD_imm8s_sh4r( -2, REG_OFFSET(r[Rn]) );
   950                         MEM_WRITE_WORD( R_EAX, R_EDX );
   951                         sh4_x86.tstate = TSTATE_NONE;
   952                         }
   953                         break;
   954                     case 0x6:
   955                         { /* MOV.L Rm, @-Rn */
   956                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   957                         load_reg( R_EAX, Rn );
   958                         ADD_imm8s_r32( -4, R_EAX );
   959                         check_walign32( R_EAX );
   960                         MMU_TRANSLATE_WRITE( R_EAX );
   961                         load_reg( R_EDX, Rm );
   962                         ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
   963                         MEM_WRITE_LONG( R_EAX, R_EDX );
   964                         sh4_x86.tstate = TSTATE_NONE;
   965                         }
   966                         break;
   967                     case 0x7:
   968                         { /* DIV0S Rm, Rn */
   969                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   970                         load_reg( R_EAX, Rm );
   971                         load_reg( R_ECX, Rn );
   972                         SHR_imm8_r32( 31, R_EAX );
   973                         SHR_imm8_r32( 31, R_ECX );
   974                         store_spreg( R_EAX, R_M );
   975                         store_spreg( R_ECX, R_Q );
   976                         CMP_r32_r32( R_EAX, R_ECX );
   977                         SETNE_t();
   978                         sh4_x86.tstate = TSTATE_NE;
   979                         }
   980                         break;
   981                     case 0x8:
   982                         { /* TST Rm, Rn */
   983                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   984                         load_reg( R_EAX, Rm );
   985                         load_reg( R_ECX, Rn );
   986                         TEST_r32_r32( R_EAX, R_ECX );
   987                         SETE_t();
   988                         sh4_x86.tstate = TSTATE_E;
   989                         }
   990                         break;
   991                     case 0x9:
   992                         { /* AND Rm, Rn */
   993                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   994                         load_reg( R_EAX, Rm );
   995                         load_reg( R_ECX, Rn );
   996                         AND_r32_r32( R_EAX, R_ECX );
   997                         store_reg( R_ECX, Rn );
   998                         sh4_x86.tstate = TSTATE_NONE;
   999                         }
  1000                         break;
  1001                     case 0xA:
  1002                         { /* XOR Rm, Rn */
  1003                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1004                         load_reg( R_EAX, Rm );
  1005                         load_reg( R_ECX, Rn );
  1006                         XOR_r32_r32( R_EAX, R_ECX );
  1007                         store_reg( R_ECX, Rn );
  1008                         sh4_x86.tstate = TSTATE_NONE;
  1010                         break;
  1011                     case 0xB:
  1012                         { /* OR Rm, Rn */
  1013                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1014                         load_reg( R_EAX, Rm );
  1015                         load_reg( R_ECX, Rn );
  1016                         OR_r32_r32( R_EAX, R_ECX );
  1017                         store_reg( R_ECX, Rn );
  1018                         sh4_x86.tstate = TSTATE_NONE;
  1020                         break;
  1021                     case 0xC:
  1022                         { /* CMP/STR Rm, Rn */
  1023                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1024                         load_reg( R_EAX, Rm );
  1025                         load_reg( R_ECX, Rn );
  1026                         XOR_r32_r32( R_ECX, R_EAX );
  1027                         TEST_r8_r8( R_AL, R_AL );
  1028                         JE_rel8(target1);
  1029                         TEST_r8_r8( R_AH, R_AH );
  1030                         JE_rel8(target2);
  1031                         SHR_imm8_r32( 16, R_EAX );
  1032                         TEST_r8_r8( R_AL, R_AL );
  1033                         JE_rel8(target3);
  1034                         TEST_r8_r8( R_AH, R_AH );
  1035                         JMP_TARGET(target1);
  1036                         JMP_TARGET(target2);
  1037                         JMP_TARGET(target3);
  1038                         SETE_t();
  1039                         sh4_x86.tstate = TSTATE_E;
  1041                         break;
  1042                     case 0xD:
  1043                         { /* XTRCT Rm, Rn */
  1044                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1045                         load_reg( R_EAX, Rm );
  1046                         load_reg( R_ECX, Rn );
  1047                         SHL_imm8_r32( 16, R_EAX );
  1048                         SHR_imm8_r32( 16, R_ECX );
  1049                         OR_r32_r32( R_EAX, R_ECX );
  1050                         store_reg( R_ECX, Rn );
  1051                         sh4_x86.tstate = TSTATE_NONE;
  1053                         break;
  1054                     case 0xE:
  1055                         { /* MULU.W Rm, Rn */
  1056                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1057                         load_reg16u( R_EAX, Rm );
  1058                         load_reg16u( R_ECX, Rn );
  1059                         MUL_r32( R_ECX );
  1060                         store_spreg( R_EAX, R_MACL );
  1061                         sh4_x86.tstate = TSTATE_NONE;
  1063                         break;
  1064                     case 0xF:
  1065                         { /* MULS.W Rm, Rn */
  1066                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1067                         load_reg16s( R_EAX, Rm );
  1068                         load_reg16s( R_ECX, Rn );
  1069                         MUL_r32( R_ECX );
  1070                         store_spreg( R_EAX, R_MACL );
  1071                         sh4_x86.tstate = TSTATE_NONE;
  1073                         break;
  1074                     default:
  1075                         UNDEF();
  1076                         break;
  1078                 break;
  1079             case 0x3:
  1080                 switch( ir&0xF ) {
  1081                     case 0x0:
  1082                         { /* CMP/EQ Rm, Rn */
  1083                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1084                         load_reg( R_EAX, Rm );
  1085                         load_reg( R_ECX, Rn );
  1086                         CMP_r32_r32( R_EAX, R_ECX );
  1087                         SETE_t();
  1088                         sh4_x86.tstate = TSTATE_E;
  1090                         break;
  1091                     case 0x2:
  1092                         { /* CMP/HS Rm, Rn */
  1093                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1094                         load_reg( R_EAX, Rm );
  1095                         load_reg( R_ECX, Rn );
  1096                         CMP_r32_r32( R_EAX, R_ECX );
  1097                         SETAE_t();
  1098                         sh4_x86.tstate = TSTATE_AE;
  1100                         break;
  1101                     case 0x3:
  1102                         { /* CMP/GE Rm, Rn */
  1103                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1104                         load_reg( R_EAX, Rm );
  1105                         load_reg( R_ECX, Rn );
  1106                         CMP_r32_r32( R_EAX, R_ECX );
  1107                         SETGE_t();
  1108                         sh4_x86.tstate = TSTATE_GE;
  1110                         break;
  1111                     case 0x4:
  1112                         { /* DIV1 Rm, Rn */
  1113                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1114                         load_spreg( R_ECX, R_M );
  1115                         load_reg( R_EAX, Rn );
  1116                         if( sh4_x86.tstate != TSTATE_C ) {
  1117                     	LDC_t();
  1119                         RCL1_r32( R_EAX );
  1120                         SETC_r8( R_DL ); // Q'
  1121                         CMP_sh4r_r32( R_Q, R_ECX );
  1122                         JE_rel8(mqequal);
  1123                         ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
  1124                         JMP_rel8(end);
  1125                         JMP_TARGET(mqequal);
  1126                         SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
  1127                         JMP_TARGET(end);
  1128                         store_reg( R_EAX, Rn ); // Done with Rn now
  1129                         SETC_r8(R_AL); // tmp1
  1130                         XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
  1131                         XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
  1132                         store_spreg( R_ECX, R_Q );
  1133                         XOR_imm8s_r32( 1, R_AL );   // T = !Q'
  1134                         MOVZX_r8_r32( R_AL, R_EAX );
  1135                         store_spreg( R_EAX, R_T );
  1136                         sh4_x86.tstate = TSTATE_NONE;
  1138                         break;
  1139                     case 0x5:
  1140                         { /* DMULU.L Rm, Rn */
  1141                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1142                         load_reg( R_EAX, Rm );
  1143                         load_reg( R_ECX, Rn );
  1144                         MUL_r32(R_ECX);
  1145                         store_spreg( R_EDX, R_MACH );
  1146                         store_spreg( R_EAX, R_MACL );    
  1147                         sh4_x86.tstate = TSTATE_NONE;
  1149                         break;
  1150                     case 0x6:
  1151                         { /* CMP/HI Rm, Rn */
  1152                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1153                         load_reg( R_EAX, Rm );
  1154                         load_reg( R_ECX, Rn );
  1155                         CMP_r32_r32( R_EAX, R_ECX );
  1156                         SETA_t();
  1157                         sh4_x86.tstate = TSTATE_A;
  1159                         break;
  1160                     case 0x7:
  1161                         { /* CMP/GT Rm, Rn */
  1162                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1163                         load_reg( R_EAX, Rm );
  1164                         load_reg( R_ECX, Rn );
  1165                         CMP_r32_r32( R_EAX, R_ECX );
  1166                         SETG_t();
  1167                         sh4_x86.tstate = TSTATE_G;
  1169                         break;
  1170                     case 0x8:
  1171                         { /* SUB Rm, Rn */
  1172                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1173                         load_reg( R_EAX, Rm );
  1174                         load_reg( R_ECX, Rn );
  1175                         SUB_r32_r32( R_EAX, R_ECX );
  1176                         store_reg( R_ECX, Rn );
  1177                         sh4_x86.tstate = TSTATE_NONE;
  1179                         break;
  1180                     case 0xA:
  1181                         { /* SUBC Rm, Rn */
  1182                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1183                         load_reg( R_EAX, Rm );
  1184                         load_reg( R_ECX, Rn );
  1185                         if( sh4_x86.tstate != TSTATE_C ) {
  1186                     	LDC_t();
  1188                         SBB_r32_r32( R_EAX, R_ECX );
  1189                         store_reg( R_ECX, Rn );
  1190                         SETC_t();
  1191                         sh4_x86.tstate = TSTATE_C;
  1193                         break;
  1194                     case 0xB:
  1195                         { /* SUBV Rm, Rn */
  1196                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1197                         load_reg( R_EAX, Rm );
  1198                         load_reg( R_ECX, Rn );
  1199                         SUB_r32_r32( R_EAX, R_ECX );
  1200                         store_reg( R_ECX, Rn );
  1201                         SETO_t();
  1202                         sh4_x86.tstate = TSTATE_O;
  1204                         break;
  1205                     case 0xC:
  1206                         { /* ADD Rm, Rn */
  1207                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1208                         load_reg( R_EAX, Rm );
  1209                         load_reg( R_ECX, Rn );
  1210                         ADD_r32_r32( R_EAX, R_ECX );
  1211                         store_reg( R_ECX, Rn );
  1212                         sh4_x86.tstate = TSTATE_NONE;
  1214                         break;
  1215                     case 0xD:
  1216                         { /* DMULS.L Rm, Rn */
  1217                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1218                         load_reg( R_EAX, Rm );
  1219                         load_reg( R_ECX, Rn );
  1220                         IMUL_r32(R_ECX);
  1221                         store_spreg( R_EDX, R_MACH );
  1222                         store_spreg( R_EAX, R_MACL );
  1223                         sh4_x86.tstate = TSTATE_NONE;
  1225                         break;
  1226                     case 0xE:
  1227                         { /* ADDC Rm, Rn */
  1228                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1229                         if( sh4_x86.tstate != TSTATE_C ) {
  1230                     	LDC_t();
  1232                         load_reg( R_EAX, Rm );
  1233                         load_reg( R_ECX, Rn );
  1234                         ADC_r32_r32( R_EAX, R_ECX );
  1235                         store_reg( R_ECX, Rn );
  1236                         SETC_t();
  1237                         sh4_x86.tstate = TSTATE_C;
  1239                         break;
  1240                     case 0xF:
  1241                         { /* ADDV Rm, Rn */
  1242                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1243                         load_reg( R_EAX, Rm );
  1244                         load_reg( R_ECX, Rn );
  1245                         ADD_r32_r32( R_EAX, R_ECX );
  1246                         store_reg( R_ECX, Rn );
  1247                         SETO_t();
  1248                         sh4_x86.tstate = TSTATE_O;
  1250                         break;
  1251                     default:
  1252                         UNDEF();
  1253                         break;
  1255                 break;
  1256             case 0x4:
  1257                 switch( ir&0xF ) {
  1258                     case 0x0:
  1259                         switch( (ir&0xF0) >> 4 ) {
  1260                             case 0x0:
  1261                                 { /* SHLL Rn */
  1262                                 uint32_t Rn = ((ir>>8)&0xF); 
  1263                                 load_reg( R_EAX, Rn );
  1264                                 SHL1_r32( R_EAX );
  1265                                 SETC_t();
  1266                                 store_reg( R_EAX, Rn );
  1267                                 sh4_x86.tstate = TSTATE_C;
  1269                                 break;
  1270                             case 0x1:
  1271                                 { /* DT Rn */
  1272                                 uint32_t Rn = ((ir>>8)&0xF); 
  1273                                 load_reg( R_EAX, Rn );
  1274                                 ADD_imm8s_r32( -1, R_EAX );
  1275                                 store_reg( R_EAX, Rn );
  1276                                 SETE_t();
  1277                                 sh4_x86.tstate = TSTATE_E;
  1279                                 break;
  1280                             case 0x2:
  1281                                 { /* SHAL Rn */
  1282                                 uint32_t Rn = ((ir>>8)&0xF); 
  1283                                 load_reg( R_EAX, Rn );
  1284                                 SHL1_r32( R_EAX );
  1285                                 SETC_t();
  1286                                 store_reg( R_EAX, Rn );
  1287                                 sh4_x86.tstate = TSTATE_C;
  1289                                 break;
  1290                             default:
  1291                                 UNDEF();
  1292                                 break;
  1294                         break;
  1295                     case 0x1:
  1296                         switch( (ir&0xF0) >> 4 ) {
  1297                             case 0x0:
  1298                                 { /* SHLR Rn */
  1299                                 uint32_t Rn = ((ir>>8)&0xF); 
  1300                                 load_reg( R_EAX, Rn );
  1301                                 SHR1_r32( R_EAX );
  1302                                 SETC_t();
  1303                                 store_reg( R_EAX, Rn );
  1304                                 sh4_x86.tstate = TSTATE_C;
  1306                                 break;
  1307                             case 0x1:
  1308                                 { /* CMP/PZ Rn */
  1309                                 uint32_t Rn = ((ir>>8)&0xF); 
  1310                                 load_reg( R_EAX, Rn );
  1311                                 CMP_imm8s_r32( 0, R_EAX );
  1312                                 SETGE_t();
  1313                                 sh4_x86.tstate = TSTATE_GE;
  1315                                 break;
  1316                             case 0x2:
  1317                                 { /* SHAR Rn */
  1318                                 uint32_t Rn = ((ir>>8)&0xF); 
  1319                                 load_reg( R_EAX, Rn );
  1320                                 SAR1_r32( R_EAX );
  1321                                 SETC_t();
  1322                                 store_reg( R_EAX, Rn );
  1323                                 sh4_x86.tstate = TSTATE_C;
  1325                                 break;
  1326                             default:
  1327                                 UNDEF();
  1328                                 break;
  1330                         break;
  1331                     case 0x2:
  1332                         switch( (ir&0xF0) >> 4 ) {
  1333                             case 0x0:
  1334                                 { /* STS.L MACH, @-Rn */
  1335                                 uint32_t Rn = ((ir>>8)&0xF); 
  1336                                 load_reg( R_EAX, Rn );
  1337                                 check_walign32( R_EAX );
  1338                                 ADD_imm8s_r32( -4, R_EAX );
  1339                                 MMU_TRANSLATE_WRITE( R_EAX );
  1340                                 load_spreg( R_EDX, R_MACH );
  1341                                 ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
  1342                                 MEM_WRITE_LONG( R_EAX, R_EDX );
  1343                                 sh4_x86.tstate = TSTATE_NONE;
  1345                                 break;
  1346                             case 0x1:
  1347                                 { /* STS.L MACL, @-Rn */
  1348                                 uint32_t Rn = ((ir>>8)&0xF); 
  1349                                 load_reg( R_EAX, Rn );
  1350                                 check_walign32( R_EAX );
  1351                                 ADD_imm8s_r32( -4, R_EAX );
  1352                                 MMU_TRANSLATE_WRITE( R_EAX );
  1353                                 load_spreg( R_EDX, R_MACL );
  1354                                 ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
  1355                                 MEM_WRITE_LONG( R_EAX, R_EDX );
  1356                                 sh4_x86.tstate = TSTATE_NONE;
  1358                                 break;
  1359                             case 0x2:
  1360                                 { /* STS.L PR, @-Rn */
  1361                                 uint32_t Rn = ((ir>>8)&0xF); 
  1362                                 load_reg( R_EAX, Rn );
  1363                                 check_walign32( R_EAX );
  1364                                 ADD_imm8s_r32( -4, R_EAX );
  1365                                 MMU_TRANSLATE_WRITE( R_EAX );
  1366                                 load_spreg( R_EDX, R_PR );
  1367                                 ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
  1368                                 MEM_WRITE_LONG( R_EAX, R_EDX );
  1369                                 sh4_x86.tstate = TSTATE_NONE;
  1371                                 break;
  1372                             case 0x3:
  1373                                 { /* STC.L SGR, @-Rn */
  1374                                 uint32_t Rn = ((ir>>8)&0xF); 
  1375                                 check_priv();
  1376                                 load_reg( R_EAX, Rn );
  1377                                 check_walign32( R_EAX );
  1378                                 ADD_imm8s_r32( -4, R_EAX );
  1379                                 MMU_TRANSLATE_WRITE( R_EAX );
  1380                                 load_spreg( R_EDX, R_SGR );
  1381                                 ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
  1382                                 MEM_WRITE_LONG( R_EAX, R_EDX );
  1383                                 sh4_x86.tstate = TSTATE_NONE;
  1385                                 break;
  1386                             case 0x5:
  1387                                 { /* STS.L FPUL, @-Rn */
  1388                                 uint32_t Rn = ((ir>>8)&0xF); 
  1389                                 check_fpuen();
  1390                                 load_reg( R_EAX, Rn );
  1391                                 check_walign32( R_EAX );
  1392                                 ADD_imm8s_r32( -4, R_EAX );
  1393                                 MMU_TRANSLATE_WRITE( R_EAX );
  1394                                 load_spreg( R_EDX, R_FPUL );
  1395                                 ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
  1396                                 MEM_WRITE_LONG( R_EAX, R_EDX );
  1397                                 sh4_x86.tstate = TSTATE_NONE;
  1399                                 break;
  1400                             case 0x6:
  1401                                 { /* STS.L FPSCR, @-Rn */
  1402                                 uint32_t Rn = ((ir>>8)&0xF); 
  1403                                 check_fpuen();
  1404                                 load_reg( R_EAX, Rn );
  1405                                 check_walign32( R_EAX );
  1406                                 ADD_imm8s_r32( -4, R_EAX );
  1407                                 MMU_TRANSLATE_WRITE( R_EAX );
  1408                                 load_spreg( R_EDX, R_FPSCR );
  1409                                 ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
  1410                                 MEM_WRITE_LONG( R_EAX, R_EDX );
  1411                                 sh4_x86.tstate = TSTATE_NONE;
  1413                                 break;
  1414                             case 0xF:
  1415                                 { /* STC.L DBR, @-Rn */
  1416                                 uint32_t Rn = ((ir>>8)&0xF); 
  1417                                 check_priv();
  1418                                 load_reg( R_EAX, Rn );
  1419                                 check_walign32( R_EAX );
  1420                                 ADD_imm8s_r32( -4, R_EAX );
  1421                                 MMU_TRANSLATE_WRITE( R_EAX );
  1422                                 load_spreg( R_EDX, R_DBR );
  1423                                 ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
  1424                                 MEM_WRITE_LONG( R_EAX, R_EDX );
  1425                                 sh4_x86.tstate = TSTATE_NONE;
  1427                                 break;
  1428                             default:
  1429                                 UNDEF();
  1430                                 break;
  1432                         break;
  1433                     case 0x3:
  1434                         switch( (ir&0x80) >> 7 ) {
  1435                             case 0x0:
  1436                                 switch( (ir&0x70) >> 4 ) {
  1437                                     case 0x0:
  1438                                         { /* STC.L SR, @-Rn */
  1439                                         uint32_t Rn = ((ir>>8)&0xF); 
  1440                                         check_priv();
  1441                                         load_reg( R_EAX, Rn );
  1442                                         check_walign32( R_EAX );
  1443                                         ADD_imm8s_r32( -4, R_EAX );
  1444                                         MMU_TRANSLATE_WRITE( R_EAX );
  1445                                         PUSH_realigned_r32( R_EAX );
  1446                                         call_func0( sh4_read_sr );
  1447                                         POP_realigned_r32( R_ECX );
  1448                                         ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
  1449                                         MEM_WRITE_LONG( R_ECX, R_EAX );
  1450                                         sh4_x86.tstate = TSTATE_NONE;
  1452                                         break;
  1453                                     case 0x1:
  1454                                         { /* STC.L GBR, @-Rn */
  1455                                         uint32_t Rn = ((ir>>8)&0xF); 
  1456                                         load_reg( R_EAX, Rn );
  1457                                         check_walign32( R_EAX );
  1458                                         ADD_imm8s_r32( -4, R_EAX );
  1459                                         MMU_TRANSLATE_WRITE( R_EAX );
  1460                                         load_spreg( R_EDX, R_GBR );
  1461                                         ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
  1462                                         MEM_WRITE_LONG( R_EAX, R_EDX );
  1463                                         sh4_x86.tstate = TSTATE_NONE;
  1465                                         break;
  1466                                     case 0x2:
  1467                                         { /* STC.L VBR, @-Rn */
  1468                                         uint32_t Rn = ((ir>>8)&0xF); 
  1469                                         check_priv();
  1470                                         load_reg( R_EAX, Rn );
  1471                                         check_walign32( R_EAX );
  1472                                         ADD_imm8s_r32( -4, R_EAX );
  1473                                         MMU_TRANSLATE_WRITE( R_EAX );
  1474                                         load_spreg( R_EDX, R_VBR );
  1475                                         ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
  1476                                         MEM_WRITE_LONG( R_EAX, R_EDX );
  1477                                         sh4_x86.tstate = TSTATE_NONE;
  1479                                         break;
  1480                                     case 0x3:
  1481                                         { /* STC.L SSR, @-Rn */
  1482                                         uint32_t Rn = ((ir>>8)&0xF); 
  1483                                         check_priv();
  1484                                         load_reg( R_EAX, Rn );
  1485                                         check_walign32( R_EAX );
  1486                                         ADD_imm8s_r32( -4, R_EAX );
  1487                                         MMU_TRANSLATE_WRITE( R_EAX );
  1488                                         load_spreg( R_EDX, R_SSR );
  1489                                         ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
  1490                                         MEM_WRITE_LONG( R_EAX, R_EDX );
  1491                                         sh4_x86.tstate = TSTATE_NONE;
  1493                                         break;
  1494                                     case 0x4:
  1495                                         { /* STC.L SPC, @-Rn */
  1496                                         uint32_t Rn = ((ir>>8)&0xF); 
  1497                                         check_priv();
  1498                                         load_reg( R_EAX, Rn );
  1499                                         check_walign32( R_EAX );
  1500                                         ADD_imm8s_r32( -4, R_EAX );
  1501                                         MMU_TRANSLATE_WRITE( R_EAX );
  1502                                         load_spreg( R_EDX, R_SPC );
  1503                                         ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
  1504                                         MEM_WRITE_LONG( R_EAX, R_EDX );
  1505                                         sh4_x86.tstate = TSTATE_NONE;
  1507                                         break;
  1508                                     default:
  1509                                         UNDEF();
  1510                                         break;
  1512                                 break;
  1513                             case 0x1:
  1514                                 { /* STC.L Rm_BANK, @-Rn */
  1515                                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
  1516                                 check_priv();
  1517                                 load_reg( R_EAX, Rn );
  1518                                 check_walign32( R_EAX );
  1519                                 ADD_imm8s_r32( -4, R_EAX );
  1520                                 MMU_TRANSLATE_WRITE( R_EAX );
  1521                                 load_spreg( R_EDX, REG_OFFSET(r_bank[Rm_BANK]) );
  1522                                 ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
  1523                                 MEM_WRITE_LONG( R_EAX, R_EDX );
  1524                                 sh4_x86.tstate = TSTATE_NONE;
  1526                                 break;
  1528                         break;
  1529                     case 0x4:
  1530                         switch( (ir&0xF0) >> 4 ) {
  1531                             case 0x0:
  1532                                 { /* ROTL Rn */
  1533                                 uint32_t Rn = ((ir>>8)&0xF); 
  1534                                 load_reg( R_EAX, Rn );
  1535                                 ROL1_r32( R_EAX );
  1536                                 store_reg( R_EAX, Rn );
  1537                                 SETC_t();
  1538                                 sh4_x86.tstate = TSTATE_C;
  1540                                 break;
  1541                             case 0x2:
  1542                                 { /* ROTCL Rn */
  1543                                 uint32_t Rn = ((ir>>8)&0xF); 
  1544                                 load_reg( R_EAX, Rn );
  1545                                 if( sh4_x86.tstate != TSTATE_C ) {
  1546                             	LDC_t();
  1548                                 RCL1_r32( R_EAX );
  1549                                 store_reg( R_EAX, Rn );
  1550                                 SETC_t();
  1551                                 sh4_x86.tstate = TSTATE_C;
  1553                                 break;
  1554                             default:
  1555                                 UNDEF();
  1556                                 break;
  1558                         break;
  1559                     case 0x5:
  1560                         switch( (ir&0xF0) >> 4 ) {
  1561                             case 0x0:
  1562                                 { /* ROTR Rn */
  1563                                 uint32_t Rn = ((ir>>8)&0xF); 
  1564                                 load_reg( R_EAX, Rn );
  1565                                 ROR1_r32( R_EAX );
  1566                                 store_reg( R_EAX, Rn );
  1567                                 SETC_t();
  1568                                 sh4_x86.tstate = TSTATE_C;
  1570                                 break;
  1571                             case 0x1:
  1572                                 { /* CMP/PL Rn */
  1573                                 uint32_t Rn = ((ir>>8)&0xF); 
  1574                                 load_reg( R_EAX, Rn );
  1575                                 CMP_imm8s_r32( 0, R_EAX );
  1576                                 SETG_t();
  1577                                 sh4_x86.tstate = TSTATE_G;
  1579                                 break;
  1580                             case 0x2:
  1581                                 { /* ROTCR Rn */
  1582                                 uint32_t Rn = ((ir>>8)&0xF); 
  1583                                 load_reg( R_EAX, Rn );
  1584                                 if( sh4_x86.tstate != TSTATE_C ) {
  1585                             	LDC_t();
  1587                                 RCR1_r32( R_EAX );
  1588                                 store_reg( R_EAX, Rn );
  1589                                 SETC_t();
  1590                                 sh4_x86.tstate = TSTATE_C;
  1592                                 break;
  1593                             default:
  1594                                 UNDEF();
  1595                                 break;
  1597                         break;
  1598                     case 0x6:
  1599                         switch( (ir&0xF0) >> 4 ) {
  1600                             case 0x0:
  1601                                 { /* LDS.L @Rm+, MACH */
  1602                                 uint32_t Rm = ((ir>>8)&0xF); 
  1603                                 load_reg( R_EAX, Rm );
  1604                                 check_ralign32( R_EAX );
  1605                                 MMU_TRANSLATE_READ( R_EAX );
  1606                                 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
  1607                                 MEM_READ_LONG( R_EAX, R_EAX );
  1608                                 store_spreg( R_EAX, R_MACH );
  1609                                 sh4_x86.tstate = TSTATE_NONE;
  1611                                 break;
  1612                             case 0x1:
  1613                                 { /* LDS.L @Rm+, MACL */
  1614                                 uint32_t Rm = ((ir>>8)&0xF); 
  1615                                 load_reg( R_EAX, Rm );
  1616                                 check_ralign32( R_EAX );
  1617                                 MMU_TRANSLATE_READ( R_EAX );
  1618                                 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
  1619                                 MEM_READ_LONG( R_EAX, R_EAX );
  1620                                 store_spreg( R_EAX, R_MACL );
  1621                                 sh4_x86.tstate = TSTATE_NONE;
  1623                                 break;
  1624                             case 0x2:
  1625                                 { /* LDS.L @Rm+, PR */
  1626                                 uint32_t Rm = ((ir>>8)&0xF); 
  1627                                 load_reg( R_EAX, Rm );
  1628                                 check_ralign32( R_EAX );
  1629                                 MMU_TRANSLATE_READ( R_EAX );
  1630                                 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
  1631                                 MEM_READ_LONG( R_EAX, R_EAX );
  1632                                 store_spreg( R_EAX, R_PR );
  1633                                 sh4_x86.tstate = TSTATE_NONE;
  1635                                 break;
  1636                             case 0x3:
  1637                                 { /* LDC.L @Rm+, SGR */
  1638                                 uint32_t Rm = ((ir>>8)&0xF); 
  1639                                 check_priv();
  1640                                 load_reg( R_EAX, Rm );
  1641                                 check_ralign32( R_EAX );
  1642                                 MMU_TRANSLATE_READ( R_EAX );
  1643                                 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
  1644                                 MEM_READ_LONG( R_EAX, R_EAX );
  1645                                 store_spreg( R_EAX, R_SGR );
  1646                                 sh4_x86.tstate = TSTATE_NONE;
  1648                                 break;
  1649                             case 0x5:
  1650                                 { /* LDS.L @Rm+, FPUL */
  1651                                 uint32_t Rm = ((ir>>8)&0xF); 
  1652                                 check_fpuen();
  1653                                 load_reg( R_EAX, Rm );
  1654                                 check_ralign32( R_EAX );
  1655                                 MMU_TRANSLATE_READ( R_EAX );
  1656                                 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
  1657                                 MEM_READ_LONG( R_EAX, R_EAX );
  1658                                 store_spreg( R_EAX, R_FPUL );
  1659                                 sh4_x86.tstate = TSTATE_NONE;
  1661                                 break;
  1662                             case 0x6:
  1663                                 { /* LDS.L @Rm+, FPSCR */
  1664                                 uint32_t Rm = ((ir>>8)&0xF); 
  1665                                 check_fpuen();
  1666                                 load_reg( R_EAX, Rm );
  1667                                 check_ralign32( R_EAX );
  1668                                 MMU_TRANSLATE_READ( R_EAX );
  1669                                 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
  1670                                 MEM_READ_LONG( R_EAX, R_EAX );
  1671                                 call_func1( sh4_write_fpscr, R_EAX );
  1672                                 sh4_x86.tstate = TSTATE_NONE;
  1674                                 break;
  1675                             case 0xF:
  1676                                 { /* LDC.L @Rm+, DBR */
  1677                                 uint32_t Rm = ((ir>>8)&0xF); 
  1678                                 check_priv();
  1679                                 load_reg( R_EAX, Rm );
  1680                                 check_ralign32( R_EAX );
  1681                                 MMU_TRANSLATE_READ( R_EAX );
  1682                                 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
  1683                                 MEM_READ_LONG( R_EAX, R_EAX );
  1684                                 store_spreg( R_EAX, R_DBR );
  1685                                 sh4_x86.tstate = TSTATE_NONE;
  1687                                 break;
  1688                             default:
  1689                                 UNDEF();
  1690                                 break;
  1692                         break;
  1693                     case 0x7:
  1694                         switch( (ir&0x80) >> 7 ) {
  1695                             case 0x0:
  1696                                 switch( (ir&0x70) >> 4 ) {
  1697                                     case 0x0:
  1698                                         { /* LDC.L @Rm+, SR */
  1699                                         uint32_t Rm = ((ir>>8)&0xF); 
  1700                                         if( sh4_x86.in_delay_slot ) {
  1701                                     	SLOTILLEGAL();
  1702                                         } else {
  1703                                     	check_priv();
  1704                                     	load_reg( R_EAX, Rm );
  1705                                     	check_ralign32( R_EAX );
  1706                                     	MMU_TRANSLATE_READ( R_EAX );
  1707                                     	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
  1708                                     	MEM_READ_LONG( R_EAX, R_EAX );
  1709                                     	call_func1( sh4_write_sr, R_EAX );
  1710                                     	sh4_x86.priv_checked = FALSE;
  1711                                     	sh4_x86.fpuen_checked = FALSE;
  1712                                     	sh4_x86.tstate = TSTATE_NONE;
  1715                                         break;
  1716                                     case 0x1:
  1717                                         { /* LDC.L @Rm+, GBR */
  1718                                         uint32_t Rm = ((ir>>8)&0xF); 
  1719                                         load_reg( R_EAX, Rm );
  1720                                         check_ralign32( R_EAX );
  1721                                         MMU_TRANSLATE_READ( R_EAX );
  1722                                         ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
  1723                                         MEM_READ_LONG( R_EAX, R_EAX );
  1724                                         store_spreg( R_EAX, R_GBR );
  1725                                         sh4_x86.tstate = TSTATE_NONE;
  1727                                         break;
  1728                                     case 0x2:
  1729                                         { /* LDC.L @Rm+, VBR */
  1730                                         uint32_t Rm = ((ir>>8)&0xF); 
  1731                                         check_priv();
  1732                                         load_reg( R_EAX, Rm );
  1733                                         check_ralign32( R_EAX );
  1734                                         MMU_TRANSLATE_READ( R_EAX );
  1735                                         ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
  1736                                         MEM_READ_LONG( R_EAX, R_EAX );
  1737                                         store_spreg( R_EAX, R_VBR );
  1738                                         sh4_x86.tstate = TSTATE_NONE;
  1740                                         break;
  1741                                     case 0x3:
  1742                                         { /* LDC.L @Rm+, SSR */
  1743                                         uint32_t Rm = ((ir>>8)&0xF); 
  1744                                         check_priv();
  1745                                         load_reg( R_EAX, Rm );
  1746                                         check_ralign32( R_EAX );
  1747                                         MMU_TRANSLATE_READ( R_EAX );
  1748                                         ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
  1749                                         MEM_READ_LONG( R_EAX, R_EAX );
  1750                                         store_spreg( R_EAX, R_SSR );
  1751                                         sh4_x86.tstate = TSTATE_NONE;
  1753                                         break;
  1754                                     case 0x4:
  1755                                         { /* LDC.L @Rm+, SPC */
  1756                                         uint32_t Rm = ((ir>>8)&0xF); 
  1757                                         check_priv();
  1758                                         load_reg( R_EAX, Rm );
  1759                                         check_ralign32( R_EAX );
  1760                                         MMU_TRANSLATE_READ( R_EAX );
  1761                                         ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
  1762                                         MEM_READ_LONG( R_EAX, R_EAX );
  1763                                         store_spreg( R_EAX, R_SPC );
  1764                                         sh4_x86.tstate = TSTATE_NONE;
  1766                                         break;
  1767                                     default:
  1768                                         UNDEF();
  1769                                         break;
  1771                                 break;
  1772                             case 0x1:
  1773                                 { /* LDC.L @Rm+, Rn_BANK */
  1774                                 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
  1775                                 check_priv();
  1776                                 load_reg( R_EAX, Rm );
  1777                                 check_ralign32( R_EAX );
  1778                                 MMU_TRANSLATE_READ( R_EAX );
  1779                                 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
  1780                                 MEM_READ_LONG( R_EAX, R_EAX );
  1781                                 store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
  1782                                 sh4_x86.tstate = TSTATE_NONE;
  1784                                 break;
  1786                         break;
  1787                     case 0x8:
  1788                         switch( (ir&0xF0) >> 4 ) {
  1789                             case 0x0:
  1790                                 { /* SHLL2 Rn */
  1791                                 uint32_t Rn = ((ir>>8)&0xF); 
  1792                                 load_reg( R_EAX, Rn );
  1793                                 SHL_imm8_r32( 2, R_EAX );
  1794                                 store_reg( R_EAX, Rn );
  1795                                 sh4_x86.tstate = TSTATE_NONE;
  1797                                 break;
  1798                             case 0x1:
  1799                                 { /* SHLL8 Rn */
  1800                                 uint32_t Rn = ((ir>>8)&0xF); 
  1801                                 load_reg( R_EAX, Rn );
  1802                                 SHL_imm8_r32( 8, R_EAX );
  1803                                 store_reg( R_EAX, Rn );
  1804                                 sh4_x86.tstate = TSTATE_NONE;
  1806                                 break;
  1807                             case 0x2:
  1808                                 { /* SHLL16 Rn */
  1809                                 uint32_t Rn = ((ir>>8)&0xF); 
  1810                                 load_reg( R_EAX, Rn );
  1811                                 SHL_imm8_r32( 16, R_EAX );
  1812                                 store_reg( R_EAX, Rn );
  1813                                 sh4_x86.tstate = TSTATE_NONE;
  1815                                 break;
  1816                             default:
  1817                                 UNDEF();
  1818                                 break;
  1820                         break;
  1821                     case 0x9:
  1822                         switch( (ir&0xF0) >> 4 ) {
  1823                             case 0x0:
  1824                                 { /* SHLR2 Rn */
  1825                                 uint32_t Rn = ((ir>>8)&0xF); 
  1826                                 load_reg( R_EAX, Rn );
  1827                                 SHR_imm8_r32( 2, R_EAX );
  1828                                 store_reg( R_EAX, Rn );
  1829                                 sh4_x86.tstate = TSTATE_NONE;
  1831                                 break;
  1832                             case 0x1:
  1833                                 { /* SHLR8 Rn */
  1834                                 uint32_t Rn = ((ir>>8)&0xF); 
  1835                                 load_reg( R_EAX, Rn );
  1836                                 SHR_imm8_r32( 8, R_EAX );
  1837                                 store_reg( R_EAX, Rn );
  1838                                 sh4_x86.tstate = TSTATE_NONE;
  1840                                 break;
  1841                             case 0x2:
  1842                                 { /* SHLR16 Rn */
  1843                                 uint32_t Rn = ((ir>>8)&0xF); 
  1844                                 load_reg( R_EAX, Rn );
  1845                                 SHR_imm8_r32( 16, R_EAX );
  1846                                 store_reg( R_EAX, Rn );
  1847                                 sh4_x86.tstate = TSTATE_NONE;
  1849                                 break;
  1850                             default:
  1851                                 UNDEF();
  1852                                 break;
  1854                         break;
  1855                     case 0xA:
  1856                         switch( (ir&0xF0) >> 4 ) {
  1857                             case 0x0:
  1858                                 { /* LDS Rm, MACH */
  1859                                 uint32_t Rm = ((ir>>8)&0xF); 
  1860                                 load_reg( R_EAX, Rm );
  1861                                 store_spreg( R_EAX, R_MACH );
  1863                                 break;
  1864                             case 0x1:
  1865                                 { /* LDS Rm, MACL */
  1866                                 uint32_t Rm = ((ir>>8)&0xF); 
  1867                                 load_reg( R_EAX, Rm );
  1868                                 store_spreg( R_EAX, R_MACL );
  1870                                 break;
  1871                             case 0x2:
  1872                                 { /* LDS Rm, PR */
  1873                                 uint32_t Rm = ((ir>>8)&0xF); 
  1874                                 load_reg( R_EAX, Rm );
  1875                                 store_spreg( R_EAX, R_PR );
  1877                                 break;
  1878                             case 0x3:
  1879                                 { /* LDC Rm, SGR */
  1880                                 uint32_t Rm = ((ir>>8)&0xF); 
  1881                                 check_priv();
  1882                                 load_reg( R_EAX, Rm );
  1883                                 store_spreg( R_EAX, R_SGR );
  1884                                 sh4_x86.tstate = TSTATE_NONE;
  1886                                 break;
  1887                             case 0x5:
  1888                                 { /* LDS Rm, FPUL */
  1889                                 uint32_t Rm = ((ir>>8)&0xF); 
  1890                                 check_fpuen();
  1891                                 load_reg( R_EAX, Rm );
  1892                                 store_spreg( R_EAX, R_FPUL );
  1894                                 break;
  1895                             case 0x6:
  1896                                 { /* LDS Rm, FPSCR */
  1897                                 uint32_t Rm = ((ir>>8)&0xF); 
  1898                                 check_fpuen();
  1899                                 load_reg( R_EAX, Rm );
  1900                                 call_func1( sh4_write_fpscr, R_EAX );
  1901                                 sh4_x86.tstate = TSTATE_NONE;
  1903                                 break;
  1904                             case 0xF:
  1905                                 { /* LDC Rm, DBR */
  1906                                 uint32_t Rm = ((ir>>8)&0xF); 
  1907                                 check_priv();
  1908                                 load_reg( R_EAX, Rm );
  1909                                 store_spreg( R_EAX, R_DBR );
  1910                                 sh4_x86.tstate = TSTATE_NONE;
  1912                                 break;
  1913                             default:
  1914                                 UNDEF();
  1915                                 break;
  1917                         break;
  1918                     case 0xB:
  1919                         switch( (ir&0xF0) >> 4 ) {
  1920                             case 0x0:
  1921                                 { /* JSR @Rn */
  1922                                 uint32_t Rn = ((ir>>8)&0xF); 
  1923                                 if( sh4_x86.in_delay_slot ) {
  1924                             	SLOTILLEGAL();
  1925                                 } else {
  1926                             	load_spreg( R_EAX, R_PC );
  1927                             	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
  1928                             	store_spreg( R_EAX, R_PR );
  1929                             	load_reg( R_ECX, Rn );
  1930                             	store_spreg( R_ECX, R_NEW_PC );
  1931                             	sh4_x86.in_delay_slot = DELAY_PC;
  1932                             	sh4_x86.branch_taken = TRUE;
  1933                             	sh4_x86.tstate = TSTATE_NONE;
  1934                             	if( UNTRANSLATABLE(pc+2) ) {
  1935                             	    exit_block_emu(pc+2);
  1936                             	    return 2;
  1937                             	} else {
  1938                             	    sh4_translate_instruction(pc+2);
  1939                             	    exit_block_newpcset(pc+2);
  1940                             	    return 4;
  1944                                 break;
  1945                             case 0x1:
  1946                                 { /* TAS.B @Rn */
  1947                                 uint32_t Rn = ((ir>>8)&0xF); 
  1948                                 load_reg( R_EAX, Rn );
  1949                                 MMU_TRANSLATE_WRITE( R_EAX );
  1950                                 PUSH_realigned_r32( R_EAX );
  1951                                 MEM_READ_BYTE( R_EAX, R_EAX );
  1952                                 TEST_r8_r8( R_AL, R_AL );
  1953                                 SETE_t();
  1954                                 OR_imm8_r8( 0x80, R_AL );
  1955                                 POP_realigned_r32( R_ECX );
  1956                                 MEM_WRITE_BYTE( R_ECX, R_EAX );
  1957                                 sh4_x86.tstate = TSTATE_NONE;
  1959                                 break;
  1960                             case 0x2:
  1961                                 { /* JMP @Rn */
  1962                                 uint32_t Rn = ((ir>>8)&0xF); 
  1963                                 if( sh4_x86.in_delay_slot ) {
  1964                             	SLOTILLEGAL();
  1965                                 } else {
  1966                             	load_reg( R_ECX, Rn );
  1967                             	store_spreg( R_ECX, R_NEW_PC );
  1968                             	sh4_x86.in_delay_slot = DELAY_PC;
  1969                             	sh4_x86.branch_taken = TRUE;
  1970                             	if( UNTRANSLATABLE(pc+2) ) {
  1971                             	    exit_block_emu(pc+2);
  1972                             	    return 2;
  1973                             	} else {
  1974                             	    sh4_translate_instruction(pc+2);
  1975                             	    exit_block_newpcset(pc+2);
  1976                             	    return 4;
  1980                                 break;
  1981                             default:
  1982                                 UNDEF();
  1983                                 break;
  1985                         break;
  1986                     case 0xC:
  1987                         { /* SHAD Rm, Rn */
  1988                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1989                         /* Annoyingly enough, not directly convertible */
  1990                         load_reg( R_EAX, Rn );
  1991                         load_reg( R_ECX, Rm );
  1992                         CMP_imm32_r32( 0, R_ECX );
  1993                         JGE_rel8(doshl);
  1995                         NEG_r32( R_ECX );      // 2
  1996                         AND_imm8_r8( 0x1F, R_CL ); // 3
  1997                         JE_rel8(emptysar);     // 2
  1998                         SAR_r32_CL( R_EAX );       // 2
  1999                         JMP_rel8(end);          // 2
  2001                         JMP_TARGET(emptysar);
  2002                         SAR_imm8_r32(31, R_EAX );  // 3
  2003                         JMP_rel8(end2);
  2005                         JMP_TARGET(doshl);
  2006                         AND_imm8_r8( 0x1F, R_CL ); // 3
  2007                         SHL_r32_CL( R_EAX );       // 2
  2008                         JMP_TARGET(end);
  2009                         JMP_TARGET(end2);
  2010                         store_reg( R_EAX, Rn );
  2011                         sh4_x86.tstate = TSTATE_NONE;
  2013                         break;
  2014                     case 0xD:
  2015                         { /* SHLD Rm, Rn */
  2016                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2017                         load_reg( R_EAX, Rn );
  2018                         load_reg( R_ECX, Rm );
  2019                         CMP_imm32_r32( 0, R_ECX );
  2020                         JGE_rel8(doshl);
  2022                         NEG_r32( R_ECX );      // 2
  2023                         AND_imm8_r8( 0x1F, R_CL ); // 3
  2024                         JE_rel8(emptyshr );
  2025                         SHR_r32_CL( R_EAX );       // 2
  2026                         JMP_rel8(end);          // 2
  2028                         JMP_TARGET(emptyshr);
  2029                         XOR_r32_r32( R_EAX, R_EAX );
  2030                         JMP_rel8(end2);
  2032                         JMP_TARGET(doshl);
  2033                         AND_imm8_r8( 0x1F, R_CL ); // 3
  2034                         SHL_r32_CL( R_EAX );       // 2
  2035                         JMP_TARGET(end);
  2036                         JMP_TARGET(end2);
  2037                         store_reg( R_EAX, Rn );
  2038                         sh4_x86.tstate = TSTATE_NONE;
  2040                         break;
  2041                     case 0xE:
  2042                         switch( (ir&0x80) >> 7 ) {
  2043                             case 0x0:
  2044                                 switch( (ir&0x70) >> 4 ) {
  2045                                     case 0x0:
  2046                                         { /* LDC Rm, SR */
  2047                                         uint32_t Rm = ((ir>>8)&0xF); 
  2048                                         if( sh4_x86.in_delay_slot ) {
  2049                                     	SLOTILLEGAL();
  2050                                         } else {
  2051                                     	check_priv();
  2052                                     	load_reg( R_EAX, Rm );
  2053                                     	call_func1( sh4_write_sr, R_EAX );
  2054                                     	sh4_x86.priv_checked = FALSE;
  2055                                     	sh4_x86.fpuen_checked = FALSE;
  2056                                     	sh4_x86.tstate = TSTATE_NONE;
  2059                                         break;
  2060                                     case 0x1:
  2061                                         { /* LDC Rm, GBR */
  2062                                         uint32_t Rm = ((ir>>8)&0xF); 
  2063                                         load_reg( R_EAX, Rm );
  2064                                         store_spreg( R_EAX, R_GBR );
  2066                                         break;
  2067                                     case 0x2:
  2068                                         { /* LDC Rm, VBR */
  2069                                         uint32_t Rm = ((ir>>8)&0xF); 
  2070                                         check_priv();
  2071                                         load_reg( R_EAX, Rm );
  2072                                         store_spreg( R_EAX, R_VBR );
  2073                                         sh4_x86.tstate = TSTATE_NONE;
  2075                                         break;
  2076                                     case 0x3:
  2077                                         { /* LDC Rm, SSR */
  2078                                         uint32_t Rm = ((ir>>8)&0xF); 
  2079                                         check_priv();
  2080                                         load_reg( R_EAX, Rm );
  2081                                         store_spreg( R_EAX, R_SSR );
  2082                                         sh4_x86.tstate = TSTATE_NONE;
  2084                                         break;
  2085                                     case 0x4:
  2086                                         { /* LDC Rm, SPC */
  2087                                         uint32_t Rm = ((ir>>8)&0xF); 
  2088                                         check_priv();
  2089                                         load_reg( R_EAX, Rm );
  2090                                         store_spreg( R_EAX, R_SPC );
  2091                                         sh4_x86.tstate = TSTATE_NONE;
  2093                                         break;
  2094                                     default:
  2095                                         UNDEF();
  2096                                         break;
  2098                                 break;
  2099                             case 0x1:
  2100                                 { /* LDC Rm, Rn_BANK */
  2101                                 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
  2102                                 check_priv();
  2103                                 load_reg( R_EAX, Rm );
  2104                                 store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
  2105                                 sh4_x86.tstate = TSTATE_NONE;
  2107                                 break;
  2109                         break;
  2110                     case 0xF:
  2111                         { /* MAC.W @Rm+, @Rn+ */
  2112                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2113                         if( Rm == Rn ) {
  2114                     	load_reg( R_EAX, Rm );
  2115                     	check_ralign16( R_EAX );
  2116                     	MMU_TRANSLATE_READ( R_EAX );
  2117                     	PUSH_realigned_r32( R_EAX );
  2118                     	load_reg( R_EAX, Rn );
  2119                     	ADD_imm8s_r32( 2, R_EAX );
  2120                     	MMU_TRANSLATE_READ_EXC( R_EAX, -5 );
  2121                     	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
  2122                     	// Note translate twice in case of page boundaries. Maybe worth
  2123                     	// adding a page-boundary check to skip the second translation
  2124                         } else {
  2125                     	load_reg( R_EAX, Rm );
  2126                     	check_ralign16( R_EAX );
  2127                     	MMU_TRANSLATE_READ( R_EAX );
  2128                     	load_reg( R_ECX, Rn );
  2129                     	check_ralign16( R_ECX );
  2130                     	PUSH_realigned_r32( R_EAX );
  2131                     	MMU_TRANSLATE_READ_EXC( R_ECX, -5 );
  2132                     	MOV_r32_r32( R_ECX, R_EAX );
  2133                     	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
  2134                     	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
  2136                         MEM_READ_WORD( R_EAX, R_EAX );
  2137                         POP_r32( R_ECX );
  2138                         PUSH_r32( R_EAX );
  2139                         MEM_READ_WORD( R_ECX, R_EAX );
  2140                         POP_realigned_r32( R_ECX );
  2141                         IMUL_r32( R_ECX );
  2143                         load_spreg( R_ECX, R_S );
  2144                         TEST_r32_r32( R_ECX, R_ECX );
  2145                         JE_rel8( nosat );
  2147                         ADD_r32_sh4r( R_EAX, R_MACL );  // 6
  2148                         JNO_rel8( end );            // 2
  2149                         load_imm32( R_EDX, 1 );         // 5
  2150                         store_spreg( R_EDX, R_MACH );   // 6
  2151                         JS_rel8( positive );        // 2
  2152                         load_imm32( R_EAX, 0x80000000 );// 5
  2153                         store_spreg( R_EAX, R_MACL );   // 6
  2154                         JMP_rel8(end2);           // 2
  2156                         JMP_TARGET(positive);
  2157                         load_imm32( R_EAX, 0x7FFFFFFF );// 5
  2158                         store_spreg( R_EAX, R_MACL );   // 6
  2159                         JMP_rel8(end3);            // 2
  2161                         JMP_TARGET(nosat);
  2162                         ADD_r32_sh4r( R_EAX, R_MACL );  // 6
  2163                         ADC_r32_sh4r( R_EDX, R_MACH );  // 6
  2164                         JMP_TARGET(end);
  2165                         JMP_TARGET(end2);
  2166                         JMP_TARGET(end3);
  2167                         sh4_x86.tstate = TSTATE_NONE;
  2169                         break;
  2171                 break;
  2172             case 0x5:
  2173                 { /* MOV.L @(disp, Rm), Rn */
  2174                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
  2175                 load_reg( R_EAX, Rm );
  2176                 ADD_imm8s_r32( disp, R_EAX );
  2177                 check_ralign32( R_EAX );
  2178                 MMU_TRANSLATE_READ( R_EAX );
  2179                 MEM_READ_LONG( R_EAX, R_EAX );
  2180                 store_reg( R_EAX, Rn );
  2181                 sh4_x86.tstate = TSTATE_NONE;
  2183                 break;
  2184             case 0x6:
  2185                 switch( ir&0xF ) {
  2186                     case 0x0:
  2187                         { /* MOV.B @Rm, Rn */
  2188                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2189                         load_reg( R_EAX, Rm );
  2190                         MMU_TRANSLATE_READ( R_EAX );
  2191                         MEM_READ_BYTE( R_EAX, R_EAX );
  2192                         store_reg( R_EAX, Rn );
  2193                         sh4_x86.tstate = TSTATE_NONE;
  2195                         break;
  2196                     case 0x1:
  2197                         { /* MOV.W @Rm, Rn */
  2198                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2199                         load_reg( R_EAX, Rm );
  2200                         check_ralign16( R_EAX );
  2201                         MMU_TRANSLATE_READ( R_EAX );
  2202                         MEM_READ_WORD( R_EAX, R_EAX );
  2203                         store_reg( R_EAX, Rn );
  2204                         sh4_x86.tstate = TSTATE_NONE;
  2206                         break;
  2207                     case 0x2:
  2208                         { /* MOV.L @Rm, Rn */
  2209                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2210                         load_reg( R_EAX, Rm );
  2211                         check_ralign32( R_EAX );
  2212                         MMU_TRANSLATE_READ( R_EAX );
  2213                         MEM_READ_LONG( R_EAX, R_EAX );
  2214                         store_reg( R_EAX, Rn );
  2215                         sh4_x86.tstate = TSTATE_NONE;
  2217                         break;
  2218                     case 0x3:
  2219                         { /* MOV Rm, Rn */
  2220                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2221                         load_reg( R_EAX, Rm );
  2222                         store_reg( R_EAX, Rn );
  2224                         break;
  2225                     case 0x4:
  2226                         { /* MOV.B @Rm+, Rn */
  2227                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2228                         load_reg( R_EAX, Rm );
  2229                         MMU_TRANSLATE_READ( R_EAX );
  2230                         ADD_imm8s_sh4r( 1, REG_OFFSET(r[Rm]) );
  2231                         MEM_READ_BYTE( R_EAX, R_EAX );
  2232                         store_reg( R_EAX, Rn );
  2233                         sh4_x86.tstate = TSTATE_NONE;
  2235                         break;
  2236                     case 0x5:
  2237                         { /* MOV.W @Rm+, Rn */
  2238                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2239                         load_reg( R_EAX, Rm );
  2240                         check_ralign16( R_EAX );
  2241                         MMU_TRANSLATE_READ( R_EAX );
  2242                         ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
  2243                         MEM_READ_WORD( R_EAX, R_EAX );
  2244                         store_reg( R_EAX, Rn );
  2245                         sh4_x86.tstate = TSTATE_NONE;
  2247                         break;
  2248                     case 0x6:
  2249                         { /* MOV.L @Rm+, Rn */
  2250                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2251                         load_reg( R_EAX, Rm );
  2252                         check_ralign32( R_EAX );
  2253                         MMU_TRANSLATE_READ( R_EAX );
  2254                         ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
  2255                         MEM_READ_LONG( R_EAX, R_EAX );
  2256                         store_reg( R_EAX, Rn );
  2257                         sh4_x86.tstate = TSTATE_NONE;
  2259                         break;
  2260                     case 0x7:
  2261                         { /* NOT Rm, Rn */
  2262                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2263                         load_reg( R_EAX, Rm );
  2264                         NOT_r32( R_EAX );
  2265                         store_reg( R_EAX, Rn );
  2266                         sh4_x86.tstate = TSTATE_NONE;
  2268                         break;
  2269                     case 0x8:
  2270                         { /* SWAP.B Rm, Rn */
  2271                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2272                         load_reg( R_EAX, Rm );
  2273                         XCHG_r8_r8( R_AL, R_AH ); // NB: does not touch EFLAGS
  2274                         store_reg( R_EAX, Rn );
  2276                         break;
  2277                     case 0x9:
  2278                         { /* SWAP.W Rm, Rn */
  2279                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2280                         load_reg( R_EAX, Rm );
  2281                         MOV_r32_r32( R_EAX, R_ECX );
  2282                         SHL_imm8_r32( 16, R_ECX );
  2283                         SHR_imm8_r32( 16, R_EAX );
  2284                         OR_r32_r32( R_EAX, R_ECX );
  2285                         store_reg( R_ECX, Rn );
  2286                         sh4_x86.tstate = TSTATE_NONE;
  2288                         break;
  2289                     case 0xA:
  2290                         { /* NEGC Rm, Rn */
  2291                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2292                         load_reg( R_EAX, Rm );
  2293                         XOR_r32_r32( R_ECX, R_ECX );
  2294                         LDC_t();
  2295                         SBB_r32_r32( R_EAX, R_ECX );
  2296                         store_reg( R_ECX, Rn );
  2297                         SETC_t();
  2298                         sh4_x86.tstate = TSTATE_C;
  2300                         break;
  2301                     case 0xB:
  2302                         { /* NEG Rm, Rn */
  2303                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2304                         load_reg( R_EAX, Rm );
  2305                         NEG_r32( R_EAX );
  2306                         store_reg( R_EAX, Rn );
  2307                         sh4_x86.tstate = TSTATE_NONE;
  2309                         break;
  2310                     case 0xC:
  2311                         { /* EXTU.B Rm, Rn */
  2312                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2313                         load_reg( R_EAX, Rm );
  2314                         MOVZX_r8_r32( R_EAX, R_EAX );
  2315                         store_reg( R_EAX, Rn );
  2317                         break;
  2318                     case 0xD:
  2319                         { /* EXTU.W Rm, Rn */
  2320                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2321                         load_reg( R_EAX, Rm );
  2322                         MOVZX_r16_r32( R_EAX, R_EAX );
  2323                         store_reg( R_EAX, Rn );
  2325                         break;
  2326                     case 0xE:
  2327                         { /* EXTS.B Rm, Rn */
  2328                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2329                         load_reg( R_EAX, Rm );
  2330                         MOVSX_r8_r32( R_EAX, R_EAX );
  2331                         store_reg( R_EAX, Rn );
  2333                         break;
  2334                     case 0xF:
  2335                         { /* EXTS.W Rm, Rn */
  2336                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2337                         load_reg( R_EAX, Rm );
  2338                         MOVSX_r16_r32( R_EAX, R_EAX );
  2339                         store_reg( R_EAX, Rn );
  2341                         break;
  2343                 break;
  2344             case 0x7:
  2345                 { /* ADD #imm, Rn */
  2346                 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
  2347                 load_reg( R_EAX, Rn );
  2348                 ADD_imm8s_r32( imm, R_EAX );
  2349                 store_reg( R_EAX, Rn );
  2350                 sh4_x86.tstate = TSTATE_NONE;
  2352                 break;
  2353             case 0x8:
  2354                 switch( (ir&0xF00) >> 8 ) {
  2355                     case 0x0:
  2356                         { /* MOV.B R0, @(disp, Rn) */
  2357                         uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
  2358                         load_reg( R_EAX, Rn );
  2359                         ADD_imm32_r32( disp, R_EAX );
  2360                         MMU_TRANSLATE_WRITE( R_EAX );
  2361                         load_reg( R_EDX, 0 );
  2362                         MEM_WRITE_BYTE( R_EAX, R_EDX );
  2363                         sh4_x86.tstate = TSTATE_NONE;
  2365                         break;
  2366                     case 0x1:
  2367                         { /* MOV.W R0, @(disp, Rn) */
  2368                         uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
  2369                         load_reg( R_EAX, Rn );
  2370                         ADD_imm32_r32( disp, R_EAX );
  2371                         check_walign16( R_EAX );
  2372                         MMU_TRANSLATE_WRITE( R_EAX );
  2373                         load_reg( R_EDX, 0 );
  2374                         MEM_WRITE_WORD( R_EAX, R_EDX );
  2375                         sh4_x86.tstate = TSTATE_NONE;
  2377                         break;
  2378                     case 0x4:
  2379                         { /* MOV.B @(disp, Rm), R0 */
  2380                         uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
  2381                         load_reg( R_EAX, Rm );
  2382                         ADD_imm32_r32( disp, R_EAX );
  2383                         MMU_TRANSLATE_READ( R_EAX );
  2384                         MEM_READ_BYTE( R_EAX, R_EAX );
  2385                         store_reg( R_EAX, 0 );
  2386                         sh4_x86.tstate = TSTATE_NONE;
  2388                         break;
  2389                     case 0x5:
  2390                         { /* MOV.W @(disp, Rm), R0 */
  2391                         uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
  2392                         load_reg( R_EAX, Rm );
  2393                         ADD_imm32_r32( disp, R_EAX );
  2394                         check_ralign16( R_EAX );
  2395                         MMU_TRANSLATE_READ( R_EAX );
  2396                         MEM_READ_WORD( R_EAX, R_EAX );
  2397                         store_reg( R_EAX, 0 );
  2398                         sh4_x86.tstate = TSTATE_NONE;
  2400                         break;
  2401                     case 0x8:
  2402                         { /* CMP/EQ #imm, R0 */
  2403                         int32_t imm = SIGNEXT8(ir&0xFF); 
  2404                         load_reg( R_EAX, 0 );
  2405                         CMP_imm8s_r32(imm, R_EAX);
  2406                         SETE_t();
  2407                         sh4_x86.tstate = TSTATE_E;
  2409                         break;
  2410                     case 0x9:
  2411                         { /* BT disp */
  2412                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  2413                         if( sh4_x86.in_delay_slot ) {
  2414                     	SLOTILLEGAL();
  2415                         } else {
  2416                     	sh4vma_t target = disp + pc + 4;
  2417                     	JF_rel8( nottaken );
  2418                     	exit_block_rel(target, pc+2 );
  2419                     	JMP_TARGET(nottaken);
  2420                     	return 2;
  2423                         break;
  2424                     case 0xB:
  2425                         { /* BF disp */
  2426                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  2427                         if( sh4_x86.in_delay_slot ) {
  2428                     	SLOTILLEGAL();
  2429                         } else {
  2430                     	sh4vma_t target = disp + pc + 4;
  2431                     	JT_rel8( nottaken );
  2432                     	exit_block_rel(target, pc+2 );
  2433                     	JMP_TARGET(nottaken);
  2434                     	return 2;
  2437                         break;
  2438                     case 0xD:
  2439                         { /* BT/S disp */
  2440                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  2441                         if( sh4_x86.in_delay_slot ) {
  2442                     	SLOTILLEGAL();
  2443                         } else {
  2444                     	sh4_x86.in_delay_slot = DELAY_PC;
  2445                     	if( UNTRANSLATABLE(pc+2) ) {
  2446                     	    load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc );
  2447                     	    JF_rel8(nottaken);
  2448                     	    ADD_imm32_r32( disp, R_EAX );
  2449                     	    JMP_TARGET(nottaken);
  2450                     	    ADD_sh4r_r32( R_PC, R_EAX );
  2451                     	    store_spreg( R_EAX, R_NEW_PC );
  2452                     	    exit_block_emu(pc+2);
  2453                     	    sh4_x86.branch_taken = TRUE;
  2454                     	    return 2;
  2455                     	} else {
  2456                     	    if( sh4_x86.tstate == TSTATE_NONE ) {
  2457                     		CMP_imm8s_sh4r( 1, R_T );
  2458                     		sh4_x86.tstate = TSTATE_E;
  2460                     	    OP(0x0F); OP(0x80+(sh4_x86.tstate^1)); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JF rel32
  2461                     	    sh4_translate_instruction(pc+2);
  2462                     	    exit_block_rel( disp + pc + 4, pc+4 );
  2463                     	    // not taken
  2464                     	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
  2465                     	    sh4_translate_instruction(pc+2);
  2466                     	    return 4;
  2470                         break;
  2471                     case 0xF:
  2472                         { /* BF/S disp */
  2473                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  2474                         if( sh4_x86.in_delay_slot ) {
  2475                     	SLOTILLEGAL();
  2476                         } else {
  2477                     	sh4_x86.in_delay_slot = DELAY_PC;
  2478                     	if( UNTRANSLATABLE(pc+2) ) {
  2479                     	    load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc );
  2480                     	    JT_rel8(nottaken);
  2481                     	    ADD_imm32_r32( disp, R_EAX );
  2482                     	    JMP_TARGET(nottaken);
  2483                     	    ADD_sh4r_r32( R_PC, R_EAX );
  2484                     	    store_spreg( R_EAX, R_NEW_PC );
  2485                     	    exit_block_emu(pc+2);
  2486                     	    sh4_x86.branch_taken = TRUE;
  2487                     	    return 2;
  2488                     	} else {
  2489                     	    if( sh4_x86.tstate == TSTATE_NONE ) {
  2490                     		CMP_imm8s_sh4r( 1, R_T );
  2491                     		sh4_x86.tstate = TSTATE_E;
  2493                     	    sh4vma_t target = disp + pc + 4;
  2494                     	    OP(0x0F); OP(0x80+sh4_x86.tstate); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JT rel32
  2495                     	    sh4_translate_instruction(pc+2);
  2496                     	    exit_block_rel( target, pc+4 );
  2498                     	    // not taken
  2499                     	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
  2500                     	    sh4_translate_instruction(pc+2);
  2501                     	    return 4;
  2505                         break;
  2506                     default:
  2507                         UNDEF();
  2508                         break;
  2510                 break;
  2511             case 0x9:
  2512                 { /* MOV.W @(disp, PC), Rn */
  2513                 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1; 
  2514                 if( sh4_x86.in_delay_slot ) {
  2515             	SLOTILLEGAL();
  2516                 } else {
  2517             	// See comments for MOV.L @(disp, PC), Rn
  2518             	uint32_t target = pc + disp + 4;
  2519             	if( IS_IN_ICACHE(target) ) {
  2520             	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
  2521             	    MOV_moff32_EAX( ptr );
  2522             	    MOVSX_r16_r32( R_EAX, R_EAX );
  2523             	} else {
  2524             	    load_imm32( R_EAX, (pc - sh4_x86.block_start_pc) + disp + 4 );
  2525             	    ADD_sh4r_r32( R_PC, R_EAX );
  2526             	    MMU_TRANSLATE_READ( R_EAX );
  2527             	    MEM_READ_WORD( R_EAX, R_EAX );
  2528             	    sh4_x86.tstate = TSTATE_NONE;
  2530             	store_reg( R_EAX, Rn );
  2533                 break;
  2534             case 0xA:
  2535                 { /* BRA disp */
  2536                 int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
  2537                 if( sh4_x86.in_delay_slot ) {
  2538             	SLOTILLEGAL();
  2539                 } else {
  2540             	sh4_x86.in_delay_slot = DELAY_PC;
  2541             	sh4_x86.branch_taken = TRUE;
  2542             	if( UNTRANSLATABLE(pc+2) ) {
  2543             	    load_spreg( R_EAX, R_PC );
  2544             	    ADD_imm32_r32( pc + disp + 4 - sh4_x86.block_start_pc, R_EAX );
  2545             	    store_spreg( R_EAX, R_NEW_PC );
  2546             	    exit_block_emu(pc+2);
  2547             	    return 2;
  2548             	} else {
  2549             	    sh4_translate_instruction( pc + 2 );
  2550             	    exit_block_rel( disp + pc + 4, pc+4 );
  2551             	    return 4;
  2555                 break;
  2556             case 0xB:
  2557                 { /* BSR disp */
  2558                 int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
  2559                 if( sh4_x86.in_delay_slot ) {
  2560             	SLOTILLEGAL();
  2561                 } else {
  2562             	load_spreg( R_EAX, R_PC );
  2563             	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
  2564             	store_spreg( R_EAX, R_PR );
  2565             	sh4_x86.in_delay_slot = DELAY_PC;
  2566             	sh4_x86.branch_taken = TRUE;
  2567             	sh4_x86.tstate = TSTATE_NONE;
  2568             	if( UNTRANSLATABLE(pc+2) ) {
  2569             	    ADD_imm32_r32( disp, R_EAX );
  2570             	    store_spreg( R_EAX, R_NEW_PC );
  2571             	    exit_block_emu(pc+2);
  2572             	    return 2;
  2573             	} else {
  2574             	    sh4_translate_instruction( pc + 2 );
  2575             	    exit_block_rel( disp + pc + 4, pc+4 );
  2576             	    return 4;
  2580                 break;
  2581             case 0xC:
  2582                 switch( (ir&0xF00) >> 8 ) {
  2583                     case 0x0:
  2584                         { /* MOV.B R0, @(disp, GBR) */
  2585                         uint32_t disp = (ir&0xFF); 
  2586                         load_spreg( R_EAX, R_GBR );
  2587                         ADD_imm32_r32( disp, R_EAX );
  2588                         MMU_TRANSLATE_WRITE( R_EAX );
  2589                         load_reg( R_EDX, 0 );
  2590                         MEM_WRITE_BYTE( R_EAX, R_EDX );
  2591                         sh4_x86.tstate = TSTATE_NONE;
  2593                         break;
  2594                     case 0x1:
  2595                         { /* MOV.W R0, @(disp, GBR) */
  2596                         uint32_t disp = (ir&0xFF)<<1; 
  2597                         load_spreg( R_EAX, R_GBR );
  2598                         ADD_imm32_r32( disp, R_EAX );
  2599                         check_walign16( R_EAX );
  2600                         MMU_TRANSLATE_WRITE( R_EAX );
  2601                         load_reg( R_EDX, 0 );
  2602                         MEM_WRITE_WORD( R_EAX, R_EDX );
  2603                         sh4_x86.tstate = TSTATE_NONE;
  2605                         break;
  2606                     case 0x2:
  2607                         { /* MOV.L R0, @(disp, GBR) */
  2608                         uint32_t disp = (ir&0xFF)<<2; 
  2609                         load_spreg( R_EAX, R_GBR );
  2610                         ADD_imm32_r32( disp, R_EAX );
  2611                         check_walign32( R_EAX );
  2612                         MMU_TRANSLATE_WRITE( R_EAX );
  2613                         load_reg( R_EDX, 0 );
  2614                         MEM_WRITE_LONG( R_EAX, R_EDX );
  2615                         sh4_x86.tstate = TSTATE_NONE;
  2617                         break;
  2618                     case 0x3:
  2619                         { /* TRAPA #imm */
  2620                         uint32_t imm = (ir&0xFF); 
  2621                         if( sh4_x86.in_delay_slot ) {
  2622                     	SLOTILLEGAL();
  2623                         } else {
  2624                     	load_imm32( R_ECX, pc+2 - sh4_x86.block_start_pc );   // 5
  2625                     	ADD_r32_sh4r( R_ECX, R_PC );
  2626                     	load_imm32( R_EAX, imm );
  2627                     	call_func1( sh4_raise_trap, R_EAX );
  2628                     	sh4_x86.tstate = TSTATE_NONE;
  2629                     	exit_block_pcset(pc);
  2630                     	sh4_x86.branch_taken = TRUE;
  2631                     	return 2;
  2634                         break;
  2635                     case 0x4:
  2636                         { /* MOV.B @(disp, GBR), R0 */
  2637                         uint32_t disp = (ir&0xFF); 
  2638                         load_spreg( R_EAX, R_GBR );
  2639                         ADD_imm32_r32( disp, R_EAX );
  2640                         MMU_TRANSLATE_READ( R_EAX );
  2641                         MEM_READ_BYTE( R_EAX, R_EAX );
  2642                         store_reg( R_EAX, 0 );
  2643                         sh4_x86.tstate = TSTATE_NONE;
  2645                         break;
  2646                     case 0x5:
  2647                         { /* MOV.W @(disp, GBR), R0 */
  2648                         uint32_t disp = (ir&0xFF)<<1; 
  2649                         load_spreg( R_EAX, R_GBR );
  2650                         ADD_imm32_r32( disp, R_EAX );
  2651                         check_ralign16( R_EAX );
  2652                         MMU_TRANSLATE_READ( R_EAX );
  2653                         MEM_READ_WORD( R_EAX, R_EAX );
  2654                         store_reg( R_EAX, 0 );
  2655                         sh4_x86.tstate = TSTATE_NONE;
  2657                         break;
  2658                     case 0x6:
  2659                         { /* MOV.L @(disp, GBR), R0 */
  2660                         uint32_t disp = (ir&0xFF)<<2; 
  2661                         load_spreg( R_EAX, R_GBR );
  2662                         ADD_imm32_r32( disp, R_EAX );
  2663                         check_ralign32( R_EAX );
  2664                         MMU_TRANSLATE_READ( R_EAX );
  2665                         MEM_READ_LONG( R_EAX, R_EAX );
  2666                         store_reg( R_EAX, 0 );
  2667                         sh4_x86.tstate = TSTATE_NONE;
  2669                         break;
  2670                     case 0x7:
  2671                         { /* MOVA @(disp, PC), R0 */
  2672                         uint32_t disp = (ir&0xFF)<<2; 
  2673                         if( sh4_x86.in_delay_slot ) {
  2674                     	SLOTILLEGAL();
  2675                         } else {
  2676                     	load_imm32( R_ECX, (pc - sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
  2677                     	ADD_sh4r_r32( R_PC, R_ECX );
  2678                     	store_reg( R_ECX, 0 );
  2679                     	sh4_x86.tstate = TSTATE_NONE;
  2682                         break;
  2683                     case 0x8:
  2684                         { /* TST #imm, R0 */
  2685                         uint32_t imm = (ir&0xFF); 
  2686                         load_reg( R_EAX, 0 );
  2687                         TEST_imm32_r32( imm, R_EAX );
  2688                         SETE_t();
  2689                         sh4_x86.tstate = TSTATE_E;
  2691                         break;
  2692                     case 0x9:
  2693                         { /* AND #imm, R0 */
  2694                         uint32_t imm = (ir&0xFF); 
  2695                         load_reg( R_EAX, 0 );
  2696                         AND_imm32_r32(imm, R_EAX); 
  2697                         store_reg( R_EAX, 0 );
  2698                         sh4_x86.tstate = TSTATE_NONE;
  2700                         break;
  2701                     case 0xA:
  2702                         { /* XOR #imm, R0 */
  2703                         uint32_t imm = (ir&0xFF); 
  2704                         load_reg( R_EAX, 0 );
  2705                         XOR_imm32_r32( imm, R_EAX );
  2706                         store_reg( R_EAX, 0 );
  2707                         sh4_x86.tstate = TSTATE_NONE;
  2709                         break;
  2710                     case 0xB:
  2711                         { /* OR #imm, R0 */
  2712                         uint32_t imm = (ir&0xFF); 
  2713                         load_reg( R_EAX, 0 );
  2714                         OR_imm32_r32(imm, R_EAX);
  2715                         store_reg( R_EAX, 0 );
  2716                         sh4_x86.tstate = TSTATE_NONE;
  2718                         break;
  2719                     case 0xC:
  2720                         { /* TST.B #imm, @(R0, GBR) */
  2721                         uint32_t imm = (ir&0xFF); 
  2722                         load_reg( R_EAX, 0);
  2723                         load_reg( R_ECX, R_GBR);
  2724                         ADD_r32_r32( R_ECX, R_EAX );
  2725                         MMU_TRANSLATE_READ( R_EAX );
  2726                         MEM_READ_BYTE( R_EAX, R_EAX );
  2727                         TEST_imm8_r8( imm, R_AL );
  2728                         SETE_t();
  2729                         sh4_x86.tstate = TSTATE_E;
  2731                         break;
  2732                     case 0xD:
  2733                         { /* AND.B #imm, @(R0, GBR) */
  2734                         uint32_t imm = (ir&0xFF); 
  2735                         load_reg( R_EAX, 0 );
  2736                         load_spreg( R_ECX, R_GBR );
  2737                         ADD_r32_r32( R_ECX, R_EAX );
  2738                         MMU_TRANSLATE_WRITE( R_EAX );
  2739                         PUSH_realigned_r32(R_EAX);
  2740                         MEM_READ_BYTE( R_EAX, R_EAX );
  2741                         POP_realigned_r32(R_ECX);
  2742                         AND_imm32_r32(imm, R_EAX );
  2743                         MEM_WRITE_BYTE( R_ECX, R_EAX );
  2744                         sh4_x86.tstate = TSTATE_NONE;
  2746                         break;
  2747                     case 0xE:
  2748                         { /* XOR.B #imm, @(R0, GBR) */
  2749                         uint32_t imm = (ir&0xFF); 
  2750                         load_reg( R_EAX, 0 );
  2751                         load_spreg( R_ECX, R_GBR );
  2752                         ADD_r32_r32( R_ECX, R_EAX );
  2753                         MMU_TRANSLATE_WRITE( R_EAX );
  2754                         PUSH_realigned_r32(R_EAX);
  2755                         MEM_READ_BYTE(R_EAX, R_EAX);
  2756                         POP_realigned_r32(R_ECX);
  2757                         XOR_imm32_r32( imm, R_EAX );
  2758                         MEM_WRITE_BYTE( R_ECX, R_EAX );
  2759                         sh4_x86.tstate = TSTATE_NONE;
  2761                         break;
  2762                     case 0xF:
  2763                         { /* OR.B #imm, @(R0, GBR) */
  2764                         uint32_t imm = (ir&0xFF); 
  2765                         load_reg( R_EAX, 0 );
  2766                         load_spreg( R_ECX, R_GBR );
  2767                         ADD_r32_r32( R_ECX, R_EAX );
  2768                         MMU_TRANSLATE_WRITE( R_EAX );
  2769                         PUSH_realigned_r32(R_EAX);
  2770                         MEM_READ_BYTE( R_EAX, R_EAX );
  2771                         POP_realigned_r32(R_ECX);
  2772                         OR_imm32_r32(imm, R_EAX );
  2773                         MEM_WRITE_BYTE( R_ECX, R_EAX );
  2774                         sh4_x86.tstate = TSTATE_NONE;
  2776                         break;
  2778                 break;
  2779             case 0xD:
  2780                 { /* MOV.L @(disp, PC), Rn */
  2781                 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<2; 
  2782                 if( sh4_x86.in_delay_slot ) {
  2783             	SLOTILLEGAL();
  2784                 } else {
  2785             	uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
  2786             	if( IS_IN_ICACHE(target) ) {
  2787             	    // If the target address is in the same page as the code, it's
  2788             	    // pretty safe to just ref it directly and circumvent the whole
  2789             	    // memory subsystem. (this is a big performance win)
  2791             	    // FIXME: There's a corner-case that's not handled here when
  2792             	    // the current code-page is in the ITLB but not in the UTLB.
  2793             	    // (should generate a TLB miss although need to test SH4 
  2794             	    // behaviour to confirm) Unlikely to be anyone depending on this
  2795             	    // behaviour though.
  2796             	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
  2797             	    MOV_moff32_EAX( ptr );
  2798             	} else {
  2799             	    // Note: we use sh4r.pc for the calc as we could be running at a
  2800             	    // different virtual address than the translation was done with,
  2801             	    // but we can safely assume that the low bits are the same.
  2802             	    load_imm32( R_EAX, (pc-sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
  2803             	    ADD_sh4r_r32( R_PC, R_EAX );
  2804             	    MMU_TRANSLATE_READ( R_EAX );
  2805             	    MEM_READ_LONG( R_EAX, R_EAX );
  2806             	    sh4_x86.tstate = TSTATE_NONE;
  2808             	store_reg( R_EAX, Rn );
  2811                 break;
  2812             case 0xE:
  2813                 { /* MOV #imm, Rn */
  2814                 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
  2815                 load_imm32( R_EAX, imm );
  2816                 store_reg( R_EAX, Rn );
  2818                 break;
  2819             case 0xF:
  2820                 switch( ir&0xF ) {
  2821                     case 0x0:
  2822                         { /* FADD FRm, FRn */
  2823                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2824                         check_fpuen();
  2825                         load_spreg( R_ECX, R_FPSCR );
  2826                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  2827                         JNE_rel8(doubleprec);
  2828                         push_fr(FRm);
  2829                         push_fr(FRn);
  2830                         FADDP_st(1);
  2831                         pop_fr(FRn);
  2832                         JMP_rel8(end);
  2833                         JMP_TARGET(doubleprec);
  2834                         push_dr(FRm);
  2835                         push_dr(FRn);
  2836                         FADDP_st(1);
  2837                         pop_dr(FRn);
  2838                         JMP_TARGET(end);
  2839                         sh4_x86.tstate = TSTATE_NONE;
  2841                         break;
  2842                     case 0x1:
  2843                         { /* FSUB FRm, FRn */
  2844                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2845                         check_fpuen();
  2846                         load_spreg( R_ECX, R_FPSCR );
  2847                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  2848                         JNE_rel8(doubleprec);
  2849                         push_fr(FRn);
  2850                         push_fr(FRm);
  2851                         FSUBP_st(1);
  2852                         pop_fr(FRn);
  2853                         JMP_rel8(end);
  2854                         JMP_TARGET(doubleprec);
  2855                         push_dr(FRn);
  2856                         push_dr(FRm);
  2857                         FSUBP_st(1);
  2858                         pop_dr(FRn);
  2859                         JMP_TARGET(end);
  2860                         sh4_x86.tstate = TSTATE_NONE;
  2862                         break;
  2863                     case 0x2:
  2864                         { /* FMUL FRm, FRn */
  2865                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2866                         check_fpuen();
  2867                         load_spreg( R_ECX, R_FPSCR );
  2868                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  2869                         JNE_rel8(doubleprec);
  2870                         push_fr(FRm);
  2871                         push_fr(FRn);
  2872                         FMULP_st(1);
  2873                         pop_fr(FRn);
  2874                         JMP_rel8(end);
  2875                         JMP_TARGET(doubleprec);
  2876                         push_dr(FRm);
  2877                         push_dr(FRn);
  2878                         FMULP_st(1);
  2879                         pop_dr(FRn);
  2880                         JMP_TARGET(end);
  2881                         sh4_x86.tstate = TSTATE_NONE;
  2883                         break;
  2884                     case 0x3:
  2885                         { /* FDIV FRm, FRn */
  2886                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2887                         check_fpuen();
  2888                         load_spreg( R_ECX, R_FPSCR );
  2889                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  2890                         JNE_rel8(doubleprec);
  2891                         push_fr(FRn);
  2892                         push_fr(FRm);
  2893                         FDIVP_st(1);
  2894                         pop_fr(FRn);
  2895                         JMP_rel8(end);
  2896                         JMP_TARGET(doubleprec);
  2897                         push_dr(FRn);
  2898                         push_dr(FRm);
  2899                         FDIVP_st(1);
  2900                         pop_dr(FRn);
  2901                         JMP_TARGET(end);
  2902                         sh4_x86.tstate = TSTATE_NONE;
  2904                         break;
  2905                     case 0x4:
  2906                         { /* FCMP/EQ FRm, FRn */
  2907                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2908                         check_fpuen();
  2909                         load_spreg( R_ECX, R_FPSCR );
  2910                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  2911                         JNE_rel8(doubleprec);
  2912                         push_fr(FRm);
  2913                         push_fr(FRn);
  2914                         JMP_rel8(end);
  2915                         JMP_TARGET(doubleprec);
  2916                         push_dr(FRm);
  2917                         push_dr(FRn);
  2918                         JMP_TARGET(end);
  2919                         FCOMIP_st(1);
  2920                         SETE_t();
  2921                         FPOP_st();
  2922                         sh4_x86.tstate = TSTATE_NONE;
  2924                         break;
  2925                     case 0x5:
  2926                         { /* FCMP/GT FRm, FRn */
  2927                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2928                         check_fpuen();
  2929                         load_spreg( R_ECX, R_FPSCR );
  2930                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  2931                         JNE_rel8(doubleprec);
  2932                         push_fr(FRm);
  2933                         push_fr(FRn);
  2934                         JMP_rel8(end);
  2935                         JMP_TARGET(doubleprec);
  2936                         push_dr(FRm);
  2937                         push_dr(FRn);
  2938                         JMP_TARGET(end);
  2939                         FCOMIP_st(1);
  2940                         SETA_t();
  2941                         FPOP_st();
  2942                         sh4_x86.tstate = TSTATE_NONE;
  2944                         break;
  2945                     case 0x6:
  2946                         { /* FMOV @(R0, Rm), FRn */
  2947                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2948                         check_fpuen();
  2949                         load_reg( R_EAX, Rm );
  2950                         ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
  2951                         check_ralign32( R_EAX );
  2952                         MMU_TRANSLATE_READ( R_EAX );
  2953                         load_spreg( R_EDX, R_FPSCR );
  2954                         TEST_imm32_r32( FPSCR_SZ, R_EDX );
  2955                         JNE_rel8(doublesize);
  2957                         MEM_READ_LONG( R_EAX, R_EAX );
  2958                         store_fr( R_EAX, FRn );
  2959                         JMP_rel8(end);
  2961                         JMP_TARGET(doublesize);
  2962                         MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
  2963                         store_dr0( R_ECX, FRn );
  2964                         store_dr1( R_EAX, FRn );
  2965                         JMP_TARGET(end);
  2967                         sh4_x86.tstate = TSTATE_NONE;
  2969                         break;
  2970                     case 0x7:
  2971                         { /* FMOV FRm, @(R0, Rn) */
  2972                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2973                         check_fpuen();
  2974                         load_reg( R_EAX, Rn );
  2975                         ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
  2976                         check_walign32( R_EAX );
  2977                         MMU_TRANSLATE_WRITE( R_EAX );
  2978                         load_spreg( R_EDX, R_FPSCR );
  2979                         TEST_imm32_r32( FPSCR_SZ, R_EDX );
  2980                         JNE_rel8(doublesize);
  2982                         load_fr( R_ECX, FRm );
  2983                         MEM_WRITE_LONG( R_EAX, R_ECX ); // 12
  2984                         JMP_rel8(end);
  2986                         JMP_TARGET(doublesize);
  2987                         load_dr0( R_ECX, FRm );
  2988                         load_dr1( R_EDX, FRm );
  2989                         MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
  2990                         JMP_TARGET(end);
  2992                         sh4_x86.tstate = TSTATE_NONE;
  2994                         break;
  2995                     case 0x8:
  2996                         { /* FMOV @Rm, FRn */
  2997                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2998                         check_fpuen();
  2999                         load_reg( R_EAX, Rm );
  3000                         check_ralign32( R_EAX );
  3001                         MMU_TRANSLATE_READ( R_EAX );
  3002                         load_spreg( R_EDX, R_FPSCR );
  3003                         TEST_imm32_r32( FPSCR_SZ, R_EDX );
  3004                         JNE_rel8(doublesize);
  3006                         MEM_READ_LONG( R_EAX, R_EAX );
  3007                         store_fr( R_EAX, FRn );
  3008                         JMP_rel8(end);
  3010                         JMP_TARGET(doublesize);
  3011                         MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
  3012                         store_dr0( R_ECX, FRn );
  3013                         store_dr1( R_EAX, FRn );
  3014                         JMP_TARGET(end);
  3015                         sh4_x86.tstate = TSTATE_NONE;
  3017                         break;
  3018                     case 0x9:
  3019                         { /* FMOV @Rm+, FRn */
  3020                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  3021                         check_fpuen();
  3022                         load_reg( R_EAX, Rm );
  3023                         check_ralign32( R_EAX );
  3024                         MMU_TRANSLATE_READ( R_EAX );
  3025                         load_spreg( R_EDX, R_FPSCR );
  3026                         TEST_imm32_r32( FPSCR_SZ, R_EDX );
  3027                         JNE_rel8(doublesize);
  3029                         ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
  3030                         MEM_READ_LONG( R_EAX, R_EAX );
  3031                         store_fr( R_EAX, FRn );
  3032                         JMP_rel8(end);
  3034                         JMP_TARGET(doublesize);
  3035                         ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rm]) );
  3036                         MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
  3037                         store_dr0( R_ECX, FRn );
  3038                         store_dr1( R_EAX, FRn );
  3039                         JMP_TARGET(end);
  3041                         sh4_x86.tstate = TSTATE_NONE;
  3043                         break;
  3044                     case 0xA:
  3045                         { /* FMOV FRm, @Rn */
  3046                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  3047                         check_fpuen();
  3048                         load_reg( R_EAX, Rn );
  3049                         check_walign32( R_EAX );
  3050                         MMU_TRANSLATE_WRITE( R_EAX );
  3051                         load_spreg( R_EDX, R_FPSCR );
  3052                         TEST_imm32_r32( FPSCR_SZ, R_EDX );
  3053                         JNE_rel8(doublesize);
  3055                         load_fr( R_ECX, FRm );
  3056                         MEM_WRITE_LONG( R_EAX, R_ECX ); // 12
  3057                         JMP_rel8(end);
  3059                         JMP_TARGET(doublesize);
  3060                         load_dr0( R_ECX, FRm );
  3061                         load_dr1( R_EDX, FRm );
  3062                         MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
  3063                         JMP_TARGET(end);
  3064                         sh4_x86.tstate = TSTATE_NONE;
  3066                         break;
  3067                     case 0xB:
  3068                         { /* FMOV FRm, @-Rn */
  3069                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  3070                         check_fpuen();
  3071                         load_reg( R_EAX, Rn );
  3072                         check_walign32( R_EAX );
  3073                         load_spreg( R_EDX, R_FPSCR );
  3074                         TEST_imm32_r32( FPSCR_SZ, R_EDX );
  3075                         JNE_rel8(doublesize);
  3077                         ADD_imm8s_r32( -4, R_EAX );
  3078                         MMU_TRANSLATE_WRITE( R_EAX );
  3079                         load_fr( R_ECX, FRm );
  3080                         ADD_imm8s_sh4r(-4,REG_OFFSET(r[Rn]));
  3081                         MEM_WRITE_LONG( R_EAX, R_ECX );
  3082                         JMP_rel8(end);
  3084                         JMP_TARGET(doublesize);
  3085                         ADD_imm8s_r32(-8,R_EAX);
  3086                         MMU_TRANSLATE_WRITE( R_EAX );
  3087                         load_dr0( R_ECX, FRm );
  3088                         load_dr1( R_EDX, FRm );
  3089                         ADD_imm8s_sh4r(-8,REG_OFFSET(r[Rn]));
  3090                         MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
  3091                         JMP_TARGET(end);
  3093                         sh4_x86.tstate = TSTATE_NONE;
  3095                         break;
  3096                     case 0xC:
  3097                         { /* FMOV FRm, FRn */
  3098                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  3099                         /* As horrible as this looks, it's actually covering 5 separate cases:
  3100                          * 1. 32-bit fr-to-fr (PR=0)
  3101                          * 2. 64-bit dr-to-dr (PR=1, FRm&1 == 0, FRn&1 == 0 )
  3102                          * 3. 64-bit dr-to-xd (PR=1, FRm&1 == 0, FRn&1 == 1 )
  3103                          * 4. 64-bit xd-to-dr (PR=1, FRm&1 == 1, FRn&1 == 0 )
  3104                          * 5. 64-bit xd-to-xd (PR=1, FRm&1 == 1, FRn&1 == 1 )
  3105                          */
  3106                         check_fpuen();
  3107                         load_spreg( R_ECX, R_FPSCR );
  3108                         TEST_imm32_r32( FPSCR_SZ, R_ECX );
  3109                         JNE_rel8(doublesize);
  3110                         load_fr( R_EAX, FRm ); // PR=0 branch
  3111                         store_fr( R_EAX, FRn );
  3112                         JMP_rel8(end);
  3113                         JMP_TARGET(doublesize);
  3114                         load_dr0( R_EAX, FRm );
  3115                         load_dr1( R_ECX, FRm );
  3116                         store_dr0( R_EAX, FRn );
  3117                         store_dr1( R_ECX, FRn );
  3118                         JMP_TARGET(end);
  3119                         sh4_x86.tstate = TSTATE_NONE;
  3121                         break;
  3122                     case 0xD:
  3123                         switch( (ir&0xF0) >> 4 ) {
  3124                             case 0x0:
  3125                                 { /* FSTS FPUL, FRn */
  3126                                 uint32_t FRn = ((ir>>8)&0xF); 
  3127                                 check_fpuen();
  3128                                 load_spreg( R_EAX, R_FPUL );
  3129                                 store_fr( R_EAX, FRn );
  3130                                 sh4_x86.tstate = TSTATE_NONE;
  3132                                 break;
  3133                             case 0x1:
  3134                                 { /* FLDS FRm, FPUL */
  3135                                 uint32_t FRm = ((ir>>8)&0xF); 
  3136                                 check_fpuen();
  3137                                 load_fr( R_EAX, FRm );
  3138                                 store_spreg( R_EAX, R_FPUL );
  3139                                 sh4_x86.tstate = TSTATE_NONE;
  3141                                 break;
  3142                             case 0x2:
  3143                                 { /* FLOAT FPUL, FRn */
  3144                                 uint32_t FRn = ((ir>>8)&0xF); 
  3145                                 check_fpuen();
  3146                                 load_spreg( R_ECX, R_FPSCR );
  3147                                 FILD_sh4r(R_FPUL);
  3148                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3149                                 JNE_rel8(doubleprec);
  3150                                 pop_fr( FRn );
  3151                                 JMP_rel8(end);
  3152                                 JMP_TARGET(doubleprec);
  3153                                 pop_dr( FRn );
  3154                                 JMP_TARGET(end);
  3155                                 sh4_x86.tstate = TSTATE_NONE;
  3157                                 break;
  3158                             case 0x3:
  3159                                 { /* FTRC FRm, FPUL */
  3160                                 uint32_t FRm = ((ir>>8)&0xF); 
  3161                                 check_fpuen();
  3162                                 load_spreg( R_ECX, R_FPSCR );
  3163                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3164                                 JNE_rel8(doubleprec);
  3165                                 push_fr( FRm );
  3166                                 JMP_rel8(doop);
  3167                                 JMP_TARGET(doubleprec);
  3168                                 push_dr( FRm );
  3169                                 JMP_TARGET( doop );
  3170                                 load_imm32( R_ECX, (uint32_t)&max_int );
  3171                                 FILD_r32ind( R_ECX );
  3172                                 FCOMIP_st(1);
  3173                                 JNA_rel8( sat );
  3174                                 load_imm32( R_ECX, (uint32_t)&min_int );  // 5
  3175                                 FILD_r32ind( R_ECX );           // 2
  3176                                 FCOMIP_st(1);                   // 2
  3177                                 JAE_rel8( sat2 );            // 2
  3178                                 load_imm32( R_EAX, (uint32_t)&save_fcw );
  3179                                 FNSTCW_r32ind( R_EAX );
  3180                                 load_imm32( R_EDX, (uint32_t)&trunc_fcw );
  3181                                 FLDCW_r32ind( R_EDX );
  3182                                 FISTP_sh4r(R_FPUL);             // 3
  3183                                 FLDCW_r32ind( R_EAX );
  3184                                 JMP_rel8(end);             // 2
  3186                                 JMP_TARGET(sat);
  3187                                 JMP_TARGET(sat2);
  3188                                 MOV_r32ind_r32( R_ECX, R_ECX ); // 2
  3189                                 store_spreg( R_ECX, R_FPUL );
  3190                                 FPOP_st();
  3191                                 JMP_TARGET(end);
  3192                                 sh4_x86.tstate = TSTATE_NONE;
  3194                                 break;
  3195                             case 0x4:
  3196                                 { /* FNEG FRn */
  3197                                 uint32_t FRn = ((ir>>8)&0xF); 
  3198                                 check_fpuen();
  3199                                 load_spreg( R_ECX, R_FPSCR );
  3200                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3201                                 JNE_rel8(doubleprec);
  3202                                 push_fr(FRn);
  3203                                 FCHS_st0();
  3204                                 pop_fr(FRn);
  3205                                 JMP_rel8(end);
  3206                                 JMP_TARGET(doubleprec);
  3207                                 push_dr(FRn);
  3208                                 FCHS_st0();
  3209                                 pop_dr(FRn);
  3210                                 JMP_TARGET(end);
  3211                                 sh4_x86.tstate = TSTATE_NONE;
  3213                                 break;
  3214                             case 0x5:
  3215                                 { /* FABS FRn */
  3216                                 uint32_t FRn = ((ir>>8)&0xF); 
  3217                                 check_fpuen();
  3218                                 load_spreg( R_ECX, R_FPSCR );
  3219                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3220                                 JNE_rel8(doubleprec);
  3221                                 push_fr(FRn); // 6
  3222                                 FABS_st0(); // 2
  3223                                 pop_fr(FRn); //6
  3224                                 JMP_rel8(end); // 2
  3225                                 JMP_TARGET(doubleprec);
  3226                                 push_dr(FRn);
  3227                                 FABS_st0();
  3228                                 pop_dr(FRn);
  3229                                 JMP_TARGET(end);
  3230                                 sh4_x86.tstate = TSTATE_NONE;
  3232                                 break;
  3233                             case 0x6:
  3234                                 { /* FSQRT FRn */
  3235                                 uint32_t FRn = ((ir>>8)&0xF); 
  3236                                 check_fpuen();
  3237                                 load_spreg( R_ECX, R_FPSCR );
  3238                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3239                                 JNE_rel8(doubleprec);
  3240                                 push_fr(FRn);
  3241                                 FSQRT_st0();
  3242                                 pop_fr(FRn);
  3243                                 JMP_rel8(end);
  3244                                 JMP_TARGET(doubleprec);
  3245                                 push_dr(FRn);
  3246                                 FSQRT_st0();
  3247                                 pop_dr(FRn);
  3248                                 JMP_TARGET(end);
  3249                                 sh4_x86.tstate = TSTATE_NONE;
  3251                                 break;
  3252                             case 0x7:
  3253                                 { /* FSRRA FRn */
  3254                                 uint32_t FRn = ((ir>>8)&0xF); 
  3255                                 check_fpuen();
  3256                                 load_spreg( R_ECX, R_FPSCR );
  3257                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3258                                 JNE_rel8(end); // PR=0 only
  3259                                 FLD1_st0();
  3260                                 push_fr(FRn);
  3261                                 FSQRT_st0();
  3262                                 FDIVP_st(1);
  3263                                 pop_fr(FRn);
  3264                                 JMP_TARGET(end);
  3265                                 sh4_x86.tstate = TSTATE_NONE;
  3267                                 break;
  3268                             case 0x8:
  3269                                 { /* FLDI0 FRn */
  3270                                 uint32_t FRn = ((ir>>8)&0xF); 
  3271                                 /* IFF PR=0 */
  3272                                   check_fpuen();
  3273                                   load_spreg( R_ECX, R_FPSCR );
  3274                                   TEST_imm32_r32( FPSCR_PR, R_ECX );
  3275                                   JNE_rel8(end);
  3276                                   XOR_r32_r32( R_EAX, R_EAX );
  3277                                   store_fr( R_EAX, FRn );
  3278                                   JMP_TARGET(end);
  3279                                   sh4_x86.tstate = TSTATE_NONE;
  3281                                 break;
  3282                             case 0x9:
  3283                                 { /* FLDI1 FRn */
  3284                                 uint32_t FRn = ((ir>>8)&0xF); 
  3285                                 /* IFF PR=0 */
  3286                                   check_fpuen();
  3287                                   load_spreg( R_ECX, R_FPSCR );
  3288                                   TEST_imm32_r32( FPSCR_PR, R_ECX );
  3289                                   JNE_rel8(end);
  3290                                   load_imm32(R_EAX, 0x3F800000);
  3291                                   store_fr( R_EAX, FRn );
  3292                                   JMP_TARGET(end);
  3293                                   sh4_x86.tstate = TSTATE_NONE;
  3295                                 break;
  3296                             case 0xA:
  3297                                 { /* FCNVSD FPUL, FRn */
  3298                                 uint32_t FRn = ((ir>>8)&0xF); 
  3299                                 check_fpuen();
  3300                                 load_spreg( R_ECX, R_FPSCR );
  3301                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3302                                 JE_rel8(end); // only when PR=1
  3303                                 push_fpul();
  3304                                 pop_dr( FRn );
  3305                                 JMP_TARGET(end);
  3306                                 sh4_x86.tstate = TSTATE_NONE;
  3308                                 break;
  3309                             case 0xB:
  3310                                 { /* FCNVDS FRm, FPUL */
  3311                                 uint32_t FRm = ((ir>>8)&0xF); 
  3312                                 check_fpuen();
  3313                                 load_spreg( R_ECX, R_FPSCR );
  3314                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3315                                 JE_rel8(end); // only when PR=1
  3316                                 push_dr( FRm );
  3317                                 pop_fpul();
  3318                                 JMP_TARGET(end);
  3319                                 sh4_x86.tstate = TSTATE_NONE;
  3321                                 break;
  3322                             case 0xE:
  3323                                 { /* FIPR FVm, FVn */
  3324                                 uint32_t FVn = ((ir>>10)&0x3); uint32_t FVm = ((ir>>8)&0x3); 
  3325                                 check_fpuen();
  3326                                 load_spreg( R_ECX, R_FPSCR );
  3327                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3328                                 JNE_rel8( doubleprec);
  3330                                 push_fr( FVm<<2 );
  3331                                 push_fr( FVn<<2 );
  3332                                 FMULP_st(1);
  3333                                 push_fr( (FVm<<2)+1);
  3334                                 push_fr( (FVn<<2)+1);
  3335                                 FMULP_st(1);
  3336                                 FADDP_st(1);
  3337                                 push_fr( (FVm<<2)+2);
  3338                                 push_fr( (FVn<<2)+2);
  3339                                 FMULP_st(1);
  3340                                 FADDP_st(1);
  3341                                 push_fr( (FVm<<2)+3);
  3342                                 push_fr( (FVn<<2)+3);
  3343                                 FMULP_st(1);
  3344                                 FADDP_st(1);
  3345                                 pop_fr( (FVn<<2)+3);
  3346                                 JMP_TARGET(doubleprec);
  3347                                 sh4_x86.tstate = TSTATE_NONE;
  3349                                 break;
  3350                             case 0xF:
  3351                                 switch( (ir&0x100) >> 8 ) {
  3352                                     case 0x0:
  3353                                         { /* FSCA FPUL, FRn */
  3354                                         uint32_t FRn = ((ir>>9)&0x7)<<1; 
  3355                                         check_fpuen();
  3356                                         load_spreg( R_ECX, R_FPSCR );
  3357                                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  3358                                         JNE_rel8(doubleprec );
  3359                                         LEA_sh4r_r32( REG_OFFSET(fr[0][FRn&0x0E]), R_ECX );
  3360                                         load_spreg( R_EDX, R_FPUL );
  3361                                         call_func2( sh4_fsca, R_EDX, R_ECX );
  3362                                         JMP_TARGET(doubleprec);
  3363                                         sh4_x86.tstate = TSTATE_NONE;
  3365                                         break;
  3366                                     case 0x1:
  3367                                         switch( (ir&0x200) >> 9 ) {
  3368                                             case 0x0:
  3369                                                 { /* FTRV XMTRX, FVn */
  3370                                                 uint32_t FVn = ((ir>>10)&0x3); 
  3371                                                 check_fpuen();
  3372                                                 load_spreg( R_ECX, R_FPSCR );
  3373                                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3374                                                 JNE_rel8( doubleprec );
  3375                                                 LEA_sh4r_r32( REG_OFFSET(fr[0][FVn<<2]), R_EDX );
  3376                                                 call_func1( sh4_ftrv, R_EDX );  // 12
  3377                                                 JMP_TARGET(doubleprec);
  3378                                                 sh4_x86.tstate = TSTATE_NONE;
  3380                                                 break;
  3381                                             case 0x1:
  3382                                                 switch( (ir&0xC00) >> 10 ) {
  3383                                                     case 0x0:
  3384                                                         { /* FSCHG */
  3385                                                         check_fpuen();
  3386                                                         load_spreg( R_ECX, R_FPSCR );
  3387                                                         XOR_imm32_r32( FPSCR_SZ, R_ECX );
  3388                                                         store_spreg( R_ECX, R_FPSCR );
  3389                                                         sh4_x86.tstate = TSTATE_NONE;
  3391                                                         break;
  3392                                                     case 0x2:
  3393                                                         { /* FRCHG */
  3394                                                         check_fpuen();
  3395                                                         load_spreg( R_ECX, R_FPSCR );
  3396                                                         XOR_imm32_r32( FPSCR_FR, R_ECX );
  3397                                                         store_spreg( R_ECX, R_FPSCR );
  3398                                                         call_func0( sh4_switch_fr_banks );
  3399                                                         sh4_x86.tstate = TSTATE_NONE;
  3401                                                         break;
  3402                                                     case 0x3:
  3403                                                         { /* UNDEF */
  3404                                                         if( sh4_x86.in_delay_slot ) {
  3405                                                     	SLOTILLEGAL();
  3406                                                         } else {
  3407                                                     	JMP_exc(EXC_ILLEGAL);
  3408                                                     	return 2;
  3411                                                         break;
  3412                                                     default:
  3413                                                         UNDEF();
  3414                                                         break;
  3416                                                 break;
  3418                                         break;
  3420                                 break;
  3421                             default:
  3422                                 UNDEF();
  3423                                 break;
  3425                         break;
  3426                     case 0xE:
  3427                         { /* FMAC FR0, FRm, FRn */
  3428                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  3429                         check_fpuen();
  3430                         load_spreg( R_ECX, R_FPSCR );
  3431                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  3432                         JNE_rel8(doubleprec);
  3433                         push_fr( 0 );
  3434                         push_fr( FRm );
  3435                         FMULP_st(1);
  3436                         push_fr( FRn );
  3437                         FADDP_st(1);
  3438                         pop_fr( FRn );
  3439                         JMP_rel8(end);
  3440                         JMP_TARGET(doubleprec);
  3441                         push_dr( 0 );
  3442                         push_dr( FRm );
  3443                         FMULP_st(1);
  3444                         push_dr( FRn );
  3445                         FADDP_st(1);
  3446                         pop_dr( FRn );
  3447                         JMP_TARGET(end);
  3448                         sh4_x86.tstate = TSTATE_NONE;
  3450                         break;
  3451                     default:
  3452                         UNDEF();
  3453                         break;
  3455                 break;
  3458     sh4_x86.in_delay_slot = DELAY_NONE;
  3459     return 0;
.