Search
lxdream.org :: lxdream/src/sh4/sh4x86.c
lxdream 0.9.1
released Jun 29
Download Now
filename src/sh4/sh4x86.c
changeset 408:af496b734734
prev401:f79327f39818
next409:549e00835448
author nkeynes
date Fri Sep 28 07:27:20 2007 +0000 (14 years ago)
permissions -rw-r--r--
last change Change block signature to return pointer to next block (if known)
Rewrite block-exit code
view annotate diff log raw
     1 /**
     2  * $Id: sh4x86.c,v 1.15 2007-09-28 07:27:20 nkeynes Exp $
     3  * 
     4  * SH4 => x86 translation. This version does no real optimization, it just
     5  * outputs straight-line x86 code - it mainly exists to provide a baseline
     6  * to test the optimizing versions against.
     7  *
     8  * Copyright (c) 2007 Nathan Keynes.
     9  *
    10  * This program is free software; you can redistribute it and/or modify
    11  * it under the terms of the GNU General Public License as published by
    12  * the Free Software Foundation; either version 2 of the License, or
    13  * (at your option) any later version.
    14  *
    15  * This program is distributed in the hope that it will be useful,
    16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    18  * GNU General Public License for more details.
    19  */
    21 #include <assert.h>
    22 #include <math.h>
    24 #ifndef NDEBUG
    25 #define DEBUG_JUMPS 1
    26 #endif
    28 #include "sh4/sh4core.h"
    29 #include "sh4/sh4trans.h"
    30 #include "sh4/sh4mmio.h"
    31 #include "sh4/x86op.h"
    32 #include "clock.h"
    34 #define DEFAULT_BACKPATCH_SIZE 4096
    36 /** 
    37  * Struct to manage internal translation state. This state is not saved -
    38  * it is only valid between calls to sh4_translate_begin_block() and
    39  * sh4_translate_end_block()
    40  */
    41 struct sh4_x86_state {
    42     gboolean in_delay_slot;
    43     gboolean priv_checked; /* true if we've already checked the cpu mode. */
    44     gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
    45     uint32_t block_start_pc;
    47     /* Allocated memory for the (block-wide) back-patch list */
    48     uint32_t **backpatch_list;
    49     uint32_t backpatch_posn;
    50     uint32_t backpatch_size;
    51 };
    53 #define EXIT_DATA_ADDR_READ 0
    54 #define EXIT_DATA_ADDR_WRITE 7
    55 #define EXIT_ILLEGAL 14
    56 #define EXIT_SLOT_ILLEGAL 21
    57 #define EXIT_FPU_DISABLED 28
    58 #define EXIT_SLOT_FPU_DISABLED 35
    60 static struct sh4_x86_state sh4_x86;
    62 static uint32_t max_int = 0x7FFFFFFF;
    63 static uint32_t min_int = 0x80000000;
    64 static uint32_t save_fcw; /* save value for fpu control word */
    65 static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
    67 void sh4_x86_init()
    68 {
    69     sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
    70     sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(uint32_t *);
    71 }
    74 static void sh4_x86_add_backpatch( uint8_t *ptr )
    75 {
    76     if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
    77 	sh4_x86.backpatch_size <<= 1;
    78 	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, sh4_x86.backpatch_size * sizeof(uint32_t *) );
    79 	assert( sh4_x86.backpatch_list != NULL );
    80     }
    81     sh4_x86.backpatch_list[sh4_x86.backpatch_posn++] = (uint32_t *)ptr;
    82 }
    84 static void sh4_x86_do_backpatch( uint8_t *reloc_base )
    85 {
    86     unsigned int i;
    87     for( i=0; i<sh4_x86.backpatch_posn; i++ ) {
    88 	*sh4_x86.backpatch_list[i] += (reloc_base - ((uint8_t *)sh4_x86.backpatch_list[i]) - 4);
    89     }
    90 }
    92 /**
    93  * Emit an instruction to load an SH4 reg into a real register
    94  */
    95 static inline void load_reg( int x86reg, int sh4reg ) 
    96 {
    97     /* mov [bp+n], reg */
    98     OP(0x8B);
    99     OP(0x45 + (x86reg<<3));
   100     OP(REG_OFFSET(r[sh4reg]));
   101 }
   103 static inline void load_reg16s( int x86reg, int sh4reg )
   104 {
   105     OP(0x0F);
   106     OP(0xBF);
   107     MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
   108 }
   110 static inline void load_reg16u( int x86reg, int sh4reg )
   111 {
   112     OP(0x0F);
   113     OP(0xB7);
   114     MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
   116 }
   118 #define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
   119 #define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
   120 /**
   121  * Emit an instruction to load an immediate value into a register
   122  */
   123 static inline void load_imm32( int x86reg, uint32_t value ) {
   124     /* mov #value, reg */
   125     OP(0xB8 + x86reg);
   126     OP32(value);
   127 }
   129 /**
   130  * Emit an instruction to store an SH4 reg (RN)
   131  */
   132 void static inline store_reg( int x86reg, int sh4reg ) {
   133     /* mov reg, [bp+n] */
   134     OP(0x89);
   135     OP(0x45 + (x86reg<<3));
   136     OP(REG_OFFSET(r[sh4reg]));
   137 }
   139 #define load_fr_bank(bankreg) load_spreg( bankreg, REG_OFFSET(fr_bank))
   141 /**
   142  * Load an FR register (single-precision floating point) into an integer x86
   143  * register (eg for register-to-register moves)
   144  */
   145 void static inline load_fr( int bankreg, int x86reg, int frm )
   146 {
   147     OP(0x8B); OP(0x40+bankreg+(x86reg<<3)); OP((frm^1)<<2);
   148 }
   150 /**
   151  * Store an FR register (single-precision floating point) into an integer x86
   152  * register (eg for register-to-register moves)
   153  */
   154 void static inline store_fr( int bankreg, int x86reg, int frn )
   155 {
   156     OP(0x89);  OP(0x40+bankreg+(x86reg<<3)); OP((frn^1)<<2);
   157 }
   160 /**
   161  * Load a pointer to the back fp back into the specified x86 register. The
   162  * bankreg must have been previously loaded with FPSCR.
   163  * NB: 12 bytes
   164  */
   165 static inline void load_xf_bank( int bankreg )
   166 {
   167     NOT_r32( bankreg );
   168     SHR_imm8_r32( (21 - 6), bankreg ); // Extract bit 21 then *64 for bank size
   169     AND_imm8s_r32( 0x40, bankreg );    // Complete extraction
   170     OP(0x8D); OP(0x44+(bankreg<<3)); OP(0x28+bankreg); OP(REG_OFFSET(fr)); // LEA [ebp+bankreg+disp], bankreg
   171 }
   173 /**
   174  * Update the fr_bank pointer based on the current fpscr value.
   175  */
   176 static inline void update_fr_bank( int fpscrreg )
   177 {
   178     SHR_imm8_r32( (21 - 6), fpscrreg ); // Extract bit 21 then *64 for bank size
   179     AND_imm8s_r32( 0x40, fpscrreg );    // Complete extraction
   180     OP(0x8D); OP(0x44+(fpscrreg<<3)); OP(0x28+fpscrreg); OP(REG_OFFSET(fr)); // LEA [ebp+fpscrreg+disp], fpscrreg
   181     store_spreg( fpscrreg, REG_OFFSET(fr_bank) );
   182 }
   183 /**
   184  * Push FPUL (as a 32-bit float) onto the FPU stack
   185  */
   186 static inline void push_fpul( )
   187 {
   188     OP(0xD9); OP(0x45); OP(R_FPUL);
   189 }
   191 /**
   192  * Pop FPUL (as a 32-bit float) from the FPU stack
   193  */
   194 static inline void pop_fpul( )
   195 {
   196     OP(0xD9); OP(0x5D); OP(R_FPUL);
   197 }
   199 /**
   200  * Push a 32-bit float onto the FPU stack, with bankreg previously loaded
   201  * with the location of the current fp bank.
   202  */
   203 static inline void push_fr( int bankreg, int frm ) 
   204 {
   205     OP(0xD9); OP(0x40 + bankreg); OP((frm^1)<<2);  // FLD.S [bankreg + frm^1*4]
   206 }
   208 /**
   209  * Pop a 32-bit float from the FPU stack and store it back into the fp bank, 
   210  * with bankreg previously loaded with the location of the current fp bank.
   211  */
   212 static inline void pop_fr( int bankreg, int frm )
   213 {
   214     OP(0xD9); OP(0x58 + bankreg); OP((frm^1)<<2); // FST.S [bankreg + frm^1*4]
   215 }
   217 /**
   218  * Push a 64-bit double onto the FPU stack, with bankreg previously loaded
   219  * with the location of the current fp bank.
   220  */
   221 static inline void push_dr( int bankreg, int frm )
   222 {
   223     OP(0xDD); OP(0x40 + bankreg); OP(frm<<2); // FLD.D [bankreg + frm*4]
   224 }
   226 static inline void pop_dr( int bankreg, int frm )
   227 {
   228     OP(0xDD); OP(0x58 + bankreg); OP(frm<<2); // FST.D [bankreg + frm*4]
   229 }
   231 /**
   232  * Note: clobbers EAX to make the indirect call - this isn't usually
   233  * a problem since the callee will usually clobber it anyway.
   234  */
   235 static inline void call_func0( void *ptr )
   236 {
   237     load_imm32(R_EAX, (uint32_t)ptr);
   238     CALL_r32(R_EAX);
   239 }
   241 static inline void call_func1( void *ptr, int arg1 )
   242 {
   243     PUSH_r32(arg1);
   244     call_func0(ptr);
   245     ADD_imm8s_r32( 4, R_ESP );
   246 }
   248 static inline void call_func2( void *ptr, int arg1, int arg2 )
   249 {
   250     PUSH_r32(arg2);
   251     PUSH_r32(arg1);
   252     call_func0(ptr);
   253     ADD_imm8s_r32( 8, R_ESP );
   254 }
   256 /**
   257  * Write a double (64-bit) value into memory, with the first word in arg2a, and
   258  * the second in arg2b
   259  * NB: 30 bytes
   260  */
   261 static inline void MEM_WRITE_DOUBLE( int addr, int arg2a, int arg2b )
   262 {
   263     ADD_imm8s_r32( 4, addr );
   264     PUSH_r32(arg2b);
   265     PUSH_r32(addr);
   266     ADD_imm8s_r32( -4, addr );
   267     PUSH_r32(arg2a);
   268     PUSH_r32(addr);
   269     call_func0(sh4_write_long);
   270     ADD_imm8s_r32( 8, R_ESP );
   271     call_func0(sh4_write_long);
   272     ADD_imm8s_r32( 8, R_ESP );
   273 }
   275 /**
   276  * Read a double (64-bit) value from memory, writing the first word into arg2a
   277  * and the second into arg2b. The addr must not be in EAX
   278  * NB: 27 bytes
   279  */
   280 static inline void MEM_READ_DOUBLE( int addr, int arg2a, int arg2b )
   281 {
   282     PUSH_r32(addr);
   283     call_func0(sh4_read_long);
   284     POP_r32(addr);
   285     PUSH_r32(R_EAX);
   286     ADD_imm8s_r32( 4, addr );
   287     PUSH_r32(addr);
   288     call_func0(sh4_read_long);
   289     ADD_imm8s_r32( 4, R_ESP );
   290     MOV_r32_r32( R_EAX, arg2b );
   291     POP_r32(arg2a);
   292 }
   294 /* Exception checks - Note that all exception checks will clobber EAX */
   295 static void check_priv( )
   296 {
   297     if( !sh4_x86.priv_checked ) {
   298 	sh4_x86.priv_checked = TRUE;
   299 	load_spreg( R_EAX, R_SR );
   300 	AND_imm32_r32( SR_MD, R_EAX );
   301 	if( sh4_x86.in_delay_slot ) {
   302 	    JE_exit( EXIT_SLOT_ILLEGAL );
   303 	} else {
   304 	    JE_exit( EXIT_ILLEGAL );
   305 	}
   306     }
   307 }
   309 static void check_fpuen( )
   310 {
   311     if( !sh4_x86.fpuen_checked ) {
   312 	sh4_x86.fpuen_checked = TRUE;
   313 	load_spreg( R_EAX, R_SR );
   314 	AND_imm32_r32( SR_FD, R_EAX );
   315 	if( sh4_x86.in_delay_slot ) {
   316 	    JNE_exit(EXIT_SLOT_FPU_DISABLED);
   317 	} else {
   318 	    JNE_exit(EXIT_FPU_DISABLED);
   319 	}
   320     }
   321 }
   323 static void check_ralign16( int x86reg )
   324 {
   325     TEST_imm32_r32( 0x00000001, x86reg );
   326     JNE_exit(EXIT_DATA_ADDR_READ);
   327 }
   329 static void check_walign16( int x86reg )
   330 {
   331     TEST_imm32_r32( 0x00000001, x86reg );
   332     JNE_exit(EXIT_DATA_ADDR_WRITE);
   333 }
   335 static void check_ralign32( int x86reg )
   336 {
   337     TEST_imm32_r32( 0x00000003, x86reg );
   338     JNE_exit(EXIT_DATA_ADDR_READ);
   339 }
   340 static void check_walign32( int x86reg )
   341 {
   342     TEST_imm32_r32( 0x00000003, x86reg );
   343     JNE_exit(EXIT_DATA_ADDR_WRITE);
   344 }
   346 #define UNDEF()
   347 #define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
   348 #define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
   349 #define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
   350 #define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
   351 #define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
   352 #define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
   353 #define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
   355 #define SLOTILLEGAL() JMP_exit(EXIT_SLOT_ILLEGAL); sh4_x86.in_delay_slot = FALSE; return 1;
   359 /**
   360  * Emit the 'start of block' assembly. Sets up the stack frame and save
   361  * SI/DI as required
   362  */
   363 void sh4_translate_begin_block( sh4addr_t pc ) 
   364 {
   365     PUSH_r32(R_EBP);
   366     /* mov &sh4r, ebp */
   367     load_imm32( R_EBP, (uint32_t)&sh4r );
   368     PUSH_r32(R_ESI);
   369     XOR_r32_r32(R_ESI, R_ESI);
   371     sh4_x86.in_delay_slot = FALSE;
   372     sh4_x86.priv_checked = FALSE;
   373     sh4_x86.fpuen_checked = FALSE;
   374     sh4_x86.backpatch_posn = 0;
   375     sh4_x86.block_start_pc = pc;
   376 }
   378 /**
   379  * Exit the block to an absolute PC
   380  * Bytes: 30
   381  */
   382 void exit_block( sh4addr_t pc, sh4addr_t endpc )
   383 {
   384     load_imm32( R_ECX, pc );                            // 5
   385     store_spreg( R_ECX, REG_OFFSET(pc) );               // 3
   386     MOV_moff32_EAX( (uint32_t)xlat_get_lut_entry(pc) ); // 5
   387     AND_imm8s_r32( 0xFC, R_EAX ); // 3
   388     load_imm32( R_ECX, ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
   389     ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );     // 6
   390     POP_r32(R_ESI);
   391     POP_r32(R_EBP);
   392     RET();
   393 }
   395 /**
   396  * Exit the block with sh4r.pc already written
   397  * Bytes: 16
   398  */
   399 void exit_block_pcset( pc )
   400 {
   401     XOR_r32_r32( R_EAX, R_EAX );                       // 2
   402     load_imm32( R_ECX, ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
   403     ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );    // 6
   404     POP_r32(R_ESI);
   405     POP_r32(R_EBP);
   406     RET();
   407 }
   409 /**
   410  * Write the block trailer (exception handling block)
   411  */
   412 void sh4_translate_end_block( sh4addr_t pc ) {
   413     if( sh4_x86.backpatch_posn != 0 ) {
   414 	uint8_t *end_ptr = xlat_output;
   415 	// Exception termination. Jump block for various exception codes:
   416 	PUSH_imm32( EXC_DATA_ADDR_READ );
   417 	JMP_rel8( 33, target1 );
   418 	PUSH_imm32( EXC_DATA_ADDR_WRITE );
   419 	JMP_rel8( 26, target2 );
   420 	PUSH_imm32( EXC_ILLEGAL );
   421 	JMP_rel8( 19, target3 );
   422 	PUSH_imm32( EXC_SLOT_ILLEGAL ); 
   423 	JMP_rel8( 12, target4 );
   424 	PUSH_imm32( EXC_FPU_DISABLED ); 
   425 	JMP_rel8( 5, target5 );
   426 	PUSH_imm32( EXC_SLOT_FPU_DISABLED );
   427 	// target
   428 	JMP_TARGET(target1);
   429 	JMP_TARGET(target2);
   430 	JMP_TARGET(target3);
   431 	JMP_TARGET(target4);
   432 	JMP_TARGET(target5);
   433 	load_spreg( R_ECX, REG_OFFSET(pc) );
   434 	ADD_r32_r32( R_ESI, R_ECX );
   435 	ADD_r32_r32( R_ESI, R_ECX );
   436 	store_spreg( R_ECX, REG_OFFSET(pc) );
   437 	MOV_moff32_EAX( (uint32_t)&sh4_cpu_period );
   438 	load_spreg( R_ECX, REG_OFFSET(slice_cycle) );
   439 	MUL_r32( R_ESI );
   440 	ADD_r32_r32( R_EAX, R_ECX );
   441 	store_spreg( R_ECX, REG_OFFSET(slice_cycle) );
   443 	load_imm32( R_EAX, (uint32_t)sh4_raise_exception ); // 6
   444 	CALL_r32( R_EAX ); // 2
   445 	ADD_imm8s_r32( 4, R_ESP );
   446 	XOR_r32_r32( R_EAX, R_EAX );
   447 	POP_r32(R_ESI);
   448 	POP_r32(R_EBP);
   449 	RET();
   451 	sh4_x86_do_backpatch( end_ptr );
   452     }
   454 }
   457 extern uint16_t *sh4_icache;
   458 extern uint32_t sh4_icache_addr;
   460 /**
   461  * Translate a single instruction. Delayed branches are handled specially
   462  * by translating both branch and delayed instruction as a single unit (as
   463  * 
   464  *
   465  * @return true if the instruction marks the end of a basic block
   466  * (eg a branch or 
   467  */
   468 uint32_t sh4_x86_translate_instruction( sh4addr_t pc )
   469 {
   470     uint32_t ir;
   471     /* Read instruction */
   472     uint32_t pageaddr = pc >> 12;
   473     if( sh4_icache != NULL && pageaddr == sh4_icache_addr ) {
   474 	ir = sh4_icache[(pc&0xFFF)>>1];
   475     } else {
   476 	sh4_icache = (uint16_t *)mem_get_page(pc);
   477 	if( ((uint32_t)sh4_icache) < MAX_IO_REGIONS ) {
   478 	    /* If someone's actually been so daft as to try to execute out of an IO
   479 	     * region, fallback on the full-blown memory read
   480 	     */
   481 	    sh4_icache = NULL;
   482 	    ir = sh4_read_word(pc);
   483 	} else {
   484 	    sh4_icache_addr = pageaddr;
   485 	    ir = sh4_icache[(pc&0xFFF)>>1];
   486 	}
   487     }
   489         switch( (ir&0xF000) >> 12 ) {
   490             case 0x0:
   491                 switch( ir&0xF ) {
   492                     case 0x2:
   493                         switch( (ir&0x80) >> 7 ) {
   494                             case 0x0:
   495                                 switch( (ir&0x70) >> 4 ) {
   496                                     case 0x0:
   497                                         { /* STC SR, Rn */
   498                                         uint32_t Rn = ((ir>>8)&0xF); 
   499                                         check_priv();
   500                                         call_func0(sh4_read_sr);
   501                                         store_reg( R_EAX, Rn );
   502                                         }
   503                                         break;
   504                                     case 0x1:
   505                                         { /* STC GBR, Rn */
   506                                         uint32_t Rn = ((ir>>8)&0xF); 
   507                                         load_spreg( R_EAX, R_GBR );
   508                                         store_reg( R_EAX, Rn );
   509                                         }
   510                                         break;
   511                                     case 0x2:
   512                                         { /* STC VBR, Rn */
   513                                         uint32_t Rn = ((ir>>8)&0xF); 
   514                                         check_priv();
   515                                         load_spreg( R_EAX, R_VBR );
   516                                         store_reg( R_EAX, Rn );
   517                                         }
   518                                         break;
   519                                     case 0x3:
   520                                         { /* STC SSR, Rn */
   521                                         uint32_t Rn = ((ir>>8)&0xF); 
   522                                         check_priv();
   523                                         load_spreg( R_EAX, R_SSR );
   524                                         store_reg( R_EAX, Rn );
   525                                         }
   526                                         break;
   527                                     case 0x4:
   528                                         { /* STC SPC, Rn */
   529                                         uint32_t Rn = ((ir>>8)&0xF); 
   530                                         check_priv();
   531                                         load_spreg( R_EAX, R_SPC );
   532                                         store_reg( R_EAX, Rn );
   533                                         }
   534                                         break;
   535                                     default:
   536                                         UNDEF();
   537                                         break;
   538                                 }
   539                                 break;
   540                             case 0x1:
   541                                 { /* STC Rm_BANK, Rn */
   542                                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
   543                                 check_priv();
   544                                 load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
   545                                 store_reg( R_EAX, Rn );
   546                                 }
   547                                 break;
   548                         }
   549                         break;
   550                     case 0x3:
   551                         switch( (ir&0xF0) >> 4 ) {
   552                             case 0x0:
   553                                 { /* BSRF Rn */
   554                                 uint32_t Rn = ((ir>>8)&0xF); 
   555                                 if( sh4_x86.in_delay_slot ) {
   556                             	SLOTILLEGAL();
   557                                 } else {
   558                             	load_imm32( R_ECX, pc + 4 );
   559                             	store_spreg( R_ECX, R_PR );
   560                             	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_ECX );
   561                             	store_spreg( R_ECX, REG_OFFSET(pc) );
   562                             	sh4_x86.in_delay_slot = TRUE;
   563                             	sh4_x86_translate_instruction( pc + 2 );
   564                             	exit_block_pcset(pc+2);
   565                             	return 4;
   566                                 }
   567                                 }
   568                                 break;
   569                             case 0x2:
   570                                 { /* BRAF Rn */
   571                                 uint32_t Rn = ((ir>>8)&0xF); 
   572                                 if( sh4_x86.in_delay_slot ) {
   573                             	SLOTILLEGAL();
   574                                 } else {
   575                             	load_reg( R_EAX, Rn );
   576                             	ADD_imm32_r32( pc + 4, R_EAX );
   577                             	store_spreg( R_EAX, REG_OFFSET(pc) );
   578                             	sh4_x86.in_delay_slot = TRUE;
   579                             	sh4_x86_translate_instruction( pc + 2 );
   580                             	exit_block_pcset(pc+2);
   581                             	return 4;
   582                                 }
   583                                 }
   584                                 break;
   585                             case 0x8:
   586                                 { /* PREF @Rn */
   587                                 uint32_t Rn = ((ir>>8)&0xF); 
   588                                 load_reg( R_EAX, Rn );
   589                                 PUSH_r32( R_EAX );
   590                                 AND_imm32_r32( 0xFC000000, R_EAX );
   591                                 CMP_imm32_r32( 0xE0000000, R_EAX );
   592                                 JNE_rel8(7, end);
   593                                 call_func0( sh4_flush_store_queue );
   594                                 JMP_TARGET(end);
   595                                 ADD_imm8s_r32( 4, R_ESP );
   596                                 }
   597                                 break;
   598                             case 0x9:
   599                                 { /* OCBI @Rn */
   600                                 uint32_t Rn = ((ir>>8)&0xF); 
   601                                 }
   602                                 break;
   603                             case 0xA:
   604                                 { /* OCBP @Rn */
   605                                 uint32_t Rn = ((ir>>8)&0xF); 
   606                                 }
   607                                 break;
   608                             case 0xB:
   609                                 { /* OCBWB @Rn */
   610                                 uint32_t Rn = ((ir>>8)&0xF); 
   611                                 }
   612                                 break;
   613                             case 0xC:
   614                                 { /* MOVCA.L R0, @Rn */
   615                                 uint32_t Rn = ((ir>>8)&0xF); 
   616                                 load_reg( R_EAX, 0 );
   617                                 load_reg( R_ECX, Rn );
   618                                 check_walign32( R_ECX );
   619                                 MEM_WRITE_LONG( R_ECX, R_EAX );
   620                                 }
   621                                 break;
   622                             default:
   623                                 UNDEF();
   624                                 break;
   625                         }
   626                         break;
   627                     case 0x4:
   628                         { /* MOV.B Rm, @(R0, Rn) */
   629                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   630                         load_reg( R_EAX, 0 );
   631                         load_reg( R_ECX, Rn );
   632                         ADD_r32_r32( R_EAX, R_ECX );
   633                         load_reg( R_EAX, Rm );
   634                         MEM_WRITE_BYTE( R_ECX, R_EAX );
   635                         }
   636                         break;
   637                     case 0x5:
   638                         { /* MOV.W Rm, @(R0, Rn) */
   639                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   640                         load_reg( R_EAX, 0 );
   641                         load_reg( R_ECX, Rn );
   642                         ADD_r32_r32( R_EAX, R_ECX );
   643                         check_walign16( R_ECX );
   644                         load_reg( R_EAX, Rm );
   645                         MEM_WRITE_WORD( R_ECX, R_EAX );
   646                         }
   647                         break;
   648                     case 0x6:
   649                         { /* MOV.L Rm, @(R0, Rn) */
   650                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   651                         load_reg( R_EAX, 0 );
   652                         load_reg( R_ECX, Rn );
   653                         ADD_r32_r32( R_EAX, R_ECX );
   654                         check_walign32( R_ECX );
   655                         load_reg( R_EAX, Rm );
   656                         MEM_WRITE_LONG( R_ECX, R_EAX );
   657                         }
   658                         break;
   659                     case 0x7:
   660                         { /* MUL.L Rm, Rn */
   661                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   662                         load_reg( R_EAX, Rm );
   663                         load_reg( R_ECX, Rn );
   664                         MUL_r32( R_ECX );
   665                         store_spreg( R_EAX, R_MACL );
   666                         }
   667                         break;
   668                     case 0x8:
   669                         switch( (ir&0xFF0) >> 4 ) {
   670                             case 0x0:
   671                                 { /* CLRT */
   672                                 CLC();
   673                                 SETC_t();
   674                                 }
   675                                 break;
   676                             case 0x1:
   677                                 { /* SETT */
   678                                 STC();
   679                                 SETC_t();
   680                                 }
   681                                 break;
   682                             case 0x2:
   683                                 { /* CLRMAC */
   684                                 XOR_r32_r32(R_EAX, R_EAX);
   685                                 store_spreg( R_EAX, R_MACL );
   686                                 store_spreg( R_EAX, R_MACH );
   687                                 }
   688                                 break;
   689                             case 0x3:
   690                                 { /* LDTLB */
   691                                 }
   692                                 break;
   693                             case 0x4:
   694                                 { /* CLRS */
   695                                 CLC();
   696                                 SETC_sh4r(R_S);
   697                                 }
   698                                 break;
   699                             case 0x5:
   700                                 { /* SETS */
   701                                 STC();
   702                                 SETC_sh4r(R_S);
   703                                 }
   704                                 break;
   705                             default:
   706                                 UNDEF();
   707                                 break;
   708                         }
   709                         break;
   710                     case 0x9:
   711                         switch( (ir&0xF0) >> 4 ) {
   712                             case 0x0:
   713                                 { /* NOP */
   714                                 /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */
   715                                 }
   716                                 break;
   717                             case 0x1:
   718                                 { /* DIV0U */
   719                                 XOR_r32_r32( R_EAX, R_EAX );
   720                                 store_spreg( R_EAX, R_Q );
   721                                 store_spreg( R_EAX, R_M );
   722                                 store_spreg( R_EAX, R_T );
   723                                 }
   724                                 break;
   725                             case 0x2:
   726                                 { /* MOVT Rn */
   727                                 uint32_t Rn = ((ir>>8)&0xF); 
   728                                 load_spreg( R_EAX, R_T );
   729                                 store_reg( R_EAX, Rn );
   730                                 }
   731                                 break;
   732                             default:
   733                                 UNDEF();
   734                                 break;
   735                         }
   736                         break;
   737                     case 0xA:
   738                         switch( (ir&0xF0) >> 4 ) {
   739                             case 0x0:
   740                                 { /* STS MACH, Rn */
   741                                 uint32_t Rn = ((ir>>8)&0xF); 
   742                                 load_spreg( R_EAX, R_MACH );
   743                                 store_reg( R_EAX, Rn );
   744                                 }
   745                                 break;
   746                             case 0x1:
   747                                 { /* STS MACL, Rn */
   748                                 uint32_t Rn = ((ir>>8)&0xF); 
   749                                 load_spreg( R_EAX, R_MACL );
   750                                 store_reg( R_EAX, Rn );
   751                                 }
   752                                 break;
   753                             case 0x2:
   754                                 { /* STS PR, Rn */
   755                                 uint32_t Rn = ((ir>>8)&0xF); 
   756                                 load_spreg( R_EAX, R_PR );
   757                                 store_reg( R_EAX, Rn );
   758                                 }
   759                                 break;
   760                             case 0x3:
   761                                 { /* STC SGR, Rn */
   762                                 uint32_t Rn = ((ir>>8)&0xF); 
   763                                 check_priv();
   764                                 load_spreg( R_EAX, R_SGR );
   765                                 store_reg( R_EAX, Rn );
   766                                 }
   767                                 break;
   768                             case 0x5:
   769                                 { /* STS FPUL, Rn */
   770                                 uint32_t Rn = ((ir>>8)&0xF); 
   771                                 load_spreg( R_EAX, R_FPUL );
   772                                 store_reg( R_EAX, Rn );
   773                                 }
   774                                 break;
   775                             case 0x6:
   776                                 { /* STS FPSCR, Rn */
   777                                 uint32_t Rn = ((ir>>8)&0xF); 
   778                                 load_spreg( R_EAX, R_FPSCR );
   779                                 store_reg( R_EAX, Rn );
   780                                 }
   781                                 break;
   782                             case 0xF:
   783                                 { /* STC DBR, Rn */
   784                                 uint32_t Rn = ((ir>>8)&0xF); 
   785                                 check_priv();
   786                                 load_spreg( R_EAX, R_DBR );
   787                                 store_reg( R_EAX, Rn );
   788                                 }
   789                                 break;
   790                             default:
   791                                 UNDEF();
   792                                 break;
   793                         }
   794                         break;
   795                     case 0xB:
   796                         switch( (ir&0xFF0) >> 4 ) {
   797                             case 0x0:
   798                                 { /* RTS */
   799                                 if( sh4_x86.in_delay_slot ) {
   800                             	SLOTILLEGAL();
   801                                 } else {
   802                             	load_spreg( R_ECX, R_PR );
   803                             	store_spreg( R_ECX, REG_OFFSET(pc) );
   804                             	sh4_x86.in_delay_slot = TRUE;
   805                             	sh4_x86_translate_instruction(pc+2);
   806                             	exit_block_pcset(pc+2);
   807                             	return 4;
   808                                 }
   809                                 }
   810                                 break;
   811                             case 0x1:
   812                                 { /* SLEEP */
   813                                 check_priv();
   814                                 call_func0( sh4_sleep );
   815                                 sh4_x86.in_delay_slot = FALSE;
   816                                 INC_r32(R_ESI);
   817                                 exit_block(pc+2, pc+2);
   818                                 return 2;
   819                                 }
   820                                 break;
   821                             case 0x2:
   822                                 { /* RTE */
   823                                 if( sh4_x86.in_delay_slot ) {
   824                             	SLOTILLEGAL();
   825                                 } else {
   826                             	check_priv();
   827                             	load_spreg( R_ECX, R_SPC );
   828                             	store_spreg( R_ECX, REG_OFFSET(pc) );
   829                             	load_spreg( R_EAX, R_SSR );
   830                             	call_func1( sh4_write_sr, R_EAX );
   831                             	sh4_x86.in_delay_slot = TRUE;
   832                             	sh4_x86.priv_checked = FALSE;
   833                             	sh4_x86.fpuen_checked = FALSE;
   834                             	sh4_x86_translate_instruction(pc+2);
   835                             	exit_block_pcset(pc+2);
   836                             	return 4;
   837                                 }
   838                                 }
   839                                 break;
   840                             default:
   841                                 UNDEF();
   842                                 break;
   843                         }
   844                         break;
   845                     case 0xC:
   846                         { /* MOV.B @(R0, Rm), Rn */
   847                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   848                         load_reg( R_EAX, 0 );
   849                         load_reg( R_ECX, Rm );
   850                         ADD_r32_r32( R_EAX, R_ECX );
   851                         MEM_READ_BYTE( R_ECX, R_EAX );
   852                         store_reg( R_EAX, Rn );
   853                         }
   854                         break;
   855                     case 0xD:
   856                         { /* MOV.W @(R0, Rm), Rn */
   857                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   858                         load_reg( R_EAX, 0 );
   859                         load_reg( R_ECX, Rm );
   860                         ADD_r32_r32( R_EAX, R_ECX );
   861                         check_ralign16( R_ECX );
   862                         MEM_READ_WORD( R_ECX, R_EAX );
   863                         store_reg( R_EAX, Rn );
   864                         }
   865                         break;
   866                     case 0xE:
   867                         { /* MOV.L @(R0, Rm), Rn */
   868                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   869                         load_reg( R_EAX, 0 );
   870                         load_reg( R_ECX, Rm );
   871                         ADD_r32_r32( R_EAX, R_ECX );
   872                         check_ralign32( R_ECX );
   873                         MEM_READ_LONG( R_ECX, R_EAX );
   874                         store_reg( R_EAX, Rn );
   875                         }
   876                         break;
   877                     case 0xF:
   878                         { /* MAC.L @Rm+, @Rn+ */
   879                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   880                         load_reg( R_ECX, Rm );
   881                         check_ralign32( R_ECX );
   882                         load_reg( R_ECX, Rn );
   883                         check_ralign32( R_ECX );
   884                         ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
   885                         MEM_READ_LONG( R_ECX, R_EAX );
   886                         PUSH_r32( R_EAX );
   887                         load_reg( R_ECX, Rm );
   888                         ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
   889                         MEM_READ_LONG( R_ECX, R_EAX );
   890                         POP_r32( R_ECX );
   891                         IMUL_r32( R_ECX );
   892                         ADD_r32_sh4r( R_EAX, R_MACL );
   893                         ADC_r32_sh4r( R_EDX, R_MACH );
   895                         load_spreg( R_ECX, R_S );
   896                         TEST_r32_r32(R_ECX, R_ECX);
   897                         JE_rel8( 7, nosat );
   898                         call_func0( signsat48 );
   899                         JMP_TARGET( nosat );
   900                         }
   901                         break;
   902                     default:
   903                         UNDEF();
   904                         break;
   905                 }
   906                 break;
   907             case 0x1:
   908                 { /* MOV.L Rm, @(disp, Rn) */
   909                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
   910                 load_reg( R_ECX, Rn );
   911                 load_reg( R_EAX, Rm );
   912                 ADD_imm32_r32( disp, R_ECX );
   913                 check_walign32( R_ECX );
   914                 MEM_WRITE_LONG( R_ECX, R_EAX );
   915                 }
   916                 break;
   917             case 0x2:
   918                 switch( ir&0xF ) {
   919                     case 0x0:
   920                         { /* MOV.B Rm, @Rn */
   921                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   922                         load_reg( R_EAX, Rm );
   923                         load_reg( R_ECX, Rn );
   924                         MEM_WRITE_BYTE( R_ECX, R_EAX );
   925                         }
   926                         break;
   927                     case 0x1:
   928                         { /* MOV.W Rm, @Rn */
   929                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   930                         load_reg( R_ECX, Rn );
   931                         check_walign16( R_ECX );
   932                         load_reg( R_EAX, Rm );
   933                         MEM_WRITE_WORD( R_ECX, R_EAX );
   934                         }
   935                         break;
   936                     case 0x2:
   937                         { /* MOV.L Rm, @Rn */
   938                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   939                         load_reg( R_EAX, Rm );
   940                         load_reg( R_ECX, Rn );
   941                         check_walign32(R_ECX);
   942                         MEM_WRITE_LONG( R_ECX, R_EAX );
   943                         }
   944                         break;
   945                     case 0x4:
   946                         { /* MOV.B Rm, @-Rn */
   947                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   948                         load_reg( R_EAX, Rm );
   949                         load_reg( R_ECX, Rn );
   950                         ADD_imm8s_r32( -1, R_ECX );
   951                         store_reg( R_ECX, Rn );
   952                         MEM_WRITE_BYTE( R_ECX, R_EAX );
   953                         }
   954                         break;
   955                     case 0x5:
   956                         { /* MOV.W Rm, @-Rn */
   957                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   958                         load_reg( R_ECX, Rn );
   959                         check_walign16( R_ECX );
   960                         load_reg( R_EAX, Rm );
   961                         ADD_imm8s_r32( -2, R_ECX );
   962                         store_reg( R_ECX, Rn );
   963                         MEM_WRITE_WORD( R_ECX, R_EAX );
   964                         }
   965                         break;
   966                     case 0x6:
   967                         { /* MOV.L Rm, @-Rn */
   968                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   969                         load_reg( R_EAX, Rm );
   970                         load_reg( R_ECX, Rn );
   971                         check_walign32( R_ECX );
   972                         ADD_imm8s_r32( -4, R_ECX );
   973                         store_reg( R_ECX, Rn );
   974                         MEM_WRITE_LONG( R_ECX, R_EAX );
   975                         }
   976                         break;
   977                     case 0x7:
   978                         { /* DIV0S Rm, Rn */
   979                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   980                         load_reg( R_EAX, Rm );
   981                         load_reg( R_ECX, Rn );
   982                         SHR_imm8_r32( 31, R_EAX );
   983                         SHR_imm8_r32( 31, R_ECX );
   984                         store_spreg( R_EAX, R_M );
   985                         store_spreg( R_ECX, R_Q );
   986                         CMP_r32_r32( R_EAX, R_ECX );
   987                         SETNE_t();
   988                         }
   989                         break;
   990                     case 0x8:
   991                         { /* TST Rm, Rn */
   992                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   993                         load_reg( R_EAX, Rm );
   994                         load_reg( R_ECX, Rn );
   995                         TEST_r32_r32( R_EAX, R_ECX );
   996                         SETE_t();
   997                         }
   998                         break;
   999                     case 0x9:
  1000                         { /* AND Rm, Rn */
  1001                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1002                         load_reg( R_EAX, Rm );
  1003                         load_reg( R_ECX, Rn );
  1004                         AND_r32_r32( R_EAX, R_ECX );
  1005                         store_reg( R_ECX, Rn );
  1007                         break;
  1008                     case 0xA:
  1009                         { /* XOR Rm, Rn */
  1010                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1011                         load_reg( R_EAX, Rm );
  1012                         load_reg( R_ECX, Rn );
  1013                         XOR_r32_r32( R_EAX, R_ECX );
  1014                         store_reg( R_ECX, Rn );
  1016                         break;
  1017                     case 0xB:
  1018                         { /* OR Rm, Rn */
  1019                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1020                         load_reg( R_EAX, Rm );
  1021                         load_reg( R_ECX, Rn );
  1022                         OR_r32_r32( R_EAX, R_ECX );
  1023                         store_reg( R_ECX, Rn );
  1025                         break;
  1026                     case 0xC:
  1027                         { /* CMP/STR Rm, Rn */
  1028                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1029                         load_reg( R_EAX, Rm );
  1030                         load_reg( R_ECX, Rn );
  1031                         XOR_r32_r32( R_ECX, R_EAX );
  1032                         TEST_r8_r8( R_AL, R_AL );
  1033                         JE_rel8(13, target1);
  1034                         TEST_r8_r8( R_AH, R_AH ); // 2
  1035                         JE_rel8(9, target2);
  1036                         SHR_imm8_r32( 16, R_EAX ); // 3
  1037                         TEST_r8_r8( R_AL, R_AL ); // 2
  1038                         JE_rel8(2, target3);
  1039                         TEST_r8_r8( R_AH, R_AH ); // 2
  1040                         JMP_TARGET(target1);
  1041                         JMP_TARGET(target2);
  1042                         JMP_TARGET(target3);
  1043                         SETE_t();
  1045                         break;
  1046                     case 0xD:
  1047                         { /* XTRCT Rm, Rn */
  1048                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1049                         load_reg( R_EAX, Rm );
  1050                         load_reg( R_ECX, Rn );
  1051                         SHL_imm8_r32( 16, R_EAX );
  1052                         SHR_imm8_r32( 16, R_ECX );
  1053                         OR_r32_r32( R_EAX, R_ECX );
  1054                         store_reg( R_ECX, Rn );
  1056                         break;
  1057                     case 0xE:
  1058                         { /* MULU.W Rm, Rn */
  1059                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1060                         load_reg16u( R_EAX, Rm );
  1061                         load_reg16u( R_ECX, Rn );
  1062                         MUL_r32( R_ECX );
  1063                         store_spreg( R_EAX, R_MACL );
  1065                         break;
  1066                     case 0xF:
  1067                         { /* MULS.W Rm, Rn */
  1068                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1069                         load_reg16s( R_EAX, Rm );
  1070                         load_reg16s( R_ECX, Rn );
  1071                         MUL_r32( R_ECX );
  1072                         store_spreg( R_EAX, R_MACL );
  1074                         break;
  1075                     default:
  1076                         UNDEF();
  1077                         break;
  1079                 break;
  1080             case 0x3:
  1081                 switch( ir&0xF ) {
  1082                     case 0x0:
  1083                         { /* CMP/EQ Rm, Rn */
  1084                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1085                         load_reg( R_EAX, Rm );
  1086                         load_reg( R_ECX, Rn );
  1087                         CMP_r32_r32( R_EAX, R_ECX );
  1088                         SETE_t();
  1090                         break;
  1091                     case 0x2:
  1092                         { /* CMP/HS Rm, Rn */
  1093                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1094                         load_reg( R_EAX, Rm );
  1095                         load_reg( R_ECX, Rn );
  1096                         CMP_r32_r32( R_EAX, R_ECX );
  1097                         SETAE_t();
  1099                         break;
  1100                     case 0x3:
  1101                         { /* CMP/GE Rm, Rn */
  1102                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1103                         load_reg( R_EAX, Rm );
  1104                         load_reg( R_ECX, Rn );
  1105                         CMP_r32_r32( R_EAX, R_ECX );
  1106                         SETGE_t();
  1108                         break;
  1109                     case 0x4:
  1110                         { /* DIV1 Rm, Rn */
  1111                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1112                         load_spreg( R_ECX, R_M );
  1113                         load_reg( R_EAX, Rn );
  1114                         LDC_t();
  1115                         RCL1_r32( R_EAX );
  1116                         SETC_r8( R_DL ); // Q'
  1117                         CMP_sh4r_r32( R_Q, R_ECX );
  1118                         JE_rel8(5, mqequal);
  1119                         ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
  1120                         JMP_rel8(3, end);
  1121                         JMP_TARGET(mqequal);
  1122                         SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
  1123                         JMP_TARGET(end);
  1124                         store_reg( R_EAX, Rn ); // Done with Rn now
  1125                         SETC_r8(R_AL); // tmp1
  1126                         XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
  1127                         XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
  1128                         store_spreg( R_ECX, R_Q );
  1129                         XOR_imm8s_r32( 1, R_AL );   // T = !Q'
  1130                         MOVZX_r8_r32( R_AL, R_EAX );
  1131                         store_spreg( R_EAX, R_T );
  1133                         break;
  1134                     case 0x5:
  1135                         { /* DMULU.L Rm, Rn */
  1136                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1137                         load_reg( R_EAX, Rm );
  1138                         load_reg( R_ECX, Rn );
  1139                         MUL_r32(R_ECX);
  1140                         store_spreg( R_EDX, R_MACH );
  1141                         store_spreg( R_EAX, R_MACL );
  1143                         break;
  1144                     case 0x6:
  1145                         { /* CMP/HI Rm, Rn */
  1146                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1147                         load_reg( R_EAX, Rm );
  1148                         load_reg( R_ECX, Rn );
  1149                         CMP_r32_r32( R_EAX, R_ECX );
  1150                         SETA_t();
  1152                         break;
  1153                     case 0x7:
  1154                         { /* CMP/GT Rm, Rn */
  1155                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1156                         load_reg( R_EAX, Rm );
  1157                         load_reg( R_ECX, Rn );
  1158                         CMP_r32_r32( R_EAX, R_ECX );
  1159                         SETG_t();
  1161                         break;
  1162                     case 0x8:
  1163                         { /* SUB Rm, Rn */
  1164                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1165                         load_reg( R_EAX, Rm );
  1166                         load_reg( R_ECX, Rn );
  1167                         SUB_r32_r32( R_EAX, R_ECX );
  1168                         store_reg( R_ECX, Rn );
  1170                         break;
  1171                     case 0xA:
  1172                         { /* SUBC Rm, Rn */
  1173                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1174                         load_reg( R_EAX, Rm );
  1175                         load_reg( R_ECX, Rn );
  1176                         LDC_t();
  1177                         SBB_r32_r32( R_EAX, R_ECX );
  1178                         store_reg( R_ECX, Rn );
  1179                         SETC_t();
  1181                         break;
  1182                     case 0xB:
  1183                         { /* SUBV Rm, Rn */
  1184                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1185                         load_reg( R_EAX, Rm );
  1186                         load_reg( R_ECX, Rn );
  1187                         SUB_r32_r32( R_EAX, R_ECX );
  1188                         store_reg( R_ECX, Rn );
  1189                         SETO_t();
  1191                         break;
  1192                     case 0xC:
  1193                         { /* ADD Rm, Rn */
  1194                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1195                         load_reg( R_EAX, Rm );
  1196                         load_reg( R_ECX, Rn );
  1197                         ADD_r32_r32( R_EAX, R_ECX );
  1198                         store_reg( R_ECX, Rn );
  1200                         break;
  1201                     case 0xD:
  1202                         { /* DMULS.L Rm, Rn */
  1203                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1204                         load_reg( R_EAX, Rm );
  1205                         load_reg( R_ECX, Rn );
  1206                         IMUL_r32(R_ECX);
  1207                         store_spreg( R_EDX, R_MACH );
  1208                         store_spreg( R_EAX, R_MACL );
  1210                         break;
  1211                     case 0xE:
  1212                         { /* ADDC Rm, Rn */
  1213                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1214                         load_reg( R_EAX, Rm );
  1215                         load_reg( R_ECX, Rn );
  1216                         LDC_t();
  1217                         ADC_r32_r32( R_EAX, R_ECX );
  1218                         store_reg( R_ECX, Rn );
  1219                         SETC_t();
  1221                         break;
  1222                     case 0xF:
  1223                         { /* ADDV Rm, Rn */
  1224                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1225                         load_reg( R_EAX, Rm );
  1226                         load_reg( R_ECX, Rn );
  1227                         ADD_r32_r32( R_EAX, R_ECX );
  1228                         store_reg( R_ECX, Rn );
  1229                         SETO_t();
  1231                         break;
  1232                     default:
  1233                         UNDEF();
  1234                         break;
  1236                 break;
  1237             case 0x4:
  1238                 switch( ir&0xF ) {
  1239                     case 0x0:
  1240                         switch( (ir&0xF0) >> 4 ) {
  1241                             case 0x0:
  1242                                 { /* SHLL Rn */
  1243                                 uint32_t Rn = ((ir>>8)&0xF); 
  1244                                 load_reg( R_EAX, Rn );
  1245                                 SHL1_r32( R_EAX );
  1246                                 SETC_t();
  1247                                 store_reg( R_EAX, Rn );
  1249                                 break;
  1250                             case 0x1:
  1251                                 { /* DT Rn */
  1252                                 uint32_t Rn = ((ir>>8)&0xF); 
  1253                                 load_reg( R_EAX, Rn );
  1254                                 ADD_imm8s_r32( -1, R_EAX );
  1255                                 store_reg( R_EAX, Rn );
  1256                                 SETE_t();
  1258                                 break;
  1259                             case 0x2:
  1260                                 { /* SHAL Rn */
  1261                                 uint32_t Rn = ((ir>>8)&0xF); 
  1262                                 load_reg( R_EAX, Rn );
  1263                                 SHL1_r32( R_EAX );
  1264                                 SETC_t();
  1265                                 store_reg( R_EAX, Rn );
  1267                                 break;
  1268                             default:
  1269                                 UNDEF();
  1270                                 break;
  1272                         break;
  1273                     case 0x1:
  1274                         switch( (ir&0xF0) >> 4 ) {
  1275                             case 0x0:
  1276                                 { /* SHLR Rn */
  1277                                 uint32_t Rn = ((ir>>8)&0xF); 
  1278                                 load_reg( R_EAX, Rn );
  1279                                 SHR1_r32( R_EAX );
  1280                                 SETC_t();
  1281                                 store_reg( R_EAX, Rn );
  1283                                 break;
  1284                             case 0x1:
  1285                                 { /* CMP/PZ Rn */
  1286                                 uint32_t Rn = ((ir>>8)&0xF); 
  1287                                 load_reg( R_EAX, Rn );
  1288                                 CMP_imm8s_r32( 0, R_EAX );
  1289                                 SETGE_t();
  1291                                 break;
  1292                             case 0x2:
  1293                                 { /* SHAR Rn */
  1294                                 uint32_t Rn = ((ir>>8)&0xF); 
  1295                                 load_reg( R_EAX, Rn );
  1296                                 SAR1_r32( R_EAX );
  1297                                 SETC_t();
  1298                                 store_reg( R_EAX, Rn );
  1300                                 break;
  1301                             default:
  1302                                 UNDEF();
  1303                                 break;
  1305                         break;
  1306                     case 0x2:
  1307                         switch( (ir&0xF0) >> 4 ) {
  1308                             case 0x0:
  1309                                 { /* STS.L MACH, @-Rn */
  1310                                 uint32_t Rn = ((ir>>8)&0xF); 
  1311                                 load_reg( R_ECX, Rn );
  1312                                 check_walign32( R_ECX );
  1313                                 ADD_imm8s_r32( -4, R_ECX );
  1314                                 store_reg( R_ECX, Rn );
  1315                                 load_spreg( R_EAX, R_MACH );
  1316                                 MEM_WRITE_LONG( R_ECX, R_EAX );
  1318                                 break;
  1319                             case 0x1:
  1320                                 { /* STS.L MACL, @-Rn */
  1321                                 uint32_t Rn = ((ir>>8)&0xF); 
  1322                                 load_reg( R_ECX, Rn );
  1323                                 check_walign32( R_ECX );
  1324                                 ADD_imm8s_r32( -4, R_ECX );
  1325                                 store_reg( R_ECX, Rn );
  1326                                 load_spreg( R_EAX, R_MACL );
  1327                                 MEM_WRITE_LONG( R_ECX, R_EAX );
  1329                                 break;
  1330                             case 0x2:
  1331                                 { /* STS.L PR, @-Rn */
  1332                                 uint32_t Rn = ((ir>>8)&0xF); 
  1333                                 load_reg( R_ECX, Rn );
  1334                                 check_walign32( R_ECX );
  1335                                 ADD_imm8s_r32( -4, R_ECX );
  1336                                 store_reg( R_ECX, Rn );
  1337                                 load_spreg( R_EAX, R_PR );
  1338                                 MEM_WRITE_LONG( R_ECX, R_EAX );
  1340                                 break;
  1341                             case 0x3:
  1342                                 { /* STC.L SGR, @-Rn */
  1343                                 uint32_t Rn = ((ir>>8)&0xF); 
  1344                                 check_priv();
  1345                                 load_reg( R_ECX, Rn );
  1346                                 check_walign32( R_ECX );
  1347                                 ADD_imm8s_r32( -4, R_ECX );
  1348                                 store_reg( R_ECX, Rn );
  1349                                 load_spreg( R_EAX, R_SGR );
  1350                                 MEM_WRITE_LONG( R_ECX, R_EAX );
  1352                                 break;
  1353                             case 0x5:
  1354                                 { /* STS.L FPUL, @-Rn */
  1355                                 uint32_t Rn = ((ir>>8)&0xF); 
  1356                                 load_reg( R_ECX, Rn );
  1357                                 check_walign32( R_ECX );
  1358                                 ADD_imm8s_r32( -4, R_ECX );
  1359                                 store_reg( R_ECX, Rn );
  1360                                 load_spreg( R_EAX, R_FPUL );
  1361                                 MEM_WRITE_LONG( R_ECX, R_EAX );
  1363                                 break;
  1364                             case 0x6:
  1365                                 { /* STS.L FPSCR, @-Rn */
  1366                                 uint32_t Rn = ((ir>>8)&0xF); 
  1367                                 load_reg( R_ECX, Rn );
  1368                                 check_walign32( R_ECX );
  1369                                 ADD_imm8s_r32( -4, R_ECX );
  1370                                 store_reg( R_ECX, Rn );
  1371                                 load_spreg( R_EAX, R_FPSCR );
  1372                                 MEM_WRITE_LONG( R_ECX, R_EAX );
  1374                                 break;
  1375                             case 0xF:
  1376                                 { /* STC.L DBR, @-Rn */
  1377                                 uint32_t Rn = ((ir>>8)&0xF); 
  1378                                 check_priv();
  1379                                 load_reg( R_ECX, Rn );
  1380                                 check_walign32( R_ECX );
  1381                                 ADD_imm8s_r32( -4, R_ECX );
  1382                                 store_reg( R_ECX, Rn );
  1383                                 load_spreg( R_EAX, R_DBR );
  1384                                 MEM_WRITE_LONG( R_ECX, R_EAX );
  1386                                 break;
  1387                             default:
  1388                                 UNDEF();
  1389                                 break;
  1391                         break;
  1392                     case 0x3:
  1393                         switch( (ir&0x80) >> 7 ) {
  1394                             case 0x0:
  1395                                 switch( (ir&0x70) >> 4 ) {
  1396                                     case 0x0:
  1397                                         { /* STC.L SR, @-Rn */
  1398                                         uint32_t Rn = ((ir>>8)&0xF); 
  1399                                         check_priv();
  1400                                         call_func0( sh4_read_sr );
  1401                                         load_reg( R_ECX, Rn );
  1402                                         check_walign32( R_ECX );
  1403                                         ADD_imm8s_r32( -4, R_ECX );
  1404                                         store_reg( R_ECX, Rn );
  1405                                         MEM_WRITE_LONG( R_ECX, R_EAX );
  1407                                         break;
  1408                                     case 0x1:
  1409                                         { /* STC.L GBR, @-Rn */
  1410                                         uint32_t Rn = ((ir>>8)&0xF); 
  1411                                         load_reg( R_ECX, Rn );
  1412                                         check_walign32( R_ECX );
  1413                                         ADD_imm8s_r32( -4, R_ECX );
  1414                                         store_reg( R_ECX, Rn );
  1415                                         load_spreg( R_EAX, R_GBR );
  1416                                         MEM_WRITE_LONG( R_ECX, R_EAX );
  1418                                         break;
  1419                                     case 0x2:
  1420                                         { /* STC.L VBR, @-Rn */
  1421                                         uint32_t Rn = ((ir>>8)&0xF); 
  1422                                         check_priv();
  1423                                         load_reg( R_ECX, Rn );
  1424                                         check_walign32( R_ECX );
  1425                                         ADD_imm8s_r32( -4, R_ECX );
  1426                                         store_reg( R_ECX, Rn );
  1427                                         load_spreg( R_EAX, R_VBR );
  1428                                         MEM_WRITE_LONG( R_ECX, R_EAX );
  1430                                         break;
  1431                                     case 0x3:
  1432                                         { /* STC.L SSR, @-Rn */
  1433                                         uint32_t Rn = ((ir>>8)&0xF); 
  1434                                         check_priv();
  1435                                         load_reg( R_ECX, Rn );
  1436                                         check_walign32( R_ECX );
  1437                                         ADD_imm8s_r32( -4, R_ECX );
  1438                                         store_reg( R_ECX, Rn );
  1439                                         load_spreg( R_EAX, R_SSR );
  1440                                         MEM_WRITE_LONG( R_ECX, R_EAX );
  1442                                         break;
  1443                                     case 0x4:
  1444                                         { /* STC.L SPC, @-Rn */
  1445                                         uint32_t Rn = ((ir>>8)&0xF); 
  1446                                         check_priv();
  1447                                         load_reg( R_ECX, Rn );
  1448                                         check_walign32( R_ECX );
  1449                                         ADD_imm8s_r32( -4, R_ECX );
  1450                                         store_reg( R_ECX, Rn );
  1451                                         load_spreg( R_EAX, R_SPC );
  1452                                         MEM_WRITE_LONG( R_ECX, R_EAX );
  1454                                         break;
  1455                                     default:
  1456                                         UNDEF();
  1457                                         break;
  1459                                 break;
  1460                             case 0x1:
  1461                                 { /* STC.L Rm_BANK, @-Rn */
  1462                                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
  1463                                 check_priv();
  1464                                 load_reg( R_ECX, Rn );
  1465                                 check_walign32( R_ECX );
  1466                                 ADD_imm8s_r32( -4, R_ECX );
  1467                                 store_reg( R_ECX, Rn );
  1468                                 load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
  1469                                 MEM_WRITE_LONG( R_ECX, R_EAX );
  1471                                 break;
  1473                         break;
  1474                     case 0x4:
  1475                         switch( (ir&0xF0) >> 4 ) {
  1476                             case 0x0:
  1477                                 { /* ROTL Rn */
  1478                                 uint32_t Rn = ((ir>>8)&0xF); 
  1479                                 load_reg( R_EAX, Rn );
  1480                                 ROL1_r32( R_EAX );
  1481                                 store_reg( R_EAX, Rn );
  1482                                 SETC_t();
  1484                                 break;
  1485                             case 0x2:
  1486                                 { /* ROTCL Rn */
  1487                                 uint32_t Rn = ((ir>>8)&0xF); 
  1488                                 load_reg( R_EAX, Rn );
  1489                                 LDC_t();
  1490                                 RCL1_r32( R_EAX );
  1491                                 store_reg( R_EAX, Rn );
  1492                                 SETC_t();
  1494                                 break;
  1495                             default:
  1496                                 UNDEF();
  1497                                 break;
  1499                         break;
  1500                     case 0x5:
  1501                         switch( (ir&0xF0) >> 4 ) {
  1502                             case 0x0:
  1503                                 { /* ROTR Rn */
  1504                                 uint32_t Rn = ((ir>>8)&0xF); 
  1505                                 load_reg( R_EAX, Rn );
  1506                                 ROR1_r32( R_EAX );
  1507                                 store_reg( R_EAX, Rn );
  1508                                 SETC_t();
  1510                                 break;
  1511                             case 0x1:
  1512                                 { /* CMP/PL Rn */
  1513                                 uint32_t Rn = ((ir>>8)&0xF); 
  1514                                 load_reg( R_EAX, Rn );
  1515                                 CMP_imm8s_r32( 0, R_EAX );
  1516                                 SETG_t();
  1518                                 break;
  1519                             case 0x2:
  1520                                 { /* ROTCR Rn */
  1521                                 uint32_t Rn = ((ir>>8)&0xF); 
  1522                                 load_reg( R_EAX, Rn );
  1523                                 LDC_t();
  1524                                 RCR1_r32( R_EAX );
  1525                                 store_reg( R_EAX, Rn );
  1526                                 SETC_t();
  1528                                 break;
  1529                             default:
  1530                                 UNDEF();
  1531                                 break;
  1533                         break;
  1534                     case 0x6:
  1535                         switch( (ir&0xF0) >> 4 ) {
  1536                             case 0x0:
  1537                                 { /* LDS.L @Rm+, MACH */
  1538                                 uint32_t Rm = ((ir>>8)&0xF); 
  1539                                 load_reg( R_EAX, Rm );
  1540                                 check_ralign32( R_EAX );
  1541                                 MOV_r32_r32( R_EAX, R_ECX );
  1542                                 ADD_imm8s_r32( 4, R_EAX );
  1543                                 store_reg( R_EAX, Rm );
  1544                                 MEM_READ_LONG( R_ECX, R_EAX );
  1545                                 store_spreg( R_EAX, R_MACH );
  1547                                 break;
  1548                             case 0x1:
  1549                                 { /* LDS.L @Rm+, MACL */
  1550                                 uint32_t Rm = ((ir>>8)&0xF); 
  1551                                 load_reg( R_EAX, Rm );
  1552                                 check_ralign32( R_EAX );
  1553                                 MOV_r32_r32( R_EAX, R_ECX );
  1554                                 ADD_imm8s_r32( 4, R_EAX );
  1555                                 store_reg( R_EAX, Rm );
  1556                                 MEM_READ_LONG( R_ECX, R_EAX );
  1557                                 store_spreg( R_EAX, R_MACL );
  1559                                 break;
  1560                             case 0x2:
  1561                                 { /* LDS.L @Rm+, PR */
  1562                                 uint32_t Rm = ((ir>>8)&0xF); 
  1563                                 load_reg( R_EAX, Rm );
  1564                                 check_ralign32( R_EAX );
  1565                                 MOV_r32_r32( R_EAX, R_ECX );
  1566                                 ADD_imm8s_r32( 4, R_EAX );
  1567                                 store_reg( R_EAX, Rm );
  1568                                 MEM_READ_LONG( R_ECX, R_EAX );
  1569                                 store_spreg( R_EAX, R_PR );
  1571                                 break;
  1572                             case 0x3:
  1573                                 { /* LDC.L @Rm+, SGR */
  1574                                 uint32_t Rm = ((ir>>8)&0xF); 
  1575                                 check_priv();
  1576                                 load_reg( R_EAX, Rm );
  1577                                 check_ralign32( R_EAX );
  1578                                 MOV_r32_r32( R_EAX, R_ECX );
  1579                                 ADD_imm8s_r32( 4, R_EAX );
  1580                                 store_reg( R_EAX, Rm );
  1581                                 MEM_READ_LONG( R_ECX, R_EAX );
  1582                                 store_spreg( R_EAX, R_SGR );
  1584                                 break;
  1585                             case 0x5:
  1586                                 { /* LDS.L @Rm+, FPUL */
  1587                                 uint32_t Rm = ((ir>>8)&0xF); 
  1588                                 load_reg( R_EAX, Rm );
  1589                                 check_ralign32( R_EAX );
  1590                                 MOV_r32_r32( R_EAX, R_ECX );
  1591                                 ADD_imm8s_r32( 4, R_EAX );
  1592                                 store_reg( R_EAX, Rm );
  1593                                 MEM_READ_LONG( R_ECX, R_EAX );
  1594                                 store_spreg( R_EAX, R_FPUL );
  1596                                 break;
  1597                             case 0x6:
  1598                                 { /* LDS.L @Rm+, FPSCR */
  1599                                 uint32_t Rm = ((ir>>8)&0xF); 
  1600                                 load_reg( R_EAX, Rm );
  1601                                 check_ralign32( R_EAX );
  1602                                 MOV_r32_r32( R_EAX, R_ECX );
  1603                                 ADD_imm8s_r32( 4, R_EAX );
  1604                                 store_reg( R_EAX, Rm );
  1605                                 MEM_READ_LONG( R_ECX, R_EAX );
  1606                                 store_spreg( R_EAX, R_FPSCR );
  1607                                 update_fr_bank( R_EAX );
  1609                                 break;
  1610                             case 0xF:
  1611                                 { /* LDC.L @Rm+, DBR */
  1612                                 uint32_t Rm = ((ir>>8)&0xF); 
  1613                                 check_priv();
  1614                                 load_reg( R_EAX, Rm );
  1615                                 check_ralign32( R_EAX );
  1616                                 MOV_r32_r32( R_EAX, R_ECX );
  1617                                 ADD_imm8s_r32( 4, R_EAX );
  1618                                 store_reg( R_EAX, Rm );
  1619                                 MEM_READ_LONG( R_ECX, R_EAX );
  1620                                 store_spreg( R_EAX, R_DBR );
  1622                                 break;
  1623                             default:
  1624                                 UNDEF();
  1625                                 break;
  1627                         break;
  1628                     case 0x7:
  1629                         switch( (ir&0x80) >> 7 ) {
  1630                             case 0x0:
  1631                                 switch( (ir&0x70) >> 4 ) {
  1632                                     case 0x0:
  1633                                         { /* LDC.L @Rm+, SR */
  1634                                         uint32_t Rm = ((ir>>8)&0xF); 
  1635                                         if( sh4_x86.in_delay_slot ) {
  1636                                     	SLOTILLEGAL();
  1637                                         } else {
  1638                                     	check_priv();
  1639                                     	load_reg( R_EAX, Rm );
  1640                                     	check_ralign32( R_EAX );
  1641                                     	MOV_r32_r32( R_EAX, R_ECX );
  1642                                     	ADD_imm8s_r32( 4, R_EAX );
  1643                                     	store_reg( R_EAX, Rm );
  1644                                     	MEM_READ_LONG( R_ECX, R_EAX );
  1645                                     	call_func1( sh4_write_sr, R_EAX );
  1646                                     	sh4_x86.priv_checked = FALSE;
  1647                                     	sh4_x86.fpuen_checked = FALSE;
  1650                                         break;
  1651                                     case 0x1:
  1652                                         { /* LDC.L @Rm+, GBR */
  1653                                         uint32_t Rm = ((ir>>8)&0xF); 
  1654                                         load_reg( R_EAX, Rm );
  1655                                         check_ralign32( R_EAX );
  1656                                         MOV_r32_r32( R_EAX, R_ECX );
  1657                                         ADD_imm8s_r32( 4, R_EAX );
  1658                                         store_reg( R_EAX, Rm );
  1659                                         MEM_READ_LONG( R_ECX, R_EAX );
  1660                                         store_spreg( R_EAX, R_GBR );
  1662                                         break;
  1663                                     case 0x2:
  1664                                         { /* LDC.L @Rm+, VBR */
  1665                                         uint32_t Rm = ((ir>>8)&0xF); 
  1666                                         check_priv();
  1667                                         load_reg( R_EAX, Rm );
  1668                                         check_ralign32( R_EAX );
  1669                                         MOV_r32_r32( R_EAX, R_ECX );
  1670                                         ADD_imm8s_r32( 4, R_EAX );
  1671                                         store_reg( R_EAX, Rm );
  1672                                         MEM_READ_LONG( R_ECX, R_EAX );
  1673                                         store_spreg( R_EAX, R_VBR );
  1675                                         break;
  1676                                     case 0x3:
  1677                                         { /* LDC.L @Rm+, SSR */
  1678                                         uint32_t Rm = ((ir>>8)&0xF); 
  1679                                         check_priv();
  1680                                         load_reg( R_EAX, Rm );
  1681                                         MOV_r32_r32( R_EAX, R_ECX );
  1682                                         ADD_imm8s_r32( 4, R_EAX );
  1683                                         store_reg( R_EAX, Rm );
  1684                                         MEM_READ_LONG( R_ECX, R_EAX );
  1685                                         store_spreg( R_EAX, R_SSR );
  1687                                         break;
  1688                                     case 0x4:
  1689                                         { /* LDC.L @Rm+, SPC */
  1690                                         uint32_t Rm = ((ir>>8)&0xF); 
  1691                                         check_priv();
  1692                                         load_reg( R_EAX, Rm );
  1693                                         check_ralign32( R_EAX );
  1694                                         MOV_r32_r32( R_EAX, R_ECX );
  1695                                         ADD_imm8s_r32( 4, R_EAX );
  1696                                         store_reg( R_EAX, Rm );
  1697                                         MEM_READ_LONG( R_ECX, R_EAX );
  1698                                         store_spreg( R_EAX, R_SPC );
  1700                                         break;
  1701                                     default:
  1702                                         UNDEF();
  1703                                         break;
  1705                                 break;
  1706                             case 0x1:
  1707                                 { /* LDC.L @Rm+, Rn_BANK */
  1708                                 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
  1709                                 check_priv();
  1710                                 load_reg( R_EAX, Rm );
  1711                                 check_ralign32( R_EAX );
  1712                                 MOV_r32_r32( R_EAX, R_ECX );
  1713                                 ADD_imm8s_r32( 4, R_EAX );
  1714                                 store_reg( R_EAX, Rm );
  1715                                 MEM_READ_LONG( R_ECX, R_EAX );
  1716                                 store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
  1718                                 break;
  1720                         break;
  1721                     case 0x8:
  1722                         switch( (ir&0xF0) >> 4 ) {
  1723                             case 0x0:
  1724                                 { /* SHLL2 Rn */
  1725                                 uint32_t Rn = ((ir>>8)&0xF); 
  1726                                 load_reg( R_EAX, Rn );
  1727                                 SHL_imm8_r32( 2, R_EAX );
  1728                                 store_reg( R_EAX, Rn );
  1730                                 break;
  1731                             case 0x1:
  1732                                 { /* SHLL8 Rn */
  1733                                 uint32_t Rn = ((ir>>8)&0xF); 
  1734                                 load_reg( R_EAX, Rn );
  1735                                 SHL_imm8_r32( 8, R_EAX );
  1736                                 store_reg( R_EAX, Rn );
  1738                                 break;
  1739                             case 0x2:
  1740                                 { /* SHLL16 Rn */
  1741                                 uint32_t Rn = ((ir>>8)&0xF); 
  1742                                 load_reg( R_EAX, Rn );
  1743                                 SHL_imm8_r32( 16, R_EAX );
  1744                                 store_reg( R_EAX, Rn );
  1746                                 break;
  1747                             default:
  1748                                 UNDEF();
  1749                                 break;
  1751                         break;
  1752                     case 0x9:
  1753                         switch( (ir&0xF0) >> 4 ) {
  1754                             case 0x0:
  1755                                 { /* SHLR2 Rn */
  1756                                 uint32_t Rn = ((ir>>8)&0xF); 
  1757                                 load_reg( R_EAX, Rn );
  1758                                 SHR_imm8_r32( 2, R_EAX );
  1759                                 store_reg( R_EAX, Rn );
  1761                                 break;
  1762                             case 0x1:
  1763                                 { /* SHLR8 Rn */
  1764                                 uint32_t Rn = ((ir>>8)&0xF); 
  1765                                 load_reg( R_EAX, Rn );
  1766                                 SHR_imm8_r32( 8, R_EAX );
  1767                                 store_reg( R_EAX, Rn );
  1769                                 break;
  1770                             case 0x2:
  1771                                 { /* SHLR16 Rn */
  1772                                 uint32_t Rn = ((ir>>8)&0xF); 
  1773                                 load_reg( R_EAX, Rn );
  1774                                 SHR_imm8_r32( 16, R_EAX );
  1775                                 store_reg( R_EAX, Rn );
  1777                                 break;
  1778                             default:
  1779                                 UNDEF();
  1780                                 break;
  1782                         break;
  1783                     case 0xA:
  1784                         switch( (ir&0xF0) >> 4 ) {
  1785                             case 0x0:
  1786                                 { /* LDS Rm, MACH */
  1787                                 uint32_t Rm = ((ir>>8)&0xF); 
  1788                                 load_reg( R_EAX, Rm );
  1789                                 store_spreg( R_EAX, R_MACH );
  1791                                 break;
  1792                             case 0x1:
  1793                                 { /* LDS Rm, MACL */
  1794                                 uint32_t Rm = ((ir>>8)&0xF); 
  1795                                 load_reg( R_EAX, Rm );
  1796                                 store_spreg( R_EAX, R_MACL );
  1798                                 break;
  1799                             case 0x2:
  1800                                 { /* LDS Rm, PR */
  1801                                 uint32_t Rm = ((ir>>8)&0xF); 
  1802                                 load_reg( R_EAX, Rm );
  1803                                 store_spreg( R_EAX, R_PR );
  1805                                 break;
  1806                             case 0x3:
  1807                                 { /* LDC Rm, SGR */
  1808                                 uint32_t Rm = ((ir>>8)&0xF); 
  1809                                 check_priv();
  1810                                 load_reg( R_EAX, Rm );
  1811                                 store_spreg( R_EAX, R_SGR );
  1813                                 break;
  1814                             case 0x5:
  1815                                 { /* LDS Rm, FPUL */
  1816                                 uint32_t Rm = ((ir>>8)&0xF); 
  1817                                 load_reg( R_EAX, Rm );
  1818                                 store_spreg( R_EAX, R_FPUL );
  1820                                 break;
  1821                             case 0x6:
  1822                                 { /* LDS Rm, FPSCR */
  1823                                 uint32_t Rm = ((ir>>8)&0xF); 
  1824                                 load_reg( R_EAX, Rm );
  1825                                 store_spreg( R_EAX, R_FPSCR );
  1826                                 update_fr_bank( R_EAX );
  1828                                 break;
  1829                             case 0xF:
  1830                                 { /* LDC Rm, DBR */
  1831                                 uint32_t Rm = ((ir>>8)&0xF); 
  1832                                 check_priv();
  1833                                 load_reg( R_EAX, Rm );
  1834                                 store_spreg( R_EAX, R_DBR );
  1836                                 break;
  1837                             default:
  1838                                 UNDEF();
  1839                                 break;
  1841                         break;
  1842                     case 0xB:
  1843                         switch( (ir&0xF0) >> 4 ) {
  1844                             case 0x0:
  1845                                 { /* JSR @Rn */
  1846                                 uint32_t Rn = ((ir>>8)&0xF); 
  1847                                 if( sh4_x86.in_delay_slot ) {
  1848                             	SLOTILLEGAL();
  1849                                 } else {
  1850                             	load_imm32( R_EAX, pc + 4 );
  1851                             	store_spreg( R_EAX, R_PR );
  1852                             	load_reg( R_ECX, Rn );
  1853                             	store_spreg( R_ECX, REG_OFFSET(pc) );
  1854                             	sh4_x86.in_delay_slot = TRUE;
  1855                             	sh4_x86_translate_instruction(pc+2);
  1856                             	exit_block_pcset(pc+2);
  1857                             	return 4;
  1860                                 break;
  1861                             case 0x1:
  1862                                 { /* TAS.B @Rn */
  1863                                 uint32_t Rn = ((ir>>8)&0xF); 
  1864                                 load_reg( R_ECX, Rn );
  1865                                 MEM_READ_BYTE( R_ECX, R_EAX );
  1866                                 TEST_r8_r8( R_AL, R_AL );
  1867                                 SETE_t();
  1868                                 OR_imm8_r8( 0x80, R_AL );
  1869                                 load_reg( R_ECX, Rn );
  1870                                 MEM_WRITE_BYTE( R_ECX, R_EAX );
  1872                                 break;
  1873                             case 0x2:
  1874                                 { /* JMP @Rn */
  1875                                 uint32_t Rn = ((ir>>8)&0xF); 
  1876                                 if( sh4_x86.in_delay_slot ) {
  1877                             	SLOTILLEGAL();
  1878                                 } else {
  1879                             	load_reg( R_ECX, Rn );
  1880                             	store_spreg( R_ECX, REG_OFFSET(pc) );
  1881                             	sh4_x86.in_delay_slot = TRUE;
  1882                             	sh4_x86_translate_instruction(pc+2);
  1883                             	exit_block_pcset(pc+2);
  1884                             	return 4;
  1887                                 break;
  1888                             default:
  1889                                 UNDEF();
  1890                                 break;
  1892                         break;
  1893                     case 0xC:
  1894                         { /* SHAD Rm, Rn */
  1895                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1896                         /* Annoyingly enough, not directly convertible */
  1897                         load_reg( R_EAX, Rn );
  1898                         load_reg( R_ECX, Rm );
  1899                         CMP_imm32_r32( 0, R_ECX );
  1900                         JGE_rel8(16, doshl);
  1902                         NEG_r32( R_ECX );      // 2
  1903                         AND_imm8_r8( 0x1F, R_CL ); // 3
  1904                         JE_rel8( 4, emptysar);     // 2
  1905                         SAR_r32_CL( R_EAX );       // 2
  1906                         JMP_rel8(10, end);          // 2
  1908                         JMP_TARGET(emptysar);
  1909                         SAR_imm8_r32(31, R_EAX );  // 3
  1910                         JMP_rel8(5, end2);
  1912                         JMP_TARGET(doshl);
  1913                         AND_imm8_r8( 0x1F, R_CL ); // 3
  1914                         SHL_r32_CL( R_EAX );       // 2
  1915                         JMP_TARGET(end);
  1916                         JMP_TARGET(end2);
  1917                         store_reg( R_EAX, Rn );
  1919                         break;
  1920                     case 0xD:
  1921                         { /* SHLD Rm, Rn */
  1922                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1923                         load_reg( R_EAX, Rn );
  1924                         load_reg( R_ECX, Rm );
  1925                         CMP_imm32_r32( 0, R_ECX );
  1926                         JGE_rel8(15, doshl);
  1928                         NEG_r32( R_ECX );      // 2
  1929                         AND_imm8_r8( 0x1F, R_CL ); // 3
  1930                         JE_rel8( 4, emptyshr );
  1931                         SHR_r32_CL( R_EAX );       // 2
  1932                         JMP_rel8(9, end);          // 2
  1934                         JMP_TARGET(emptyshr);
  1935                         XOR_r32_r32( R_EAX, R_EAX );
  1936                         JMP_rel8(5, end2);
  1938                         JMP_TARGET(doshl);
  1939                         AND_imm8_r8( 0x1F, R_CL ); // 3
  1940                         SHL_r32_CL( R_EAX );       // 2
  1941                         JMP_TARGET(end);
  1942                         JMP_TARGET(end2);
  1943                         store_reg( R_EAX, Rn );
  1945                         break;
  1946                     case 0xE:
  1947                         switch( (ir&0x80) >> 7 ) {
  1948                             case 0x0:
  1949                                 switch( (ir&0x70) >> 4 ) {
  1950                                     case 0x0:
  1951                                         { /* LDC Rm, SR */
  1952                                         uint32_t Rm = ((ir>>8)&0xF); 
  1953                                         if( sh4_x86.in_delay_slot ) {
  1954                                     	SLOTILLEGAL();
  1955                                         } else {
  1956                                     	check_priv();
  1957                                     	load_reg( R_EAX, Rm );
  1958                                     	call_func1( sh4_write_sr, R_EAX );
  1959                                     	sh4_x86.priv_checked = FALSE;
  1960                                     	sh4_x86.fpuen_checked = FALSE;
  1963                                         break;
  1964                                     case 0x1:
  1965                                         { /* LDC Rm, GBR */
  1966                                         uint32_t Rm = ((ir>>8)&0xF); 
  1967                                         load_reg( R_EAX, Rm );
  1968                                         store_spreg( R_EAX, R_GBR );
  1970                                         break;
  1971                                     case 0x2:
  1972                                         { /* LDC Rm, VBR */
  1973                                         uint32_t Rm = ((ir>>8)&0xF); 
  1974                                         check_priv();
  1975                                         load_reg( R_EAX, Rm );
  1976                                         store_spreg( R_EAX, R_VBR );
  1978                                         break;
  1979                                     case 0x3:
  1980                                         { /* LDC Rm, SSR */
  1981                                         uint32_t Rm = ((ir>>8)&0xF); 
  1982                                         check_priv();
  1983                                         load_reg( R_EAX, Rm );
  1984                                         store_spreg( R_EAX, R_SSR );
  1986                                         break;
  1987                                     case 0x4:
  1988                                         { /* LDC Rm, SPC */
  1989                                         uint32_t Rm = ((ir>>8)&0xF); 
  1990                                         check_priv();
  1991                                         load_reg( R_EAX, Rm );
  1992                                         store_spreg( R_EAX, R_SPC );
  1994                                         break;
  1995                                     default:
  1996                                         UNDEF();
  1997                                         break;
  1999                                 break;
  2000                             case 0x1:
  2001                                 { /* LDC Rm, Rn_BANK */
  2002                                 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
  2003                                 check_priv();
  2004                                 load_reg( R_EAX, Rm );
  2005                                 store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
  2007                                 break;
  2009                         break;
  2010                     case 0xF:
  2011                         { /* MAC.W @Rm+, @Rn+ */
  2012                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2013                         load_reg( R_ECX, Rm );
  2014                         check_ralign16( R_ECX );
  2015                         load_reg( R_ECX, Rn );
  2016                         check_ralign16( R_ECX );
  2017                         ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
  2018                         MEM_READ_WORD( R_ECX, R_EAX );
  2019                         PUSH_r32( R_EAX );
  2020                         load_reg( R_ECX, Rm );
  2021                         ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
  2022                         MEM_READ_WORD( R_ECX, R_EAX );
  2023                         POP_r32( R_ECX );
  2024                         IMUL_r32( R_ECX );
  2026                         load_spreg( R_ECX, R_S );
  2027                         TEST_r32_r32( R_ECX, R_ECX );
  2028                         JE_rel8( 47, nosat );
  2030                         ADD_r32_sh4r( R_EAX, R_MACL );  // 6
  2031                         JNO_rel8( 51, end );            // 2
  2032                         load_imm32( R_EDX, 1 );         // 5
  2033                         store_spreg( R_EDX, R_MACH );   // 6
  2034                         JS_rel8( 13, positive );        // 2
  2035                         load_imm32( R_EAX, 0x80000000 );// 5
  2036                         store_spreg( R_EAX, R_MACL );   // 6
  2037                         JMP_rel8( 25, end2 );           // 2
  2039                         JMP_TARGET(positive);
  2040                         load_imm32( R_EAX, 0x7FFFFFFF );// 5
  2041                         store_spreg( R_EAX, R_MACL );   // 6
  2042                         JMP_rel8( 12, end3);            // 2
  2044                         JMP_TARGET(nosat);
  2045                         ADD_r32_sh4r( R_EAX, R_MACL );  // 6
  2046                         ADC_r32_sh4r( R_EDX, R_MACH );  // 6
  2047                         JMP_TARGET(end);
  2048                         JMP_TARGET(end2);
  2049                         JMP_TARGET(end3);
  2051                         break;
  2053                 break;
  2054             case 0x5:
  2055                 { /* MOV.L @(disp, Rm), Rn */
  2056                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
  2057                 load_reg( R_ECX, Rm );
  2058                 ADD_imm8s_r32( disp, R_ECX );
  2059                 check_ralign32( R_ECX );
  2060                 MEM_READ_LONG( R_ECX, R_EAX );
  2061                 store_reg( R_EAX, Rn );
  2063                 break;
  2064             case 0x6:
  2065                 switch( ir&0xF ) {
  2066                     case 0x0:
  2067                         { /* MOV.B @Rm, Rn */
  2068                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2069                         load_reg( R_ECX, Rm );
  2070                         MEM_READ_BYTE( R_ECX, R_EAX );
  2071                         store_reg( R_EAX, Rn );
  2073                         break;
  2074                     case 0x1:
  2075                         { /* MOV.W @Rm, Rn */
  2076                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2077                         load_reg( R_ECX, Rm );
  2078                         check_ralign16( R_ECX );
  2079                         MEM_READ_WORD( R_ECX, R_EAX );
  2080                         store_reg( R_EAX, Rn );
  2082                         break;
  2083                     case 0x2:
  2084                         { /* MOV.L @Rm, Rn */
  2085                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2086                         load_reg( R_ECX, Rm );
  2087                         check_ralign32( R_ECX );
  2088                         MEM_READ_LONG( R_ECX, R_EAX );
  2089                         store_reg( R_EAX, Rn );
  2091                         break;
  2092                     case 0x3:
  2093                         { /* MOV Rm, Rn */
  2094                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2095                         load_reg( R_EAX, Rm );
  2096                         store_reg( R_EAX, Rn );
  2098                         break;
  2099                     case 0x4:
  2100                         { /* MOV.B @Rm+, Rn */
  2101                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2102                         load_reg( R_ECX, Rm );
  2103                         MOV_r32_r32( R_ECX, R_EAX );
  2104                         ADD_imm8s_r32( 1, R_EAX );
  2105                         store_reg( R_EAX, Rm );
  2106                         MEM_READ_BYTE( R_ECX, R_EAX );
  2107                         store_reg( R_EAX, Rn );
  2109                         break;
  2110                     case 0x5:
  2111                         { /* MOV.W @Rm+, Rn */
  2112                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2113                         load_reg( R_EAX, Rm );
  2114                         check_ralign16( R_EAX );
  2115                         MOV_r32_r32( R_EAX, R_ECX );
  2116                         ADD_imm8s_r32( 2, R_EAX );
  2117                         store_reg( R_EAX, Rm );
  2118                         MEM_READ_WORD( R_ECX, R_EAX );
  2119                         store_reg( R_EAX, Rn );
  2121                         break;
  2122                     case 0x6:
  2123                         { /* MOV.L @Rm+, Rn */
  2124                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2125                         load_reg( R_EAX, Rm );
  2126                         check_ralign32( R_EAX );
  2127                         MOV_r32_r32( R_EAX, R_ECX );
  2128                         ADD_imm8s_r32( 4, R_EAX );
  2129                         store_reg( R_EAX, Rm );
  2130                         MEM_READ_LONG( R_ECX, R_EAX );
  2131                         store_reg( R_EAX, Rn );
  2133                         break;
  2134                     case 0x7:
  2135                         { /* NOT Rm, Rn */
  2136                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2137                         load_reg( R_EAX, Rm );
  2138                         NOT_r32( R_EAX );
  2139                         store_reg( R_EAX, Rn );
  2141                         break;
  2142                     case 0x8:
  2143                         { /* SWAP.B Rm, Rn */
  2144                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2145                         load_reg( R_EAX, Rm );
  2146                         XCHG_r8_r8( R_AL, R_AH );
  2147                         store_reg( R_EAX, Rn );
  2149                         break;
  2150                     case 0x9:
  2151                         { /* SWAP.W Rm, Rn */
  2152                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2153                         load_reg( R_EAX, Rm );
  2154                         MOV_r32_r32( R_EAX, R_ECX );
  2155                         SHL_imm8_r32( 16, R_ECX );
  2156                         SHR_imm8_r32( 16, R_EAX );
  2157                         OR_r32_r32( R_EAX, R_ECX );
  2158                         store_reg( R_ECX, Rn );
  2160                         break;
  2161                     case 0xA:
  2162                         { /* NEGC Rm, Rn */
  2163                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2164                         load_reg( R_EAX, Rm );
  2165                         XOR_r32_r32( R_ECX, R_ECX );
  2166                         LDC_t();
  2167                         SBB_r32_r32( R_EAX, R_ECX );
  2168                         store_reg( R_ECX, Rn );
  2169                         SETC_t();
  2171                         break;
  2172                     case 0xB:
  2173                         { /* NEG Rm, Rn */
  2174                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2175                         load_reg( R_EAX, Rm );
  2176                         NEG_r32( R_EAX );
  2177                         store_reg( R_EAX, Rn );
  2179                         break;
  2180                     case 0xC:
  2181                         { /* EXTU.B Rm, Rn */
  2182                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2183                         load_reg( R_EAX, Rm );
  2184                         MOVZX_r8_r32( R_EAX, R_EAX );
  2185                         store_reg( R_EAX, Rn );
  2187                         break;
  2188                     case 0xD:
  2189                         { /* EXTU.W Rm, Rn */
  2190                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2191                         load_reg( R_EAX, Rm );
  2192                         MOVZX_r16_r32( R_EAX, R_EAX );
  2193                         store_reg( R_EAX, Rn );
  2195                         break;
  2196                     case 0xE:
  2197                         { /* EXTS.B Rm, Rn */
  2198                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2199                         load_reg( R_EAX, Rm );
  2200                         MOVSX_r8_r32( R_EAX, R_EAX );
  2201                         store_reg( R_EAX, Rn );
  2203                         break;
  2204                     case 0xF:
  2205                         { /* EXTS.W Rm, Rn */
  2206                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2207                         load_reg( R_EAX, Rm );
  2208                         MOVSX_r16_r32( R_EAX, R_EAX );
  2209                         store_reg( R_EAX, Rn );
  2211                         break;
  2213                 break;
  2214             case 0x7:
  2215                 { /* ADD #imm, Rn */
  2216                 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
  2217                 load_reg( R_EAX, Rn );
  2218                 ADD_imm8s_r32( imm, R_EAX );
  2219                 store_reg( R_EAX, Rn );
  2221                 break;
  2222             case 0x8:
  2223                 switch( (ir&0xF00) >> 8 ) {
  2224                     case 0x0:
  2225                         { /* MOV.B R0, @(disp, Rn) */
  2226                         uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
  2227                         load_reg( R_EAX, 0 );
  2228                         load_reg( R_ECX, Rn );
  2229                         ADD_imm32_r32( disp, R_ECX );
  2230                         MEM_WRITE_BYTE( R_ECX, R_EAX );
  2232                         break;
  2233                     case 0x1:
  2234                         { /* MOV.W R0, @(disp, Rn) */
  2235                         uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
  2236                         load_reg( R_ECX, Rn );
  2237                         load_reg( R_EAX, 0 );
  2238                         ADD_imm32_r32( disp, R_ECX );
  2239                         check_walign16( R_ECX );
  2240                         MEM_WRITE_WORD( R_ECX, R_EAX );
  2242                         break;
  2243                     case 0x4:
  2244                         { /* MOV.B @(disp, Rm), R0 */
  2245                         uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
  2246                         load_reg( R_ECX, Rm );
  2247                         ADD_imm32_r32( disp, R_ECX );
  2248                         MEM_READ_BYTE( R_ECX, R_EAX );
  2249                         store_reg( R_EAX, 0 );
  2251                         break;
  2252                     case 0x5:
  2253                         { /* MOV.W @(disp, Rm), R0 */
  2254                         uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
  2255                         load_reg( R_ECX, Rm );
  2256                         ADD_imm32_r32( disp, R_ECX );
  2257                         check_ralign16( R_ECX );
  2258                         MEM_READ_WORD( R_ECX, R_EAX );
  2259                         store_reg( R_EAX, 0 );
  2261                         break;
  2262                     case 0x8:
  2263                         { /* CMP/EQ #imm, R0 */
  2264                         int32_t imm = SIGNEXT8(ir&0xFF); 
  2265                         load_reg( R_EAX, 0 );
  2266                         CMP_imm8s_r32(imm, R_EAX);
  2267                         SETE_t();
  2269                         break;
  2270                     case 0x9:
  2271                         { /* BT disp */
  2272                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  2273                         if( sh4_x86.in_delay_slot ) {
  2274                     	SLOTILLEGAL();
  2275                         } else {
  2276                     	CMP_imm8s_sh4r( 0, R_T );
  2277                     	JE_rel8( 30, nottaken );
  2278                     	exit_block( disp + pc + 4, pc+2 );
  2279                     	JMP_TARGET(nottaken);
  2280                     	exit_block( pc + 2, pc+2 );
  2281                     	return 2;
  2284                         break;
  2285                     case 0xB:
  2286                         { /* BF disp */
  2287                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  2288                         if( sh4_x86.in_delay_slot ) {
  2289                     	SLOTILLEGAL();
  2290                         } else {
  2291                     	CMP_imm8s_sh4r( 0, R_T );
  2292                     	JNE_rel8( 30, nottaken );
  2293                     	exit_block( disp + pc + 4, pc+2 );
  2294                     	JMP_TARGET(nottaken);
  2295                     	exit_block( pc + 2, pc + 2 );
  2296                     	return 2;
  2299                         break;
  2300                     case 0xD:
  2301                         { /* BT/S disp */
  2302                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  2303                         if( sh4_x86.in_delay_slot ) {
  2304                     	SLOTILLEGAL();
  2305                         } else {
  2306                     	sh4_x86.in_delay_slot = TRUE;
  2307                     	CMP_imm8s_sh4r( 0, R_T );
  2308                     	OP(0x0F); OP(0x84); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JE rel32
  2309                     	sh4_x86_translate_instruction(pc+2);
  2310                     	exit_block( disp + pc + 4, pc+4 );
  2311                     	// not taken
  2312                     	*patch = (xlat_output - ((uint8_t *)patch)) - 4;
  2313                     	sh4_x86_translate_instruction(pc+2);
  2314                     	exit_block( pc + 4, pc+4 );
  2315                     	return 4;
  2318                         break;
  2319                     case 0xF:
  2320                         { /* BF/S disp */
  2321                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  2322                         if( sh4_x86.in_delay_slot ) {
  2323                     	SLOTILLEGAL();
  2324                         } else {
  2325                     	sh4_x86.in_delay_slot = TRUE;
  2326                     	CMP_imm8s_sh4r( 0, R_T );
  2327                     	OP(0x0F); OP(0x85); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JNE rel32
  2328                     	sh4_x86_translate_instruction(pc+2);
  2329                     	exit_block( disp + pc + 4, pc+4 );
  2330                     	// not taken
  2331                     	*patch = (xlat_output - ((uint8_t *)patch)) - 4;
  2332                     	sh4_x86_translate_instruction(pc+2);
  2333                     	exit_block( pc + 4, pc+4 );
  2334                     	return 4;
  2337                         break;
  2338                     default:
  2339                         UNDEF();
  2340                         break;
  2342                 break;
  2343             case 0x9:
  2344                 { /* MOV.W @(disp, PC), Rn */
  2345                 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1; 
  2346                 if( sh4_x86.in_delay_slot ) {
  2347             	SLOTILLEGAL();
  2348                 } else {
  2349             	load_imm32( R_ECX, pc + disp + 4 );
  2350             	MEM_READ_WORD( R_ECX, R_EAX );
  2351             	store_reg( R_EAX, Rn );
  2354                 break;
  2355             case 0xA:
  2356                 { /* BRA disp */
  2357                 int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
  2358                 if( sh4_x86.in_delay_slot ) {
  2359             	SLOTILLEGAL();
  2360                 } else {
  2361             	sh4_x86.in_delay_slot = TRUE;
  2362             	sh4_x86_translate_instruction( pc + 2 );
  2363             	exit_block( disp + pc + 4, pc+4 );
  2364             	return 4;
  2367                 break;
  2368             case 0xB:
  2369                 { /* BSR disp */
  2370                 int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
  2371                 if( sh4_x86.in_delay_slot ) {
  2372             	SLOTILLEGAL();
  2373                 } else {
  2374             	load_imm32( R_EAX, pc + 4 );
  2375             	store_spreg( R_EAX, R_PR );
  2376             	sh4_x86.in_delay_slot = TRUE;
  2377             	sh4_x86_translate_instruction( pc + 2 );
  2378             	exit_block( disp + pc + 4, pc+4 );
  2379             	return 4;
  2382                 break;
  2383             case 0xC:
  2384                 switch( (ir&0xF00) >> 8 ) {
  2385                     case 0x0:
  2386                         { /* MOV.B R0, @(disp, GBR) */
  2387                         uint32_t disp = (ir&0xFF); 
  2388                         load_reg( R_EAX, 0 );
  2389                         load_spreg( R_ECX, R_GBR );
  2390                         ADD_imm32_r32( disp, R_ECX );
  2391                         MEM_WRITE_BYTE( R_ECX, R_EAX );
  2393                         break;
  2394                     case 0x1:
  2395                         { /* MOV.W R0, @(disp, GBR) */
  2396                         uint32_t disp = (ir&0xFF)<<1; 
  2397                         load_spreg( R_ECX, R_GBR );
  2398                         load_reg( R_EAX, 0 );
  2399                         ADD_imm32_r32( disp, R_ECX );
  2400                         check_walign16( R_ECX );
  2401                         MEM_WRITE_WORD( R_ECX, R_EAX );
  2403                         break;
  2404                     case 0x2:
  2405                         { /* MOV.L R0, @(disp, GBR) */
  2406                         uint32_t disp = (ir&0xFF)<<2; 
  2407                         load_spreg( R_ECX, R_GBR );
  2408                         load_reg( R_EAX, 0 );
  2409                         ADD_imm32_r32( disp, R_ECX );
  2410                         check_walign32( R_ECX );
  2411                         MEM_WRITE_LONG( R_ECX, R_EAX );
  2413                         break;
  2414                     case 0x3:
  2415                         { /* TRAPA #imm */
  2416                         uint32_t imm = (ir&0xFF); 
  2417                         if( sh4_x86.in_delay_slot ) {
  2418                     	SLOTILLEGAL();
  2419                         } else {
  2420                     	PUSH_imm32( imm );
  2421                     	call_func0( sh4_raise_trap );
  2422                     	ADD_imm8s_r32( 4, R_ESP );
  2423                     	exit_block_pcset(pc);
  2424                     	return 2;
  2427                         break;
  2428                     case 0x4:
  2429                         { /* MOV.B @(disp, GBR), R0 */
  2430                         uint32_t disp = (ir&0xFF); 
  2431                         load_spreg( R_ECX, R_GBR );
  2432                         ADD_imm32_r32( disp, R_ECX );
  2433                         MEM_READ_BYTE( R_ECX, R_EAX );
  2434                         store_reg( R_EAX, 0 );
  2436                         break;
  2437                     case 0x5:
  2438                         { /* MOV.W @(disp, GBR), R0 */
  2439                         uint32_t disp = (ir&0xFF)<<1; 
  2440                         load_spreg( R_ECX, R_GBR );
  2441                         ADD_imm32_r32( disp, R_ECX );
  2442                         check_ralign16( R_ECX );
  2443                         MEM_READ_WORD( R_ECX, R_EAX );
  2444                         store_reg( R_EAX, 0 );
  2446                         break;
  2447                     case 0x6:
  2448                         { /* MOV.L @(disp, GBR), R0 */
  2449                         uint32_t disp = (ir&0xFF)<<2; 
  2450                         load_spreg( R_ECX, R_GBR );
  2451                         ADD_imm32_r32( disp, R_ECX );
  2452                         check_ralign32( R_ECX );
  2453                         MEM_READ_LONG( R_ECX, R_EAX );
  2454                         store_reg( R_EAX, 0 );
  2456                         break;
  2457                     case 0x7:
  2458                         { /* MOVA @(disp, PC), R0 */
  2459                         uint32_t disp = (ir&0xFF)<<2; 
  2460                         if( sh4_x86.in_delay_slot ) {
  2461                     	SLOTILLEGAL();
  2462                         } else {
  2463                     	load_imm32( R_ECX, (pc & 0xFFFFFFFC) + disp + 4 );
  2464                     	store_reg( R_ECX, 0 );
  2467                         break;
  2468                     case 0x8:
  2469                         { /* TST #imm, R0 */
  2470                         uint32_t imm = (ir&0xFF); 
  2471                         load_reg( R_EAX, 0 );
  2472                         TEST_imm32_r32( imm, R_EAX );
  2473                         SETE_t();
  2475                         break;
  2476                     case 0x9:
  2477                         { /* AND #imm, R0 */
  2478                         uint32_t imm = (ir&0xFF); 
  2479                         load_reg( R_EAX, 0 );
  2480                         AND_imm32_r32(imm, R_EAX); 
  2481                         store_reg( R_EAX, 0 );
  2483                         break;
  2484                     case 0xA:
  2485                         { /* XOR #imm, R0 */
  2486                         uint32_t imm = (ir&0xFF); 
  2487                         load_reg( R_EAX, 0 );
  2488                         XOR_imm32_r32( imm, R_EAX );
  2489                         store_reg( R_EAX, 0 );
  2491                         break;
  2492                     case 0xB:
  2493                         { /* OR #imm, R0 */
  2494                         uint32_t imm = (ir&0xFF); 
  2495                         load_reg( R_EAX, 0 );
  2496                         OR_imm32_r32(imm, R_EAX);
  2497                         store_reg( R_EAX, 0 );
  2499                         break;
  2500                     case 0xC:
  2501                         { /* TST.B #imm, @(R0, GBR) */
  2502                         uint32_t imm = (ir&0xFF); 
  2503                         load_reg( R_EAX, 0);
  2504                         load_reg( R_ECX, R_GBR);
  2505                         ADD_r32_r32( R_EAX, R_ECX );
  2506                         MEM_READ_BYTE( R_ECX, R_EAX );
  2507                         TEST_imm8_r8( imm, R_AL );
  2508                         SETE_t();
  2510                         break;
  2511                     case 0xD:
  2512                         { /* AND.B #imm, @(R0, GBR) */
  2513                         uint32_t imm = (ir&0xFF); 
  2514                         load_reg( R_EAX, 0 );
  2515                         load_spreg( R_ECX, R_GBR );
  2516                         ADD_r32_r32( R_EAX, R_ECX );
  2517                         PUSH_r32(R_ECX);
  2518                         call_func0(sh4_read_byte);
  2519                         POP_r32(R_ECX);
  2520                         AND_imm32_r32(imm, R_EAX );
  2521                         MEM_WRITE_BYTE( R_ECX, R_EAX );
  2523                         break;
  2524                     case 0xE:
  2525                         { /* XOR.B #imm, @(R0, GBR) */
  2526                         uint32_t imm = (ir&0xFF); 
  2527                         load_reg( R_EAX, 0 );
  2528                         load_spreg( R_ECX, R_GBR );
  2529                         ADD_r32_r32( R_EAX, R_ECX );
  2530                         PUSH_r32(R_ECX);
  2531                         call_func0(sh4_read_byte);
  2532                         POP_r32(R_ECX);
  2533                         XOR_imm32_r32( imm, R_EAX );
  2534                         MEM_WRITE_BYTE( R_ECX, R_EAX );
  2536                         break;
  2537                     case 0xF:
  2538                         { /* OR.B #imm, @(R0, GBR) */
  2539                         uint32_t imm = (ir&0xFF); 
  2540                         load_reg( R_EAX, 0 );
  2541                         load_spreg( R_ECX, R_GBR );
  2542                         ADD_r32_r32( R_EAX, R_ECX );
  2543                         PUSH_r32(R_ECX);
  2544                         call_func0(sh4_read_byte);
  2545                         POP_r32(R_ECX);
  2546                         OR_imm32_r32(imm, R_EAX );
  2547                         MEM_WRITE_BYTE( R_ECX, R_EAX );
  2549                         break;
  2551                 break;
  2552             case 0xD:
  2553                 { /* MOV.L @(disp, PC), Rn */
  2554                 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<2; 
  2555                 if( sh4_x86.in_delay_slot ) {
  2556             	SLOTILLEGAL();
  2557                 } else {
  2558             	uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
  2559             	char *ptr = mem_get_region(target);
  2560             	if( ptr != NULL ) {
  2561             	    MOV_moff32_EAX( (uint32_t)ptr );
  2562             	} else {
  2563             	    load_imm32( R_ECX, target );
  2564             	    MEM_READ_LONG( R_ECX, R_EAX );
  2566             	store_reg( R_EAX, Rn );
  2569                 break;
  2570             case 0xE:
  2571                 { /* MOV #imm, Rn */
  2572                 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
  2573                 load_imm32( R_EAX, imm );
  2574                 store_reg( R_EAX, Rn );
  2576                 break;
  2577             case 0xF:
  2578                 switch( ir&0xF ) {
  2579                     case 0x0:
  2580                         { /* FADD FRm, FRn */
  2581                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2582                         check_fpuen();
  2583                         load_spreg( R_ECX, R_FPSCR );
  2584                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  2585                         load_fr_bank( R_EDX );
  2586                         JNE_rel8(13,doubleprec);
  2587                         push_fr(R_EDX, FRm);
  2588                         push_fr(R_EDX, FRn);
  2589                         FADDP_st(1);
  2590                         pop_fr(R_EDX, FRn);
  2591                         JMP_rel8(11,end);
  2592                         JMP_TARGET(doubleprec);
  2593                         push_dr(R_EDX, FRm);
  2594                         push_dr(R_EDX, FRn);
  2595                         FADDP_st(1);
  2596                         pop_dr(R_EDX, FRn);
  2597                         JMP_TARGET(end);
  2599                         break;
  2600                     case 0x1:
  2601                         { /* FSUB FRm, FRn */
  2602                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2603                         check_fpuen();
  2604                         load_spreg( R_ECX, R_FPSCR );
  2605                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  2606                         load_fr_bank( R_EDX );
  2607                         JNE_rel8(13, doubleprec);
  2608                         push_fr(R_EDX, FRn);
  2609                         push_fr(R_EDX, FRm);
  2610                         FSUBP_st(1);
  2611                         pop_fr(R_EDX, FRn);
  2612                         JMP_rel8(11, end);
  2613                         JMP_TARGET(doubleprec);
  2614                         push_dr(R_EDX, FRn);
  2615                         push_dr(R_EDX, FRm);
  2616                         FSUBP_st(1);
  2617                         pop_dr(R_EDX, FRn);
  2618                         JMP_TARGET(end);
  2620                         break;
  2621                     case 0x2:
  2622                         { /* FMUL FRm, FRn */
  2623                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2624                         check_fpuen();
  2625                         load_spreg( R_ECX, R_FPSCR );
  2626                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  2627                         load_fr_bank( R_EDX );
  2628                         JNE_rel8(13, doubleprec);
  2629                         push_fr(R_EDX, FRm);
  2630                         push_fr(R_EDX, FRn);
  2631                         FMULP_st(1);
  2632                         pop_fr(R_EDX, FRn);
  2633                         JMP_rel8(11, end);
  2634                         JMP_TARGET(doubleprec);
  2635                         push_dr(R_EDX, FRm);
  2636                         push_dr(R_EDX, FRn);
  2637                         FMULP_st(1);
  2638                         pop_dr(R_EDX, FRn);
  2639                         JMP_TARGET(end);
  2641                         break;
  2642                     case 0x3:
  2643                         { /* FDIV FRm, FRn */
  2644                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2645                         check_fpuen();
  2646                         load_spreg( R_ECX, R_FPSCR );
  2647                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  2648                         load_fr_bank( R_EDX );
  2649                         JNE_rel8(13, doubleprec);
  2650                         push_fr(R_EDX, FRn);
  2651                         push_fr(R_EDX, FRm);
  2652                         FDIVP_st(1);
  2653                         pop_fr(R_EDX, FRn);
  2654                         JMP_rel8(11, end);
  2655                         JMP_TARGET(doubleprec);
  2656                         push_dr(R_EDX, FRn);
  2657                         push_dr(R_EDX, FRm);
  2658                         FDIVP_st(1);
  2659                         pop_dr(R_EDX, FRn);
  2660                         JMP_TARGET(end);
  2662                         break;
  2663                     case 0x4:
  2664                         { /* FCMP/EQ FRm, FRn */
  2665                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2666                         check_fpuen();
  2667                         load_spreg( R_ECX, R_FPSCR );
  2668                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  2669                         load_fr_bank( R_EDX );
  2670                         JNE_rel8(8, doubleprec);
  2671                         push_fr(R_EDX, FRm);
  2672                         push_fr(R_EDX, FRn);
  2673                         JMP_rel8(6, end);
  2674                         JMP_TARGET(doubleprec);
  2675                         push_dr(R_EDX, FRm);
  2676                         push_dr(R_EDX, FRn);
  2677                         JMP_TARGET(end);
  2678                         FCOMIP_st(1);
  2679                         SETE_t();
  2680                         FPOP_st();
  2682                         break;
  2683                     case 0x5:
  2684                         { /* FCMP/GT FRm, FRn */
  2685                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2686                         check_fpuen();
  2687                         load_spreg( R_ECX, R_FPSCR );
  2688                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  2689                         load_fr_bank( R_EDX );
  2690                         JNE_rel8(8, doubleprec);
  2691                         push_fr(R_EDX, FRm);
  2692                         push_fr(R_EDX, FRn);
  2693                         JMP_rel8(6, end);
  2694                         JMP_TARGET(doubleprec);
  2695                         push_dr(R_EDX, FRm);
  2696                         push_dr(R_EDX, FRn);
  2697                         JMP_TARGET(end);
  2698                         FCOMIP_st(1);
  2699                         SETA_t();
  2700                         FPOP_st();
  2702                         break;
  2703                     case 0x6:
  2704                         { /* FMOV @(R0, Rm), FRn */
  2705                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2706                         check_fpuen();
  2707                         load_reg( R_EDX, Rm );
  2708                         ADD_sh4r_r32( REG_OFFSET(r[0]), R_EDX );
  2709                         check_ralign32( R_EDX );
  2710                         load_spreg( R_ECX, R_FPSCR );
  2711                         TEST_imm32_r32( FPSCR_SZ, R_ECX );
  2712                         JNE_rel8(19, doublesize);
  2713                         MEM_READ_LONG( R_EDX, R_EAX );
  2714                         load_fr_bank( R_ECX );
  2715                         store_fr( R_ECX, R_EAX, FRn );
  2716                         if( FRn&1 ) {
  2717                     	JMP_rel8(48, end);
  2718                     	JMP_TARGET(doublesize);
  2719                     	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
  2720                     	load_spreg( R_ECX, R_FPSCR ); // assume read_long clobbered it
  2721                     	load_xf_bank( R_ECX );
  2722                     	store_fr( R_ECX, R_EAX, FRn&0x0E );
  2723                     	store_fr( R_ECX, R_EDX, FRn|0x01 );
  2724                     	JMP_TARGET(end);
  2725                         } else {
  2726                     	JMP_rel8(36, end);
  2727                     	JMP_TARGET(doublesize);
  2728                     	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
  2729                     	load_fr_bank( R_ECX );
  2730                     	store_fr( R_ECX, R_EAX, FRn&0x0E );
  2731                     	store_fr( R_ECX, R_EDX, FRn|0x01 );
  2732                     	JMP_TARGET(end);
  2735                         break;
  2736                     case 0x7:
  2737                         { /* FMOV FRm, @(R0, Rn) */
  2738                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2739                         check_fpuen();
  2740                         load_reg( R_EDX, Rn );
  2741                         ADD_sh4r_r32( REG_OFFSET(r[0]), R_EDX );
  2742                         check_walign32( R_EDX );
  2743                         load_spreg( R_ECX, R_FPSCR );
  2744                         TEST_imm32_r32( FPSCR_SZ, R_ECX );
  2745                         JNE_rel8(20, doublesize);
  2746                         load_fr_bank( R_ECX );
  2747                         load_fr( R_ECX, R_EAX, FRm );
  2748                         MEM_WRITE_LONG( R_EDX, R_EAX ); // 12
  2749                         if( FRm&1 ) {
  2750                     	JMP_rel8( 48, end );
  2751                     	JMP_TARGET(doublesize);
  2752                     	load_xf_bank( R_ECX );
  2753                     	load_fr( R_ECX, R_EAX, FRm&0x0E );
  2754                     	load_fr( R_ECX, R_ECX, FRm|0x01 );
  2755                     	MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
  2756                     	JMP_TARGET(end);
  2757                         } else {
  2758                     	JMP_rel8( 39, end );
  2759                     	JMP_TARGET(doublesize);
  2760                     	load_fr_bank( R_ECX );
  2761                     	load_fr( R_ECX, R_EAX, FRm&0x0E );
  2762                     	load_fr( R_ECX, R_ECX, FRm|0x01 );
  2763                     	MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
  2764                     	JMP_TARGET(end);
  2767                         break;
  2768                     case 0x8:
  2769                         { /* FMOV @Rm, FRn */
  2770                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2771                         check_fpuen();
  2772                         load_reg( R_EDX, Rm );
  2773                         check_ralign32( R_EDX );
  2774                         load_spreg( R_ECX, R_FPSCR );
  2775                         TEST_imm32_r32( FPSCR_SZ, R_ECX );
  2776                         JNE_rel8(19, doublesize);
  2777                         MEM_READ_LONG( R_EDX, R_EAX );
  2778                         load_fr_bank( R_ECX );
  2779                         store_fr( R_ECX, R_EAX, FRn );
  2780                         if( FRn&1 ) {
  2781                     	JMP_rel8(48, end);
  2782                     	JMP_TARGET(doublesize);
  2783                     	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
  2784                     	load_spreg( R_ECX, R_FPSCR ); // assume read_long clobbered it
  2785                     	load_xf_bank( R_ECX );
  2786                     	store_fr( R_ECX, R_EAX, FRn&0x0E );
  2787                     	store_fr( R_ECX, R_EDX, FRn|0x01 );
  2788                     	JMP_TARGET(end);
  2789                         } else {
  2790                     	JMP_rel8(36, end);
  2791                     	JMP_TARGET(doublesize);
  2792                     	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
  2793                     	load_fr_bank( R_ECX );
  2794                     	store_fr( R_ECX, R_EAX, FRn&0x0E );
  2795                     	store_fr( R_ECX, R_EDX, FRn|0x01 );
  2796                     	JMP_TARGET(end);
  2799                         break;
  2800                     case 0x9:
  2801                         { /* FMOV @Rm+, FRn */
  2802                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2803                         check_fpuen();
  2804                         load_reg( R_EDX, Rm );
  2805                         check_ralign32( R_EDX );
  2806                         MOV_r32_r32( R_EDX, R_EAX );
  2807                         load_spreg( R_ECX, R_FPSCR );
  2808                         TEST_imm32_r32( FPSCR_SZ, R_ECX );
  2809                         JNE_rel8(25, doublesize);
  2810                         ADD_imm8s_r32( 4, R_EAX );
  2811                         store_reg( R_EAX, Rm );
  2812                         MEM_READ_LONG( R_EDX, R_EAX );
  2813                         load_fr_bank( R_ECX );
  2814                         store_fr( R_ECX, R_EAX, FRn );
  2815                         if( FRn&1 ) {
  2816                     	JMP_rel8(54, end);
  2817                     	JMP_TARGET(doublesize);
  2818                     	ADD_imm8s_r32( 8, R_EAX );
  2819                     	store_reg(R_EAX, Rm);
  2820                     	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
  2821                     	load_spreg( R_ECX, R_FPSCR ); // assume read_long clobbered it
  2822                     	load_xf_bank( R_ECX );
  2823                     	store_fr( R_ECX, R_EAX, FRn&0x0E );
  2824                     	store_fr( R_ECX, R_EDX, FRn|0x01 );
  2825                     	JMP_TARGET(end);
  2826                         } else {
  2827                     	JMP_rel8(42, end);
  2828                     	ADD_imm8s_r32( 8, R_EAX );
  2829                     	store_reg(R_EAX, Rm);
  2830                     	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
  2831                     	load_fr_bank( R_ECX );
  2832                     	store_fr( R_ECX, R_EAX, FRn&0x0E );
  2833                     	store_fr( R_ECX, R_EDX, FRn|0x01 );
  2834                     	JMP_TARGET(end);
  2837                         break;
  2838                     case 0xA:
  2839                         { /* FMOV FRm, @Rn */
  2840                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2841                         check_fpuen();
  2842                         load_reg( R_EDX, Rn );
  2843                         check_walign32( R_EDX );
  2844                         load_spreg( R_ECX, R_FPSCR );
  2845                         TEST_imm32_r32( FPSCR_SZ, R_ECX );
  2846                         JNE_rel8(20, doublesize);
  2847                         load_fr_bank( R_ECX );
  2848                         load_fr( R_ECX, R_EAX, FRm );
  2849                         MEM_WRITE_LONG( R_EDX, R_EAX ); // 12
  2850                         if( FRm&1 ) {
  2851                     	JMP_rel8( 48, end );
  2852                     	JMP_TARGET(doublesize);
  2853                     	load_xf_bank( R_ECX );
  2854                     	load_fr( R_ECX, R_EAX, FRm&0x0E );
  2855                     	load_fr( R_ECX, R_ECX, FRm|0x01 );
  2856                     	MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
  2857                     	JMP_TARGET(end);
  2858                         } else {
  2859                     	JMP_rel8( 39, end );
  2860                     	JMP_TARGET(doublesize);
  2861                     	load_fr_bank( R_ECX );
  2862                     	load_fr( R_ECX, R_EAX, FRm&0x0E );
  2863                     	load_fr( R_ECX, R_ECX, FRm|0x01 );
  2864                     	MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
  2865                     	JMP_TARGET(end);
  2868                         break;
  2869                     case 0xB:
  2870                         { /* FMOV FRm, @-Rn */
  2871                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2872                         check_fpuen();
  2873                         load_reg( R_EDX, Rn );
  2874                         check_walign32( R_EDX );
  2875                         load_spreg( R_ECX, R_FPSCR );
  2876                         TEST_imm32_r32( FPSCR_SZ, R_ECX );
  2877                         JNE_rel8(26, doublesize);
  2878                         load_fr_bank( R_ECX );
  2879                         load_fr( R_ECX, R_EAX, FRm );
  2880                         ADD_imm8s_r32(-4,R_EDX);
  2881                         store_reg( R_EDX, Rn );
  2882                         MEM_WRITE_LONG( R_EDX, R_EAX ); // 12
  2883                         if( FRm&1 ) {
  2884                     	JMP_rel8( 54, end );
  2885                     	JMP_TARGET(doublesize);
  2886                     	load_xf_bank( R_ECX );
  2887                     	load_fr( R_ECX, R_EAX, FRm&0x0E );
  2888                     	load_fr( R_ECX, R_ECX, FRm|0x01 );
  2889                     	ADD_imm8s_r32(-8,R_EDX);
  2890                     	store_reg( R_EDX, Rn );
  2891                     	MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
  2892                     	JMP_TARGET(end);
  2893                         } else {
  2894                     	JMP_rel8( 45, end );
  2895                     	JMP_TARGET(doublesize);
  2896                     	load_fr_bank( R_ECX );
  2897                     	load_fr( R_ECX, R_EAX, FRm&0x0E );
  2898                     	load_fr( R_ECX, R_ECX, FRm|0x01 );
  2899                     	ADD_imm8s_r32(-8,R_EDX);
  2900                     	store_reg( R_EDX, Rn );
  2901                     	MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
  2902                     	JMP_TARGET(end);
  2905                         break;
  2906                     case 0xC:
  2907                         { /* FMOV FRm, FRn */
  2908                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2909                         /* As horrible as this looks, it's actually covering 5 separate cases:
  2910                          * 1. 32-bit fr-to-fr (PR=0)
  2911                          * 2. 64-bit dr-to-dr (PR=1, FRm&1 == 0, FRn&1 == 0 )
  2912                          * 3. 64-bit dr-to-xd (PR=1, FRm&1 == 0, FRn&1 == 1 )
  2913                          * 4. 64-bit xd-to-dr (PR=1, FRm&1 == 1, FRn&1 == 0 )
  2914                          * 5. 64-bit xd-to-xd (PR=1, FRm&1 == 1, FRn&1 == 1 )
  2915                          */
  2916                         check_fpuen();
  2917                         load_spreg( R_ECX, R_FPSCR );
  2918                         load_fr_bank( R_EDX );
  2919                         TEST_imm32_r32( FPSCR_SZ, R_ECX );
  2920                         JNE_rel8(8, doublesize);
  2921                         load_fr( R_EDX, R_EAX, FRm ); // PR=0 branch
  2922                         store_fr( R_EDX, R_EAX, FRn );
  2923                         if( FRm&1 ) {
  2924                     	JMP_rel8(24, end);
  2925                     	JMP_TARGET(doublesize);
  2926                     	load_xf_bank( R_ECX ); 
  2927                     	load_fr( R_ECX, R_EAX, FRm-1 );
  2928                     	if( FRn&1 ) {
  2929                     	    load_fr( R_ECX, R_EDX, FRm );
  2930                     	    store_fr( R_ECX, R_EAX, FRn-1 );
  2931                     	    store_fr( R_ECX, R_EDX, FRn );
  2932                     	} else /* FRn&1 == 0 */ {
  2933                     	    load_fr( R_ECX, R_ECX, FRm );
  2934                     	    store_fr( R_EDX, R_EAX, FRn );
  2935                     	    store_fr( R_EDX, R_ECX, FRn+1 );
  2937                     	JMP_TARGET(end);
  2938                         } else /* FRm&1 == 0 */ {
  2939                     	if( FRn&1 ) {
  2940                     	    JMP_rel8(24, end);
  2941                     	    load_xf_bank( R_ECX );
  2942                     	    load_fr( R_EDX, R_EAX, FRm );
  2943                     	    load_fr( R_EDX, R_EDX, FRm+1 );
  2944                     	    store_fr( R_ECX, R_EAX, FRn-1 );
  2945                     	    store_fr( R_ECX, R_EDX, FRn );
  2946                     	    JMP_TARGET(end);
  2947                     	} else /* FRn&1 == 0 */ {
  2948                     	    JMP_rel8(12, end);
  2949                     	    load_fr( R_EDX, R_EAX, FRm );
  2950                     	    load_fr( R_EDX, R_ECX, FRm+1 );
  2951                     	    store_fr( R_EDX, R_EAX, FRn );
  2952                     	    store_fr( R_EDX, R_ECX, FRn+1 );
  2953                     	    JMP_TARGET(end);
  2957                         break;
  2958                     case 0xD:
  2959                         switch( (ir&0xF0) >> 4 ) {
  2960                             case 0x0:
  2961                                 { /* FSTS FPUL, FRn */
  2962                                 uint32_t FRn = ((ir>>8)&0xF); 
  2963                                 check_fpuen();
  2964                                 load_fr_bank( R_ECX );
  2965                                 load_spreg( R_EAX, R_FPUL );
  2966                                 store_fr( R_ECX, R_EAX, FRn );
  2968                                 break;
  2969                             case 0x1:
  2970                                 { /* FLDS FRm, FPUL */
  2971                                 uint32_t FRm = ((ir>>8)&0xF); 
  2972                                 check_fpuen();
  2973                                 load_fr_bank( R_ECX );
  2974                                 load_fr( R_ECX, R_EAX, FRm );
  2975                                 store_spreg( R_EAX, R_FPUL );
  2977                                 break;
  2978                             case 0x2:
  2979                                 { /* FLOAT FPUL, FRn */
  2980                                 uint32_t FRn = ((ir>>8)&0xF); 
  2981                                 check_fpuen();
  2982                                 load_spreg( R_ECX, R_FPSCR );
  2983                                 load_spreg(R_EDX, REG_OFFSET(fr_bank));
  2984                                 FILD_sh4r(R_FPUL);
  2985                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  2986                                 JNE_rel8(5, doubleprec);
  2987                                 pop_fr( R_EDX, FRn );
  2988                                 JMP_rel8(3, end);
  2989                                 JMP_TARGET(doubleprec);
  2990                                 pop_dr( R_EDX, FRn );
  2991                                 JMP_TARGET(end);
  2993                                 break;
  2994                             case 0x3:
  2995                                 { /* FTRC FRm, FPUL */
  2996                                 uint32_t FRm = ((ir>>8)&0xF); 
  2997                                 check_fpuen();
  2998                                 load_spreg( R_ECX, R_FPSCR );
  2999                                 load_fr_bank( R_EDX );
  3000                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3001                                 JNE_rel8(5, doubleprec);
  3002                                 push_fr( R_EDX, FRm );
  3003                                 JMP_rel8(3, doop);
  3004                                 JMP_TARGET(doubleprec);
  3005                                 push_dr( R_EDX, FRm );
  3006                                 JMP_TARGET( doop );
  3007                                 load_imm32( R_ECX, (uint32_t)&max_int );
  3008                                 FILD_r32ind( R_ECX );
  3009                                 FCOMIP_st(1);
  3010                                 JNA_rel8( 32, sat );
  3011                                 load_imm32( R_ECX, (uint32_t)&min_int );  // 5
  3012                                 FILD_r32ind( R_ECX );           // 2
  3013                                 FCOMIP_st(1);                   // 2
  3014                                 JAE_rel8( 21, sat2 );            // 2
  3015                                 load_imm32( R_EAX, (uint32_t)&save_fcw );
  3016                                 FNSTCW_r32ind( R_EAX );
  3017                                 load_imm32( R_EDX, (uint32_t)&trunc_fcw );
  3018                                 FLDCW_r32ind( R_EDX );
  3019                                 FISTP_sh4r(R_FPUL);             // 3
  3020                                 FLDCW_r32ind( R_EAX );
  3021                                 JMP_rel8( 9, end );             // 2
  3023                                 JMP_TARGET(sat);
  3024                                 JMP_TARGET(sat2);
  3025                                 MOV_r32ind_r32( R_ECX, R_ECX ); // 2
  3026                                 store_spreg( R_ECX, R_FPUL );
  3027                                 FPOP_st();
  3028                                 JMP_TARGET(end);
  3030                                 break;
  3031                             case 0x4:
  3032                                 { /* FNEG FRn */
  3033                                 uint32_t FRn = ((ir>>8)&0xF); 
  3034                                 check_fpuen();
  3035                                 load_spreg( R_ECX, R_FPSCR );
  3036                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3037                                 load_fr_bank( R_EDX );
  3038                                 JNE_rel8(10, doubleprec);
  3039                                 push_fr(R_EDX, FRn);
  3040                                 FCHS_st0();
  3041                                 pop_fr(R_EDX, FRn);
  3042                                 JMP_rel8(8, end);
  3043                                 JMP_TARGET(doubleprec);
  3044                                 push_dr(R_EDX, FRn);
  3045                                 FCHS_st0();
  3046                                 pop_dr(R_EDX, FRn);
  3047                                 JMP_TARGET(end);
  3049                                 break;
  3050                             case 0x5:
  3051                                 { /* FABS FRn */
  3052                                 uint32_t FRn = ((ir>>8)&0xF); 
  3053                                 check_fpuen();
  3054                                 load_spreg( R_ECX, R_FPSCR );
  3055                                 load_fr_bank( R_EDX );
  3056                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3057                                 JNE_rel8(10, doubleprec);
  3058                                 push_fr(R_EDX, FRn); // 3
  3059                                 FABS_st0(); // 2
  3060                                 pop_fr( R_EDX, FRn); //3
  3061                                 JMP_rel8(8,end); // 2
  3062                                 JMP_TARGET(doubleprec);
  3063                                 push_dr(R_EDX, FRn);
  3064                                 FABS_st0();
  3065                                 pop_dr(R_EDX, FRn);
  3066                                 JMP_TARGET(end);
  3068                                 break;
  3069                             case 0x6:
  3070                                 { /* FSQRT FRn */
  3071                                 uint32_t FRn = ((ir>>8)&0xF); 
  3072                                 check_fpuen();
  3073                                 load_spreg( R_ECX, R_FPSCR );
  3074                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3075                                 load_fr_bank( R_EDX );
  3076                                 JNE_rel8(10, doubleprec);
  3077                                 push_fr(R_EDX, FRn);
  3078                                 FSQRT_st0();
  3079                                 pop_fr(R_EDX, FRn);
  3080                                 JMP_rel8(8, end);
  3081                                 JMP_TARGET(doubleprec);
  3082                                 push_dr(R_EDX, FRn);
  3083                                 FSQRT_st0();
  3084                                 pop_dr(R_EDX, FRn);
  3085                                 JMP_TARGET(end);
  3087                                 break;
  3088                             case 0x7:
  3089                                 { /* FSRRA FRn */
  3090                                 uint32_t FRn = ((ir>>8)&0xF); 
  3091                                 check_fpuen();
  3092                                 load_spreg( R_ECX, R_FPSCR );
  3093                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3094                                 load_fr_bank( R_EDX );
  3095                                 JNE_rel8(12, end); // PR=0 only
  3096                                 FLD1_st0();
  3097                                 push_fr(R_EDX, FRn);
  3098                                 FSQRT_st0();
  3099                                 FDIVP_st(1);
  3100                                 pop_fr(R_EDX, FRn);
  3101                                 JMP_TARGET(end);
  3103                                 break;
  3104                             case 0x8:
  3105                                 { /* FLDI0 FRn */
  3106                                 uint32_t FRn = ((ir>>8)&0xF); 
  3107                                 /* IFF PR=0 */
  3108                                   check_fpuen();
  3109                                   load_spreg( R_ECX, R_FPSCR );
  3110                                   TEST_imm32_r32( FPSCR_PR, R_ECX );
  3111                                   JNE_rel8(8, end);
  3112                                   XOR_r32_r32( R_EAX, R_EAX );
  3113                                   load_spreg( R_ECX, REG_OFFSET(fr_bank) );
  3114                                   store_fr( R_ECX, R_EAX, FRn );
  3115                                   JMP_TARGET(end);
  3117                                 break;
  3118                             case 0x9:
  3119                                 { /* FLDI1 FRn */
  3120                                 uint32_t FRn = ((ir>>8)&0xF); 
  3121                                 /* IFF PR=0 */
  3122                                   check_fpuen();
  3123                                   load_spreg( R_ECX, R_FPSCR );
  3124                                   TEST_imm32_r32( FPSCR_PR, R_ECX );
  3125                                   JNE_rel8(11, end);
  3126                                   load_imm32(R_EAX, 0x3F800000);
  3127                                   load_spreg( R_ECX, REG_OFFSET(fr_bank) );
  3128                                   store_fr( R_ECX, R_EAX, FRn );
  3129                                   JMP_TARGET(end);
  3131                                 break;
  3132                             case 0xA:
  3133                                 { /* FCNVSD FPUL, FRn */
  3134                                 uint32_t FRn = ((ir>>8)&0xF); 
  3135                                 check_fpuen();
  3136                                 load_spreg( R_ECX, R_FPSCR );
  3137                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3138                                 JE_rel8(9, end); // only when PR=1
  3139                                 load_fr_bank( R_ECX );
  3140                                 push_fpul();
  3141                                 pop_dr( R_ECX, FRn );
  3142                                 JMP_TARGET(end);
  3144                                 break;
  3145                             case 0xB:
  3146                                 { /* FCNVDS FRm, FPUL */
  3147                                 uint32_t FRm = ((ir>>8)&0xF); 
  3148                                 check_fpuen();
  3149                                 load_spreg( R_ECX, R_FPSCR );
  3150                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3151                                 JE_rel8(9, end); // only when PR=1
  3152                                 load_fr_bank( R_ECX );
  3153                                 push_dr( R_ECX, FRm );
  3154                                 pop_fpul();
  3155                                 JMP_TARGET(end);
  3157                                 break;
  3158                             case 0xE:
  3159                                 { /* FIPR FVm, FVn */
  3160                                 uint32_t FVn = ((ir>>10)&0x3); uint32_t FVm = ((ir>>8)&0x3); 
  3161                                 check_fpuen();
  3162                                 load_spreg( R_ECX, R_FPSCR );
  3163                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3164                                 JNE_rel8(44, doubleprec);
  3166                                 load_fr_bank( R_ECX );
  3167                                 push_fr( R_ECX, FVm<<2 );
  3168                                 push_fr( R_ECX, FVn<<2 );
  3169                                 FMULP_st(1);
  3170                                 push_fr( R_ECX, (FVm<<2)+1);
  3171                                 push_fr( R_ECX, (FVn<<2)+1);
  3172                                 FMULP_st(1);
  3173                                 FADDP_st(1);
  3174                                 push_fr( R_ECX, (FVm<<2)+2);
  3175                                 push_fr( R_ECX, (FVn<<2)+2);
  3176                                 FMULP_st(1);
  3177                                 FADDP_st(1);
  3178                                 push_fr( R_ECX, (FVm<<2)+3);
  3179                                 push_fr( R_ECX, (FVn<<2)+3);
  3180                                 FMULP_st(1);
  3181                                 FADDP_st(1);
  3182                                 pop_fr( R_ECX, (FVn<<2)+3);
  3183                                 JMP_TARGET(doubleprec);
  3185                                 break;
  3186                             case 0xF:
  3187                                 switch( (ir&0x100) >> 8 ) {
  3188                                     case 0x0:
  3189                                         { /* FSCA FPUL, FRn */
  3190                                         uint32_t FRn = ((ir>>9)&0x7)<<1; 
  3191                                         check_fpuen();
  3192                                         load_spreg( R_ECX, R_FPSCR );
  3193                                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  3194                                         JNE_rel8( 21, doubleprec );
  3195                                         load_fr_bank( R_ECX );
  3196                                         ADD_imm8s_r32( (FRn&0x0E)<<2, R_ECX );
  3197                                         load_spreg( R_EDX, R_FPUL );
  3198                                         call_func2( sh4_fsca, R_EDX, R_ECX );
  3199                                         JMP_TARGET(doubleprec);
  3201                                         break;
  3202                                     case 0x1:
  3203                                         switch( (ir&0x200) >> 9 ) {
  3204                                             case 0x0:
  3205                                                 { /* FTRV XMTRX, FVn */
  3206                                                 uint32_t FVn = ((ir>>10)&0x3); 
  3207                                                 check_fpuen();
  3208                                                 load_spreg( R_ECX, R_FPSCR );
  3209                                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3210                                                 JNE_rel8( 30, doubleprec );
  3211                                                 load_fr_bank( R_EDX );                 // 3
  3212                                                 ADD_imm8s_r32( FVn<<4, R_EDX );        // 3
  3213                                                 load_xf_bank( R_ECX );                 // 12
  3214                                                 call_func2( sh4_ftrv, R_EDX, R_ECX );  // 12
  3215                                                 JMP_TARGET(doubleprec);
  3217                                                 break;
  3218                                             case 0x1:
  3219                                                 switch( (ir&0xC00) >> 10 ) {
  3220                                                     case 0x0:
  3221                                                         { /* FSCHG */
  3222                                                         check_fpuen();
  3223                                                         load_spreg( R_ECX, R_FPSCR );
  3224                                                         XOR_imm32_r32( FPSCR_SZ, R_ECX );
  3225                                                         store_spreg( R_ECX, R_FPSCR );
  3227                                                         break;
  3228                                                     case 0x2:
  3229                                                         { /* FRCHG */
  3230                                                         check_fpuen();
  3231                                                         load_spreg( R_ECX, R_FPSCR );
  3232                                                         XOR_imm32_r32( FPSCR_FR, R_ECX );
  3233                                                         store_spreg( R_ECX, R_FPSCR );
  3234                                                         update_fr_bank( R_ECX );
  3236                                                         break;
  3237                                                     case 0x3:
  3238                                                         { /* UNDEF */
  3239                                                         if( sh4_x86.in_delay_slot ) {
  3240                                                     	SLOTILLEGAL();
  3241                                                         } else {
  3242                                                     	JMP_exit(EXIT_ILLEGAL);
  3243                                                     	return 2;
  3246                                                         break;
  3247                                                     default:
  3248                                                         UNDEF();
  3249                                                         break;
  3251                                                 break;
  3253                                         break;
  3255                                 break;
  3256                             default:
  3257                                 UNDEF();
  3258                                 break;
  3260                         break;
  3261                     case 0xE:
  3262                         { /* FMAC FR0, FRm, FRn */
  3263                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  3264                         check_fpuen();
  3265                         load_spreg( R_ECX, R_FPSCR );
  3266                         load_spreg( R_EDX, REG_OFFSET(fr_bank));
  3267                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  3268                         JNE_rel8(18, doubleprec);
  3269                         push_fr( R_EDX, 0 );
  3270                         push_fr( R_EDX, FRm );
  3271                         FMULP_st(1);
  3272                         push_fr( R_EDX, FRn );
  3273                         FADDP_st(1);
  3274                         pop_fr( R_EDX, FRn );
  3275                         JMP_rel8(16, end);
  3276                         JMP_TARGET(doubleprec);
  3277                         push_dr( R_EDX, 0 );
  3278                         push_dr( R_EDX, FRm );
  3279                         FMULP_st(1);
  3280                         push_dr( R_EDX, FRn );
  3281                         FADDP_st(1);
  3282                         pop_dr( R_EDX, FRn );
  3283                         JMP_TARGET(end);
  3285                         break;
  3286                     default:
  3287                         UNDEF();
  3288                         break;
  3290                 break;
  3293     if( sh4_x86.in_delay_slot ) {
  3294 	ADD_imm8s_r32(2,R_ESI);
  3295 	sh4_x86.in_delay_slot = FALSE;
  3296     } else {
  3297 	INC_r32(R_ESI);
  3299     return 0;
.