filename | src/sh4/sh4stat.c |
changeset | 673:44c579439d73 |
prev | 671:a530ea88eebd |
next | 730:a0f02e769c2e |
author | nkeynes |
date | Mon May 26 11:01:42 2008 +0000 (15 years ago) |
permissions | -rw-r--r-- |
last change | hange 64-bit configuration to use sizeof(void *) rather than the system id returned by config.guess - config.guess gets it wrong in some situations. |
view | annotate | diff | log | raw |
1 /**
2 * $Id$
3 *
4 * Support module for collecting instruction stats
5 *
6 * Copyright (c) 2005 Nathan Keynes.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
19 #include "dream.h"
20 #include "sh4stat.h"
21 #include "sh4core.h"
23 static uint64_t sh4_stats[SH4_INSTRUCTION_COUNT+1];
24 static uint64_t sh4_stats_total;
25 static const char *sh4_stats_names[] = {
26 "???",
27 "ADD Rm, Rn",
28 "ADD #imm, Rn",
29 "ADDC Rm, Rn",
30 "ADDV Rm, Rn",
31 "AND Rm, Rn",
32 "AND #imm, R0",
33 "AND.B #imm, @(R0, GBR)",
34 "BF disp",
35 "BF/S disp",
36 "BRA disp",
37 "BRAF Rn",
38 "BSR disp",
39 "BSRF Rn",
40 "BT disp",
41 "BT/S disp",
42 "CLRMAC",
43 "CLRS",
44 "CLRT",
45 "CMP/EQ Rm, Rn",
46 "CMP/EQ #imm, R0",
47 "CMP/GE Rm, Rn",
48 "CMP/GT Rm, Rn",
49 "CMP/HI Rm, Rn",
50 "CMP/HS Rm, Rn",
51 "CMP/PL Rn",
52 "CMP/PZ Rn",
53 "CMP/STR Rm, Rn",
54 "DIV0S Rm, Rn",
55 "DIV0U",
56 "DIV1 Rm, Rn",
57 "DMULS.L Rm, Rn",
58 "DMULU.L Rm, Rn",
59 "DT Rn",
60 "EXTS.B Rm, Rn",
61 "EXTS.W Rm, Rn",
62 "EXTU.B Rm, Rn",
63 "EXTU.W Rm, Rn",
64 "FABS FRn",
65 "FADD FRm, FRn",
66 "FCMP/EQ FRm, FRn",
67 "FCMP/GT FRm, FRn",
68 "FCNVDS FRm, FPUL",
69 "FCNVSD FPUL, FRn",
70 "FDIV FRm, FRn",
71 "FIPR FVm, FVn",
72 "FLDS FRm, FPUL",
73 "FLDI0 FRn",
74 "FLDI1 FRn",
75 "FLOAT FPUL, FRn",
76 "FMAC FR0, FRm, FRn",
77 "FMOV FRm, FRn",
78 "FMOV FRm, @Rn",
79 "FMOV FRm, @-Rn",
80 "FMOV FRm, @(R0, Rn)",
81 "FMOV @Rm, FRn",
82 "FMOV @Rm+, FRn",
83 "FMOV @(R0, Rm), FRn",
84 "FMUL FRm, FRn",
85 "FNEG FRn",
86 "FRCHG",
87 "FSCA FPUL, FRn",
88 "FSCHG",
89 "FSQRT FRn",
90 "FSRRA FRn",
91 "FSTS FPUL, FRn",
92 "FSUB FRm, FRn",
93 "FTRC FRm, FPUL",
94 "FTRV XMTRX, FVn",
95 "JMP @Rn",
96 "JSR @Rn",
97 "LDC Rm, SR",
98 "LDC Rm, *",
99 "LDC.L @Rm+, SR",
100 "LDC.L @Rm+, *",
101 "LDS Rm, FPSCR",
102 "LDS Rm, *",
103 "LDS.L @Rm+, FPSCR",
104 "LDS.L @Rm+, *",
105 "LDTLB",
106 "MAC.L @Rm+, @Rn+",
107 "MAC.W @Rm+, @Rn+",
108 "MOV Rm, Rn",
109 "MOV #imm, Rn",
110 "MOV.B ...",
111 "MOV.L ...",
112 "MOV.L @(disp, PC)",
113 "MOV.W ...",
114 "MOVA @(disp, PC), R0",
115 "MOVCA.L R0, @Rn",
116 "MOVT Rn",
117 "MUL.L Rm, Rn",
118 "MULS.W Rm, Rn",
119 "MULU.W Rm, Rn",
120 "NEG Rm, Rn",
121 "NEGC Rm, Rn",
122 "NOP",
123 "NOT Rm, Rn",
124 "OCBI @Rn",
125 "OCBP @Rn",
126 "OCBWB @Rn",
127 "OR Rm, Rn",
128 "OR #imm, R0",
129 "OR.B #imm, @(R0, GBR)",
130 "PREF @Rn",
131 "ROTCL Rn",
132 "ROTCR Rn",
133 "ROTL Rn",
134 "ROTR Rn",
135 "RTE",
136 "RTS",
137 "SETS",
138 "SETT",
139 "SHAD Rm, Rn",
140 "SHAL Rn",
141 "SHAR Rn",
142 "SHLD Rm, Rn",
143 "SHLL* Rn",
144 "SHLR* Rn",
145 "SLEEP",
146 "STC SR, Rn",
147 "STC *, Rn",
148 "STC.L SR, @-Rn",
149 "STC.L *, @-Rn",
150 "STS FPSCR, Rn",
151 "STS *, Rn",
152 "STS.L FPSCR, @-Rn",
153 "STS.L *, @-Rn",
154 "SUB Rm, Rn",
155 "SUBC Rm, Rn",
156 "SUBV Rm, Rn",
157 "SWAP.B Rm, Rn",
158 "SWAP.W Rm, Rn",
159 "TAS.B @Rn",
160 "TRAPA #imm",
161 "TST Rm, Rn",
162 "TST #imm, R0",
163 "TST.B #imm, @(R0, GBR)",
164 "XOR Rm, Rn",
165 "XOR #imm, R0",
166 "XOR.B #imm, @(R0, GBR)",
167 "XTRCT Rm, Rn",
168 "UNDEF"
169 };
171 void sh4_stats_reset( void )
172 {
173 int i;
174 for( i=0; i<= I_UNDEF; i++ ) {
175 sh4_stats[i] = 0;
176 }
177 sh4_stats_total = 0;
178 }
180 void sh4_stats_print( FILE *out )
181 {
182 int i;
183 for( i=0; i<= I_UNDEF; i++ ) {
184 fprintf( out, "%-20s\t%d\t%.2f%%\n", sh4_stats_names[i], (uint32_t)sh4_stats[i], ((double)sh4_stats[i])*100.0/(double)sh4_stats_total );
185 }
186 fprintf( out, "Total: %lld\n", sh4_stats_total );
187 }
189 void sh4_stats_add( sh4_inst_id item )
190 {
191 sh4_stats[item]++;
192 sh4_stats_total++;
193 }
195 void sh4_stats_add_by_pc( uint32_t pc )
196 {
197 uint16_t ir = sh4_read_word(pc);
198 #define UNDEF() sh4_stats[0]++
199 switch( (ir&0xF000) >> 12 ) {
200 case 0x0:
201 switch( ir&0xF ) {
202 case 0x2:
203 switch( (ir&0x80) >> 7 ) {
204 case 0x0:
205 switch( (ir&0x70) >> 4 ) {
206 case 0x0:
207 { /* STC SR, Rn */
208 uint32_t Rn = ((ir>>8)&0xF);
209 sh4_stats[I_STCSR]++;
210 }
211 break;
212 case 0x1:
213 { /* STC GBR, Rn */
214 uint32_t Rn = ((ir>>8)&0xF);
215 sh4_stats[I_STC]++;
216 }
217 break;
218 case 0x2:
219 { /* STC VBR, Rn */
220 uint32_t Rn = ((ir>>8)&0xF);
221 sh4_stats[I_STC]++;
222 }
223 break;
224 case 0x3:
225 { /* STC SSR, Rn */
226 uint32_t Rn = ((ir>>8)&0xF);
227 sh4_stats[I_STC]++;
228 }
229 break;
230 case 0x4:
231 { /* STC SPC, Rn */
232 uint32_t Rn = ((ir>>8)&0xF);
233 sh4_stats[I_STC]++;
234 }
235 break;
236 default:
237 UNDEF();
238 break;
239 }
240 break;
241 case 0x1:
242 { /* STC Rm_BANK, Rn */
243 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7);
244 sh4_stats[I_STC]++;
245 }
246 break;
247 }
248 break;
249 case 0x3:
250 switch( (ir&0xF0) >> 4 ) {
251 case 0x0:
252 { /* BSRF Rn */
253 uint32_t Rn = ((ir>>8)&0xF);
254 sh4_stats[I_BSRF]++;
255 }
256 break;
257 case 0x2:
258 { /* BRAF Rn */
259 uint32_t Rn = ((ir>>8)&0xF);
260 sh4_stats[I_BRAF]++;
261 }
262 break;
263 case 0x8:
264 { /* PREF @Rn */
265 uint32_t Rn = ((ir>>8)&0xF);
266 sh4_stats[I_PREF]++;
267 }
268 break;
269 case 0x9:
270 { /* OCBI @Rn */
271 uint32_t Rn = ((ir>>8)&0xF);
272 sh4_stats[I_OCBI]++;
273 }
274 break;
275 case 0xA:
276 { /* OCBP @Rn */
277 uint32_t Rn = ((ir>>8)&0xF);
278 sh4_stats[I_OCBP]++;
279 }
280 break;
281 case 0xB:
282 { /* OCBWB @Rn */
283 uint32_t Rn = ((ir>>8)&0xF);
284 sh4_stats[I_OCBWB]++;
285 }
286 break;
287 case 0xC:
288 { /* MOVCA.L R0, @Rn */
289 uint32_t Rn = ((ir>>8)&0xF);
290 sh4_stats[I_MOVCA]++;
291 }
292 break;
293 default:
294 UNDEF();
295 break;
296 }
297 break;
298 case 0x4:
299 { /* MOV.B Rm, @(R0, Rn) */
300 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
301 sh4_stats[I_MOVB]++;
302 }
303 break;
304 case 0x5:
305 { /* MOV.W Rm, @(R0, Rn) */
306 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
307 sh4_stats[I_MOVW]++;
308 }
309 break;
310 case 0x6:
311 { /* MOV.L Rm, @(R0, Rn) */
312 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
313 sh4_stats[I_MOVL]++;
314 }
315 break;
316 case 0x7:
317 { /* MUL.L Rm, Rn */
318 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
319 sh4_stats[I_MULL]++;
320 }
321 break;
322 case 0x8:
323 switch( (ir&0xFF0) >> 4 ) {
324 case 0x0:
325 { /* CLRT */
326 sh4_stats[I_CLRT]++;
327 }
328 break;
329 case 0x1:
330 { /* SETT */
331 sh4_stats[I_SETT]++;
332 }
333 break;
334 case 0x2:
335 { /* CLRMAC */
336 sh4_stats[I_CLRMAC]++;
337 }
338 break;
339 case 0x3:
340 { /* LDTLB */
341 sh4_stats[I_LDTLB]++;
342 }
343 break;
344 case 0x4:
345 { /* CLRS */
346 sh4_stats[I_CLRS]++;
347 }
348 break;
349 case 0x5:
350 { /* SETS */
351 sh4_stats[I_SETS]++;
352 }
353 break;
354 default:
355 UNDEF();
356 break;
357 }
358 break;
359 case 0x9:
360 switch( (ir&0xF0) >> 4 ) {
361 case 0x0:
362 { /* NOP */
363 sh4_stats[I_NOP]++;
364 }
365 break;
366 case 0x1:
367 { /* DIV0U */
368 sh4_stats[I_DIV0U]++;
369 }
370 break;
371 case 0x2:
372 { /* MOVT Rn */
373 uint32_t Rn = ((ir>>8)&0xF);
374 sh4_stats[I_MOVT]++;
375 }
376 break;
377 default:
378 UNDEF();
379 break;
380 }
381 break;
382 case 0xA:
383 switch( (ir&0xF0) >> 4 ) {
384 case 0x0:
385 { /* STS MACH, Rn */
386 uint32_t Rn = ((ir>>8)&0xF);
387 sh4_stats[I_STS]++;
388 }
389 break;
390 case 0x1:
391 { /* STS MACL, Rn */
392 uint32_t Rn = ((ir>>8)&0xF);
393 sh4_stats[I_STS]++;
394 }
395 break;
396 case 0x2:
397 { /* STS PR, Rn */
398 uint32_t Rn = ((ir>>8)&0xF);
399 sh4_stats[I_STS]++;
400 }
401 break;
402 case 0x3:
403 { /* STC SGR, Rn */
404 uint32_t Rn = ((ir>>8)&0xF);
405 sh4_stats[I_STC]++;
406 }
407 break;
408 case 0x5:
409 { /* STS FPUL, Rn */
410 uint32_t Rn = ((ir>>8)&0xF);
411 sh4_stats[I_STS]++;
412 }
413 break;
414 case 0x6:
415 { /* STS FPSCR, Rn */
416 uint32_t Rn = ((ir>>8)&0xF);
417 sh4_stats[I_STSFPSCR]++;
418 }
419 break;
420 case 0xF:
421 { /* STC DBR, Rn */
422 uint32_t Rn = ((ir>>8)&0xF);
423 sh4_stats[I_STC]++;
424 }
425 break;
426 default:
427 UNDEF();
428 break;
429 }
430 break;
431 case 0xB:
432 switch( (ir&0xFF0) >> 4 ) {
433 case 0x0:
434 { /* RTS */
435 sh4_stats[I_RTS]++;
436 }
437 break;
438 case 0x1:
439 { /* SLEEP */
440 sh4_stats[I_SLEEP]++;
441 }
442 break;
443 case 0x2:
444 { /* RTE */
445 sh4_stats[I_RTE]++;
446 }
447 break;
448 default:
449 UNDEF();
450 break;
451 }
452 break;
453 case 0xC:
454 { /* MOV.B @(R0, Rm), Rn */
455 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
456 sh4_stats[I_MOVB]++;
457 }
458 break;
459 case 0xD:
460 { /* MOV.W @(R0, Rm), Rn */
461 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
462 sh4_stats[I_MOVW]++;
463 }
464 break;
465 case 0xE:
466 { /* MOV.L @(R0, Rm), Rn */
467 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
468 sh4_stats[I_MOVL]++;
469 }
470 break;
471 case 0xF:
472 { /* MAC.L @Rm+, @Rn+ */
473 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
474 sh4_stats[I_MACL]++;
475 }
476 break;
477 default:
478 UNDEF();
479 break;
480 }
481 break;
482 case 0x1:
483 { /* MOV.L Rm, @(disp, Rn) */
484 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2;
485 sh4_stats[I_MOVL]++;
486 }
487 break;
488 case 0x2:
489 switch( ir&0xF ) {
490 case 0x0:
491 { /* MOV.B Rm, @Rn */
492 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
493 sh4_stats[I_MOVB]++;
494 }
495 break;
496 case 0x1:
497 { /* MOV.W Rm, @Rn */
498 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
499 sh4_stats[I_MOVW]++;
500 }
501 break;
502 case 0x2:
503 { /* MOV.L Rm, @Rn */
504 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
505 sh4_stats[I_MOVL]++;
506 }
507 break;
508 case 0x4:
509 { /* MOV.B Rm, @-Rn */
510 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
511 sh4_stats[I_MOVB]++;
512 }
513 break;
514 case 0x5:
515 { /* MOV.W Rm, @-Rn */
516 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
517 sh4_stats[I_MOVW]++;
518 }
519 break;
520 case 0x6:
521 { /* MOV.L Rm, @-Rn */
522 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
523 sh4_stats[I_MOVL]++;
524 }
525 break;
526 case 0x7:
527 { /* DIV0S Rm, Rn */
528 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
529 sh4_stats[I_DIV0S]++;
530 }
531 break;
532 case 0x8:
533 { /* TST Rm, Rn */
534 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
535 sh4_stats[I_TST]++;
536 }
537 break;
538 case 0x9:
539 { /* AND Rm, Rn */
540 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
541 sh4_stats[I_AND]++;
542 }
543 break;
544 case 0xA:
545 { /* XOR Rm, Rn */
546 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
547 sh4_stats[I_XOR]++;
548 }
549 break;
550 case 0xB:
551 { /* OR Rm, Rn */
552 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
553 sh4_stats[I_OR]++;
554 }
555 break;
556 case 0xC:
557 { /* CMP/STR Rm, Rn */
558 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
559 sh4_stats[I_CMPSTR]++;
560 }
561 break;
562 case 0xD:
563 { /* XTRCT Rm, Rn */
564 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
565 sh4_stats[I_XTRCT]++;
566 }
567 break;
568 case 0xE:
569 { /* MULU.W Rm, Rn */
570 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
571 sh4_stats[I_MULUW]++;
572 }
573 break;
574 case 0xF:
575 { /* MULS.W Rm, Rn */
576 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
577 sh4_stats[I_MULSW]++;
578 }
579 break;
580 default:
581 UNDEF();
582 break;
583 }
584 break;
585 case 0x3:
586 switch( ir&0xF ) {
587 case 0x0:
588 { /* CMP/EQ Rm, Rn */
589 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
590 sh4_stats[I_CMPEQ]++;
591 }
592 break;
593 case 0x2:
594 { /* CMP/HS Rm, Rn */
595 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
596 sh4_stats[I_CMPHS]++;
597 }
598 break;
599 case 0x3:
600 { /* CMP/GE Rm, Rn */
601 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
602 sh4_stats[I_CMPGE]++;
603 }
604 break;
605 case 0x4:
606 { /* DIV1 Rm, Rn */
607 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
608 sh4_stats[I_DIV1]++;
609 }
610 break;
611 case 0x5:
612 { /* DMULU.L Rm, Rn */
613 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
614 sh4_stats[I_DMULU]++;
615 }
616 break;
617 case 0x6:
618 { /* CMP/HI Rm, Rn */
619 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
620 sh4_stats[I_CMPHI]++;
621 }
622 break;
623 case 0x7:
624 { /* CMP/GT Rm, Rn */
625 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
626 sh4_stats[I_CMPGT]++;
627 }
628 break;
629 case 0x8:
630 { /* SUB Rm, Rn */
631 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
632 sh4_stats[I_SUB]++;
633 }
634 break;
635 case 0xA:
636 { /* SUBC Rm, Rn */
637 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
638 sh4_stats[I_SUBC]++;
639 }
640 break;
641 case 0xB:
642 { /* SUBV Rm, Rn */
643 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
644 sh4_stats[I_SUBV]++;
645 }
646 break;
647 case 0xC:
648 { /* ADD Rm, Rn */
649 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
650 sh4_stats[I_ADD]++;
651 }
652 break;
653 case 0xD:
654 { /* DMULS.L Rm, Rn */
655 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
656 sh4_stats[I_DMULS]++;
657 }
658 break;
659 case 0xE:
660 { /* ADDC Rm, Rn */
661 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
662 sh4_stats[I_ADDC]++;
663 }
664 break;
665 case 0xF:
666 { /* ADDV Rm, Rn */
667 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
668 sh4_stats[I_ADDV]++;
669 }
670 break;
671 default:
672 UNDEF();
673 break;
674 }
675 break;
676 case 0x4:
677 switch( ir&0xF ) {
678 case 0x0:
679 switch( (ir&0xF0) >> 4 ) {
680 case 0x0:
681 { /* SHLL Rn */
682 uint32_t Rn = ((ir>>8)&0xF);
683 sh4_stats[I_SHLL]++;
684 }
685 break;
686 case 0x1:
687 { /* DT Rn */
688 uint32_t Rn = ((ir>>8)&0xF);
689 sh4_stats[I_DT]++;
690 }
691 break;
692 case 0x2:
693 { /* SHAL Rn */
694 uint32_t Rn = ((ir>>8)&0xF);
695 sh4_stats[I_SHAL]++;
696 }
697 break;
698 default:
699 UNDEF();
700 break;
701 }
702 break;
703 case 0x1:
704 switch( (ir&0xF0) >> 4 ) {
705 case 0x0:
706 { /* SHLR Rn */
707 uint32_t Rn = ((ir>>8)&0xF);
708 sh4_stats[I_SHLR]++;
709 }
710 break;
711 case 0x1:
712 { /* CMP/PZ Rn */
713 uint32_t Rn = ((ir>>8)&0xF);
714 sh4_stats[I_CMPPZ]++;
715 }
716 break;
717 case 0x2:
718 { /* SHAR Rn */
719 uint32_t Rn = ((ir>>8)&0xF);
720 sh4_stats[I_SHAR]++;
721 }
722 break;
723 default:
724 UNDEF();
725 break;
726 }
727 break;
728 case 0x2:
729 switch( (ir&0xF0) >> 4 ) {
730 case 0x0:
731 { /* STS.L MACH, @-Rn */
732 uint32_t Rn = ((ir>>8)&0xF);
733 sh4_stats[I_STSM]++;
734 }
735 break;
736 case 0x1:
737 { /* STS.L MACL, @-Rn */
738 uint32_t Rn = ((ir>>8)&0xF);
739 sh4_stats[I_STSM]++;
740 }
741 break;
742 case 0x2:
743 { /* STS.L PR, @-Rn */
744 uint32_t Rn = ((ir>>8)&0xF);
745 sh4_stats[I_STSM]++;
746 }
747 break;
748 case 0x3:
749 { /* STC.L SGR, @-Rn */
750 uint32_t Rn = ((ir>>8)&0xF);
751 sh4_stats[I_STCM]++;
752 }
753 break;
754 case 0x5:
755 { /* STS.L FPUL, @-Rn */
756 uint32_t Rn = ((ir>>8)&0xF);
757 sh4_stats[I_STSM]++;
758 }
759 break;
760 case 0x6:
761 { /* STS.L FPSCR, @-Rn */
762 uint32_t Rn = ((ir>>8)&0xF);
763 sh4_stats[I_STSFPSCRM]++;
764 }
765 break;
766 case 0xF:
767 { /* STC.L DBR, @-Rn */
768 uint32_t Rn = ((ir>>8)&0xF);
769 sh4_stats[I_STCM]++;
770 }
771 break;
772 default:
773 UNDEF();
774 break;
775 }
776 break;
777 case 0x3:
778 switch( (ir&0x80) >> 7 ) {
779 case 0x0:
780 switch( (ir&0x70) >> 4 ) {
781 case 0x0:
782 { /* STC.L SR, @-Rn */
783 uint32_t Rn = ((ir>>8)&0xF);
784 sh4_stats[I_STCSRM]++;
785 }
786 break;
787 case 0x1:
788 { /* STC.L GBR, @-Rn */
789 uint32_t Rn = ((ir>>8)&0xF);
790 sh4_stats[I_STCM]++;
791 }
792 break;
793 case 0x2:
794 { /* STC.L VBR, @-Rn */
795 uint32_t Rn = ((ir>>8)&0xF);
796 sh4_stats[I_STCM]++;
797 }
798 break;
799 case 0x3:
800 { /* STC.L SSR, @-Rn */
801 uint32_t Rn = ((ir>>8)&0xF);
802 sh4_stats[I_STCM]++;
803 }
804 break;
805 case 0x4:
806 { /* STC.L SPC, @-Rn */
807 uint32_t Rn = ((ir>>8)&0xF);
808 sh4_stats[I_STCM]++;
809 }
810 break;
811 default:
812 UNDEF();
813 break;
814 }
815 break;
816 case 0x1:
817 { /* STC.L Rm_BANK, @-Rn */
818 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7);
819 sh4_stats[I_STCM]++;
820 }
821 break;
822 }
823 break;
824 case 0x4:
825 switch( (ir&0xF0) >> 4 ) {
826 case 0x0:
827 { /* ROTL Rn */
828 uint32_t Rn = ((ir>>8)&0xF);
829 sh4_stats[I_ROTL]++;
830 }
831 break;
832 case 0x2:
833 { /* ROTCL Rn */
834 uint32_t Rn = ((ir>>8)&0xF);
835 sh4_stats[I_ROTCL]++;
836 }
837 break;
838 default:
839 UNDEF();
840 break;
841 }
842 break;
843 case 0x5:
844 switch( (ir&0xF0) >> 4 ) {
845 case 0x0:
846 { /* ROTR Rn */
847 uint32_t Rn = ((ir>>8)&0xF);
848 sh4_stats[I_ROTR]++;
849 }
850 break;
851 case 0x1:
852 { /* CMP/PL Rn */
853 uint32_t Rn = ((ir>>8)&0xF);
854 sh4_stats[I_CMPPL]++;
855 }
856 break;
857 case 0x2:
858 { /* ROTCR Rn */
859 uint32_t Rn = ((ir>>8)&0xF);
860 sh4_stats[I_ROTCR]++;
861 }
862 break;
863 default:
864 UNDEF();
865 break;
866 }
867 break;
868 case 0x6:
869 switch( (ir&0xF0) >> 4 ) {
870 case 0x0:
871 { /* LDS.L @Rm+, MACH */
872 uint32_t Rm = ((ir>>8)&0xF);
873 sh4_stats[I_LDSM]++;
874 }
875 break;
876 case 0x1:
877 { /* LDS.L @Rm+, MACL */
878 uint32_t Rm = ((ir>>8)&0xF);
879 sh4_stats[I_LDSM]++;
880 }
881 break;
882 case 0x2:
883 { /* LDS.L @Rm+, PR */
884 uint32_t Rm = ((ir>>8)&0xF);
885 sh4_stats[I_LDSM]++;
886 }
887 break;
888 case 0x3:
889 { /* LDC.L @Rm+, SGR */
890 uint32_t Rm = ((ir>>8)&0xF);
891 sh4_stats[I_LDCM]++;
892 }
893 break;
894 case 0x5:
895 { /* LDS.L @Rm+, FPUL */
896 uint32_t Rm = ((ir>>8)&0xF);
897 sh4_stats[I_LDSM]++;
898 }
899 break;
900 case 0x6:
901 { /* LDS.L @Rm+, FPSCR */
902 uint32_t Rm = ((ir>>8)&0xF);
903 sh4_stats[I_LDSFPSCRM]++;
904 }
905 break;
906 case 0xF:
907 { /* LDC.L @Rm+, DBR */
908 uint32_t Rm = ((ir>>8)&0xF);
909 sh4_stats[I_LDCM]++;
910 }
911 break;
912 default:
913 UNDEF();
914 break;
915 }
916 break;
917 case 0x7:
918 switch( (ir&0x80) >> 7 ) {
919 case 0x0:
920 switch( (ir&0x70) >> 4 ) {
921 case 0x0:
922 { /* LDC.L @Rm+, SR */
923 uint32_t Rm = ((ir>>8)&0xF);
924 sh4_stats[I_LDCSRM]++;
925 }
926 break;
927 case 0x1:
928 { /* LDC.L @Rm+, GBR */
929 uint32_t Rm = ((ir>>8)&0xF);
930 sh4_stats[I_LDCM]++;
931 }
932 break;
933 case 0x2:
934 { /* LDC.L @Rm+, VBR */
935 uint32_t Rm = ((ir>>8)&0xF);
936 sh4_stats[I_LDCM]++;
937 }
938 break;
939 case 0x3:
940 { /* LDC.L @Rm+, SSR */
941 uint32_t Rm = ((ir>>8)&0xF);
942 sh4_stats[I_LDCM]++;
943 }
944 break;
945 case 0x4:
946 { /* LDC.L @Rm+, SPC */
947 uint32_t Rm = ((ir>>8)&0xF);
948 sh4_stats[I_LDCM]++;
949 }
950 break;
951 default:
952 UNDEF();
953 break;
954 }
955 break;
956 case 0x1:
957 { /* LDC.L @Rm+, Rn_BANK */
958 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7);
959 sh4_stats[I_LDCM]++;
960 }
961 break;
962 }
963 break;
964 case 0x8:
965 switch( (ir&0xF0) >> 4 ) {
966 case 0x0:
967 { /* SHLL2 Rn */
968 uint32_t Rn = ((ir>>8)&0xF);
969 sh4_stats[I_SHLL]++;
970 }
971 break;
972 case 0x1:
973 { /* SHLL8 Rn */
974 uint32_t Rn = ((ir>>8)&0xF);
975 sh4_stats[I_SHLL]++;
976 }
977 break;
978 case 0x2:
979 { /* SHLL16 Rn */
980 uint32_t Rn = ((ir>>8)&0xF);
981 sh4_stats[I_SHLL]++;
982 }
983 break;
984 default:
985 UNDEF();
986 break;
987 }
988 break;
989 case 0x9:
990 switch( (ir&0xF0) >> 4 ) {
991 case 0x0:
992 { /* SHLR2 Rn */
993 uint32_t Rn = ((ir>>8)&0xF);
994 sh4_stats[I_SHLR]++;
995 }
996 break;
997 case 0x1:
998 { /* SHLR8 Rn */
999 uint32_t Rn = ((ir>>8)&0xF);
1000 sh4_stats[I_SHLR]++;
1001 }
1002 break;
1003 case 0x2:
1004 { /* SHLR16 Rn */
1005 uint32_t Rn = ((ir>>8)&0xF);
1006 sh4_stats[I_SHLR]++;
1007 }
1008 break;
1009 default:
1010 UNDEF();
1011 break;
1012 }
1013 break;
1014 case 0xA:
1015 switch( (ir&0xF0) >> 4 ) {
1016 case 0x0:
1017 { /* LDS Rm, MACH */
1018 uint32_t Rm = ((ir>>8)&0xF);
1019 sh4_stats[I_LDS]++;
1020 }
1021 break;
1022 case 0x1:
1023 { /* LDS Rm, MACL */
1024 uint32_t Rm = ((ir>>8)&0xF);
1025 sh4_stats[I_LDS]++;
1026 }
1027 break;
1028 case 0x2:
1029 { /* LDS Rm, PR */
1030 uint32_t Rm = ((ir>>8)&0xF);
1031 sh4_stats[I_LDS]++;
1032 }
1033 break;
1034 case 0x3:
1035 { /* LDC Rm, SGR */
1036 uint32_t Rm = ((ir>>8)&0xF);
1037 sh4_stats[I_LDC]++;
1038 }
1039 break;
1040 case 0x5:
1041 { /* LDS Rm, FPUL */
1042 uint32_t Rm = ((ir>>8)&0xF);
1043 sh4_stats[I_LDS]++;
1044 }
1045 break;
1046 case 0x6:
1047 { /* LDS Rm, FPSCR */
1048 uint32_t Rm = ((ir>>8)&0xF);
1049 sh4_stats[I_LDSFPSCR]++;
1050 }
1051 break;
1052 case 0xF:
1053 { /* LDC Rm, DBR */
1054 uint32_t Rm = ((ir>>8)&0xF);
1055 sh4_stats[I_LDC]++;
1056 }
1057 break;
1058 default:
1059 UNDEF();
1060 break;
1061 }
1062 break;
1063 case 0xB:
1064 switch( (ir&0xF0) >> 4 ) {
1065 case 0x0:
1066 { /* JSR @Rn */
1067 uint32_t Rn = ((ir>>8)&0xF);
1068 sh4_stats[I_JSR]++;
1069 }
1070 break;
1071 case 0x1:
1072 { /* TAS.B @Rn */
1073 uint32_t Rn = ((ir>>8)&0xF);
1074 sh4_stats[I_TASB]++;
1075 }
1076 break;
1077 case 0x2:
1078 { /* JMP @Rn */
1079 uint32_t Rn = ((ir>>8)&0xF);
1080 sh4_stats[I_JMP]++;
1081 }
1082 break;
1083 default:
1084 UNDEF();
1085 break;
1086 }
1087 break;
1088 case 0xC:
1089 { /* SHAD Rm, Rn */
1090 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1091 sh4_stats[I_SHAD]++;
1092 }
1093 break;
1094 case 0xD:
1095 { /* SHLD Rm, Rn */
1096 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1097 sh4_stats[I_SHLD]++;
1098 }
1099 break;
1100 case 0xE:
1101 switch( (ir&0x80) >> 7 ) {
1102 case 0x0:
1103 switch( (ir&0x70) >> 4 ) {
1104 case 0x0:
1105 { /* LDC Rm, SR */
1106 uint32_t Rm = ((ir>>8)&0xF);
1107 sh4_stats[I_LDCSR]++;
1108 }
1109 break;
1110 case 0x1:
1111 { /* LDC Rm, GBR */
1112 uint32_t Rm = ((ir>>8)&0xF);
1113 sh4_stats[I_LDC]++;
1114 }
1115 break;
1116 case 0x2:
1117 { /* LDC Rm, VBR */
1118 uint32_t Rm = ((ir>>8)&0xF);
1119 sh4_stats[I_LDC]++;
1120 }
1121 break;
1122 case 0x3:
1123 { /* LDC Rm, SSR */
1124 uint32_t Rm = ((ir>>8)&0xF);
1125 sh4_stats[I_LDC]++;
1126 }
1127 break;
1128 case 0x4:
1129 { /* LDC Rm, SPC */
1130 uint32_t Rm = ((ir>>8)&0xF);
1131 sh4_stats[I_LDC]++;
1132 }
1133 break;
1134 default:
1135 UNDEF();
1136 break;
1137 }
1138 break;
1139 case 0x1:
1140 { /* LDC Rm, Rn_BANK */
1141 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7);
1142 sh4_stats[I_LDC]++;
1143 }
1144 break;
1145 }
1146 break;
1147 case 0xF:
1148 { /* MAC.W @Rm+, @Rn+ */
1149 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1150 sh4_stats[I_MACW]++;
1151 }
1152 break;
1153 }
1154 break;
1155 case 0x5:
1156 { /* MOV.L @(disp, Rm), Rn */
1157 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2;
1158 sh4_stats[I_MOVL]++;
1159 }
1160 break;
1161 case 0x6:
1162 switch( ir&0xF ) {
1163 case 0x0:
1164 { /* MOV.B @Rm, Rn */
1165 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1166 sh4_stats[I_MOVB]++;
1167 }
1168 break;
1169 case 0x1:
1170 { /* MOV.W @Rm, Rn */
1171 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1172 sh4_stats[I_MOVW]++;
1173 }
1174 break;
1175 case 0x2:
1176 { /* MOV.L @Rm, Rn */
1177 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1178 sh4_stats[I_MOVL]++;
1179 }
1180 break;
1181 case 0x3:
1182 { /* MOV Rm, Rn */
1183 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1184 sh4_stats[I_MOV]++;
1185 }
1186 break;
1187 case 0x4:
1188 { /* MOV.B @Rm+, Rn */
1189 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1190 sh4_stats[I_MOVB]++;
1191 }
1192 break;
1193 case 0x5:
1194 { /* MOV.W @Rm+, Rn */
1195 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1196 sh4_stats[I_MOVW]++;
1197 }
1198 break;
1199 case 0x6:
1200 { /* MOV.L @Rm+, Rn */
1201 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1202 sh4_stats[I_MOVL]++;
1203 }
1204 break;
1205 case 0x7:
1206 { /* NOT Rm, Rn */
1207 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1208 sh4_stats[I_NOT]++;
1209 }
1210 break;
1211 case 0x8:
1212 { /* SWAP.B Rm, Rn */
1213 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1214 sh4_stats[I_SWAPB]++;
1215 }
1216 break;
1217 case 0x9:
1218 { /* SWAP.W Rm, Rn */
1219 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1220 sh4_stats[I_SWAPW]++;
1221 }
1222 break;
1223 case 0xA:
1224 { /* NEGC Rm, Rn */
1225 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1226 sh4_stats[I_NEGC]++;
1227 }
1228 break;
1229 case 0xB:
1230 { /* NEG Rm, Rn */
1231 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1232 sh4_stats[I_NEG]++;
1233 }
1234 break;
1235 case 0xC:
1236 { /* EXTU.B Rm, Rn */
1237 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1238 sh4_stats[I_EXTUB]++;
1239 }
1240 break;
1241 case 0xD:
1242 { /* EXTU.W Rm, Rn */
1243 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1244 sh4_stats[I_EXTUW]++;
1245 }
1246 break;
1247 case 0xE:
1248 { /* EXTS.B Rm, Rn */
1249 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1250 sh4_stats[I_EXTSB]++;
1251 }
1252 break;
1253 case 0xF:
1254 { /* EXTS.W Rm, Rn */
1255 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1256 sh4_stats[I_EXTSW]++;
1257 }
1258 break;
1259 }
1260 break;
1261 case 0x7:
1262 { /* ADD #imm, Rn */
1263 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF);
1264 sh4_stats[I_ADDI]++;
1265 }
1266 break;
1267 case 0x8:
1268 switch( (ir&0xF00) >> 8 ) {
1269 case 0x0:
1270 { /* MOV.B R0, @(disp, Rn) */
1271 uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF);
1272 sh4_stats[I_MOVB]++;
1273 }
1274 break;
1275 case 0x1:
1276 { /* MOV.W R0, @(disp, Rn) */
1277 uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1;
1278 sh4_stats[I_MOVW]++;
1279 }
1280 break;
1281 case 0x4:
1282 { /* MOV.B @(disp, Rm), R0 */
1283 uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF);
1284 sh4_stats[I_MOVB]++;
1285 }
1286 break;
1287 case 0x5:
1288 { /* MOV.W @(disp, Rm), R0 */
1289 uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1;
1290 sh4_stats[I_MOVW]++;
1291 }
1292 break;
1293 case 0x8:
1294 { /* CMP/EQ #imm, R0 */
1295 int32_t imm = SIGNEXT8(ir&0xFF);
1296 sh4_stats[I_CMPEQI]++;
1297 }
1298 break;
1299 case 0x9:
1300 { /* BT disp */
1301 int32_t disp = SIGNEXT8(ir&0xFF)<<1;
1302 sh4_stats[I_BT]++;
1303 }
1304 break;
1305 case 0xB:
1306 { /* BF disp */
1307 int32_t disp = SIGNEXT8(ir&0xFF)<<1;
1308 sh4_stats[I_BF]++;
1309 }
1310 break;
1311 case 0xD:
1312 { /* BT/S disp */
1313 int32_t disp = SIGNEXT8(ir&0xFF)<<1;
1314 sh4_stats[I_BTS]++;
1315 }
1316 break;
1317 case 0xF:
1318 { /* BF/S disp */
1319 int32_t disp = SIGNEXT8(ir&0xFF)<<1;
1320 sh4_stats[I_BFS]++;
1321 }
1322 break;
1323 default:
1324 UNDEF();
1325 break;
1326 }
1327 break;
1328 case 0x9:
1329 { /* MOV.W @(disp, PC), Rn */
1330 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1;
1331 sh4_stats[I_MOVW]++;
1332 }
1333 break;
1334 case 0xA:
1335 { /* BRA disp */
1336 int32_t disp = SIGNEXT12(ir&0xFFF)<<1;
1337 sh4_stats[I_BRA]++;
1338 }
1339 break;
1340 case 0xB:
1341 { /* BSR disp */
1342 int32_t disp = SIGNEXT12(ir&0xFFF)<<1;
1343 sh4_stats[I_BSR]++;
1344 }
1345 break;
1346 case 0xC:
1347 switch( (ir&0xF00) >> 8 ) {
1348 case 0x0:
1349 { /* MOV.B R0, @(disp, GBR) */
1350 uint32_t disp = (ir&0xFF);
1351 sh4_stats[I_MOVB]++;
1352 }
1353 break;
1354 case 0x1:
1355 { /* MOV.W R0, @(disp, GBR) */
1356 uint32_t disp = (ir&0xFF)<<1;
1357 sh4_stats[I_MOVW]++;
1358 }
1359 break;
1360 case 0x2:
1361 { /* MOV.L R0, @(disp, GBR) */
1362 uint32_t disp = (ir&0xFF)<<2;
1363 sh4_stats[I_MOVL]++;
1364 }
1365 break;
1366 case 0x3:
1367 { /* TRAPA #imm */
1368 uint32_t imm = (ir&0xFF);
1369 sh4_stats[I_TRAPA]++;
1370 }
1371 break;
1372 case 0x4:
1373 { /* MOV.B @(disp, GBR), R0 */
1374 uint32_t disp = (ir&0xFF);
1375 sh4_stats[I_MOVB]++;
1376 }
1377 break;
1378 case 0x5:
1379 { /* MOV.W @(disp, GBR), R0 */
1380 uint32_t disp = (ir&0xFF)<<1;
1381 sh4_stats[I_MOVW]++;
1382 }
1383 break;
1384 case 0x6:
1385 { /* MOV.L @(disp, GBR), R0 */
1386 uint32_t disp = (ir&0xFF)<<2;
1387 sh4_stats[I_MOVL]++;
1388 }
1389 break;
1390 case 0x7:
1391 { /* MOVA @(disp, PC), R0 */
1392 uint32_t disp = (ir&0xFF)<<2;
1393 sh4_stats[I_MOVA]++;
1394 }
1395 break;
1396 case 0x8:
1397 { /* TST #imm, R0 */
1398 uint32_t imm = (ir&0xFF);
1399 sh4_stats[I_TSTI]++;
1400 }
1401 break;
1402 case 0x9:
1403 { /* AND #imm, R0 */
1404 uint32_t imm = (ir&0xFF);
1405 sh4_stats[I_ANDI]++;
1406 }
1407 break;
1408 case 0xA:
1409 { /* XOR #imm, R0 */
1410 uint32_t imm = (ir&0xFF);
1411 sh4_stats[I_XORI]++;
1412 }
1413 break;
1414 case 0xB:
1415 { /* OR #imm, R0 */
1416 uint32_t imm = (ir&0xFF);
1417 sh4_stats[I_ORI]++;
1418 }
1419 break;
1420 case 0xC:
1421 { /* TST.B #imm, @(R0, GBR) */
1422 uint32_t imm = (ir&0xFF);
1423 sh4_stats[I_TSTB]++;
1424 }
1425 break;
1426 case 0xD:
1427 { /* AND.B #imm, @(R0, GBR) */
1428 uint32_t imm = (ir&0xFF);
1429 sh4_stats[I_ANDB]++;
1430 }
1431 break;
1432 case 0xE:
1433 { /* XOR.B #imm, @(R0, GBR) */
1434 uint32_t imm = (ir&0xFF);
1435 sh4_stats[I_XORB]++;
1436 }
1437 break;
1438 case 0xF:
1439 { /* OR.B #imm, @(R0, GBR) */
1440 uint32_t imm = (ir&0xFF);
1441 sh4_stats[I_ORB]++;
1442 }
1443 break;
1444 }
1445 break;
1446 case 0xD:
1447 { /* MOV.L @(disp, PC), Rn */
1448 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<2;
1449 sh4_stats[I_MOVLPC]++;
1450 }
1451 break;
1452 case 0xE:
1453 { /* MOV #imm, Rn */
1454 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF);
1455 sh4_stats[I_MOVI]++;
1456 }
1457 break;
1458 case 0xF:
1459 switch( ir&0xF ) {
1460 case 0x0:
1461 { /* FADD FRm, FRn */
1462 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1463 sh4_stats[I_FADD]++;
1464 }
1465 break;
1466 case 0x1:
1467 { /* FSUB FRm, FRn */
1468 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1469 sh4_stats[I_FSUB]++;
1470 }
1471 break;
1472 case 0x2:
1473 { /* FMUL FRm, FRn */
1474 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1475 sh4_stats[I_FMUL]++;
1476 }
1477 break;
1478 case 0x3:
1479 { /* FDIV FRm, FRn */
1480 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1481 sh4_stats[I_FDIV]++;
1482 }
1483 break;
1484 case 0x4:
1485 { /* FCMP/EQ FRm, FRn */
1486 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1487 sh4_stats[I_FCMPEQ]++;
1488 }
1489 break;
1490 case 0x5:
1491 { /* FCMP/GT FRm, FRn */
1492 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1493 sh4_stats[I_FCMPGT]++;
1494 }
1495 break;
1496 case 0x6:
1497 { /* FMOV @(R0, Rm), FRn */
1498 uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1499 sh4_stats[I_FMOV7]++;
1500 }
1501 break;
1502 case 0x7:
1503 { /* FMOV FRm, @(R0, Rn) */
1504 uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1505 sh4_stats[I_FMOV4]++;
1506 }
1507 break;
1508 case 0x8:
1509 { /* FMOV @Rm, FRn */
1510 uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1511 sh4_stats[I_FMOV5]++;
1512 }
1513 break;
1514 case 0x9:
1515 { /* FMOV @Rm+, FRn */
1516 uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1517 sh4_stats[I_FMOV6]++;
1518 }
1519 break;
1520 case 0xA:
1521 { /* FMOV FRm, @Rn */
1522 uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1523 sh4_stats[I_FMOV2]++;
1524 }
1525 break;
1526 case 0xB:
1527 { /* FMOV FRm, @-Rn */
1528 uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1529 sh4_stats[I_FMOV3]++;
1530 }
1531 break;
1532 case 0xC:
1533 { /* FMOV FRm, FRn */
1534 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1535 sh4_stats[I_FMOV1]++;
1536 }
1537 break;
1538 case 0xD:
1539 switch( (ir&0xF0) >> 4 ) {
1540 case 0x0:
1541 { /* FSTS FPUL, FRn */
1542 uint32_t FRn = ((ir>>8)&0xF);
1543 sh4_stats[I_FSTS]++;
1544 }
1545 break;
1546 case 0x1:
1547 { /* FLDS FRm, FPUL */
1548 uint32_t FRm = ((ir>>8)&0xF);
1549 sh4_stats[I_FLDS]++;
1550 }
1551 break;
1552 case 0x2:
1553 { /* FLOAT FPUL, FRn */
1554 uint32_t FRn = ((ir>>8)&0xF);
1555 sh4_stats[I_FLOAT]++;
1556 }
1557 break;
1558 case 0x3:
1559 { /* FTRC FRm, FPUL */
1560 uint32_t FRm = ((ir>>8)&0xF);
1561 sh4_stats[I_FTRC]++;
1562 }
1563 break;
1564 case 0x4:
1565 { /* FNEG FRn */
1566 uint32_t FRn = ((ir>>8)&0xF);
1567 sh4_stats[I_FNEG]++;
1568 }
1569 break;
1570 case 0x5:
1571 { /* FABS FRn */
1572 uint32_t FRn = ((ir>>8)&0xF);
1573 sh4_stats[I_FABS]++;
1574 }
1575 break;
1576 case 0x6:
1577 { /* FSQRT FRn */
1578 uint32_t FRn = ((ir>>8)&0xF);
1579 sh4_stats[I_FSQRT]++;
1580 }
1581 break;
1582 case 0x7:
1583 { /* FSRRA FRn */
1584 uint32_t FRn = ((ir>>8)&0xF);
1585 sh4_stats[I_FSRRA]++;
1586 }
1587 break;
1588 case 0x8:
1589 { /* FLDI0 FRn */
1590 uint32_t FRn = ((ir>>8)&0xF);
1591 sh4_stats[I_FLDI0]++;
1592 }
1593 break;
1594 case 0x9:
1595 { /* FLDI1 FRn */
1596 uint32_t FRn = ((ir>>8)&0xF);
1597 sh4_stats[I_FLDI1]++;
1598 }
1599 break;
1600 case 0xA:
1601 { /* FCNVSD FPUL, FRn */
1602 uint32_t FRn = ((ir>>8)&0xF);
1603 sh4_stats[I_FCNVSD]++;
1604 }
1605 break;
1606 case 0xB:
1607 { /* FCNVDS FRm, FPUL */
1608 uint32_t FRm = ((ir>>8)&0xF);
1609 sh4_stats[I_FCNVDS]++;
1610 }
1611 break;
1612 case 0xE:
1613 { /* FIPR FVm, FVn */
1614 uint32_t FVn = ((ir>>10)&0x3); uint32_t FVm = ((ir>>8)&0x3);
1615 sh4_stats[I_FIPR]++;
1616 }
1617 break;
1618 case 0xF:
1619 switch( (ir&0x100) >> 8 ) {
1620 case 0x0:
1621 { /* FSCA FPUL, FRn */
1622 uint32_t FRn = ((ir>>9)&0x7)<<1;
1623 sh4_stats[I_FSCA]++;
1624 }
1625 break;
1626 case 0x1:
1627 switch( (ir&0x200) >> 9 ) {
1628 case 0x0:
1629 { /* FTRV XMTRX, FVn */
1630 uint32_t FVn = ((ir>>10)&0x3);
1631 sh4_stats[I_FTRV]++;
1632 }
1633 break;
1634 case 0x1:
1635 switch( (ir&0xC00) >> 10 ) {
1636 case 0x0:
1637 { /* FSCHG */
1638 sh4_stats[I_FSCHG]++;
1639 }
1640 break;
1641 case 0x2:
1642 { /* FRCHG */
1643 sh4_stats[I_FRCHG]++;
1644 }
1645 break;
1646 case 0x3:
1647 { /* UNDEF */
1648 sh4_stats[I_UNDEF]++;
1649 }
1650 break;
1651 default:
1652 UNDEF();
1653 break;
1654 }
1655 break;
1656 }
1657 break;
1658 }
1659 break;
1660 default:
1661 UNDEF();
1662 break;
1663 }
1664 break;
1665 case 0xE:
1666 { /* FMAC FR0, FRm, FRn */
1667 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1668 sh4_stats[I_FMAC]++;
1669 }
1670 break;
1671 default:
1672 UNDEF();
1673 break;
1674 }
1675 break;
1676 }
1679 sh4_stats_total++;
1680 }
.