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lxdream.org :: lxdream/src/sh4/x86op.h
lxdream 0.9.1
released Jun 29
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filename src/sh4/x86op.h
changeset 675:b97020f9af1c
prev669:ab344e42bca9
next736:a02d1475ccfd
author nkeynes
date Mon May 26 11:01:42 2008 +0000 (11 years ago)
permissions -rw-r--r--
last change hange 64-bit configuration to use sizeof(void *) rather than the system id
returned by config.guess - config.guess gets it wrong in some situations.
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     1 /**
     2  * $Id$
     3  * 
     4  * Definitions of x86 opcodes for use by the translator.
     5  *
     6  * Copyright (c) 2007 Nathan Keynes.
     7  *
     8  * This program is free software; you can redistribute it and/or modify
     9  * it under the terms of the GNU General Public License as published by
    10  * the Free Software Foundation; either version 2 of the License, or
    11  * (at your option) any later version.
    12  *
    13  * This program is distributed in the hope that it will be useful,
    14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    16  * GNU General Public License for more details.
    17  */
    19 #ifndef __lxdream_x86op_H
    20 #define __lxdream_x86op_H
    22 #define R_NONE -1
    23 #define R_EAX 0
    24 #define R_ECX 1
    25 #define R_EDX 2
    26 #define R_EBX 3
    27 #define R_ESP 4
    28 #define R_EBP 5
    29 #define R_ESI 6 
    30 #define R_EDI 7 
    32 #define R_AL 0
    33 #define R_CL 1
    34 #define R_DL 2
    35 #define R_BL 3
    36 #define R_AH 4
    37 #define R_CH 5
    38 #define R_DH 6
    39 #define R_BH 7
    41 #define MARK_JMP8(x) uint8_t *_mark_jmp_##x = xlat_output
    42 #define MARK_JMP32(x) uint32_t *_mark_jmp_##x = (uint32_t *)xlat_output
    43 #define JMP_TARGET(x) *_mark_jmp_##x += (xlat_output - _mark_jmp_##x)
    45 #define OP(x) *xlat_output++ = (x)
    46 #define OP32(x) *((uint32_t *)xlat_output) = (x); xlat_output+=4
    47 #define OP64(x) *((uint64_t *)xlat_output) = (x); xlat_output+=8
    48 #if SIZEOF_VOID_P == 8
    49 #define OPPTR(x) OP64((uint64_t)(x))
    50 #define AND_imm8s_rptr(imm, r1)  REXW(); AND_imm8s_r32( imm, r1 )
    51 #define MOV_moffptr_EAX(offptr)  REXW(); MOV_moff32_EAX( offptr )
    52 #define STACK_ALIGN 16
    53 #define POP_r32(r1)           OP(0x58 + r1);
    54 #define POP_realigned_r32(r1)   OP(0x58 + r1); REXW(); ADD_imm8s_r32(8,R_ESP)
    55 #define PUSH_r32(r1)          OP(0x50 + r1);
    56 #define PUSH_realigned_r32(r1)  REXW(); SUB_imm8s_r32(8, R_ESP); OP(0x50 + r1)
    57 #define PUSH_imm32(imm)       OP(0x68); OP32(imm);
    58 #define PUSH_imm64(imm)       REXW(); OP(0x68); OP64(imm);
    59 #else /* 32-bit system */
    60 #define OPPTR(x) OP32((uint32_t)(x))
    61 #define AND_imm8s_rptr(imm, r1) AND_imm8s_r32( imm, r1 )
    62 #define MOV_moffptr_EAX(offptr) MOV_moff32_EAX( offptr )
    63 #define POP_realigned_r32(r1)   POP_r32(r1)
    64 #define PUSH_realigned_r32(r1)  PUSH_r32(r1)
    65 #ifdef APPLE_BUILD
    66 #define STACK_ALIGN 16
    67 #define POP_r32(r1)           OP(0x58 + r1); sh4_x86.stack_posn -= 4;
    68 #define PUSH_r32(r1)          OP(0x50 + r1); sh4_x86.stack_posn += 4;
    69 #define PUSH_imm32(imm)       OP(0x68); OP32(imm); sh4_x86.stack_posn += 4;
    70 #else
    71 #define POP_r32(r1)           OP(0x58 + r1)
    72 #define PUSH_r32(r1)          OP(0x50 + r1)
    73 #define PUSH_imm32(imm)       OP(0x68); OP32(imm)
    74 #endif
    75 #endif
    77 #ifdef STACK_ALIGN
    78 #else
    79 #define POP_r32(r1)           OP(0x58 + r1)
    80 #define PUSH_r32(r1)          OP(0x50 + r1)
    81 #endif
    84 /* Offset of a reg relative to the sh4r structure */
    85 #define REG_OFFSET(reg)  (((char *)&sh4r.reg) - ((char *)&sh4r) - 128)
    87 #define R_T   REG_OFFSET(t)
    88 #define R_Q   REG_OFFSET(q)
    89 #define R_S   REG_OFFSET(s)
    90 #define R_M   REG_OFFSET(m)
    91 #define R_SR  REG_OFFSET(sr)
    92 #define R_GBR REG_OFFSET(gbr)
    93 #define R_SSR REG_OFFSET(ssr)
    94 #define R_SPC REG_OFFSET(spc)
    95 #define R_VBR REG_OFFSET(vbr)
    96 #define R_MACH REG_OFFSET(mac)+4
    97 #define R_MACL REG_OFFSET(mac)
    98 #define R_PC REG_OFFSET(pc)
    99 #define R_NEW_PC REG_OFFSET(new_pc)
   100 #define R_PR REG_OFFSET(pr)
   101 #define R_SGR REG_OFFSET(sgr)
   102 #define R_FPUL REG_OFFSET(fpul)
   103 #define R_FPSCR REG_OFFSET(fpscr)
   104 #define R_DBR REG_OFFSET(dbr)
   106 /**************** Basic X86 operations *********************/
   107 /* Note: operands follow SH4 convention (source, dest) rather than x86 
   108  * conventions (dest, source)
   109  */
   111 /* Two-reg modrm form - first arg is the r32 reg, second arg is the r/m32 reg */
   112 #define MODRM_r32_rm32(r1,r2) OP(0xC0 | (r1<<3) | r2)
   113 #define MODRM_rm32_r32(r1,r2) OP(0xC0 | (r2<<3) | r1)
   115 /* ebp+disp8 modrm form */
   116 #define MODRM_r32_ebp8(r1,disp) OP(0x45 | (r1<<3)); OP(disp)
   118 /* ebp+disp32 modrm form */
   119 #define MODRM_r32_ebp32(r1,disp) OP(0x85 | (r1<<3)); OP32(disp)
   121 #define MODRM_r32_sh4r(r1,disp) if(disp>127){ MODRM_r32_ebp32(r1,disp);}else{ MODRM_r32_ebp8(r1,(unsigned char)disp); }
   123 #define REXW() OP(0x48)
   125 /* Major opcodes */
   126 #define ADD_sh4r_r32(disp,r1) OP(0x03); MODRM_r32_sh4r(r1,disp)
   127 #define ADD_r32_sh4r(r1,disp) OP(0x01); MODRM_r32_sh4r(r1,disp)
   128 #define ADD_r32_r32(r1,r2) OP(0x03); MODRM_rm32_r32(r1,r2)
   129 #define ADD_imm8s_r32(imm,r1) OP(0x83); MODRM_rm32_r32(r1, 0); OP(imm)
   130 #define ADD_imm8s_sh4r(imm,disp) OP(0x83); MODRM_r32_sh4r(0,disp); OP(imm)
   131 #define ADD_imm32_r32(imm32,r1) OP(0x81); MODRM_rm32_r32(r1,0); OP32(imm32)
   132 #define ADC_r32_r32(r1,r2)    OP(0x13); MODRM_rm32_r32(r1,r2)
   133 #define ADC_sh4r_r32(disp,r1) OP(0x13); MODRM_r32_sh4r(r1,disp)
   134 #define ADC_r32_sh4r(r1,disp) OP(0x11); MODRM_r32_sh4r(r1,disp)
   135 #define AND_r32_r32(r1,r2)    OP(0x23); MODRM_rm32_r32(r1,r2)
   136 #define AND_imm8_r8(imm8, r1) OP(0x80); MODRM_rm32_r32(r1,4); OP(imm8)
   137 #define AND_imm8s_r32(imm8,r1) OP(0x83); MODRM_rm32_r32(r1,4); OP(imm8)
   138 #define AND_imm32_r32(imm,r1) OP(0x81); MODRM_rm32_r32(r1,4); OP32(imm)
   139 #define CALL_r32(r1)          OP(0xFF); MODRM_rm32_r32(r1,2)
   140 #define CLC()                 OP(0xF8)
   141 #define CMC()                 OP(0xF5)
   142 #define CMP_sh4r_r32(disp,r1)  OP(0x3B); MODRM_r32_sh4r(r1,disp)
   143 #define CMP_r32_r32(r1,r2)    OP(0x3B); MODRM_rm32_r32(r1,r2)
   144 #define CMP_imm32_r32(imm32, r1) OP(0x81); MODRM_rm32_r32(r1,7); OP32(imm32)
   145 #define CMP_imm8s_r32(imm,r1) OP(0x83); MODRM_rm32_r32(r1,7); OP(imm)
   146 #define CMP_imm8s_sh4r(imm,disp) OP(0x83); MODRM_r32_sh4r(7,disp) OP(imm)
   147 #define DEC_r32(r1)           OP(0x48+r1)
   148 #define IMUL_r32(r1)          OP(0xF7); MODRM_rm32_r32(r1,5)
   149 #define INC_r32(r1)           OP(0x40+r1)
   150 #define JMP_rel8(label)  OP(0xEB); MARK_JMP8(label); OP(-1); 
   151 #define LEA_sh4r_r32(disp,r1) OP(0x8D); MODRM_r32_sh4r(r1,disp)
   152 #define MOV_r32_r32(r1,r2)    OP(0x89); MODRM_r32_rm32(r1,r2)
   153 #define MOV_r32_sh4r(r1,disp) OP(0x89); MODRM_r32_sh4r(r1,disp)
   154 #define MOV_moff32_EAX(off)   OP(0xA1); OPPTR(off)
   155 #define MOV_sh4r_r32(disp, r1)  OP(0x8B); MODRM_r32_sh4r(r1,disp)
   156 #define MOV_r32ind_r32(r1,r2) OP(0x8B); OP(0 + (r2<<3) + r1 )
   157 #define MOVSX_r8_r32(r1,r2)   OP(0x0F); OP(0xBE); MODRM_rm32_r32(r1,r2)
   158 #define MOVSX_r16_r32(r1,r2)  OP(0x0F); OP(0xBF); MODRM_rm32_r32(r1,r2)
   159 #define MOVZX_r8_r32(r1,r2)   OP(0x0F); OP(0xB6); MODRM_rm32_r32(r1,r2)
   160 #define MOVZX_r16_r32(r1,r2)  OP(0x0F); OP(0xB7); MODRM_rm32_r32(r1,r2)
   161 #define MUL_r32(r1)           OP(0xF7); MODRM_rm32_r32(r1,4)
   162 #define NEG_r32(r1)           OP(0xF7); MODRM_rm32_r32(r1,3)
   163 #define NOT_r32(r1)           OP(0xF7); MODRM_rm32_r32(r1,2)
   164 #define OR_r32_r32(r1,r2)     OP(0x0B); MODRM_rm32_r32(r1,r2)
   165 #define OR_imm8_r8(imm,r1)    OP(0x80); MODRM_rm32_r32(r1,1); OP(imm)
   166 #define OR_imm32_r32(imm,r1)  OP(0x81); MODRM_rm32_r32(r1,1); OP32(imm)
   167 #define OR_sh4r_r32(disp,r1)  OP(0x0B); MODRM_r32_sh4r(r1,disp)
   168 #define RCL1_r32(r1)          OP(0xD1); MODRM_rm32_r32(r1,2)
   169 #define RCR1_r32(r1)          OP(0xD1); MODRM_rm32_r32(r1,3)
   170 #define RET()                 OP(0xC3)
   171 #define ROL1_r32(r1)          OP(0xD1); MODRM_rm32_r32(r1,0)
   172 #define ROR1_r32(r1)          OP(0xD1); MODRM_rm32_r32(r1,1)
   173 #define SAR1_r32(r1)          OP(0xD1); MODRM_rm32_r32(r1,7)
   174 #define SAR_imm8_r32(imm,r1)  OP(0xC1); MODRM_rm32_r32(r1,7); OP(imm)
   175 #define SAR_r32_CL(r1)        OP(0xD3); MODRM_rm32_r32(r1,7)
   176 #define SBB_r32_r32(r1,r2)    OP(0x1B); MODRM_rm32_r32(r1,r2)
   177 #define SHL1_r32(r1)          OP(0xD1); MODRM_rm32_r32(r1,4)
   178 #define SHL_r32_CL(r1)        OP(0xD3); MODRM_rm32_r32(r1,4)
   179 #define SHL_imm8_r32(imm,r1)  OP(0xC1); MODRM_rm32_r32(r1,4); OP(imm)
   180 #define SHR1_r32(r1)          OP(0xD1); MODRM_rm32_r32(r1,5)
   181 #define SHR_r32_CL(r1)        OP(0xD3); MODRM_rm32_r32(r1,5)
   182 #define SHR_imm8_r32(imm,r1)  OP(0xC1); MODRM_rm32_r32(r1,5); OP(imm)
   183 #define STC()                 OP(0xF9)
   184 #define SUB_r32_r32(r1,r2)    OP(0x2B); MODRM_rm32_r32(r1,r2)
   185 #define SUB_sh4r_r32(disp,r1)  OP(0x2B); MODRM_r32_sh4r(r1, disp)
   186 #define SUB_imm8s_r32(imm,r1) ADD_imm8s_r32(-(imm),r1)
   187 #define TEST_r8_r8(r1,r2)     OP(0x84); MODRM_r32_rm32(r1,r2)
   188 #define TEST_r32_r32(r1,r2)   OP(0x85); MODRM_rm32_r32(r1,r2)
   189 #define TEST_imm8_r8(imm8,r1) OP(0xF6); MODRM_rm32_r32(r1,0); OP(imm8)
   190 #define TEST_imm32_r32(imm,r1) OP(0xF7); MODRM_rm32_r32(r1,0); OP32(imm)
   191 #define XCHG_r8_r8(r1,r2)     OP(0x86); MODRM_rm32_r32(r1,r2)
   192 #define XOR_r8_r8(r1,r2)      OP(0x32); MODRM_rm32_r32(r1,r2)
   193 #define XOR_imm8s_r32(imm,r1)   OP(0x83); MODRM_rm32_r32(r1,6); OP(imm)
   194 #define XOR_r32_r32(r1,r2)    OP(0x33); MODRM_rm32_r32(r1,r2)
   195 #define XOR_sh4r_r32(disp,r1)    OP(0x33); MODRM_r32_sh4r(r1,disp)
   196 #define XOR_imm32_r32(imm,r1) OP(0x81); MODRM_rm32_r32(r1,6); OP32(imm)
   199 /* Floating point ops */
   200 #define FABS_st0() OP(0xD9); OP(0xE1)
   201 #define FADDP_st(st) OP(0xDE); OP(0xC0+st)
   202 #define FCHS_st0() OP(0xD9); OP(0xE0)
   203 #define FCOMIP_st(st) OP(0xDF); OP(0xF0+st)
   204 #define FDIVP_st(st) OP(0xDE); OP(0xF8+st)
   205 #define FILD_r32ind(r32) OP(0xDB); OP(0x00+r32)
   206 #define FLD0_st0() OP(0xD9); OP(0xEE);
   207 #define FLD1_st0() OP(0xD9); OP(0xE8);
   208 #define FLDf_sh4r(disp) OP(0xD9); MODRM_r32_sh4r(0, disp)
   209 #define FLDd_sh4r(disp) OP(0xDD); MODRM_r32_sh4r(0, disp)
   210 #define FLDCW_r32ind(r32) OP(0xD9); OP(0x28+r32)
   211 #define FMULP_st(st) OP(0xDE); OP(0xC8+st)
   212 #define FNSTCW_r32ind(r32) OP(0xD9); OP(0x38+r32)
   213 #define FPOP_st()  OP(0xDD); OP(0xC0); OP(0xD9); OP(0xF7)
   214 #define FSTPf_sh4r(disp) OP(0xD9); MODRM_r32_sh4r(3, disp)
   215 #define FSTPd_sh4r(disp) OP(0xDD); MODRM_r32_sh4r(3, disp)
   216 #define FSUBP_st(st) OP(0xDE); OP(0xE8+st)
   217 #define FSQRT_st0() OP(0xD9); OP(0xFA)
   219 #define FILD_sh4r(disp) OP(0xDB); MODRM_r32_sh4r(0, disp)
   220 #define FLDF_sh4r(disp) OP(0xD9); MODRM_r32_sh4r(0, disp)
   221 #define FLDD_sh4r(disp) OP(0xDD); MODRM_r32_sh4r(0, disp)
   222 #define FISTP_sh4r(disp) OP(0xDB); MODRM_r32_sh4r(3, disp)
   223 #define FSTPF_sh4r(disp) OP(0xD9); MODRM_r32_sh4r(3,disp)
   224 #define FSTPD_sh4r(disp) OP(0xDD); MODRM_r32_sh4r(3,disp)
   226 /* Conditional branches */
   227 #define JE_rel8(label)   OP(0x74); MARK_JMP8(label); OP(-1)
   228 #define JA_rel8(label)   OP(0x77); MARK_JMP8(label); OP(-1)
   229 #define JAE_rel8(label)  OP(0x73); MARK_JMP8(label); OP(-1)
   230 #define JG_rel8(label)   OP(0x7F); MARK_JMP8(label); OP(-1)
   231 #define JGE_rel8(label)  OP(0x7D); MARK_JMP8(label); OP(-1)
   232 #define JC_rel8(label)   OP(0x72); MARK_JMP8(label); OP(-1)
   233 #define JO_rel8(label)   OP(0x70); MARK_JMP8(label); OP(-1)
   234 #define JNE_rel8(label)  OP(0x75); MARK_JMP8(label); OP(-1)
   235 #define JNA_rel8(label)  OP(0x76); MARK_JMP8(label); OP(-1)
   236 #define JNAE_rel8(label) OP(0x72); MARK_JMP8(label); OP(-1)
   237 #define JNG_rel8(label)  OP(0x7E); MARK_JMP8(label); OP(-1)
   238 #define JNGE_rel8(label) OP(0x7C); MARK_JMP8(label); OP(-1)
   239 #define JNC_rel8(label)  OP(0x73); MARK_JMP8(label); OP(-1)
   240 #define JNO_rel8(label)  OP(0x71); MARK_JMP8(label); OP(-1)
   241 #define JNS_rel8(label)  OP(0x79); MARK_JMP8(label); OP(-1)
   242 #define JS_rel8(label)   OP(0x78); MARK_JMP8(label); OP(-1)
   244 /** JMP relative 8 or 32 depending on size of rel. rel offset
   245  * from the start of the instruction (not end)
   246  */
   247 #define JMP_rel(rel) if((rel)<-126||(rel)>129) { OP(0xE9); OP32((rel)-5); } else { OP(0xEB); OP((rel)-2); }
   249 /* 32-bit long forms w/ backpatching to an exception routine */
   250 #define JMP_exc(exc)  OP(0xE9); sh4_x86_add_backpatch(xlat_output, pc, exc); OP32(0)
   251 #define JE_exc(exc)  OP(0x0F); OP(0x84); sh4_x86_add_backpatch(xlat_output, pc, exc); OP32(0)
   252 #define JA_exc(exc)  OP(0x0F); OP(0x87); sh4_x86_add_backpatch(xlat_output, pc, exc); OP32(0)
   253 #define JAE_exc(exc) OP(0x0F); OP(0x83); sh4_x86_add_backpatch(xlat_output, pc, exc); OP32(0)
   254 #define JG_exc(exc)  OP(0x0F); OP(0x8F); sh4_x86_add_backpatch(xlat_output, pc, exc); OP32(0)
   255 #define JGE_exc(exc) OP(0x0F); OP(0x8D); sh4_x86_add_backpatch(xlat_output, pc, exc); OP32(0)
   256 #define JC_exc(exc)  OP(0x0F); OP(0x82); sh4_x86_add_backpatch(xlat_output, pc, exc); OP32(0)
   257 #define JO_exc(exc)  OP(0x0F); OP(0x80); sh4_x86_add_backpatch(xlat_output, pc, exc); OP32(0)
   258 #define JNE_exc(exc) OP(0x0F); OP(0x85); sh4_x86_add_backpatch(xlat_output, pc, exc); OP32(0)
   259 #define JNA_exc(exc) OP(0x0F); OP(0x86); sh4_x86_add_backpatch(xlat_output, pc, exc); OP32(0)
   260 #define JNAE_exc(exc) OP(0x0F);OP(0x82); sh4_x86_add_backpatch(xlat_output, pc, exc); OP32(0)
   261 #define JNG_exc(exc) OP(0x0F); OP(0x8E); sh4_x86_add_backpatch(xlat_output, pc, exc); OP32(0)
   262 #define JNGE_exc(exc) OP(0x0F);OP(0x8C); sh4_x86_add_backpatch(xlat_output, pc, exc); OP32(0)
   263 #define JNC_exc(exc) OP(0x0F); OP(0x83); sh4_x86_add_backpatch(xlat_output, pc, exc); OP32(0)
   264 #define JNO_exc(exc) OP(0x0F); OP(0x81); sh4_x86_add_backpatch(xlat_output, pc, exc); OP32(0)
   267 /* Conditional moves ebp-rel */
   268 #define CMOVE_r32_r32(r1,r2)  OP(0x0F); OP(0x44); MODRM_rm32_r32(r1,r2)
   269 #define CMOVA_r32_r32(r1,r2)  OP(0x0F); OP(0x47); MODRM_rm32_r32(r1,r2)
   270 #define CMOVAE_r32_r32(r1,r2) OP(0x0F); OP(0x43); MODRM_rm32_r32(r1,r2)
   271 #define CMOVG_r32_r32(r1,r2)  OP(0x0F); OP(0x4F); MODRM_rm32_r32(r1,r2)
   272 #define CMOVGE_r32_r32(r1,r2)  OP(0x0F); OP(0x4D); MODRM_rm32_r32(r1,r2)
   273 #define CMOVC_r32_r32(r1,r2)  OP(0x0F); OP(0x42); MODRM_rm32_r32(r1,r2)
   274 #define CMOVO_r32_r32(r1,r2)  OP(0x0F); OP(0x40); MODRM_rm32_r32(r1,r2)
   277 /* Conditional setcc - writeback to sh4r.t */
   278 #define SETE_sh4r(disp)    OP(0x0F); OP(0x94); MODRM_r32_sh4r(0, disp);
   279 #define SETA_sh4r(disp)    OP(0x0F); OP(0x97); MODRM_r32_sh4r(0, disp);
   280 #define SETAE_sh4r(disp)   OP(0x0F); OP(0x93); MODRM_r32_sh4r(0, disp);
   281 #define SETG_sh4r(disp)    OP(0x0F); OP(0x9F); MODRM_r32_sh4r(0, disp);
   282 #define SETGE_sh4r(disp)   OP(0x0F); OP(0x9D); MODRM_r32_sh4r(0, disp);
   283 #define SETC_sh4r(disp)    OP(0x0F); OP(0x92); MODRM_r32_sh4r(0, disp);
   284 #define SETO_sh4r(disp)    OP(0x0F); OP(0x90); MODRM_r32_sh4r(0, disp);
   286 #define SETNE_sh4r(disp)   OP(0x0F); OP(0x95); MODRM_r32_sh4r(0, disp);
   287 #define SETNA_sh4r(disp)   OP(0x0F); OP(0x96); MODRM_r32_sh4r(0, disp);
   288 #define SETNAE_sh4r(disp)  OP(0x0F); OP(0x92); MODRM_r32_sh4r(0, disp);
   289 #define SETNG_sh4r(disp)   OP(0x0F); OP(0x9E); MODRM_r32_sh4r(0, disp);
   290 #define SETNGE_sh4r(disp)  OP(0x0F); OP(0x9C); MODRM_r32_sh4r(0, disp);
   291 #define SETNC_sh4r(disp)   OP(0x0F); OP(0x93); MODRM_r32_sh4r(0, disp);
   292 #define SETNO_sh4r(disp)   OP(0x0F); OP(0x91); MODRM_r32_sh4r(0, disp);
   294 #define SETE_t() SETE_sh4r(R_T)
   295 #define SETA_t() SETA_sh4r(R_T)
   296 #define SETAE_t() SETAE_sh4r(R_T)
   297 #define SETG_t() SETG_sh4r(R_T)
   298 #define SETGE_t() SETGE_sh4r(R_T)
   299 #define SETC_t() SETC_sh4r(R_T)
   300 #define SETO_t() SETO_sh4r(R_T)
   301 #define SETNE_t() SETNE_sh4r(R_T)
   303 #define SETC_r8(r1)      OP(0x0F); OP(0x92); MODRM_rm32_r32(r1, 0)
   305 /* Pseudo-op Load carry from T: CMP [EBP+t], #01 ; CMC */
   306 #define LDC_t()     OP(0x83); MODRM_r32_sh4r(7,R_T); OP(0x01); CMC()
   308 #endif /* !__lxdream_x86op_H */
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