lxdream.org :: lxdream/src/sh4/sh4core.c r84:b993a8d8fbf3

tree revision 84:b993a8d8fbf3

filename	src/sh4/sh4core.c
changeset	84:b993a8d8fbf3
prev	53:f2981805b929
next	92:108450d84ce8
author	nkeynes
date	Sat Jan 21 11:38:36 2006 +0000 (14 years ago)
permissions	-rw-r--r--
last change	Fix double-precision floating point

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     1 /**

     2  * $Id: sh4core.c,v 1.18 2006-01-21 11:38:36 nkeynes Exp $

     3  *

     4  * SH4 emulation core, and parent module for all the SH4 peripheral

     5  * modules.

     6  *

     7  * Copyright (c) 2005 Nathan Keynes.

     8  *

     9  * This program is free software; you can redistribute it and/or modify

    10  * it under the terms of the GNU General Public License as published by

    11  * the Free Software Foundation; either version 2 of the License, or

    12  * (at your option) any later version.

    13  *

    14  * This program is distributed in the hope that it will be useful,

    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of

    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

    17  * GNU General Public License for more details.

    18  */

    20 #define MODULE sh4_module

    21 #include <math.h>

    22 #include "dream.h"

    23 #include "sh4/sh4core.h"

    24 #include "sh4/sh4mmio.h"

    25 #include "sh4/intc.h"

    26 #include "mem.h"

    27 #include "clock.h"

    28 #include "bios.h"

    30 /* CPU-generated exception code/vector pairs */

    31 #define EXC_POWER_RESET  0x000 /* vector special */

    32 #define EXC_MANUAL_RESET 0x020

    33 #define EXC_SLOT_ILLEGAL 0x1A0

    34 #define EXC_ILLEGAL      0x180

    35 #define EXV_ILLEGAL      0x100

    36 #define EXC_TRAP         0x160

    37 #define EXV_TRAP         0x100

    38 #define EXC_FPDISABLE    0x800

    39 #define EXV_FPDISABLE    0x100

    41 /********************** SH4 Module Definition ****************************/

    43 void sh4_init( void );

    44 void sh4_reset( void );

    45 uint32_t sh4_run_slice( uint32_t );

    46 void sh4_start( void );

    47 void sh4_stop( void );

    48 void sh4_save_state( FILE *f );

    49 int sh4_load_state( FILE *f );

    51 struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset,

    52 				       NULL, sh4_run_slice, sh4_stop,

    53 				       sh4_save_state, sh4_load_state };

    55 struct sh4_registers sh4r;

    57 void sh4_init(void)

    58 {

    59     register_io_regions( mmio_list_sh4mmio );

    60     mmu_init();

    61     sh4_reset();

    62 }

    64 void sh4_reset(void)

    65 {

    66     /* zero everything out, for the sake of having a consistent state. */

    67     memset( &sh4r, 0, sizeof(sh4r) );

    69     /* Resume running if we were halted */

    70     sh4r.sh4_state = SH4_STATE_RUNNING;

    72     sh4r.pc    = 0xA0000000;

    73     sh4r.new_pc= 0xA0000002;

    74     sh4r.vbr   = 0x00000000;

    75     sh4r.fpscr = 0x00040001;

    76     sh4r.sr    = 0x700000F0;

    78     /* Mem reset will do this, but if we want to reset _just_ the SH4... */

    79     MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );

    81     /* Peripheral modules */

    82     intc_reset();

    83     SCIF_reset();

    84 }

    86 static struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];

    87 static int sh4_breakpoint_count = 0;

    89 void sh4_set_breakpoint( uint32_t pc, int type )

    90 {

    91     sh4_breakpoints[sh4_breakpoint_count].address = pc;

    92     sh4_breakpoints[sh4_breakpoint_count].type = type;

    93     sh4_breakpoint_count++;

    94 }

    96 gboolean sh4_clear_breakpoint( uint32_t pc, int type )

    97 {

    98     int i;

   100     for( i=0; i<sh4_breakpoint_count; i++ ) {

   101 	if( sh4_breakpoints[i].address == pc &&

   102 	    sh4_breakpoints[i].type == type ) {

   103 	    while( ++i < sh4_breakpoint_count ) {

   104 		sh4_breakpoints[i-1].address = sh4_breakpoints[i].address;

   105 		sh4_breakpoints[i-1].type = sh4_breakpoints[i].type;

   106 	    }

   107 	    sh4_breakpoint_count--;

   108 	    return TRUE;

   109 	}

   110     }

   111     return FALSE;

   112 }

   114 int sh4_get_breakpoint( uint32_t pc )

   115 {

   116     int i;

   117     for( i=0; i<sh4_breakpoint_count; i++ ) {

   118 	if( sh4_breakpoints[i].address == pc )

   119 	    return sh4_breakpoints[i].type;

   120     }

   121     return 0;

   122 }

   124 uint32_t sh4_run_slice( uint32_t nanosecs )

   125 {

   126     int target = sh4r.icount + nanosecs / sh4_cpu_period;

   127     int start = sh4r.icount;

   128     int i;

   130     if( sh4r.sh4_state != SH4_STATE_RUNNING ) {

   131 	if( sh4r.int_pending != 0 )

   132 	    sh4r.sh4_state = SH4_STATE_RUNNING;;

   133     }

   135     for( sh4r.slice_cycle = 0; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {

   136 	if( !sh4_execute_instruction() )

   137 	    break;

   138 #ifdef ENABLE_DEBUG_MODE

   139 	for( i=0; i<sh4_breakpoint_count; i++ ) {

   140 	    if( sh4_breakpoints[i].address == sh4r.pc ) {

   141 		break;

   142 	    }

   143 	}

   144 	if( i != sh4_breakpoint_count ) {

   145 	    dreamcast_stop();

   146 	    if( sh4_breakpoints[i].type == BREAK_ONESHOT )

   147 		sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );

   148 	    break;

   149 	}

   150 #endif

   151     }

   153     /* If we aborted early, but the cpu is still technically running,

   154      * we're doing a hard abort - cut the timeslice back to what we

   155      * actually executed

   156      */

   157     if( sh4r.slice_cycle != nanosecs && sh4r.sh4_state == SH4_STATE_RUNNING ) {

   158 	nanosecs = sh4r.slice_cycle;

   159     }

   160     if( sh4r.sh4_state != SH4_STATE_STANDBY ) {

   161 	TMU_run_slice( nanosecs );

   162 	SCIF_run_slice( nanosecs );

   163     }

   164     sh4r.icount += sh4r.slice_cycle / sh4_cpu_period;

   165     return nanosecs;

   166 }

   168 void sh4_stop(void)

   169 {

   171 }

   173 void sh4_save_state( FILE *f )

   174 {

   175     fwrite( &sh4r, sizeof(sh4r), 1, f );

   176     TMU_save_state( f );

   177     SCIF_save_state( f );

   178 }

   180 int sh4_load_state( FILE * f )

   181 {

   182     fread( &sh4r, sizeof(sh4r), 1, f );

   183     TMU_load_state( f );

   184     return SCIF_load_state( f );

   185 }

   187 /********************** SH4 emulation core  ****************************/

   189 void sh4_set_pc( int pc )

   190 {

   191     sh4r.pc = pc;

   192     sh4r.new_pc = pc+2;

   193 }

   195 #define UNDEF(ir) do{ ERROR( "Raising exception on undefined instruction at %08x, opcode = %04x", sh4r.pc, ir ); RAISE( EXC_ILLEGAL, EXV_ILLEGAL ); }while(0)

   196 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)

   198 #define RAISE( x, v ) do{ \

   199     if( sh4r.vbr == 0 ) { \

   200         ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \

   201         sh4_stop(); \

   202     } else { \

   203         sh4r.spc = sh4r.pc + 2; \

   204         sh4r.ssr = sh4_read_sr(); \

   205         sh4r.sgr = sh4r.r[15]; \

   206         MMIO_WRITE(MMU,EXPEVT,x); \

   207         sh4r.pc = sh4r.vbr + v; \

   208         sh4r.new_pc = sh4r.pc + 2; \

   209         sh4_load_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \

   210     } \

   211     return TRUE; } while(0)

   213 #define MEM_READ_BYTE( addr ) sh4_read_byte(addr)

   214 #define MEM_READ_WORD( addr ) sh4_read_word(addr)

   215 #define MEM_READ_LONG( addr ) sh4_read_long(addr)

   216 #define MEM_WRITE_BYTE( addr, val ) sh4_write_byte(addr, val)

   217 #define MEM_WRITE_WORD( addr, val ) sh4_write_word(addr, val)

   218 #define MEM_WRITE_LONG( addr, val ) sh4_write_long(addr, val)

   220 #define MEM_FR_READ( addr, reg ) *((uint32_t *)&FR(reg)) = sh4_read_long(addr)

   222 #define MEM_DR_READ( addr, reg ) do { \

   223 	*((uint32_t *)&FR((reg) & 0x0E)) = sh4_read_long(addr);		\

   224 	*((uint32_t *)&FR((reg) | 0x01)) = sh4_read_long(addr+4); } while(0)

   226 #define MEM_FR_WRITE( addr, reg ) sh4_write_long( addr, *((uint32_t *)&FR((reg))) )

   228 #define MEM_DR_WRITE( addr, reg ) do { \

   229 	sh4_write_long( addr, *((uint32_t *)&FR((reg)&0x0E)) );	\

   230 	sh4_write_long( addr+4, *((uint32_t *)&FR((reg)|0x01)) ); } while(0)

   232 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)

   234 #define MEM_FP_READ( addr, reg ) if( IS_FPU_DOUBLESIZE() ) MEM_DR_READ(addr, reg ); else MEM_FR_READ( addr, reg )

   236 #define MEM_FP_WRITE( addr, reg ) if( IS_FPU_DOUBLESIZE() ) MEM_DR_WRITE(addr, reg ); else MEM_FR_WRITE( addr, reg )

   238 #define CHECK( x, c, v ) if( !x ) RAISE( c, v )

   239 #define CHECKPRIV() CHECK( IS_SH4_PRIVMODE(), EXC_ILLEGAL, EXV_ILLEGAL )

   240 #define CHECKFPUEN() CHECK( IS_FPU_ENABLED(), EXC_FPDISABLE, EXV_FPDISABLE )

   241 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); dreamcast_stop(); return FALSE; }

   242 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) { RAISE(EXC_SLOT_ILLEGAL,EXV_ILLEGAL); }

   244 static void sh4_switch_banks( )

   245 {

   246     uint32_t tmp[8];

   248     memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );

   249     memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );

   250     memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );

   251 }

   253 static void sh4_load_sr( uint32_t newval )

   254 {

   255     if( (newval ^ sh4r.sr) & SR_RB )

   256         sh4_switch_banks();

   257     sh4r.sr = newval;

   258     sh4r.t = (newval&SR_T) ? 1 : 0;

   259     sh4r.s = (newval&SR_S) ? 1 : 0;

   260     sh4r.m = (newval&SR_M) ? 1 : 0;

   261     sh4r.q = (newval&SR_Q) ? 1 : 0;

   262     intc_mask_changed();

   263 }

   265 static uint32_t sh4_read_sr( void )

   266 {

   267     /* synchronize sh4r.sr with the various bitflags */

   268     sh4r.sr &= SR_MQSTMASK;

   269     if( sh4r.t ) sh4r.sr |= SR_T;

   270     if( sh4r.s ) sh4r.sr |= SR_S;

   271     if( sh4r.m ) sh4r.sr |= SR_M;

   272     if( sh4r.q ) sh4r.sr |= SR_Q;

   273     return sh4r.sr;

   274 }

   275 /* function for external use */

   276 void sh4_raise_exception( int code, int vector )

   277 {

   278     RAISE(code, vector);

   279 }

   281 static void sh4_accept_interrupt( void )

   282 {

   283     uint32_t code = intc_accept_interrupt();

   284     sh4r.ssr = sh4_read_sr();

   285     sh4r.spc = sh4r.pc;

   286     sh4r.sgr = sh4r.r[15];

   287     sh4_load_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );

   288     MMIO_WRITE( MMU, INTEVT, code );

   289     sh4r.pc = sh4r.vbr + 0x600;

   290     sh4r.new_pc = sh4r.pc + 2;

   291     WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );

   292 }

   294 gboolean sh4_execute_instruction( void )

   295 {

   296     uint32_t pc;

   297     unsigned short ir;

   298     uint32_t tmp;

   299     uint64_t tmpl;

   301 #define R0 sh4r.r[0]

   302 #define FR0 FR(0)

   303 #define DR0 DR(0)

   304 #define RN(ir) sh4r.r[(ir&0x0F00)>>8]

   305 #define RN_BANK(ir) sh4r.r_bank[(ir&0x0070)>>4]

   306 #define RM(ir) sh4r.r[(ir&0x00F0)>>4]

   307 #define DISP4(ir) (ir&0x000F) /* 4-bit displacements are *NOT* sign-extended */

   308 #define DISP8(ir) (ir&0x00FF)

   309 #define PCDISP8(ir) SIGNEXT8(ir&0x00FF)

   310 #define IMM8(ir) SIGNEXT8(ir&0x00FF)

   311 #define UIMM8(ir) (ir&0x00FF) /* Unsigned immmediate */

   312 #define DISP12(ir) SIGNEXT12(ir&0x0FFF)

   313 #define FRNn(ir) ((ir&0x0F00)>>8)

   314 #define FRMn(ir) ((ir&0x00F0)>>4)

   315 #define DRNn(ir) ((ir&0x0E00)>>9)

   316 #define DRMn(ir) ((ir&0x00E0)>>5)

   317 #define FVN(ir) ((ir&0x0C00)>>8)

   318 #define FVM(ir) ((ir&0x0300)>>6)

   319 #define FRN(ir) FR(FRNn(ir))

   320 #define FRM(ir) FR(FRMn(ir))

   321 #define FRNi(ir) (*((uint32_t *)&FR(FRNn(ir))))

   322 #define FRMi(ir) (*((uint32_t *)&FR(FRMn(ir))))

   323 #define DRN(ir) DR(DRNn(ir))

   324 #define DRM(ir) DR(DRMn(ir))

   325 #define DRNi(ir) (*((uint64_t *)&DR(FRNn(ir))))

   326 #define DRMi(ir) (*((uint64_t *)&DR(FRMn(ir))))

   327 #define FPULf   *((float *)&sh4r.fpul)

   328 #define FPULi    (sh4r.fpul)

   330     if( SH4_INT_PENDING() )

   331         sh4_accept_interrupt();

   333     pc = sh4r.pc;

   334     if( pc > 0xFFFFFF00 ) {

   335 	/* SYSCALL Magic */

   336 	bios_syscall( pc & 0xFF );

   337 	sh4r.in_delay_slot = 1;

   338 	pc = sh4r.pc = sh4r.pr;

   339 	sh4r.new_pc = sh4r.pc + 2;

   340     }

   341     ir = MEM_READ_WORD(pc);

   342     sh4r.icount++;

   344     switch( (ir&0xF000)>>12 ) {

   345         case 0: /* 0000nnnnmmmmxxxx */

   346             switch( ir&0x000F ) {

   347                 case 2:

   348                     switch( (ir&0x00F0)>>4 ) {

   349                         case 0: /* STC     SR, Rn */

   350                             CHECKPRIV();

   351                             RN(ir) = sh4_read_sr();

   352                             break;

   353                         case 1: /* STC     GBR, Rn */

   354                             RN(ir) = sh4r.gbr;

   355                             break;

   356                         case 2: /* STC     VBR, Rn */

   357                             CHECKPRIV();

   358                             RN(ir) = sh4r.vbr;

   359                             break;

   360                         case 3: /* STC     SSR, Rn */

   361                             CHECKPRIV();

   362                             RN(ir) = sh4r.ssr;

   363                             break;

   364                         case 4: /* STC     SPC, Rn */

   365                             CHECKPRIV();

   366                             RN(ir) = sh4r.spc;

   367                             break;

   368                         case 8: case 9: case 10: case 11: case 12: case 13:

   369                         case 14: case 15:/* STC     Rm_bank, Rn */

   370                             CHECKPRIV();

   371                             RN(ir) = RN_BANK(ir);

   372                             break;

   373                         default: UNDEF(ir);

   374                     }

   375                     break;

   376                 case 3:

   377                     switch( (ir&0x00F0)>>4 ) {

   378                         case 0: /* BSRF    Rn */

   379                             CHECKDEST( pc + 4 + RN(ir) );

   380                             CHECKSLOTILLEGAL();

   381                             sh4r.in_delay_slot = 1;

   382                             sh4r.pr = sh4r.pc + 4;

   383                             sh4r.pc = sh4r.new_pc;

   384                             sh4r.new_pc = pc + 4 + RN(ir);

   385                             return TRUE;

   386                         case 2: /* BRAF    Rn */

   387                             CHECKDEST( pc + 4 + RN(ir) );

   388                             CHECKSLOTILLEGAL();

   389                             sh4r.in_delay_slot = 1;

   390                             sh4r.pc = sh4r.new_pc;

   391                             sh4r.new_pc = pc + 4 + RN(ir);

   392                             return TRUE;

   393                         case 8: /* PREF    [Rn] */

   394                             tmp = RN(ir);

   395                             if( (tmp & 0xFC000000) == 0xE0000000 ) {

   396                                 /* Store queue operation */

   397                                 int queue = (tmp&0x20)>>2;

   398                                 int32_t *src = &sh4r.store_queue[queue];

   399                                 uint32_t hi = (MMIO_READ( MMU, (queue == 0 ? QACR0 : QACR1) ) & 0x1C) << 24;

   400                                 uint32_t target = tmp&0x03FFFFE0 | hi;

   401                                 mem_copy_to_sh4( target, src, 32 );

   402 				//				WARN( "Executed SQ%c => %08X",

   403 				//				      (queue == 0 ? '0' : '1'), target );

   404                             }

   405                             break;

   406                         case 9: /* OCBI    [Rn] */

   407                         case 10:/* OCBP    [Rn] */

   408                         case 11:/* OCBWB   [Rn] */

   409                             /* anything? */

   410                             break;

   411                         case 12:/* MOVCA.L R0, [Rn] */

   412                             UNIMP(ir);

   413                         default: UNDEF(ir);

   414                     }

   415                     break;

   416                 case 4: /* MOV.B   Rm, [R0 + Rn] */

   417                     MEM_WRITE_BYTE( R0 + RN(ir), RM(ir) );

   418                     break;

   419                 case 5: /* MOV.W   Rm, [R0 + Rn] */

   420                     MEM_WRITE_WORD( R0 + RN(ir), RM(ir) );

   421                     break;

   422                 case 6: /* MOV.L   Rm, [R0 + Rn] */

   423                     MEM_WRITE_LONG( R0 + RN(ir), RM(ir) );

   424                     break;

   425                 case 7: /* MUL.L   Rm, Rn */

   426                     sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |

   427                         (RM(ir) * RN(ir));

   428                     break;

   429                 case 8:

   430                     switch( (ir&0x0FF0)>>4 ) {

   431                         case 0: /* CLRT    */

   432                             sh4r.t = 0;

   433                             break;

   434                         case 1: /* SETT    */

   435                             sh4r.t = 1;

   436                             break;

   437                         case 2: /* CLRMAC  */

   438                             sh4r.mac = 0;

   439                             break;

   440                         case 3: /* LDTLB   */

   441                             break;

   442                         case 4: /* CLRS    */

   443                             sh4r.s = 0;

   444                             break;

   445                         case 5: /* SETS    */

   446                             sh4r.s = 1;

   447                             break;

   448                         default: UNDEF(ir);

   449                     }

   450                     break;

   451                 case 9:

   452                     if( (ir&0x00F0) == 0x20 ) /* MOVT    Rn */

   453                         RN(ir) = sh4r.t;

   454                     else if( ir == 0x0019 ) /* DIV0U   */

   455                         sh4r.m = sh4r.q = sh4r.t = 0;

   456                     else if( ir == 0x0009 )

   457                         /* NOP     */;

   458                     else UNDEF(ir);

   459                     break;

   460                 case 10:

   461                     switch( (ir&0x00F0) >> 4 ) {

   462                         case 0: /* STS     MACH, Rn */

   463                             RN(ir) = sh4r.mac >> 32;

   464                             break;

   465                         case 1: /* STS     MACL, Rn */

   466                             RN(ir) = (uint32_t)sh4r.mac;

   467                             break;

   468                         case 2: /* STS     PR, Rn */

   469                             RN(ir) = sh4r.pr;

   470                             break;

   471                         case 3: /* STC     SGR, Rn */

   472                             CHECKPRIV();

   473                             RN(ir) = sh4r.sgr;

   474                             break;

   475                         case 5:/* STS      FPUL, Rn */

   476                             RN(ir) = sh4r.fpul;

   477                             break;

   478                         case 6: /* STS     FPSCR, Rn */

   479                             RN(ir) = sh4r.fpscr;

   480                             break;

   481                         case 15:/* STC     DBR, Rn */

   482                             CHECKPRIV();

   483                             RN(ir) = sh4r.dbr;

   484                             break;

   485                         default: UNDEF(ir);

   486                     }

   487                     break;

   488                 case 11:

   489                     switch( (ir&0x0FF0)>>4 ) {

   490                         case 0: /* RTS     */

   491                             CHECKDEST( sh4r.pr );

   492                             CHECKSLOTILLEGAL();

   493                             sh4r.in_delay_slot = 1;

   494                             sh4r.pc = sh4r.new_pc;

   495                             sh4r.new_pc = sh4r.pr;

   496                             return TRUE;

   497                         case 1: /* SLEEP   */

   498 			    if( MMIO_READ( CPG, STBCR ) & 0x80 ) {

   499 				sh4r.sh4_state = SH4_STATE_STANDBY;

   500 			    } else {

   501 				sh4r.sh4_state = SH4_STATE_SLEEP;

   502 			    }

   503 			    return FALSE; /* Halt CPU */

   504                         case 2: /* RTE     */

   505                             CHECKPRIV();

   506                             CHECKDEST( sh4r.spc );

   507                             CHECKSLOTILLEGAL();

   508                             sh4r.in_delay_slot = 1;

   509                             sh4r.pc = sh4r.new_pc;

   510                             sh4r.new_pc = sh4r.spc;

   511                             sh4_load_sr( sh4r.ssr );

   512                             return TRUE;

   513                         default:UNDEF(ir);

   514                     }

   515                     break;

   516                 case 12:/* MOV.B   [R0+R%d], R%d */

   517                     RN(ir) = MEM_READ_BYTE( R0 + RM(ir) );

   518                     break;

   519                 case 13:/* MOV.W   [R0+R%d], R%d */

   520                     RN(ir) = MEM_READ_WORD( R0 + RM(ir) );

   521                     break;

   522                 case 14:/* MOV.L   [R0+R%d], R%d */

   523                     RN(ir) = MEM_READ_LONG( R0 + RM(ir) );

   524                     break;

   525                 case 15:/* MAC.L   [Rm++], [Rn++] */

   526                     tmpl = ( SIGNEXT32(MEM_READ_LONG(RM(ir))) *

   527                                   SIGNEXT32(MEM_READ_LONG(RN(ir))) );

   528                     if( sh4r.s ) {

   529                         /* 48-bit Saturation. Yuch */

   530                         tmpl += SIGNEXT48(sh4r.mac);

   531                         if( tmpl < 0xFFFF800000000000LL )

   532                             tmpl = 0xFFFF800000000000LL;

   533                         else if( tmpl > 0x00007FFFFFFFFFFFLL )

   534                             tmpl = 0x00007FFFFFFFFFFFLL;

   535                         sh4r.mac = (sh4r.mac&0xFFFF000000000000LL) |

   536                             (tmpl&0x0000FFFFFFFFFFFFLL);

   537                     } else sh4r.mac = tmpl;

   539                     RM(ir) += 4;

   540                     RN(ir) += 4;

   542                     break;

   543                 default: UNDEF(ir);

   544             }

   545             break;

   546         case 1: /* 0001nnnnmmmmdddd */

   547             /* MOV.L   Rm, [Rn + disp4*4] */

   548             MEM_WRITE_LONG( RN(ir) + (DISP4(ir)<<2), RM(ir) );

   549             break;

   550         case 2: /* 0010nnnnmmmmxxxx */

   551             switch( ir&0x000F ) {

   552                 case 0: /* MOV.B   Rm, [Rn] */

   553                     MEM_WRITE_BYTE( RN(ir), RM(ir) );

   554                     break;

   555                 case 1: /* MOV.W   Rm, [Rn] */

   556                     MEM_WRITE_WORD( RN(ir), RM(ir) );

   557                     break;

   558                 case 2: /* MOV.L   Rm, [Rn] */

   559                     MEM_WRITE_LONG( RN(ir), RM(ir) );

   560                     break;

   561                 case 3: UNDEF(ir);

   562                     break;

   563                 case 4: /* MOV.B   Rm, [--Rn] */

   564                     RN(ir) --;

   565                     MEM_WRITE_BYTE( RN(ir), RM(ir) );

   566                     break;

   567                 case 5: /* MOV.W   Rm, [--Rn] */

   568                     RN(ir) -= 2;

   569                     MEM_WRITE_WORD( RN(ir), RM(ir) );

   570                     break;

   571                 case 6: /* MOV.L   Rm, [--Rn] */

   572                     RN(ir) -= 4;

   573                     MEM_WRITE_LONG( RN(ir), RM(ir) );

   574                     break;

   575                 case 7: /* DIV0S   Rm, Rn */

   576                     sh4r.q = RN(ir)>>31;

   577                     sh4r.m = RM(ir)>>31;

   578                     sh4r.t = sh4r.q ^ sh4r.m;

   579                     break;

   580                 case 8: /* TST     Rm, Rn */

   581                     sh4r.t = (RN(ir)&RM(ir) ? 0 : 1);

   582                     break;

   583                 case 9: /* AND     Rm, Rn */

   584                     RN(ir) &= RM(ir);

   585                     break;

   586                 case 10:/* XOR     Rm, Rn */

   587                     RN(ir) ^= RM(ir);

   588                     break;

   589                 case 11:/* OR      Rm, Rn */

   590                     RN(ir) |= RM(ir);

   591                     break;

   592                 case 12:/* CMP/STR Rm, Rn */

   593                     /* set T = 1 if any byte in RM & RN is the same */

   594                     tmp = RM(ir) ^ RN(ir);

   595                     sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||

   596                               (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;

   597                     break;

   598                 case 13:/* XTRCT   Rm, Rn */

   599                     RN(ir) = (RN(ir)>>16) | (RM(ir)<<16);

   600                     break;

   601                 case 14:/* MULU.W  Rm, Rn */

   602                     sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |

   603                         (uint32_t)((RM(ir)&0xFFFF) * (RN(ir)&0xFFFF));

   604                     break;

   605                 case 15:/* MULS.W  Rm, Rn */

   606                     sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |

   607                         (uint32_t)(SIGNEXT32(RM(ir)&0xFFFF) * SIGNEXT32(RN(ir)&0xFFFF));

   608                     break;

   609             }

   610             break;

   611         case 3: /* 0011nnnnmmmmxxxx */

   612             switch( ir&0x000F ) {

   613                 case 0: /* CMP/EQ  Rm, Rn */

   614                     sh4r.t = ( RM(ir) == RN(ir) ? 1 : 0 );

   615                     break;

   616                 case 2: /* CMP/HS  Rm, Rn */

   617                     sh4r.t = ( RN(ir) >= RM(ir) ? 1 : 0 );

   618                     break;

   619                 case 3: /* CMP/GE  Rm, Rn */

   620                     sh4r.t = ( ((int32_t)RN(ir)) >= ((int32_t)RM(ir)) ? 1 : 0 );

   621                     break;

   622                 case 4: { /* DIV1    Rm, Rn */

   623                     /* This is just from the sh4p manual with some

   624                      * simplifications (someone want to check it's correct? :)

   625                      * Why they couldn't just provide a real DIV instruction...

   626                      * Please oh please let the translator batch these things

   627                      * up into a single DIV... */

   628                     uint32_t tmp0, tmp1, tmp2, dir;

   630                     dir = sh4r.q ^ sh4r.m;

   631                     sh4r.q = (RN(ir) >> 31);

   632                     tmp2 = RM(ir);

   633                     RN(ir) = (RN(ir) << 1) | sh4r.t;

   634                     tmp0 = RN(ir);

   635                     if( dir ) {

   636                         RN(ir) += tmp2;

   637                         tmp1 = (RN(ir)<tmp0 ? 1 : 0 );

   638                     } else {

   639                         RN(ir) -= tmp2;

   640                         tmp1 = (RN(ir)>tmp0 ? 1 : 0 );

   641                     }

   642                     sh4r.q ^= sh4r.m ^ tmp1;

   643                     sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );

   644                     break; }

   645                 case 5: /* DMULU.L Rm, Rn */

   646                     sh4r.mac = ((uint64_t)RM(ir)) * ((uint64_t)RN(ir));

   647                     break;

   648                 case 6: /* CMP/HI  Rm, Rn */

   649                     sh4r.t = ( RN(ir) > RM(ir) ? 1 : 0 );

   650                     break;

   651                 case 7: /* CMP/GT  Rm, Rn */

   652                     sh4r.t = ( ((int32_t)RN(ir)) > ((int32_t)RM(ir)) ? 1 : 0 );

   653                     break;

   654                 case 8: /* SUB     Rm, Rn */

   655                     RN(ir) -= RM(ir);

   656                     break;

   657                 case 10:/* SUBC    Rm, Rn */

   658                     tmp = RN(ir);

   659                     RN(ir) = RN(ir) - RM(ir) - sh4r.t;

   660                     sh4r.t = (RN(ir) > tmp || (RN(ir) == tmp && sh4r.t == 1));

   661                     break;

   662                 case 11:/* SUBV    Rm, Rn */

   663                     UNIMP(ir);

   664                     break;

   665                 case 12:/* ADD     Rm, Rn */

   666                     RN(ir) += RM(ir);

   667                     break;

   668                 case 13:/* DMULS.L Rm, Rn */

   669                     sh4r.mac = SIGNEXT32(RM(ir)) * SIGNEXT32(RN(ir));

   670                     break;

   671                 case 14:/* ADDC    Rm, Rn */

   672                     tmp = RN(ir);

   673                     RN(ir) += RM(ir) + sh4r.t;

   674                     sh4r.t = ( RN(ir) < tmp || (RN(ir) == tmp && sh4r.t != 0) ? 1 : 0 );

   675                     break;

   676                 case 15:/* ADDV    Rm, Rn */

   677                     UNIMP(ir);

   678                     break;

   679                 default: UNDEF(ir);

   680             }

   681             break;

   682         case 4: /* 0100nnnnxxxxxxxx */

   683             switch( ir&0x00FF ) {

   684                 case 0x00: /* SHLL    Rn */

   685                     sh4r.t = RN(ir) >> 31;

   686                     RN(ir) <<= 1;

   687                     break;

   688                 case 0x01: /* SHLR    Rn */

   689                     sh4r.t = RN(ir) & 0x00000001;

   690                     RN(ir) >>= 1;

   691                     break;

   692                 case 0x02: /* STS.L   MACH, [--Rn] */

   693                     RN(ir) -= 4;

   694                     MEM_WRITE_LONG( RN(ir), (sh4r.mac>>32) );

   695                     break;

   696                 case 0x03: /* STC.L   SR, [--Rn] */

   697                     CHECKPRIV();

   698                     RN(ir) -= 4;

   699                     MEM_WRITE_LONG( RN(ir), sh4_read_sr() );

   700                     break;

   701                 case 0x04: /* ROTL    Rn */

   702                     sh4r.t = RN(ir) >> 31;

   703                     RN(ir) <<= 1;

   704                     RN(ir) |= sh4r.t;

   705                     break;

   706                 case 0x05: /* ROTR    Rn */

   707                     sh4r.t = RN(ir) & 0x00000001;

   708                     RN(ir) >>= 1;

   709                     RN(ir) |= (sh4r.t << 31);

   710                     break;

   711                 case 0x06: /* LDS.L   [Rn++], MACH */

   712                     sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |

   713                         (((uint64_t)MEM_READ_LONG(RN(ir)))<<32);

   714                     RN(ir) += 4;

   715                     break;

   716                 case 0x07: /* LDC.L   [Rn++], SR */

   717                     CHECKPRIV();

   718                     sh4_load_sr( MEM_READ_LONG(RN(ir)) );

   719                     RN(ir) +=4;

   720                     break;

   721                 case 0x08: /* SHLL2   Rn */

   722                     RN(ir) <<= 2;

   723                     break;

   724                 case 0x09: /* SHLR2   Rn */

   725                     RN(ir) >>= 2;

   726                     break;

   727                 case 0x0A: /* LDS     Rn, MACH */

   728                     sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |

   729                         (((uint64_t)RN(ir))<<32);

   730                     break;

   731                 case 0x0B: /* JSR     [Rn] */

   732                     CHECKDEST( RN(ir) );

   733                     CHECKSLOTILLEGAL();

   734                     sh4r.in_delay_slot = 1;

   735                     sh4r.pc = sh4r.new_pc;

   736                     sh4r.new_pc = RN(ir);

   737                     sh4r.pr = pc + 4;

   738                     return TRUE;

   739                 case 0x0E: /* LDC     Rn, SR */

   740                     CHECKPRIV();

   741                     sh4_load_sr( RN(ir) );

   742                     break;

   743                 case 0x10: /* DT      Rn */

   744                     RN(ir) --;

   745                     sh4r.t = ( RN(ir) == 0 ? 1 : 0 );

   746                     break;

   747                 case 0x11: /* CMP/PZ  Rn */

   748                     sh4r.t = ( ((int32_t)RN(ir)) >= 0 ? 1 : 0 );

   749                     break;

   750                 case 0x12: /* STS.L   MACL, [--Rn] */

   751                     RN(ir) -= 4;

   752                     MEM_WRITE_LONG( RN(ir), (uint32_t)sh4r.mac );

   753                     break;

   754                 case 0x13: /* STC.L   GBR, [--Rn] */

   755                     RN(ir) -= 4;

   756                     MEM_WRITE_LONG( RN(ir), sh4r.gbr );

   757                     break;

   758                 case 0x15: /* CMP/PL  Rn */

   759                     sh4r.t = ( ((int32_t)RN(ir)) > 0 ? 1 : 0 );

   760                     break;

   761                 case 0x16: /* LDS.L   [Rn++], MACL */

   762                     sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |

   763                         (uint64_t)((uint32_t)MEM_READ_LONG(RN(ir)));

   764                     RN(ir) += 4;

   765                     break;

   766                 case 0x17: /* LDC.L   [Rn++], GBR */

   767                     sh4r.gbr = MEM_READ_LONG(RN(ir));

   768                     RN(ir) +=4;

   769                     break;

   770                 case 0x18: /* SHLL8   Rn */

   771                     RN(ir) <<= 8;

   772                     break;

   773                 case 0x19: /* SHLR8   Rn */

   774                     RN(ir) >>= 8;

   775                     break;

   776                 case 0x1A: /* LDS     Rn, MACL */

   777                     sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |

   778                         (uint64_t)((uint32_t)(RN(ir)));

   779                     break;

   780                 case 0x1B: /* TAS.B   [Rn] */

   781                     tmp = MEM_READ_BYTE( RN(ir) );

   782                     sh4r.t = ( tmp == 0 ? 1 : 0 );

   783                     MEM_WRITE_BYTE( RN(ir), tmp | 0x80 );

   784                     break;

   785                 case 0x1E: /* LDC     Rn, GBR */

   786                     sh4r.gbr = RN(ir);

   787                     break;

   788                 case 0x20: /* SHAL    Rn */

   789                     sh4r.t = RN(ir) >> 31;

   790                     RN(ir) <<= 1;

   791                     break;

   792                 case 0x21: /* SHAR    Rn */

   793                     sh4r.t = RN(ir) & 0x00000001;

   794                     RN(ir) = ((int32_t)RN(ir)) >> 1;

   795                     break;

   796                 case 0x22: /* STS.L   PR, [--Rn] */

   797                     RN(ir) -= 4;

   798                     MEM_WRITE_LONG( RN(ir), sh4r.pr );

   799                     break;

   800                 case 0x23: /* STC.L   VBR, [--Rn] */

   801                     CHECKPRIV();

   802                     RN(ir) -= 4;

   803                     MEM_WRITE_LONG( RN(ir), sh4r.vbr );

   804                     break;

   805                 case 0x24: /* ROTCL   Rn */

   806                     tmp = RN(ir) >> 31;

   807                     RN(ir) <<= 1;

   808                     RN(ir) |= sh4r.t;

   809                     sh4r.t = tmp;

   810                     break;

   811                 case 0x25: /* ROTCR   Rn */

   812                     tmp = RN(ir) & 0x00000001;

   813                     RN(ir) >>= 1;

   814                     RN(ir) |= (sh4r.t << 31 );

   815                     sh4r.t = tmp;

   816                     break;

   817                 case 0x26: /* LDS.L   [Rn++], PR */

   818                     sh4r.pr = MEM_READ_LONG( RN(ir) );

   819                     RN(ir) += 4;

   820                     break;

   821                 case 0x27: /* LDC.L   [Rn++], VBR */

   822                     CHECKPRIV();

   823                     sh4r.vbr = MEM_READ_LONG(RN(ir));

   824                     RN(ir) +=4;

   825                     break;

   826                 case 0x28: /* SHLL16  Rn */

   827                     RN(ir) <<= 16;

   828                     break;

   829                 case 0x29: /* SHLR16  Rn */

   830                     RN(ir) >>= 16;

   831                     break;

   832                 case 0x2A: /* LDS     Rn, PR */

   833                     sh4r.pr = RN(ir);

   834                     break;

   835                 case 0x2B: /* JMP     [Rn] */

   836                     CHECKDEST( RN(ir) );

   837                     CHECKSLOTILLEGAL();

   838                     sh4r.in_delay_slot = 1;

   839                     sh4r.pc = sh4r.new_pc;

   840                     sh4r.new_pc = RN(ir);

   841                     return TRUE;

   842                 case 0x2E: /* LDC     Rn, VBR */

   843                     CHECKPRIV();

   844                     sh4r.vbr = RN(ir);

   845                     break;

   846                 case 0x32: /* STC.L   SGR, [--Rn] */

   847                     CHECKPRIV();

   848                     RN(ir) -= 4;

   849                     MEM_WRITE_LONG( RN(ir), sh4r.sgr );

   850                     break;

   851                 case 0x33: /* STC.L   SSR, [--Rn] */

   852                     CHECKPRIV();

   853                     RN(ir) -= 4;

   854                     MEM_WRITE_LONG( RN(ir), sh4r.ssr );

   855                     break;

   856                 case 0x37: /* LDC.L   [Rn++], SSR */

   857                     CHECKPRIV();

   858                     sh4r.ssr = MEM_READ_LONG(RN(ir));

   859                     RN(ir) +=4;

   860                     break;

   861                 case 0x3E: /* LDC     Rn, SSR */

   862                     CHECKPRIV();

   863                     sh4r.ssr = RN(ir);

   864                     break;

   865                 case 0x43: /* STC.L   SPC, [--Rn] */

   866                     CHECKPRIV();

   867                     RN(ir) -= 4;

   868                     MEM_WRITE_LONG( RN(ir), sh4r.spc );

   869                     break;

   870                 case 0x47: /* LDC.L   [Rn++], SPC */

   871                     CHECKPRIV();

   872                     sh4r.spc = MEM_READ_LONG(RN(ir));

   873                     RN(ir) +=4;

   874                     break;

   875                 case 0x4E: /* LDC     Rn, SPC */

   876                     CHECKPRIV();

   877                     sh4r.spc = RN(ir);

   878                     break;

   879                 case 0x52: /* STS.L   FPUL, [--Rn] */

   880                     RN(ir) -= 4;

   881                     MEM_WRITE_LONG( RN(ir), sh4r.fpul );

   882                     break;

   883                 case 0x56: /* LDS.L   [Rn++], FPUL */

   884                     sh4r.fpul = MEM_READ_LONG(RN(ir));

   885                     RN(ir) +=4;

   886                     break;

   887                 case 0x5A: /* LDS     Rn, FPUL */

   888                     sh4r.fpul = RN(ir);

   889                     break;

   890                 case 0x62: /* STS.L   FPSCR, [--Rn] */

   891                     RN(ir) -= 4;

   892                     MEM_WRITE_LONG( RN(ir), sh4r.fpscr );

   893                     break;

   894                 case 0x66: /* LDS.L   [Rn++], FPSCR */

   895                     sh4r.fpscr = MEM_READ_LONG(RN(ir));

   896                     RN(ir) +=4;

   897                     break;

   898                 case 0x6A: /* LDS     Rn, FPSCR */

   899                     sh4r.fpscr = RN(ir);

   900                     break;

   901                 case 0xF2: /* STC.L   DBR, [--Rn] */

   902                     CHECKPRIV();

   903                     RN(ir) -= 4;

   904                     MEM_WRITE_LONG( RN(ir), sh4r.dbr );

   905                     break;

   906                 case 0xF6: /* LDC.L   [Rn++], DBR */

   907                     CHECKPRIV();

   908                     sh4r.dbr = MEM_READ_LONG(RN(ir));

   909                     RN(ir) +=4;

   910                     break;

   911                 case 0xFA: /* LDC     Rn, DBR */

   912                     CHECKPRIV();

   913                     sh4r.dbr = RN(ir);

   914                     break;

   915                 case 0x83: case 0x93: case 0xA3: case 0xB3: case 0xC3:

   916                 case 0xD3: case 0xE3: case 0xF3: /* STC.L   Rn_BANK, [--Rn] */

   917                     CHECKPRIV();

   918                     RN(ir) -= 4;

   919                     MEM_WRITE_LONG( RN(ir), RN_BANK(ir) );

   920                     break;

   921                 case 0x87: case 0x97: case 0xA7: case 0xB7: case 0xC7:

   922                 case 0xD7: case 0xE7: case 0xF7: /* LDC.L   [Rn++], Rn_BANK */

   923                     CHECKPRIV();

   924                     RN_BANK(ir) = MEM_READ_LONG( RN(ir) );

   925                     RN(ir) += 4;

   926                     break;

   927                 case 0x8E: case 0x9E: case 0xAE: case 0xBE: case 0xCE:

   928                 case 0xDE: case 0xEE: case 0xFE: /* LDC     Rm, Rn_BANK */

   929                     CHECKPRIV();

   930                     RN_BANK(ir) = RM(ir);

   931                     break;

   932                 default:

   933                     if( (ir&0x000F) == 0x0F ) {

   934                         /* MAC.W   [Rm++], [Rn++] */

   935                         tmp = SIGNEXT16(MEM_READ_WORD(RM(ir))) *

   936                             SIGNEXT16(MEM_READ_WORD(RN(ir)));

   937                         if( sh4r.s ) {

   938                             /* FIXME */

   939                             UNIMP(ir);

   940                         } else sh4r.mac += SIGNEXT32(tmp);

   941                         RM(ir) += 2;

   942                         RN(ir) += 2;

   943                     } else if( (ir&0x000F) == 0x0C ) {

   944                         /* SHAD    Rm, Rn */

   945                         tmp = RM(ir);

   946                         if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);

   947                         else if( (tmp & 0x1F) == 0 )

   948 			  RN(ir) = ((int32_t)RN(ir)) >> 31;

   949                         else

   950 			  RN(ir) = ((int32_t)RN(ir)) >> (((~RM(ir)) & 0x1F)+1);

   951                     } else if( (ir&0x000F) == 0x0D ) {

   952                         /* SHLD    Rm, Rn */

   953                         tmp = RM(ir);

   954                         if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);

   955                         else if( (tmp & 0x1F) == 0 ) RN(ir) = 0;

   956                         else RN(ir) >>= (((~tmp) & 0x1F)+1);

   957                     } else UNDEF(ir);

   958             }

   959             break;

   960         case 5: /* 0101nnnnmmmmdddd */

   961             /* MOV.L   [Rm + disp4*4], Rn */

   962             RN(ir) = MEM_READ_LONG( RM(ir) + (DISP4(ir)<<2) );

   963             break;

   964         case 6: /* 0110xxxxxxxxxxxx */

   965             switch( ir&0x000f ) {

   966                 case 0: /* MOV.B   [Rm], Rn */

   967                     RN(ir) = MEM_READ_BYTE( RM(ir) );

   968                     break;

   969                 case 1: /* MOV.W   [Rm], Rn */

   970                     RN(ir) = MEM_READ_WORD( RM(ir) );

   971                     break;

   972                 case 2: /* MOV.L   [Rm], Rn */

   973                     RN(ir) = MEM_READ_LONG( RM(ir) );

   974                     break;

   975                 case 3: /* MOV     Rm, Rn */

   976                     RN(ir) = RM(ir);

   977                     break;

   978                 case 4: /* MOV.B   [Rm++], Rn */

   979                     RN(ir) = MEM_READ_BYTE( RM(ir) );

   980                     RM(ir) ++;

   981                     break;

   982                 case 5: /* MOV.W   [Rm++], Rn */

   983                     RN(ir) = MEM_READ_WORD( RM(ir) );

   984                     RM(ir) += 2;

   985                     break;

   986                 case 6: /* MOV.L   [Rm++], Rn */

   987                     RN(ir) = MEM_READ_LONG( RM(ir) );

   988                     RM(ir) += 4;

   989                     break;

   990                 case 7: /* NOT     Rm, Rn */

   991                     RN(ir) = ~RM(ir);

   992                     break;

   993                 case 8: /* SWAP.B  Rm, Rn */

   994                     RN(ir) = (RM(ir)&0xFFFF0000) | ((RM(ir)&0x0000FF00)>>8) |

   995                         ((RM(ir)&0x000000FF)<<8);

   996                     break;

   997                 case 9: /* SWAP.W  Rm, Rn */

   998                     RN(ir) = (RM(ir)>>16) | (RM(ir)<<16);

   999                     break;

  1000                 case 10:/* NEGC    Rm, Rn */

  1001                     tmp = 0 - RM(ir);

  1002                     RN(ir) = tmp - sh4r.t;

  1003                     sh4r.t = ( 0<tmp || tmp<RN(ir) ? 1 : 0 );

  1004                     break;

  1005                 case 11:/* NEG     Rm, Rn */

  1006                     RN(ir) = 0 - RM(ir);

  1007                     break;

  1008                 case 12:/* EXTU.B  Rm, Rn */

  1009                     RN(ir) = RM(ir)&0x000000FF;

  1010                     break;

  1011                 case 13:/* EXTU.W  Rm, Rn */

  1012                     RN(ir) = RM(ir)&0x0000FFFF;

  1013                     break;

  1014                 case 14:/* EXTS.B  Rm, Rn */

  1015                     RN(ir) = SIGNEXT8( RM(ir)&0x000000FF );

  1016                     break;

  1017                 case 15:/* EXTS.W  Rm, Rn */

  1018                     RN(ir) = SIGNEXT16( RM(ir)&0x0000FFFF );

  1019                     break;

  1020             }

  1021             break;

  1022         case 7: /* 0111nnnniiiiiiii */

  1023             /* ADD    imm8, Rn */

  1024             RN(ir) += IMM8(ir);

  1025             break;

  1026         case 8: /* 1000xxxxxxxxxxxx */

  1027             switch( (ir&0x0F00) >> 8 ) {

  1028                 case 0: /* MOV.B   R0, [Rm + disp4] */

  1029                     MEM_WRITE_BYTE( RM(ir) + DISP4(ir), R0 );

  1030                     break;

  1031                 case 1: /* MOV.W   R0, [Rm + disp4*2] */

  1032                     MEM_WRITE_WORD( RM(ir) + (DISP4(ir)<<1), R0 );

  1033                     break;

  1034                 case 4: /* MOV.B   [Rm + disp4], R0 */

  1035                     R0 = MEM_READ_BYTE( RM(ir) + DISP4(ir) );

  1036                     break;

  1037                 case 5: /* MOV.W   [Rm + disp4*2], R0 */

  1038                     R0 = MEM_READ_WORD( RM(ir) + (DISP4(ir)<<1) );

  1039                     break;

  1040                 case 8: /* CMP/EQ  imm, R0 */

  1041                     sh4r.t = ( R0 == IMM8(ir) ? 1 : 0 );

  1042                     break;

  1043                 case 9: /* BT      disp8 */

  1044                     CHECKSLOTILLEGAL()

  1045                     if( sh4r.t ) {

  1046                         CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )

  1047                         sh4r.pc += (PCDISP8(ir)<<1) + 4;

  1048                         sh4r.new_pc = sh4r.pc + 2;

  1049                         return TRUE;

  1050                     }

  1051                     break;

  1052                 case 11:/* BF      disp8 */

  1053                     CHECKSLOTILLEGAL()

  1054                     if( !sh4r.t ) {

  1055                         CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )

  1056                         sh4r.pc += (PCDISP8(ir)<<1) + 4;

  1057                         sh4r.new_pc = sh4r.pc + 2;

  1058                         return TRUE;

  1059                     }

  1060                     break;

  1061                 case 13:/* BT/S    disp8 */

  1062                     CHECKSLOTILLEGAL()

  1063                     if( sh4r.t ) {

  1064                         CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )

  1065                         sh4r.in_delay_slot = 1;

  1066                         sh4r.pc = sh4r.new_pc;

  1067                         sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;

  1068                         sh4r.in_delay_slot = 1;

  1069                         return TRUE;

  1070                     }

  1071                     break;

  1072                 case 15:/* BF/S    disp8 */

  1073                     CHECKSLOTILLEGAL()

  1074                     if( !sh4r.t ) {

  1075                         CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )

  1076                         sh4r.in_delay_slot = 1;

  1077                         sh4r.pc = sh4r.new_pc;

  1078                         sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;

  1079                         return TRUE;

  1080                     }

  1081                     break;

  1082                 default: UNDEF(ir);

  1083             }

  1084             break;

  1085         case 9: /* 1001xxxxxxxxxxxx */

  1086             /* MOV.W   [disp8*2 + pc + 4], Rn */

  1087             RN(ir) = MEM_READ_WORD( pc + 4 + (DISP8(ir)<<1) );

  1088             break;

  1089         case 10:/* 1010dddddddddddd */

  1090             /* BRA     disp12 */

  1091             CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 )

  1092             CHECKSLOTILLEGAL()

  1093             sh4r.in_delay_slot = 1;

  1094             sh4r.pc = sh4r.new_pc;

  1095             sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);

  1096             return TRUE;

  1097         case 11:/* 1011dddddddddddd */

  1098             /* BSR     disp12 */

  1099             CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 )

  1100             CHECKSLOTILLEGAL()

  1101             sh4r.in_delay_slot = 1;

  1102             sh4r.pr = pc + 4;

  1103             sh4r.pc = sh4r.new_pc;

  1104             sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);

  1105             return TRUE;

  1106         case 12:/* 1100xxxxdddddddd */

  1107         switch( (ir&0x0F00)>>8 ) {

  1108                 case 0: /* MOV.B  R0, [GBR + disp8] */

  1109                     MEM_WRITE_BYTE( sh4r.gbr + DISP8(ir), R0 );

  1110                     break;

  1111                 case 1: /* MOV.W  R0, [GBR + disp8*2] */

  1112                     MEM_WRITE_WORD( sh4r.gbr + (DISP8(ir)<<1), R0 );

  1113                     break;

  1114                 case  2: /*MOV.L   R0, [GBR + disp8*4] */

  1115                     MEM_WRITE_LONG( sh4r.gbr + (DISP8(ir)<<2), R0 );

  1116                     break;

  1117                 case 3: /* TRAPA   imm8 */

  1118                     CHECKSLOTILLEGAL()

  1119                     sh4r.in_delay_slot = 1;

  1120                     MMIO_WRITE( MMU, TRA, UIMM8(ir) );

  1121                     sh4r.pc = sh4r.new_pc;  /* RAISE ends the instruction */

  1122                     sh4r.new_pc += 2;

  1123                     RAISE( EXC_TRAP, EXV_TRAP );

  1124                     break;

  1125                 case 4: /* MOV.B   [GBR + disp8], R0 */

  1126                     R0 = MEM_READ_BYTE( sh4r.gbr + DISP8(ir) );

  1127                     break;

  1128                 case 5: /* MOV.W   [GBR + disp8*2], R0 */

  1129                     R0 = MEM_READ_WORD( sh4r.gbr + (DISP8(ir)<<1) );

  1130                     break;

  1131                 case 6: /* MOV.L   [GBR + disp8*4], R0 */

  1132                     R0 = MEM_READ_LONG( sh4r.gbr + (DISP8(ir)<<2) );

  1133                     break;

  1134                 case 7: /* MOVA    disp8 + pc&~3 + 4, R0 */

  1135                     R0 = (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4;

  1136                     break;

  1137                 case 8: /* TST     imm8, R0 */

  1138                     sh4r.t = (R0 & UIMM8(ir) ? 0 : 1);

  1139                     break;

  1140                 case 9: /* AND     imm8, R0 */

  1141                     R0 &= UIMM8(ir);

  1142                     break;

  1143                 case 10:/* XOR     imm8, R0 */

  1144                     R0 ^= UIMM8(ir);

  1145                     break;

  1146                 case 11:/* OR      imm8, R0 */

  1147                     R0 |= UIMM8(ir);

  1148                     break;

  1149                 case 12:/* TST.B   imm8, [R0+GBR] */

  1150                     sh4r.t = ( MEM_READ_BYTE(R0 + sh4r.gbr) & UIMM8(ir) ? 0 : 1 );

  1151                     break;

  1152                 case 13:/* AND.B   imm8, [R0+GBR] */

  1153                     MEM_WRITE_BYTE( R0 + sh4r.gbr,

  1154                                     UIMM8(ir) & MEM_READ_BYTE(R0 + sh4r.gbr) );

  1155                     break;

  1156                 case 14:/* XOR.B   imm8, [R0+GBR] */

  1157                     MEM_WRITE_BYTE( R0 + sh4r.gbr,

  1158                                     UIMM8(ir) ^ MEM_READ_BYTE(R0 + sh4r.gbr) );

  1159                     break;

  1160                 case 15:/* OR.B    imm8, [R0+GBR] */

  1161                     MEM_WRITE_BYTE( R0 + sh4r.gbr,

  1162                                     UIMM8(ir) | MEM_READ_BYTE(R0 + sh4r.gbr) );

  1163                     break;

  1164             }

  1165             break;

  1166         case 13:/* 1101nnnndddddddd */

  1167             /* MOV.L   [disp8*4 + pc&~3 + 4], Rn */

  1168             RN(ir) = MEM_READ_LONG( (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4 );

  1169             break;

  1170         case 14:/* 1110nnnniiiiiiii */

  1171             /* MOV     imm8, Rn */

  1172             RN(ir) = IMM8(ir);

  1173             break;

  1174         case 15:/* 1111xxxxxxxxxxxx */

  1175             CHECKFPUEN();

  1176 	    if( IS_FPU_DOUBLEPREC() ) {

  1177 		switch( ir&0x000F ) {

  1178                 case 0: /* FADD    FRm, FRn */

  1179                     DRN(ir) += DRM(ir);

  1180                     break;

  1181                 case 1: /* FSUB    FRm, FRn */

  1182                     DRN(ir) -= DRM(ir);

  1183                     break;

  1184                 case 2: /* FMUL    FRm, FRn */

  1185                     DRN(ir) = DRN(ir) * DRM(ir);

  1186                     break;

  1187                 case 3: /* FDIV    FRm, FRn */

  1188                     DRN(ir) = DRN(ir) / DRM(ir);

  1189                     break;

  1190                 case 4: /* FCMP/EQ FRm, FRn */

  1191                     sh4r.t = ( DRN(ir) == DRM(ir) ? 1 : 0 );

  1192                     break;

  1193                 case 5: /* FCMP/GT FRm, FRn */

  1194                     sh4r.t = ( DRN(ir) > DRM(ir) ? 1 : 0 );

  1195                     break;

  1196                 case 6: /* FMOV.S  [Rm+R0], FRn */

  1197                     MEM_FP_READ( RM(ir) + R0, FRNn(ir) );

  1198                     break;

  1199                 case 7: /* FMOV.S  FRm, [Rn+R0] */

  1200                     MEM_FP_WRITE( RN(ir) + R0, FRMn(ir) );

  1201                     break;

  1202                 case 8: /* FMOV.S  [Rm], FRn */

  1203                     MEM_FP_READ( RM(ir), FRNn(ir) );

  1204                     break;

  1205                 case 9: /* FMOV.S  [Rm++], FRn */

  1206                     MEM_FP_READ( RM(ir), FRNn(ir) );

  1207                     RM(ir) += FP_WIDTH;

  1208                     break;

  1209                 case 10:/* FMOV.S  FRm, [Rn] */

  1210                     MEM_FP_WRITE( RN(ir), FRMn(ir) );

  1211                     break;

  1212                 case 11:/* FMOV.S  FRm, [--Rn] */

  1213                     RN(ir) -= FP_WIDTH;

  1214                     MEM_FP_WRITE( RN(ir), FRMn(ir) );

  1215                     break;

  1216                 case 12:/* FMOV    FRm, FRn */

  1217 		    if( IS_FPU_DOUBLESIZE() )

  1218 			DRN(ir) = DRM(ir);

  1219 		    else

  1220 			FRN(ir) = FRM(ir);

  1221                     break;

  1222                 case 13:

  1223                     switch( (ir&0x00F0) >> 4 ) {

  1224 		    case 0: /* FSTS    FPUL, FRn */

  1225 			FRN(ir) = FPULf;

  1226 			break;

  1227 		    case 1: /* FLDS    FRn,FPUL */

  1228 			FPULf = FRN(ir);

  1229 			break;

  1230 		    case 2: /* FLOAT   FPUL, FRn */

  1231 			DRN(ir) = (float)FPULi;

  1232 			break;

  1233 		    case 3: /* FTRC    FRn, FPUL */

  1234 			FPULi = (uint32_t)DRN(ir);

  1235 			/* FIXME: is this sufficient? */

  1236 			break;

  1237 		    case 4: /* FNEG    FRn */

  1238 			DRN(ir) = -DRN(ir);

  1239 			break;

  1240 		    case 5: /* FABS    FRn */

  1241 			DRN(ir) = fabs(DRN(ir));

  1242 			break;

  1243 		    case 6: /* FSQRT   FRn */

  1244 			DRN(ir) = sqrt(DRN(ir));

  1245 			break;

  1246 		    case 7: /* FSRRA FRn */

  1247 			DRN(ir) = 1.0/sqrt(DRN(ir));

  1248 			break;

  1249 		    case 8: /* FLDI0   FRn */

  1250 			DRN(ir) = 0.0;

  1251 			break;

  1252 		    case 9: /* FLDI1   FRn */

  1253 			DRN(ir) = 1.0;

  1254 			break;

  1255 		    case 10: /* FCNVSD FPUL, DRn */

  1256 			DRN(ir) = (double)FPULf;

  1257 			break;

  1258 		    case 11: /* FCNVDS DRn, FPUL */

  1259 			FPULf = (float)DRN(ir);

  1260 			break;

  1261 		    case 14:/* FIPR    FVm, FVn */

  1262 			UNDEF(ir);

  1263 			break;

  1264 		    case 15:

  1265 			if( (ir&0x0300) == 0x0100 ) { /* FTRV    XMTRX,FVn */

  1266 			    break;

  1267 			}

  1268 			else if( (ir&0x0100) == 0 ) { /* FSCA    FPUL, DRn */

  1269 			    float angle = (((float)(short)(FPULi>>16)) +

  1270 					   ((float)(FPULi&16)/65536.0)) *

  1271 				2 * M_PI;

  1272 			    int reg = DRNn(ir);

  1273 			    DR(reg) = sinf(angle);

  1274 			    DR(reg+1) = cosf(angle);

  1275 			    break;

  1276 			}

  1277 			else if( ir == 0xFBFD ) {

  1278 			    /* FRCHG   */

  1279 			    sh4r.fpscr ^= FPSCR_FR;

  1280 			    break;

  1281 			}

  1282 			else if( ir == 0xF3FD ) {

  1283 			    /* FSCHG   */

  1284 			    sh4r.fpscr ^= FPSCR_SZ;

  1285 			    break;

  1286 			}

  1287 		    default: UNDEF(ir);

  1288                     }

  1289                     break;

  1290                 case 14:/* FMAC    FR0, FRm, FRn */

  1291                     DRN(ir) += DRM(ir)*DR0;

  1292                     break;

  1293                 default: UNDEF(ir);

  1294 		}

  1295 	    } else {

  1296 		switch( ir&0x000F ) {

  1297                 case 0: /* FADD    FRm, FRn */

  1298                     FRN(ir) += FRM(ir);

  1299                     break;

  1300                 case 1: /* FSUB    FRm, FRn */

  1301                     FRN(ir) -= FRM(ir);

  1302                     break;

  1303                 case 2: /* FMUL    FRm, FRn */

  1304                     FRN(ir) = FRN(ir) * FRM(ir);

  1305                     break;

  1306                 case 3: /* FDIV    FRm, FRn */

  1307                     FRN(ir) = FRN(ir) / FRM(ir);

  1308                     break;

  1309                 case 4: /* FCMP/EQ FRm, FRn */

  1310                     sh4r.t = ( FRN(ir) == FRM(ir) ? 1 : 0 );

  1311                     break;

  1312                 case 5: /* FCMP/GT FRm, FRn */

  1313                     sh4r.t = ( FRN(ir) > FRM(ir) ? 1 : 0 );

  1314                     break;

  1315                 case 6: /* FMOV.S  [Rm+R0], FRn */

  1316                     MEM_FP_READ( RM(ir) + R0, FRNn(ir) );

  1317                     break;

  1318                 case 7: /* FMOV.S  FRm, [Rn+R0] */

  1319                     MEM_FP_WRITE( RN(ir) + R0, FRMn(ir) );

  1320                     break;

  1321                 case 8: /* FMOV.S  [Rm], FRn */

  1322                     MEM_FP_READ( RM(ir), FRNn(ir) );

  1323                     break;

  1324                 case 9: /* FMOV.S  [Rm++], FRn */

  1325                     MEM_FP_READ( RM(ir), FRNn(ir) );

  1326                     RM(ir) += FP_WIDTH;

  1327                     break;

  1328                 case 10:/* FMOV.S  FRm, [Rn] */

  1329                     MEM_FP_WRITE( RN(ir), FRMn(ir) );

  1330                     break;

  1331                 case 11:/* FMOV.S  FRm, [--Rn] */

  1332                     RN(ir) -= FP_WIDTH;

  1333                     MEM_FP_WRITE( RN(ir), FRMn(ir) );

  1334                     break;

  1335                 case 12:/* FMOV    FRm, FRn */

  1336 		    if( IS_FPU_DOUBLESIZE() )

  1337 			DRN(ir) = DRM(ir);

  1338 		    else

  1339 			FRN(ir) = FRM(ir);

  1340                     break;

  1341                 case 13:

  1342                     switch( (ir&0x00F0) >> 4 ) {

  1343 		    case 0: /* FSTS    FPUL, FRn */

  1344 			FRN(ir) = FPULf;

  1345 			break;

  1346 		    case 1: /* FLDS    FRn,FPUL */

  1347 			FPULf = FRN(ir);

  1348 			break;

  1349 		    case 2: /* FLOAT   FPUL, FRn */

  1350 			FRN(ir) = (float)FPULi;

  1351 			break;

  1352 		    case 3: /* FTRC    FRn, FPUL */

  1353 			FPULi = (uint32_t)FRN(ir);

  1354 			/* FIXME: is this sufficient? */

  1355 			break;

  1356 		    case 4: /* FNEG    FRn */

  1357 			FRN(ir) = -FRN(ir);

  1358 			break;

  1359 		    case 5: /* FABS    FRn */

  1360 			FRN(ir) = fabsf(FRN(ir));

  1361 			break;

  1362 		    case 6: /* FSQRT   FRn */

  1363 			FRN(ir) = sqrtf(FRN(ir));

  1364 			break;

  1365 		    case 7: /* FSRRA FRn */

  1366 			FRN(ir) = 1.0/sqrtf(FRN(ir));

  1367 			break;

  1368 		    case 8: /* FLDI0   FRn */

  1369 			FRN(ir) = 0.0;

  1370 			break;

  1371 		    case 9: /* FLDI1   FRn */

  1372 			FRN(ir) = 1.0;

  1373 			break;

  1374 		    case 10: /* FCNVSD FPUL, DRn */

  1375 			UNDEF(ir);

  1376 			break;

  1377 		    case 11: /* FCNVDS DRn, FPUL */

  1378 			UNDEF(ir);

  1379 			break;

  1380 		    case 14:/* FIPR    FVm, FVn */

  1381                             /* FIXME: This is not going to be entirely accurate

  1382                              * as the SH4 instruction is less precise. Also

  1383                              * need to check for 0s and infinities.

  1384                              */

  1385                         {

  1386                             int tmp2 = FVN(ir);

  1387                             tmp = FVM(ir);

  1388                             FR(tmp2+3) = FR(tmp)*FR(tmp2) +

  1389                                 FR(tmp+1)*FR(tmp2+1) +

  1390                                 FR(tmp+2)*FR(tmp2+2) +

  1391                                 FR(tmp+3)*FR(tmp2+3);

  1392                             break;

  1393                         }

  1394 		    case 15:

  1395 			if( (ir&0x0300) == 0x0100 ) { /* FTRV    XMTRX,FVn */

  1396 			    tmp = FVN(ir);

  1397 			    float fv[4] = { FR(tmp), FR(tmp+1), FR(tmp+2), FR(tmp+3) };

  1398 			    FR(tmp) = XF(0) * fv[0] + XF(4)*fv[1] +

  1399 				XF(8)*fv[2] + XF(12)*fv[3];

  1400 			    FR(tmp+1) = XF(1) * fv[0] + XF(5)*fv[1] +

  1401 				XF(9)*fv[2] + XF(13)*fv[3];

  1402 			    FR(tmp+2) = XF(2) * fv[0] + XF(6)*fv[1] +

  1403 				XF(10)*fv[2] + XF(14)*fv[3];

  1404 			    FR(tmp+3) = XF(3) * fv[0] + XF(7)*fv[1] +

  1405 				XF(11)*fv[2] + XF(15)*fv[3];

  1406 			    break;

  1407 			}

  1408 			else if( (ir&0x0100) == 0 ) { /* FSCA    FPUL, DRn */

  1409 			    float angle = (((float)(short)(FPULi>>16)) +

  1410 					   ((float)(FPULi&16)/65536.0)) *

  1411 				2 * M_PI;

  1412 			    int reg = FRNn(ir);

  1413 			    FR(reg) = sinf(angle);

  1414 			    FR(reg+1) = cosf(angle);

  1415 			    break;

  1416 			}

  1417 			else if( ir == 0xFBFD ) {

  1418 			    /* FRCHG   */

  1419 			    sh4r.fpscr ^= FPSCR_FR;

  1420 			    break;

  1421 			}

  1422 			else if( ir == 0xF3FD ) {

  1423 			    /* FSCHG   */

  1424 			    sh4r.fpscr ^= FPSCR_SZ;

  1425 			    break;

  1426 			}

  1427 		    default: UNDEF(ir);

  1428                     }

  1429                     break;

  1430                 case 14:/* FMAC    FR0, FRm, FRn */

  1431                     FRN(ir) += FRM(ir)*FR0;

  1432                     break;

  1433                 default: UNDEF(ir);

  1434 		}

  1435 	    }

  1436 	    break;

  1437     }

  1438     sh4r.pc = sh4r.new_pc;

  1439     sh4r.new_pc += 2;

  1440     sh4r.in_delay_slot = 0;

  1441 }