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lxdream.org :: lxdream/src/sh4/sh4.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4.c
changeset 418:b9b14afa0959
prev412:d58e4d69de16
next422:61a0598e07ff
author nkeynes
date Thu Oct 04 08:47:52 2007 +0000 (14 years ago)
permissions -rw-r--r--
last change Add explicit branch cases for main ram - yes it's faster...
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     1 /**
     2  * $Id: sh4.c,v 1.4 2007-10-04 08:47:52 nkeynes Exp $
     3  * 
     4  * SH4 parent module for all CPU modes and SH4 peripheral
     5  * modules.
     6  *
     7  * Copyright (c) 2005 Nathan Keynes.
     8  *
     9  * This program is free software; you can redistribute it and/or modify
    10  * it under the terms of the GNU General Public License as published by
    11  * the Free Software Foundation; either version 2 of the License, or
    12  * (at your option) any later version.
    13  *
    14  * This program is distributed in the hope that it will be useful,
    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17  * GNU General Public License for more details.
    18  */
    20 #define MODULE sh4_module
    21 #include <math.h>
    22 #include "dream.h"
    23 #include "sh4/sh4core.h"
    24 #include "sh4/sh4mmio.h"
    25 #include "sh4/intc.h"
    26 #include "mem.h"
    27 #include "clock.h"
    28 #include "syscall.h"
    30 #define EXV_EXCEPTION    0x100  /* General exception vector */
    31 #define EXV_TLBMISS      0x400  /* TLB-miss exception vector */
    32 #define EXV_INTERRUPT    0x600  /* External interrupt vector */
    34 void sh4_init( void );
    35 void sh4_reset( void );
    36 void sh4_start( void );
    37 void sh4_stop( void );
    38 void sh4_save_state( FILE *f );
    39 int sh4_load_state( FILE *f );
    41 uint32_t sh4_run_slice( uint32_t );
    42 uint32_t sh4_xlat_run_slice( uint32_t );
    44 struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset, 
    45 				       NULL, sh4_run_slice, sh4_stop,
    46 				       sh4_save_state, sh4_load_state };
    48 struct sh4_registers sh4r;
    49 struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
    50 int sh4_breakpoint_count = 0;
    51 extern char *sh4_main_ram;
    53 void sh4_set_use_xlat( gboolean use )
    54 {
    55     if( use ) {
    56 	xlat_cache_init();
    57 	sh4_x86_init();
    58 	sh4_module.run_time_slice = sh4_xlat_run_slice;
    59     } else {
    60 	sh4_module.run_time_slice = sh4_run_slice;
    61     }
    62 }
    64 void sh4_init(void)
    65 {
    66     register_io_regions( mmio_list_sh4mmio );
    67     sh4_main_ram = mem_get_region_by_name(MEM_REGION_MAIN);
    68     MMU_init();
    69     sh4_reset();
    70 }
    72 void sh4_reset(void)
    73 {
    74     /* zero everything out, for the sake of having a consistent state. */
    75     memset( &sh4r, 0, sizeof(sh4r) );
    77     /* Resume running if we were halted */
    78     sh4r.sh4_state = SH4_STATE_RUNNING;
    80     sh4r.pc    = 0xA0000000;
    81     sh4r.new_pc= 0xA0000002;
    82     sh4r.vbr   = 0x00000000;
    83     sh4r.fpscr = 0x00040001;
    84     sh4r.sr    = 0x700000F0;
    85     sh4r.fr_bank = &sh4r.fr[0][0];
    87     /* Mem reset will do this, but if we want to reset _just_ the SH4... */
    88     MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
    90     /* Peripheral modules */
    91     CPG_reset();
    92     INTC_reset();
    93     MMU_reset();
    94     TMU_reset();
    95     SCIF_reset();
    96     sh4_stats_reset();
    97 }
    99 void sh4_stop(void)
   100 {
   102 }
   104 void sh4_save_state( FILE *f )
   105 {
   106     if(	sh4_module.run_time_slice == sh4_xlat_run_slice ) {
   107 	/* If we were running with the translator, update new_pc and in_delay_slot */
   108 	sh4r.new_pc = sh4r.pc+2;
   109 	sh4r.in_delay_slot = FALSE;
   110     }
   112     fwrite( &sh4r, sizeof(sh4r), 1, f );
   113     MMU_save_state( f );
   114     INTC_save_state( f );
   115     TMU_save_state( f );
   116     SCIF_save_state( f );
   117 }
   119 int sh4_load_state( FILE * f )
   120 {
   121     fread( &sh4r, sizeof(sh4r), 1, f );
   122     sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0]; // Fixup internal FR pointer
   123     MMU_load_state( f );
   124     INTC_load_state( f );
   125     TMU_load_state( f );
   126     return SCIF_load_state( f );
   127 }
   130 void sh4_set_breakpoint( uint32_t pc, int type )
   131 {
   132     sh4_breakpoints[sh4_breakpoint_count].address = pc;
   133     sh4_breakpoints[sh4_breakpoint_count].type = type;
   134     sh4_breakpoint_count++;
   135 }
   137 gboolean sh4_clear_breakpoint( uint32_t pc, int type )
   138 {
   139     int i;
   141     for( i=0; i<sh4_breakpoint_count; i++ ) {
   142 	if( sh4_breakpoints[i].address == pc && 
   143 	    sh4_breakpoints[i].type == type ) {
   144 	    while( ++i < sh4_breakpoint_count ) {
   145 		sh4_breakpoints[i-1].address = sh4_breakpoints[i].address;
   146 		sh4_breakpoints[i-1].type = sh4_breakpoints[i].type;
   147 	    }
   148 	    sh4_breakpoint_count--;
   149 	    return TRUE;
   150 	}
   151     }
   152     return FALSE;
   153 }
   155 int sh4_get_breakpoint( uint32_t pc )
   156 {
   157     int i;
   158     for( i=0; i<sh4_breakpoint_count; i++ ) {
   159 	if( sh4_breakpoints[i].address == pc )
   160 	    return sh4_breakpoints[i].type;
   161     }
   162     return 0;
   163 }
   165 void sh4_set_pc( int pc )
   166 {
   167     sh4r.pc = pc;
   168     sh4r.new_pc = pc+2;
   169 }
   172 /******************************* Support methods ***************************/
   174 static void sh4_switch_banks( )
   175 {
   176     uint32_t tmp[8];
   178     memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
   179     memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
   180     memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
   181 }
   183 void sh4_write_sr( uint32_t newval )
   184 {
   185     if( (newval ^ sh4r.sr) & SR_RB )
   186         sh4_switch_banks();
   187     sh4r.sr = newval;
   188     sh4r.t = (newval&SR_T) ? 1 : 0;
   189     sh4r.s = (newval&SR_S) ? 1 : 0;
   190     sh4r.m = (newval&SR_M) ? 1 : 0;
   191     sh4r.q = (newval&SR_Q) ? 1 : 0;
   192     intc_mask_changed();
   193 }
   195 uint32_t sh4_read_sr( void )
   196 {
   197     /* synchronize sh4r.sr with the various bitflags */
   198     sh4r.sr &= SR_MQSTMASK;
   199     if( sh4r.t ) sh4r.sr |= SR_T;
   200     if( sh4r.s ) sh4r.sr |= SR_S;
   201     if( sh4r.m ) sh4r.sr |= SR_M;
   202     if( sh4r.q ) sh4r.sr |= SR_Q;
   203     return sh4r.sr;
   204 }
   208 #define RAISE( x, v ) do{			\
   209     if( sh4r.vbr == 0 ) { \
   210         ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
   211         dreamcast_stop(); return FALSE;	\
   212     } else { \
   213         sh4r.spc = sh4r.pc;	\
   214         sh4r.ssr = sh4_read_sr(); \
   215         sh4r.sgr = sh4r.r[15]; \
   216         MMIO_WRITE(MMU,EXPEVT,x); \
   217         sh4r.pc = sh4r.vbr + v; \
   218         sh4r.new_pc = sh4r.pc + 2; \
   219         sh4_write_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
   220 	if( sh4r.in_delay_slot ) { \
   221 	    sh4r.in_delay_slot = 0; \
   222 	    sh4r.spc -= 2; \
   223 	} \
   224     } \
   225     return TRUE; } while(0)
   227 /**
   228  * Raise a general CPU exception for the specified exception code.
   229  * (NOT for TRAPA or TLB exceptions)
   230  */
   231 gboolean sh4_raise_exception( int code )
   232 {
   233     RAISE( code, EXV_EXCEPTION );
   234 }
   236 gboolean sh4_raise_trap( int trap )
   237 {
   238     MMIO_WRITE( MMU, TRA, trap<<2 );
   239     return sh4_raise_exception( EXC_TRAP );
   240 }
   242 gboolean sh4_raise_slot_exception( int normal_code, int slot_code ) {
   243     if( sh4r.in_delay_slot ) {
   244 	return sh4_raise_exception(slot_code);
   245     } else {
   246 	return sh4_raise_exception(normal_code);
   247     }
   248 }
   250 gboolean sh4_raise_tlb_exception( int code )
   251 {
   252     RAISE( code, EXV_TLBMISS );
   253 }
   255 void sh4_accept_interrupt( void )
   256 {
   257     uint32_t code = intc_accept_interrupt();
   258     sh4r.ssr = sh4_read_sr();
   259     sh4r.spc = sh4r.pc;
   260     sh4r.sgr = sh4r.r[15];
   261     sh4_write_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
   262     MMIO_WRITE( MMU, INTEVT, code );
   263     sh4r.pc = sh4r.vbr + 0x600;
   264     sh4r.new_pc = sh4r.pc + 2;
   265     //    WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
   266 }
   268 void signsat48( void )
   269 {
   270     if( ((int64_t)sh4r.mac) < (int64_t)0xFFFF800000000000LL )
   271 	sh4r.mac = 0xFFFF800000000000LL;
   272     else if( ((int64_t)sh4r.mac) > (int64_t)0x00007FFFFFFFFFFFLL )
   273 	sh4r.mac = 0x00007FFFFFFFFFFFLL;
   274 }
   276 void sh4_fsca( uint32_t anglei, float *fr )
   277 {
   278     float angle = (((float)(anglei&0xFFFF))/65536.0) * 2 * M_PI;
   279     *fr++ = cosf(angle);
   280     *fr = sinf(angle);
   281 }
   283 void sh4_sleep(void)
   284 {
   285     if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
   286 	sh4r.sh4_state = SH4_STATE_STANDBY;
   287     } else {
   288 	sh4r.sh4_state = SH4_STATE_SLEEP;
   289     }
   290 }
   292 /**
   293  * Compute the matrix tranform of fv given the matrix xf.
   294  * Both fv and xf are word-swapped as per the sh4r.fr banks
   295  */
   296 void sh4_ftrv( float *target, float *xf )
   297 {
   298     float fv[4] = { target[1], target[0], target[3], target[2] };
   299     target[1] = xf[1] * fv[0] + xf[5]*fv[1] +
   300 	xf[9]*fv[2] + xf[13]*fv[3];
   301     target[0] = xf[0] * fv[0] + xf[4]*fv[1] +
   302 	xf[8]*fv[2] + xf[12]*fv[3];
   303     target[3] = xf[3] * fv[0] + xf[7]*fv[1] +
   304 	xf[11]*fv[2] + xf[15]*fv[3];
   305     target[2] = xf[2] * fv[0] + xf[6]*fv[1] +
   306 	xf[10]*fv[2] + xf[14]*fv[3];
   307 }
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