Search
lxdream.org :: lxdream/src/sh4/sh4.c
lxdream 0.9.1
released Jun 29
Download Now
filename src/sh4/sh4.c
changeset 526:ba3da45b5754
prev502:c4ecae2b1b5e
next559:06714bc64271
next586:2a3ba82cf243
author nkeynes
date Sat Nov 17 06:04:19 2007 +0000 (13 years ago)
permissions -rw-r--r--
last change Don't build the translator if the architecture is unsupported. Also tidy things up a little to allow (theoretically) different translators to be selected at build time.
view annotate diff log raw
     1 /**
     2  * $Id: sh4.c,v 1.7 2007-11-08 11:54:16 nkeynes Exp $
     3  * 
     4  * SH4 parent module for all CPU modes and SH4 peripheral
     5  * modules.
     6  *
     7  * Copyright (c) 2005 Nathan Keynes.
     8  *
     9  * This program is free software; you can redistribute it and/or modify
    10  * it under the terms of the GNU General Public License as published by
    11  * the Free Software Foundation; either version 2 of the License, or
    12  * (at your option) any later version.
    13  *
    14  * This program is distributed in the hope that it will be useful,
    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17  * GNU General Public License for more details.
    18  */
    20 #define MODULE sh4_module
    21 #include <math.h>
    22 #include "dream.h"
    23 #include "dreamcast.h"
    24 #include "sh4/sh4core.h"
    25 #include "sh4/sh4mmio.h"
    26 #include "sh4/intc.h"
    27 #include "sh4/xltcache.h"
    28 #include "sh4/sh4stat.h"
    29 #include "mem.h"
    30 #include "clock.h"
    31 #include "syscall.h"
    33 #define EXV_EXCEPTION    0x100  /* General exception vector */
    34 #define EXV_TLBMISS      0x400  /* TLB-miss exception vector */
    35 #define EXV_INTERRUPT    0x600  /* External interrupt vector */
    37 void sh4_init( void );
    38 void sh4_xlat_init( void );
    39 void sh4_reset( void );
    40 void sh4_start( void );
    41 void sh4_stop( void );
    42 void sh4_save_state( FILE *f );
    43 int sh4_load_state( FILE *f );
    45 uint32_t sh4_run_slice( uint32_t );
    46 uint32_t sh4_xlat_run_slice( uint32_t );
    48 struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset, 
    49 				       NULL, sh4_run_slice, sh4_stop,
    50 				       sh4_save_state, sh4_load_state };
    52 struct sh4_registers sh4r;
    53 struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
    54 int sh4_breakpoint_count = 0;
    55 extern sh4ptr_t sh4_main_ram;
    56 static gboolean sh4_use_translator = FALSE;
    58 void sh4_set_use_xlat( gboolean use )
    59 {
    60 // No-op if the translator was not built
    61 #ifdef SH4_TRANSLATOR
    62     if( use ) {
    63 	xlat_cache_init();
    64 	sh4_x86_init();
    65 	sh4_module.run_time_slice = sh4_xlat_run_slice;
    66     } else {
    67 	sh4_module.run_time_slice = sh4_run_slice;
    68     }
    69     sh4_use_translator = use;
    70 #endif
    71 }
    73 void sh4_init(void)
    74 {
    75     register_io_regions( mmio_list_sh4mmio );
    76     sh4_main_ram = mem_get_region_by_name(MEM_REGION_MAIN);
    77     MMU_init();
    78     sh4_reset();
    79 }
    81 void sh4_reset(void)
    82 {
    83     if(	sh4_use_translator ) {
    84 	xlat_flush_cache();
    85     }
    87     /* zero everything out, for the sake of having a consistent state. */
    88     memset( &sh4r, 0, sizeof(sh4r) );
    90     /* Resume running if we were halted */
    91     sh4r.sh4_state = SH4_STATE_RUNNING;
    93     sh4r.pc    = 0xA0000000;
    94     sh4r.new_pc= 0xA0000002;
    95     sh4r.vbr   = 0x00000000;
    96     sh4r.fpscr = 0x00040001;
    97     sh4r.sr    = 0x700000F0;
    98     sh4r.fr_bank = &sh4r.fr[0][0];
   100     /* Mem reset will do this, but if we want to reset _just_ the SH4... */
   101     MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
   103     /* Peripheral modules */
   104     CPG_reset();
   105     INTC_reset();
   106     MMU_reset();
   107     TMU_reset();
   108     SCIF_reset();
   109     sh4_stats_reset();
   110 }
   112 void sh4_stop(void)
   113 {
   114     if(	sh4_use_translator ) {
   115 	/* If we were running with the translator, update new_pc and in_delay_slot */
   116 	sh4r.new_pc = sh4r.pc+2;
   117 	sh4r.in_delay_slot = FALSE;
   118     }
   120 }
   122 void sh4_save_state( FILE *f )
   123 {
   124     if(	sh4_use_translator ) {
   125 	/* If we were running with the translator, update new_pc and in_delay_slot */
   126 	sh4r.new_pc = sh4r.pc+2;
   127 	sh4r.in_delay_slot = FALSE;
   128     }
   130     fwrite( &sh4r, sizeof(sh4r), 1, f );
   131     MMU_save_state( f );
   132     INTC_save_state( f );
   133     TMU_save_state( f );
   134     SCIF_save_state( f );
   135 }
   137 int sh4_load_state( FILE * f )
   138 {
   139     if(	sh4_use_translator ) {
   140 	xlat_flush_cache();
   141     }
   142     fread( &sh4r, sizeof(sh4r), 1, f );
   143     sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0]; // Fixup internal FR pointer
   144     MMU_load_state( f );
   145     INTC_load_state( f );
   146     TMU_load_state( f );
   147     return SCIF_load_state( f );
   148 }
   151 void sh4_set_breakpoint( uint32_t pc, int type )
   152 {
   153     sh4_breakpoints[sh4_breakpoint_count].address = pc;
   154     sh4_breakpoints[sh4_breakpoint_count].type = type;
   155     sh4_breakpoint_count++;
   156 }
   158 gboolean sh4_clear_breakpoint( uint32_t pc, int type )
   159 {
   160     int i;
   162     for( i=0; i<sh4_breakpoint_count; i++ ) {
   163 	if( sh4_breakpoints[i].address == pc && 
   164 	    sh4_breakpoints[i].type == type ) {
   165 	    while( ++i < sh4_breakpoint_count ) {
   166 		sh4_breakpoints[i-1].address = sh4_breakpoints[i].address;
   167 		sh4_breakpoints[i-1].type = sh4_breakpoints[i].type;
   168 	    }
   169 	    sh4_breakpoint_count--;
   170 	    return TRUE;
   171 	}
   172     }
   173     return FALSE;
   174 }
   176 int sh4_get_breakpoint( uint32_t pc )
   177 {
   178     int i;
   179     for( i=0; i<sh4_breakpoint_count; i++ ) {
   180 	if( sh4_breakpoints[i].address == pc )
   181 	    return sh4_breakpoints[i].type;
   182     }
   183     return 0;
   184 }
   186 void sh4_set_pc( int pc )
   187 {
   188     sh4r.pc = pc;
   189     sh4r.new_pc = pc+2;
   190 }
   193 /******************************* Support methods ***************************/
   195 static void sh4_switch_banks( )
   196 {
   197     uint32_t tmp[8];
   199     memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
   200     memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
   201     memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
   202 }
   204 void sh4_write_sr( uint32_t newval )
   205 {
   206     if( (newval ^ sh4r.sr) & SR_RB )
   207         sh4_switch_banks();
   208     sh4r.sr = newval;
   209     sh4r.t = (newval&SR_T) ? 1 : 0;
   210     sh4r.s = (newval&SR_S) ? 1 : 0;
   211     sh4r.m = (newval&SR_M) ? 1 : 0;
   212     sh4r.q = (newval&SR_Q) ? 1 : 0;
   213     intc_mask_changed();
   214 }
   216 uint32_t sh4_read_sr( void )
   217 {
   218     /* synchronize sh4r.sr with the various bitflags */
   219     sh4r.sr &= SR_MQSTMASK;
   220     if( sh4r.t ) sh4r.sr |= SR_T;
   221     if( sh4r.s ) sh4r.sr |= SR_S;
   222     if( sh4r.m ) sh4r.sr |= SR_M;
   223     if( sh4r.q ) sh4r.sr |= SR_Q;
   224     return sh4r.sr;
   225 }
   229 #define RAISE( x, v ) do{			\
   230     if( sh4r.vbr == 0 ) { \
   231         ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
   232         dreamcast_stop(); return FALSE;	\
   233     } else { \
   234         sh4r.spc = sh4r.pc;	\
   235         sh4r.ssr = sh4_read_sr(); \
   236         sh4r.sgr = sh4r.r[15]; \
   237         MMIO_WRITE(MMU,EXPEVT,x); \
   238         sh4r.pc = sh4r.vbr + v; \
   239         sh4r.new_pc = sh4r.pc + 2; \
   240         sh4_write_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
   241 	if( sh4r.in_delay_slot ) { \
   242 	    sh4r.in_delay_slot = 0; \
   243 	    sh4r.spc -= 2; \
   244 	} \
   245     } \
   246     return TRUE; } while(0)
   248 /**
   249  * Raise a general CPU exception for the specified exception code.
   250  * (NOT for TRAPA or TLB exceptions)
   251  */
   252 gboolean sh4_raise_exception( int code )
   253 {
   254     RAISE( code, EXV_EXCEPTION );
   255 }
   257 gboolean sh4_raise_trap( int trap )
   258 {
   259     MMIO_WRITE( MMU, TRA, trap<<2 );
   260     return sh4_raise_exception( EXC_TRAP );
   261 }
   263 gboolean sh4_raise_slot_exception( int normal_code, int slot_code ) {
   264     if( sh4r.in_delay_slot ) {
   265 	return sh4_raise_exception(slot_code);
   266     } else {
   267 	return sh4_raise_exception(normal_code);
   268     }
   269 }
   271 gboolean sh4_raise_tlb_exception( int code )
   272 {
   273     RAISE( code, EXV_TLBMISS );
   274 }
   276 void sh4_accept_interrupt( void )
   277 {
   278     uint32_t code = intc_accept_interrupt();
   279     sh4r.ssr = sh4_read_sr();
   280     sh4r.spc = sh4r.pc;
   281     sh4r.sgr = sh4r.r[15];
   282     sh4_write_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
   283     MMIO_WRITE( MMU, INTEVT, code );
   284     sh4r.pc = sh4r.vbr + 0x600;
   285     sh4r.new_pc = sh4r.pc + 2;
   286     //    WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
   287 }
   289 void signsat48( void )
   290 {
   291     if( ((int64_t)sh4r.mac) < (int64_t)0xFFFF800000000000LL )
   292 	sh4r.mac = 0xFFFF800000000000LL;
   293     else if( ((int64_t)sh4r.mac) > (int64_t)0x00007FFFFFFFFFFFLL )
   294 	sh4r.mac = 0x00007FFFFFFFFFFFLL;
   295 }
   297 void sh4_fsca( uint32_t anglei, float *fr )
   298 {
   299     float angle = (((float)(anglei&0xFFFF))/65536.0) * 2 * M_PI;
   300     *fr++ = cosf(angle);
   301     *fr = sinf(angle);
   302 }
   304 void sh4_sleep(void)
   305 {
   306     if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
   307 	sh4r.sh4_state = SH4_STATE_STANDBY;
   308     } else {
   309 	sh4r.sh4_state = SH4_STATE_SLEEP;
   310     }
   311 }
   313 /**
   314  * Compute the matrix tranform of fv given the matrix xf.
   315  * Both fv and xf are word-swapped as per the sh4r.fr banks
   316  */
   317 void sh4_ftrv( float *target, float *xf )
   318 {
   319     float fv[4] = { target[1], target[0], target[3], target[2] };
   320     target[1] = xf[1] * fv[0] + xf[5]*fv[1] +
   321 	xf[9]*fv[2] + xf[13]*fv[3];
   322     target[0] = xf[0] * fv[0] + xf[4]*fv[1] +
   323 	xf[8]*fv[2] + xf[12]*fv[3];
   324     target[3] = xf[3] * fv[0] + xf[7]*fv[1] +
   325 	xf[11]*fv[2] + xf[15]*fv[3];
   326     target[2] = xf[2] * fv[0] + xf[6]*fv[1] +
   327 	xf[10]*fv[2] + xf[14]*fv[3];
   328 }
.