4 * This file defines the public functions and definitions exported by the SH4
7 * Copyright (c) 2005 Nathan Keynes.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 #define lxdream_sh4_H 1
32 * SH4 is running normally
34 #define SH4_STATE_RUNNING 1
36 * SH4 is not executing instructions but all peripheral modules are still
39 #define SH4_STATE_SLEEP 2
41 * SH4 is not executing instructions, DMAC is halted, but all other peripheral
42 * modules are still running
44 #define SH4_STATE_DEEP_SLEEP 3
46 * SH4 is not executing instructions and all peripheral modules are also
47 * stopped. As close as you can get to powered-off without actually being
50 #define SH4_STATE_STANDBY 4
53 * sh4r.event_types flag indicating a pending IRQ
58 * sh4r.event_types flag indicating a pending event (from the event queue)
60 #define PENDING_EVENT 2
63 * SH4 register structure
65 struct sh4_registers {
72 uint32_t t, m, q, s; /* really boolean - 0 or 1 */
73 float fr[2][16]; /* Must be aligned on 16-byte boundary */
75 uint32_t pad; /* Pad up to 64-bit boundaries */
77 uint32_t gbr, ssr, spc, sgr, dbr, vbr;
79 uint32_t r_bank[8]; /* hidden banked registers */
80 int32_t store_queue[16]; /* technically 2 banks of 32 bytes */
82 uint32_t new_pc; /* Not a real register, but used to handle delay slots */
83 uint32_t event_pending; /* slice cycle time of the next pending event, or FFFFFFFF
84 when no events are pending */
85 uint32_t event_types; /* bit 0 = IRQ pending, bit 1 = general event pending */
86 int in_delay_slot; /* flag to indicate the current instruction is in
87 * a delay slot (certain rules apply) */
88 uint32_t slice_cycle; /* Current nanosecond within the timeslice */
89 uint32_t bus_cycle; /* Nanosecond within the timeslice that the bus will be free */
90 int sh4_state; /* Current power-on state (one of the SH4_STATE_* values ) */
93 int xlat_sh4_mode; /* Collection of execution mode flags (derived) from fpscr, sr, etc */
96 extern struct sh4_registers sh4r;
98 extern const struct cpu_desc_struct sh4_cpu_desc;
101 * Switch between translation and emulation execution modes. Note that this
102 * should only be used while the system is stopped. If the system was built
103 * without translation support, this method has no effect.
105 * @param use TRUE for translation mode, FALSE for emulation mode.
107 void sh4_translate_set_enabled( gboolean use );
110 * Test if system is currently using the translation engine.
112 gboolean sh4_translate_is_enabled();
115 * Explicitly set the SH4 PC to the supplied value - this will be the next
116 * instruction executed. This should only be called while the system is stopped.
118 void sh4_set_pc( int pc );
121 * Execute (using the emulator) a single instruction (in other words, perform a
122 * single-step operation).
124 gboolean sh4_execute_instruction( void );
126 /* SH4 breakpoints */
127 void sh4_set_breakpoint( uint32_t pc, breakpoint_type_t type );
128 gboolean sh4_clear_breakpoint( uint32_t pc, breakpoint_type_t type );
129 int sh4_get_breakpoint( uint32_t pc );
134 #endif /* !lxdream_sh4_H */
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lxdream 0.9.1