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lxdream.org :: lxdream/src/sh4/sh4core.in
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4core.in
changeset 1065:bc1cc0c54917
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author nkeynes
date Sun Jul 05 13:52:50 2009 +1000 (11 years ago)
permissions -rw-r--r--
last change No-op merge lxdream-mmu to remove head (actually merged long ago)
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     1 /**
     2  * $Id$
     3  * 
     4  * SH4 emulation core, and parent module for all the SH4 peripheral
     5  * modules.
     6  *
     7  * Copyright (c) 2005 Nathan Keynes.
     8  *
     9  * This program is free software; you can redistribute it and/or modify
    10  * it under the terms of the GNU General Public License as published by
    11  * the Free Software Foundation; either version 2 of the License, or
    12  * (at your option) any later version.
    13  *
    14  * This program is distributed in the hope that it will be useful,
    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17  * GNU General Public License for more details.
    18  */
    20 #define MODULE sh4_module
    21 #include <assert.h>
    22 #include <math.h>
    23 #include "dream.h"
    24 #include "dreamcast.h"
    25 #include "eventq.h"
    26 #include "mem.h"
    27 #include "clock.h"
    28 #include "syscall.h"
    29 #include "sh4/sh4core.h"
    30 #include "sh4/sh4mmio.h"
    31 #include "sh4/sh4stat.h"
    32 #include "sh4/mmu.h"
    34 #define SH4_CALLTRACE 1
    36 #define MAX_INT 0x7FFFFFFF
    37 #define MIN_INT 0x80000000
    38 #define MAX_INTF 2147483647.0
    39 #define MIN_INTF -2147483648.0
    41 /********************** SH4 Module Definition ****************************/
    43 uint32_t sh4_emulate_run_slice( uint32_t nanosecs ) 
    44 {
    45     int i;
    47     if( sh4_breakpoint_count == 0 ) {
    48 	for( ; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
    49 	    if( SH4_EVENT_PENDING() ) {
    50 		if( sh4r.event_types & PENDING_EVENT ) {
    51 		    event_execute();
    52 		}
    53 		/* Eventq execute may (quite likely) deliver an immediate IRQ */
    54 		if( sh4r.event_types & PENDING_IRQ ) {
    55 		    sh4_accept_interrupt();
    56 		}
    57 	    }
    58 	    if( !sh4_execute_instruction() ) {
    59 		break;
    60 	    }
    61 	}
    62     } else {
    63 	for( ;sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
    64 	    if( SH4_EVENT_PENDING() ) {
    65 		if( sh4r.event_types & PENDING_EVENT ) {
    66 		    event_execute();
    67 		}
    68 		/* Eventq execute may (quite likely) deliver an immediate IRQ */
    69 		if( sh4r.event_types & PENDING_IRQ ) {
    70 		    sh4_accept_interrupt();
    71 		}
    72 	    }
    74 	    if( !sh4_execute_instruction() )
    75 		break;
    76 #ifdef ENABLE_DEBUG_MODE
    77 	    for( i=0; i<sh4_breakpoint_count; i++ ) {
    78 		if( sh4_breakpoints[i].address == sh4r.pc ) {
    79 		    break;
    80 		}
    81 	    }
    82 	    if( i != sh4_breakpoint_count ) {
    83 	    	sh4_core_exit( CORE_EXIT_BREAKPOINT );
    84 	    }
    85 #endif	
    86 	}
    87     }
    89     /* If we aborted early, but the cpu is still technically running,
    90      * we're doing a hard abort - cut the timeslice back to what we
    91      * actually executed
    92      */
    93     if( sh4r.slice_cycle != nanosecs && sh4r.sh4_state == SH4_STATE_RUNNING ) {
    94 	nanosecs = sh4r.slice_cycle;
    95     }
    96     if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
    97 	TMU_run_slice( nanosecs );
    98 	SCIF_run_slice( nanosecs );
    99     }
   100     return nanosecs;
   101 }
   103 /********************** SH4 emulation core  ****************************/
   105 #if(SH4_CALLTRACE == 1)
   106 #define MAX_CALLSTACK 32
   107 static struct call_stack {
   108     sh4addr_t call_addr;
   109     sh4addr_t target_addr;
   110     sh4addr_t stack_pointer;
   111 } call_stack[MAX_CALLSTACK];
   113 static int call_stack_depth = 0;
   114 int sh4_call_trace_on = 0;
   116 static inline void trace_call( sh4addr_t source, sh4addr_t dest ) 
   117 {
   118     if( call_stack_depth < MAX_CALLSTACK ) {
   119 	call_stack[call_stack_depth].call_addr = source;
   120 	call_stack[call_stack_depth].target_addr = dest;
   121 	call_stack[call_stack_depth].stack_pointer = sh4r.r[15];
   122     }
   123     call_stack_depth++;
   124 }
   126 static inline void trace_return( sh4addr_t source, sh4addr_t dest )
   127 {
   128     if( call_stack_depth > 0 ) {
   129 	call_stack_depth--;
   130     }
   131 }
   133 void fprint_stack_trace( FILE *f )
   134 {
   135     int i = call_stack_depth -1;
   136     if( i >= MAX_CALLSTACK )
   137 	i = MAX_CALLSTACK - 1;
   138     for( ; i >= 0; i-- ) {
   139 	fprintf( f, "%d. Call from %08X => %08X, SP=%08X\n", 
   140 		 (call_stack_depth - i), call_stack[i].call_addr,
   141 		 call_stack[i].target_addr, call_stack[i].stack_pointer );
   142     }
   143 }
   145 #define TRACE_CALL( source, dest ) trace_call(source, dest)
   146 #define TRACE_RETURN( source, dest ) trace_return(source, dest)
   147 #else
   148 #define TRACE_CALL( dest, rts ) 
   149 #define TRACE_RETURN( source, dest )
   150 #endif
   152 static gboolean FASTCALL sh4_raise_slot_exception( int normal_code, int slot_code ) {
   153     if( sh4r.in_delay_slot ) {
   154         sh4_raise_exception(slot_code);
   155     } else {
   156         sh4_raise_exception(normal_code);
   157     }
   158     return TRUE;
   159 }
   162 #define CHECKPRIV() if( !IS_SH4_PRIVMODE() ) { return sh4_raise_slot_exception( EXC_ILLEGAL, EXC_SLOT_ILLEGAL ); }
   163 #define CHECKRALIGN16(addr) if( (addr)&0x01 ) { sh4_raise_exception( EXC_DATA_ADDR_READ ); return TRUE; }
   164 #define CHECKRALIGN32(addr) if( (addr)&0x03 ) { sh4_raise_exception( EXC_DATA_ADDR_READ ); return TRUE; }
   165 #define CHECKRALIGN64(addr) if( (addr)&0x07 ) { sh4_raise_exception( EXC_DATA_ADDR_READ ); return TRUE; }
   166 #define CHECKWALIGN16(addr) if( (addr)&0x01 ) { sh4_raise_exception( EXC_DATA_ADDR_WRITE ); return TRUE; }
   167 #define CHECKWALIGN32(addr) if( (addr)&0x03 ) { sh4_raise_exception( EXC_DATA_ADDR_WRITE ); return TRUE; }
   168 #define CHECKWALIGN64(addr) if( (addr)&0x07 ) { sh4_raise_exception( EXC_DATA_ADDR_WRITE ); return TRUE; }
   170 #define CHECKFPUEN() if( !IS_FPU_ENABLED() ) { if( ir == 0xFFFD ) { UNDEF(ir); } else { return sh4_raise_slot_exception( EXC_FPU_DISABLED, EXC_SLOT_FPU_DISABLED ); } }
   171 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); sh4_core_exit(CORE_EXIT_HALT); return FALSE; }
   172 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) { sh4_raise_exception(EXC_SLOT_ILLEGAL); return TRUE; }
   174 #define ADDRSPACE (IS_SH4_PRIVMODE() ? sh4_address_space : sh4_user_address_space)
   175 #define SQADDRSPACE (IS_SH4_PRIVMODE() ? storequeue_address_space : storequeue_user_address_space)
   177 #ifdef HAVE_FRAME_ADDRESS
   178 static FASTCALL __attribute__((noinline)) void *__first_arg(void *a, void *b) { return a; }
   179 #define INIT_EXCEPTIONS(label) goto *__first_arg(&&fnstart,&&label); fnstart:
   180 #define MEM_READ_BYTE( addr, val ) val = ((mem_read_exc_fn_t)ADDRSPACE[(addr)>>12]->read_byte)((addr), &&except)
   181 #define MEM_READ_WORD( addr, val ) val = ((mem_read_exc_fn_t)ADDRSPACE[(addr)>>12]->read_word)((addr), &&except)
   182 #define MEM_READ_LONG( addr, val ) val = ((mem_read_exc_fn_t)ADDRSPACE[(addr)>>12]->read_long)((addr), &&except)
   183 #define MEM_WRITE_BYTE( addr, val ) ((mem_write_exc_fn_t)ADDRSPACE[(addr)>>12]->write_byte)((addr), (val), &&except)
   184 #define MEM_WRITE_WORD( addr, val ) ((mem_write_exc_fn_t)ADDRSPACE[(addr)>>12]->write_word)((addr), (val), &&except)
   185 #define MEM_WRITE_LONG( addr, val ) ((mem_write_exc_fn_t)ADDRSPACE[(addr)>>12]->write_long)((addr), (val), &&except)
   186 #define MEM_PREFETCH( addr ) ((mem_prefetch_exc_fn_t)ADDRSPACE[(addr)>>12]->prefetch)((addr), &&except)
   187 #else
   188 #define INIT_EXCEPTIONS(label)
   189 #define MEM_READ_BYTE( addr, val ) val = ADDRSPACE[(addr)>>12]->read_byte(addr)
   190 #define MEM_READ_WORD( addr, val ) val = ADDRSPACE[(addr)>>12]->read_word(addr)
   191 #define MEM_READ_LONG( addr, val ) val = ADDRSPACE[(addr)>>12]->read_long(addr)
   192 #define MEM_WRITE_BYTE( addr, val ) ADDRSPACE[(addr)>>12]->write_byte(addr, val)
   193 #define MEM_WRITE_WORD( addr, val ) ADDRSPACE[(addr)>>12]->write_word(addr, val)
   194 #define MEM_WRITE_LONG( addr, val ) ADDRSPACE[(addr)>>12]->write_long(addr, val)
   195 #define MEM_PREFETCH( addr ) ADDRSPACE[(addr)>>12]->prefetch(addr)
   196 #endif
   198 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
   200 #define MEM_FP_READ( addr, reg ) \
   201     if( IS_FPU_DOUBLESIZE() ) { \
   202 	CHECKRALIGN64(addr); \
   203         if( reg & 1 ) { \
   204             MEM_READ_LONG( addr, *((uint32_t *)&XF((reg) & 0x0E)) ); \
   205             MEM_READ_LONG( addr+4, *((uint32_t *)&XF(reg)) ); \
   206         } else { \
   207             MEM_READ_LONG( addr, *((uint32_t *)&FR(reg)) ); \
   208             MEM_READ_LONG( addr+4, *((uint32_t *)&FR((reg)|0x01)) ); \
   209 	} \
   210     } else { \
   211         CHECKRALIGN32(addr); \
   212         MEM_READ_LONG( addr, *((uint32_t *)&FR(reg)) ); \
   213     }
   214 #define MEM_FP_WRITE( addr, reg ) \
   215     if( IS_FPU_DOUBLESIZE() ) { \
   216         CHECKWALIGN64(addr); \
   217         if( reg & 1 ) { \
   218 	    MEM_WRITE_LONG( addr, *((uint32_t *)&XF((reg)&0x0E)) ); \
   219 	    MEM_WRITE_LONG( addr+4, *((uint32_t *)&XF(reg)) ); \
   220         } else { \
   221 	    MEM_WRITE_LONG( addr, *((uint32_t *)&FR(reg)) ); \
   222 	    MEM_WRITE_LONG( addr+4, *((uint32_t *)&FR((reg)|0x01)) ); \
   223 	} \
   224     } else { \
   225     	CHECKWALIGN32(addr); \
   226         MEM_WRITE_LONG(addr, *((uint32_t *)&FR((reg))) ); \
   227     }
   229 #define UNDEF(ir)
   230 #define UNIMP(ir)
   232 /**
   233  * Perform instruction-completion following core exit of a partially completed
   234  * instruction. NOTE: This is only allowed on memory writes, operation is not
   235  * guaranteed in any other case.
   236  */
   237 void sh4_finalize_instruction( void )
   238 {
   239     unsigned short ir;
   240     uint32_t tmp;
   242     if( IS_SYSCALL(sh4r.pc) ) {
   243         return;
   244     }
   245     assert( IS_IN_ICACHE(sh4r.pc) );
   246     ir = *(uint16_t *)GET_ICACHE_PTR(sh4r.pc);
   248     /**
   249      * Note - we can't take an exit on a control transfer instruction itself,
   250      * which means the exit must have happened in the delay slot. So for these
   251      * cases, finalize the delay slot instruction, and re-execute the control transfer.
   252      *
   253      * For delay slots which modify the argument used in the branch instruction,
   254      * we pretty much just assume that that can't have already happened in an exit case.
   255      */
   257 %%
   258 BRA disp {: 
   259     sh4r.pc += 2; 
   260     sh4_finalize_instruction(); 
   261     sh4r.pc += disp;
   262 :}
   263 BRAF Rn {: 
   264     sh4r.pc += 2; 
   265     tmp = sh4r.r[Rn];
   266     sh4_finalize_instruction(); 
   267     sh4r.pc += tmp;
   268 :}
   269 BSR disp {: 
   270     /* Note: PR is already set */ 
   271     sh4r.pc += 2;
   272     sh4_finalize_instruction();
   273     sh4r.pc += disp;
   274 :}
   275 BSRF Rn {:
   276     /* Note: PR is already set */ 
   277     sh4r.pc += 2;
   278     tmp = sh4r.r[Rn];
   279     sh4_finalize_instruction();
   280     sh4r.pc += tmp;
   281 :}
   282 BF/S disp {: 
   283     sh4r.pc += 2;
   284     sh4_finalize_instruction();
   285     if( !sh4r.t ) {
   286         sh4r.pc += disp;
   287     }
   288 :}
   289 BT/S disp {: 
   290     sh4r.pc += 2;
   291     sh4_finalize_instruction();
   292     if( sh4r.t ) {
   293         sh4r.pc += disp;
   294     }
   295 :}
   296 JMP @Rn {:
   297     sh4r.pc += 2;
   298     tmp = sh4r.r[Rn];
   299     sh4_finalize_instruction();
   300     sh4r.pc = tmp;
   301     sh4r.new_pc = tmp + 2;
   302     sh4r.slice_cycle += sh4_cpu_period;
   303     return;
   304 :}
   305 JSR @Rn {: 
   306     /* Note: PR is already set */ 
   307     sh4r.pc += 2;
   308     tmp = sh4r.r[Rn];
   309     sh4_finalize_instruction();
   310     sh4r.pc = tmp;
   311     sh4r.new_pc = tmp + 2;
   312     sh4r.slice_cycle += sh4_cpu_period;
   313     return;
   314 :}
   315 RTS {: 
   316     sh4r.pc += 2;
   317     sh4_finalize_instruction();
   318     sh4r.pc = sh4r.pr;
   319     sh4r.new_pc = sh4r.pr + 2;
   320     sh4r.slice_cycle += sh4_cpu_period;
   321     return;
   322 :}
   323 RTE {: 
   324     /* SR is already set */
   325     sh4r.pc += 2;
   326     sh4_finalize_instruction();
   327     sh4r.pc = sh4r.spc;
   328     sh4r.new_pc = sh4r.pr + 2;
   329     sh4r.slice_cycle += sh4_cpu_period;
   330     return;
   331 :}
   332 MOV.B Rm, @-Rn {: sh4r.r[Rn]--; :}
   333 MOV.W Rm, @-Rn {: sh4r.r[Rn] -= 2; :}
   334 MOV.L Rm, @-Rn {: sh4r.r[Rn] -= 4; :}
   335 MOV.B @Rm+, Rn {: if( Rm != Rn ) { sh4r.r[Rm] ++;  } :}
   336 MOV.W @Rm+, Rn {: if( Rm != Rn ) { sh4r.r[Rm] += 2; } :}
   337 MOV.L @Rm+, Rn {: if( Rm != Rn ) { sh4r.r[Rm] += 4; } :}
   338 %%
   339     sh4r.in_delay_slot = 0;
   340     sh4r.pc += 2;
   341     sh4r.new_pc = sh4r.pc+2;
   342     sh4r.slice_cycle += sh4_cpu_period;
   343 }
   345 #undef UNDEF
   346 #undef UNIMP
   348 #define UNDEF(ir) return sh4_raise_slot_exception(EXC_ILLEGAL, EXC_SLOT_ILLEGAL)
   349 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); sh4_core_exit(CORE_EXIT_HALT); return FALSE; }while(0)
   352 gboolean sh4_execute_instruction( void )
   353 {
   354     uint32_t pc;
   355     unsigned short ir;
   356     uint32_t tmp;
   357     float ftmp;
   358     double dtmp;
   359     int64_t memtmp; // temporary holder for memory reads
   361     INIT_EXCEPTIONS(except)
   363 #define R0 sh4r.r[0]
   364     pc = sh4r.pc;
   365     if( pc > 0xFFFFFF00 ) {
   366 	/* SYSCALL Magic */
   367 	syscall_invoke( pc );
   368 	sh4r.in_delay_slot = 0;
   369 	pc = sh4r.pc = sh4r.pr;
   370 	sh4r.new_pc = sh4r.pc + 2;
   371         return TRUE;
   372     }
   373     CHECKRALIGN16(pc);
   375 #ifdef ENABLE_SH4STATS
   376     sh4_stats_add_by_pc(sh4r.pc);
   377 #endif
   379     /* Read instruction */
   380     if( !IS_IN_ICACHE(pc) ) {
   381         gboolean delay_slot = sh4r.in_delay_slot;
   382 	if( !mmu_update_icache(pc) ) {
   383 	    if( delay_slot ) {
   384 	        sh4r.spc -= 2;
   385 	    }
   386 	    // Fault - look for the fault handler
   387 	    if( !mmu_update_icache(sh4r.pc) ) {
   388 		// double fault - halt
   389 		ERROR( "Double fault - halting" );
   390 		sh4_core_exit(CORE_EXIT_HALT);
   391 		return FALSE;
   392 	    }
   393 	}
   394 	pc = sh4r.pc;
   395     }
   396     assert( IS_IN_ICACHE(pc) );
   397     ir = *(uint16_t *)GET_ICACHE_PTR(sh4r.pc);
   399     /* FIXME: This is a bit of a hack, but the PC of the delay slot should not
   400      * be visible until after the instruction has executed (for exception 
   401      * correctness)
   402      */
   403     if( sh4r.in_delay_slot ) {
   404     	sh4r.pc -= 2;
   405     }
   406 %%
   407 AND Rm, Rn {: sh4r.r[Rn] &= sh4r.r[Rm]; :}
   408 AND #imm, R0 {: R0 &= imm; :}
   409  AND.B #imm, @(R0, GBR) {: MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm & tmp ); :}
   410 NOT Rm, Rn {: sh4r.r[Rn] = ~sh4r.r[Rm]; :}
   411 OR Rm, Rn {: sh4r.r[Rn] |= sh4r.r[Rm]; :}
   412 OR #imm, R0  {: R0 |= imm; :}
   413  OR.B #imm, @(R0, GBR) {: MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm | tmp ); :}
   414 TAS.B @Rn {:
   415     MEM_READ_BYTE( sh4r.r[Rn], tmp );
   416     sh4r.t = ( tmp == 0 ? 1 : 0 );
   417     MEM_WRITE_BYTE( sh4r.r[Rn], tmp | 0x80 );
   418 :}
   419 TST Rm, Rn {: sh4r.t = (sh4r.r[Rn]&sh4r.r[Rm] ? 0 : 1); :}
   420 TST #imm, R0 {: sh4r.t = (R0 & imm ? 0 : 1); :}
   421  TST.B #imm, @(R0, GBR) {: MEM_READ_BYTE(R0+sh4r.gbr, tmp); sh4r.t = ( tmp & imm ? 0 : 1 ); :}
   422 XOR Rm, Rn {: sh4r.r[Rn] ^= sh4r.r[Rm]; :}
   423 XOR #imm, R0 {: R0 ^= imm; :}
   424  XOR.B #imm, @(R0, GBR) {: MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm ^ tmp ); :}
   425 XTRCT Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rn]>>16) | (sh4r.r[Rm]<<16); :}
   427 ROTL Rn {:
   428     sh4r.t = sh4r.r[Rn] >> 31;
   429     sh4r.r[Rn] <<= 1;
   430     sh4r.r[Rn] |= sh4r.t;
   431 :}
   432 ROTR Rn {:
   433     sh4r.t = sh4r.r[Rn] & 0x00000001;
   434     sh4r.r[Rn] >>= 1;
   435     sh4r.r[Rn] |= (sh4r.t << 31);
   436 :}
   437 ROTCL Rn {:
   438     tmp = sh4r.r[Rn] >> 31;
   439     sh4r.r[Rn] <<= 1;
   440     sh4r.r[Rn] |= sh4r.t;
   441     sh4r.t = tmp;
   442 :}
   443 ROTCR Rn {:
   444     tmp = sh4r.r[Rn] & 0x00000001;
   445     sh4r.r[Rn] >>= 1;
   446     sh4r.r[Rn] |= (sh4r.t << 31 );
   447     sh4r.t = tmp;
   448 :}
   449 SHAD Rm, Rn {:
   450     tmp = sh4r.r[Rm];
   451     if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
   452     else if( (tmp & 0x1F) == 0 )  
   453         sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 31;
   454     else 
   455 	sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> (((~sh4r.r[Rm]) & 0x1F)+1);
   456 :}
   457 SHLD Rm, Rn {:
   458     tmp = sh4r.r[Rm];
   459     if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
   460     else if( (tmp & 0x1F) == 0 ) sh4r.r[Rn] = 0;
   461     else sh4r.r[Rn] >>= (((~tmp) & 0x1F)+1);
   462 :}
   463 SHAL Rn {:
   464     sh4r.t = sh4r.r[Rn] >> 31;
   465     sh4r.r[Rn] <<= 1;
   466 :}
   467 SHAR Rn {:
   468     sh4r.t = sh4r.r[Rn] & 0x00000001;
   469     sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 1;
   470 :}
   471 SHLL Rn {: sh4r.t = sh4r.r[Rn] >> 31; sh4r.r[Rn] <<= 1; :}
   472 SHLR Rn {: sh4r.t = sh4r.r[Rn] & 0x00000001; sh4r.r[Rn] >>= 1; :}
   473 SHLL2 Rn {: sh4r.r[Rn] <<= 2; :}
   474 SHLR2 Rn {: sh4r.r[Rn] >>= 2; :}
   475 SHLL8 Rn {: sh4r.r[Rn] <<= 8; :}
   476 SHLR8 Rn {: sh4r.r[Rn] >>= 8; :}
   477 SHLL16 Rn {: sh4r.r[Rn] <<= 16; :}
   478 SHLR16 Rn {: sh4r.r[Rn] >>= 16; :}
   480 EXTU.B Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]&0x000000FF; :}
   481 EXTU.W Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]&0x0000FFFF; :}
   482 EXTS.B Rm, Rn {: sh4r.r[Rn] = SIGNEXT8( sh4r.r[Rm]&0x000000FF ); :}
   483 EXTS.W Rm, Rn {: sh4r.r[Rn] = SIGNEXT16( sh4r.r[Rm]&0x0000FFFF ); :}
   484 SWAP.B Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rm]&0xFFFF0000) | ((sh4r.r[Rm]&0x0000FF00)>>8) | ((sh4r.r[Rm]&0x000000FF)<<8); :}
   485 SWAP.W Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rm]>>16) | (sh4r.r[Rm]<<16); :}
   487 CLRT {: sh4r.t = 0; :}
   488 SETT {: sh4r.t = 1; :}
   489 CLRMAC {: sh4r.mac = 0; :}
   490 LDTLB {: MMU_ldtlb(); :}
   491 CLRS {: sh4r.s = 0; :}
   492 SETS {: sh4r.s = 1; :}
   493 MOVT Rn {: sh4r.r[Rn] = sh4r.t; :}
   494 NOP {: /* NOP */ :}
   496 PREF @Rn {:
   497     MEM_PREFETCH(sh4r.r[Rn]);
   498 :}
   499 OCBI @Rn {: :}
   500 OCBP @Rn {: :}
   501 OCBWB @Rn {: :}
   502 MOVCA.L R0, @Rn {:
   503     tmp = sh4r.r[Rn];
   504     CHECKWALIGN32(tmp);
   505     MEM_WRITE_LONG( tmp, R0 );
   506 :}
   507 MOV.B Rm, @(R0, Rn) {: MEM_WRITE_BYTE( R0 + sh4r.r[Rn], sh4r.r[Rm] ); :}
   508 MOV.W Rm, @(R0, Rn) {: 
   509     CHECKWALIGN16( R0 + sh4r.r[Rn] );
   510     MEM_WRITE_WORD( R0 + sh4r.r[Rn], sh4r.r[Rm] );
   511 :}
   512 MOV.L Rm, @(R0, Rn) {:
   513     CHECKWALIGN32( R0 + sh4r.r[Rn] );
   514     MEM_WRITE_LONG( R0 + sh4r.r[Rn], sh4r.r[Rm] );
   515 :}
   516 MOV.B @(R0, Rm), Rn {: MEM_READ_BYTE( R0 + sh4r.r[Rm], sh4r.r[Rn] ); :}
   517 MOV.W @(R0, Rm), Rn {: CHECKRALIGN16( R0 + sh4r.r[Rm] );
   518     MEM_READ_WORD( R0 + sh4r.r[Rm], sh4r.r[Rn] );
   519 :}
   520 MOV.L @(R0, Rm), Rn {: CHECKRALIGN32( R0 + sh4r.r[Rm] );
   521     MEM_READ_LONG( R0 + sh4r.r[Rm], sh4r.r[Rn] );
   522 :}
   523 MOV.L Rm, @(disp, Rn) {:
   524     tmp = sh4r.r[Rn] + disp;
   525     CHECKWALIGN32( tmp );
   526     MEM_WRITE_LONG( tmp, sh4r.r[Rm] );
   527 :}
   528 MOV.B Rm, @Rn {: MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] ); :}
   529 MOV.W Rm, @Rn {: CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] ); :}
   530 MOV.L Rm, @Rn {: CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] ); :}
   531  MOV.B Rm, @-Rn {: MEM_WRITE_BYTE( sh4r.r[Rn]-1, sh4r.r[Rm] ); sh4r.r[Rn]--; :}
   532  MOV.W Rm, @-Rn {: CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn]-2, sh4r.r[Rm] ); sh4r.r[Rn] -= 2; :}
   533  MOV.L Rm, @-Rn {: CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.r[Rm] ); sh4r.r[Rn] -= 4; :}
   534 MOV.L @(disp, Rm), Rn {:
   535     tmp = sh4r.r[Rm] + disp;
   536     CHECKRALIGN32( tmp );
   537     MEM_READ_LONG( tmp, sh4r.r[Rn] );
   538 :}
   539 MOV.B @Rm, Rn {: MEM_READ_BYTE( sh4r.r[Rm], sh4r.r[Rn] ); :}
   540  MOV.W @Rm, Rn {: CHECKRALIGN16( sh4r.r[Rm] ); MEM_READ_WORD( sh4r.r[Rm], sh4r.r[Rn] ); :}
   541  MOV.L @Rm, Rn {: CHECKRALIGN32( sh4r.r[Rm] ); MEM_READ_LONG( sh4r.r[Rm], sh4r.r[Rn] ); :}
   542 MOV Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]; :}
   543  MOV.B @Rm+, Rn {: MEM_READ_BYTE( sh4r.r[Rm], sh4r.r[Rn] ); if( Rm != Rn ) { sh4r.r[Rm] ++; } :}
   544  MOV.W @Rm+, Rn {: CHECKRALIGN16( sh4r.r[Rm] ); MEM_READ_WORD( sh4r.r[Rm], sh4r.r[Rn] ); if( Rm != Rn ) { sh4r.r[Rm] += 2; } :}
   545  MOV.L @Rm+, Rn {: CHECKRALIGN32( sh4r.r[Rm] ); MEM_READ_LONG( sh4r.r[Rm], sh4r.r[Rn] ); if( Rm != Rn ) { sh4r.r[Rm] += 4; } :}
   546 MOV.L @(disp, PC), Rn {:
   547     CHECKSLOTILLEGAL();
   548     tmp = (pc&0xFFFFFFFC) + disp + 4;
   549     MEM_READ_LONG( tmp, sh4r.r[Rn] );
   550 :}
   551 MOV.B R0, @(disp, GBR) {: MEM_WRITE_BYTE( sh4r.gbr + disp, R0 ); :}
   552 MOV.W R0, @(disp, GBR) {:
   553     tmp = sh4r.gbr + disp;
   554     CHECKWALIGN16( tmp );
   555     MEM_WRITE_WORD( tmp, R0 );
   556 :}
   557 MOV.L R0, @(disp, GBR) {:
   558     tmp = sh4r.gbr + disp;
   559     CHECKWALIGN32( tmp );
   560     MEM_WRITE_LONG( tmp, R0 );
   561 :}
   562  MOV.B @(disp, GBR), R0 {: MEM_READ_BYTE( sh4r.gbr + disp, R0 ); :}
   563 MOV.W @(disp, GBR), R0 {: 
   564     tmp = sh4r.gbr + disp;
   565     CHECKRALIGN16( tmp );
   566     MEM_READ_WORD( tmp, R0 );
   567 :}
   568 MOV.L @(disp, GBR), R0 {:
   569     tmp = sh4r.gbr + disp;
   570     CHECKRALIGN32( tmp );
   571     MEM_READ_LONG( tmp, R0 );
   572 :}
   573 MOV.B R0, @(disp, Rn) {: MEM_WRITE_BYTE( sh4r.r[Rn] + disp, R0 ); :}
   574 MOV.W R0, @(disp, Rn) {: 
   575     tmp = sh4r.r[Rn] + disp;
   576     CHECKWALIGN16( tmp );
   577     MEM_WRITE_WORD( tmp, R0 );
   578 :}
   579  MOV.B @(disp, Rm), R0 {: MEM_READ_BYTE( sh4r.r[Rm] + disp, R0 ); :}
   580 MOV.W @(disp, Rm), R0 {: 
   581     tmp = sh4r.r[Rm] + disp;
   582     CHECKRALIGN16( tmp );
   583     MEM_READ_WORD( tmp, R0 );
   584 :}
   585 MOV.W @(disp, PC), Rn {:
   586     CHECKSLOTILLEGAL();
   587     tmp = pc + 4 + disp;
   588     MEM_READ_WORD( tmp, sh4r.r[Rn] );
   589 :}
   590 MOVA @(disp, PC), R0 {:
   591     CHECKSLOTILLEGAL();
   592     R0 = (pc&0xFFFFFFFC) + disp + 4;
   593 :}
   594 MOV #imm, Rn {:  sh4r.r[Rn] = imm; :}
   596 FMOV @(R0, Rm), FRn {: MEM_FP_READ( sh4r.r[Rm] + R0, FRn ); :}
   597 FMOV FRm, @(R0, Rn) {: MEM_FP_WRITE( sh4r.r[Rn] + R0, FRm ); :}
   598 FMOV @Rm, FRn {: MEM_FP_READ( sh4r.r[Rm], FRn ); :}
   599 FMOV @Rm+, FRn {: MEM_FP_READ( sh4r.r[Rm], FRn ); sh4r.r[Rm] += FP_WIDTH; :}
   600 FMOV FRm, @Rn {: MEM_FP_WRITE( sh4r.r[Rn], FRm ); :}
   601  FMOV FRm, @-Rn {: MEM_FP_WRITE( sh4r.r[Rn] - FP_WIDTH, FRm ); sh4r.r[Rn] -= FP_WIDTH; :}
   602 FMOV FRm, FRn {: 
   603     if( IS_FPU_DOUBLESIZE() )
   604 	DR(FRn) = DR(FRm);
   605     else
   606 	FR(FRn) = FR(FRm);
   607 :}
   609 CMP/EQ #imm, R0 {: sh4r.t = ( R0 == imm ? 1 : 0 ); :}
   610 CMP/EQ Rm, Rn {: sh4r.t = ( sh4r.r[Rm] == sh4r.r[Rn] ? 1 : 0 ); :}
   611 CMP/GE Rm, Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= ((int32_t)sh4r.r[Rm]) ? 1 : 0 ); :}
   612 CMP/GT Rm, Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) > ((int32_t)sh4r.r[Rm]) ? 1 : 0 ); :}
   613 CMP/HI Rm, Rn {: sh4r.t = ( sh4r.r[Rn] > sh4r.r[Rm] ? 1 : 0 ); :}
   614 CMP/HS Rm, Rn {: sh4r.t = ( sh4r.r[Rn] >= sh4r.r[Rm] ? 1 : 0 ); :}
   615 CMP/PL Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) > 0 ? 1 : 0 ); :}
   616 CMP/PZ Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= 0 ? 1 : 0 ); :}
   617 CMP/STR Rm, Rn {: 
   618     /* set T = 1 if any byte in RM & RN is the same */
   619     tmp = sh4r.r[Rm] ^ sh4r.r[Rn];
   620     sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
   621              (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
   622 :}
   624 ADD Rm, Rn {: sh4r.r[Rn] += sh4r.r[Rm]; :}
   625 ADD #imm, Rn {: sh4r.r[Rn] += imm; :}
   626 ADDC Rm, Rn {:
   627     tmp = sh4r.r[Rn];
   628     sh4r.r[Rn] += sh4r.r[Rm] + sh4r.t;
   629     sh4r.t = ( sh4r.r[Rn] < tmp || (sh4r.r[Rn] == tmp && sh4r.t != 0) ? 1 : 0 );
   630 :}
   631 ADDV Rm, Rn {:
   632     tmp = sh4r.r[Rn] + sh4r.r[Rm];
   633     sh4r.t = ( (sh4r.r[Rn]>>31) == (sh4r.r[Rm]>>31) && ((sh4r.r[Rn]>>31) != (tmp>>31)) );
   634     sh4r.r[Rn] = tmp;
   635 :}
   636 DIV0U {: sh4r.m = sh4r.q = sh4r.t = 0; :}
   637 DIV0S Rm, Rn {: 
   638     sh4r.q = sh4r.r[Rn]>>31;
   639     sh4r.m = sh4r.r[Rm]>>31;
   640     sh4r.t = sh4r.q ^ sh4r.m;
   641 :}
   642 DIV1 Rm, Rn {:
   643     /* This is derived from the sh4 manual with some simplifications */
   644     uint32_t tmp0, tmp1, tmp2, dir;
   646     dir = sh4r.q ^ sh4r.m;
   647     sh4r.q = (sh4r.r[Rn] >> 31);
   648     tmp2 = sh4r.r[Rm];
   649     sh4r.r[Rn] = (sh4r.r[Rn] << 1) | sh4r.t;
   650     tmp0 = sh4r.r[Rn];
   651     if( dir ) {
   652          sh4r.r[Rn] += tmp2;
   653          tmp1 = (sh4r.r[Rn]<tmp0 ? 1 : 0 );
   654     } else {
   655          sh4r.r[Rn] -= tmp2;
   656          tmp1 = (sh4r.r[Rn]>tmp0 ? 1 : 0 );
   657     }
   658     sh4r.q ^= sh4r.m ^ tmp1;
   659     sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
   660 :}
   661 DMULS.L Rm, Rn {: sh4r.mac = SIGNEXT32(sh4r.r[Rm]) * SIGNEXT32(sh4r.r[Rn]); :}
   662 DMULU.L Rm, Rn {: sh4r.mac = ((uint64_t)sh4r.r[Rm]) * ((uint64_t)sh4r.r[Rn]); :}
   663 DT Rn {:
   664     sh4r.r[Rn] --;
   665     sh4r.t = ( sh4r.r[Rn] == 0 ? 1 : 0 );
   666 :}
   667 MAC.W @Rm+, @Rn+ {:
   668     int32_t stmp;
   669     if( Rm == Rn ) {
   670 	CHECKRALIGN16(sh4r.r[Rn]);
   671 	MEM_READ_WORD( sh4r.r[Rn], tmp );
   672 	stmp = SIGNEXT16(tmp);
   673 	MEM_READ_WORD( sh4r.r[Rn]+2, tmp );
   674 	stmp *= SIGNEXT16(tmp);
   675 	sh4r.r[Rn] += 4;
   676     } else {
   677 	CHECKRALIGN16( sh4r.r[Rn] );
   678 	CHECKRALIGN16( sh4r.r[Rm] );
   679 	MEM_READ_WORD(sh4r.r[Rn], tmp);
   680 	stmp = SIGNEXT16(tmp);
   681 	MEM_READ_WORD(sh4r.r[Rm], tmp);
   682 	stmp = stmp * SIGNEXT16(tmp);
   683 	sh4r.r[Rn] += 2;
   684 	sh4r.r[Rm] += 2;
   685     }
   686     if( sh4r.s ) {
   687 	int64_t tmpl = (int64_t)((int32_t)sh4r.mac) + (int64_t)stmp;
   688 	if( tmpl > (int64_t)0x000000007FFFFFFFLL ) {
   689 	    sh4r.mac = 0x000000017FFFFFFFLL;
   690 	} else if( tmpl < (int64_t)0xFFFFFFFF80000000LL ) {
   691 	    sh4r.mac = 0x0000000180000000LL;
   692 	} else {
   693 	    sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
   694 		((uint32_t)(sh4r.mac + stmp));
   695 	}
   696     } else {
   697 	sh4r.mac += SIGNEXT32(stmp);
   698     }
   699 :}
   700 MAC.L @Rm+, @Rn+ {:
   701     int64_t tmpl;
   702     if( Rm == Rn ) {
   703 	CHECKRALIGN32( sh4r.r[Rn] );
   704 	MEM_READ_LONG(sh4r.r[Rn], tmp);
   705 	tmpl = SIGNEXT32(tmp);
   706 	MEM_READ_LONG(sh4r.r[Rn]+4, tmp);
   707 	tmpl = tmpl * SIGNEXT32(tmp) + sh4r.mac;
   708 	sh4r.r[Rn] += 8;
   709     } else {
   710 	CHECKRALIGN32( sh4r.r[Rm] );
   711 	CHECKRALIGN32( sh4r.r[Rn] );
   712 	MEM_READ_LONG(sh4r.r[Rn], tmp);
   713 	tmpl = SIGNEXT32(tmp);
   714 	MEM_READ_LONG(sh4r.r[Rm], tmp);
   715 	tmpl = tmpl * SIGNEXT32(tmp) + sh4r.mac;
   716 	sh4r.r[Rn] += 4;
   717 	sh4r.r[Rm] += 4;
   718     }
   719     if( sh4r.s ) {
   720         /* 48-bit Saturation. Yuch */
   721         if( tmpl < (int64_t)0xFFFF800000000000LL )
   722             tmpl = 0xFFFF800000000000LL;
   723         else if( tmpl > (int64_t)0x00007FFFFFFFFFFFLL )
   724             tmpl = 0x00007FFFFFFFFFFFLL;
   725     }
   726     sh4r.mac = tmpl;
   727 :}
   728 MUL.L Rm, Rn {: sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   729                         (sh4r.r[Rm] * sh4r.r[Rn]); :}
   730 MULU.W Rm, Rn {:
   731     sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   732                (uint32_t)((sh4r.r[Rm]&0xFFFF) * (sh4r.r[Rn]&0xFFFF));
   733 :}
   734 MULS.W Rm, Rn {:
   735     sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   736                (uint32_t)(SIGNEXT32(sh4r.r[Rm]&0xFFFF) * SIGNEXT32(sh4r.r[Rn]&0xFFFF));
   737 :}
   738 NEGC Rm, Rn {:
   739     tmp = 0 - sh4r.r[Rm];
   740     sh4r.r[Rn] = tmp - sh4r.t;
   741     sh4r.t = ( 0<tmp || tmp<sh4r.r[Rn] ? 1 : 0 );
   742 :}
   743 NEG Rm, Rn {: sh4r.r[Rn] = 0 - sh4r.r[Rm]; :}
   744 SUB Rm, Rn {: sh4r.r[Rn] -= sh4r.r[Rm]; :}
   745 SUBC Rm, Rn {: 
   746     tmp = sh4r.r[Rn];
   747     sh4r.r[Rn] = sh4r.r[Rn] - sh4r.r[Rm] - sh4r.t;
   748     sh4r.t = (sh4r.r[Rn] > tmp || (sh4r.r[Rn] == tmp && sh4r.t == 1));
   749 :}
   751 BRAF Rn {:
   752      CHECKSLOTILLEGAL();
   753      CHECKDEST( pc + 4 + sh4r.r[Rn] );
   754      sh4r.in_delay_slot = 1;
   755      sh4r.pc = sh4r.new_pc;
   756      sh4r.new_pc = pc + 4 + sh4r.r[Rn];
   757      return TRUE;
   758 :}
   759 BSRF Rn {:
   760      CHECKSLOTILLEGAL();
   761      CHECKDEST( pc + 4 + sh4r.r[Rn] );
   762      sh4r.in_delay_slot = 1;
   763      sh4r.pr = sh4r.pc + 4;
   764      sh4r.pc = sh4r.new_pc;
   765      sh4r.new_pc = pc + 4 + sh4r.r[Rn];
   766      TRACE_CALL( pc, sh4r.new_pc );
   767      return TRUE;
   768 :}
   769 BT disp {:
   770     CHECKSLOTILLEGAL();
   771     if( sh4r.t ) {
   772         CHECKDEST( sh4r.pc + disp + 4 )
   773         sh4r.pc += disp + 4;
   774         sh4r.new_pc = sh4r.pc + 2;
   775         return TRUE;
   776     }
   777 :}
   778 BF disp {:
   779     CHECKSLOTILLEGAL();
   780     if( !sh4r.t ) {
   781         CHECKDEST( sh4r.pc + disp + 4 )
   782         sh4r.pc += disp + 4;
   783         sh4r.new_pc = sh4r.pc + 2;
   784         return TRUE;
   785     }
   786 :}
   787 BT/S disp {:
   788     CHECKSLOTILLEGAL();
   789     if( sh4r.t ) {
   790         CHECKDEST( sh4r.pc + disp + 4 )
   791         sh4r.in_delay_slot = 1;
   792         sh4r.pc = sh4r.new_pc;
   793         sh4r.new_pc = pc + disp + 4;
   794         sh4r.in_delay_slot = 1;
   795         return TRUE;
   796     }
   797 :}
   798 BF/S disp {:
   799     CHECKSLOTILLEGAL();
   800     if( !sh4r.t ) {
   801         CHECKDEST( sh4r.pc + disp + 4 )
   802         sh4r.in_delay_slot = 1;
   803         sh4r.pc = sh4r.new_pc;
   804         sh4r.new_pc = pc + disp + 4;
   805         return TRUE;
   806     }
   807 :}
   808 BRA disp {:
   809     CHECKSLOTILLEGAL();
   810     CHECKDEST( sh4r.pc + disp + 4 );
   811     sh4r.in_delay_slot = 1;
   812     sh4r.pc = sh4r.new_pc;
   813     sh4r.new_pc = pc + 4 + disp;
   814     return TRUE;
   815 :}
   816 BSR disp {:
   817     CHECKDEST( sh4r.pc + disp + 4 );
   818     CHECKSLOTILLEGAL();
   819     sh4r.in_delay_slot = 1;
   820     sh4r.pr = pc + 4;
   821     sh4r.pc = sh4r.new_pc;
   822     sh4r.new_pc = pc + 4 + disp;
   823     TRACE_CALL( pc, sh4r.new_pc );
   824     return TRUE;
   825 :}
   826 TRAPA #imm {:
   827     CHECKSLOTILLEGAL();
   828     sh4r.pc += 2;
   829     sh4_raise_trap( imm );
   830     return TRUE;
   831 :}
   832 RTS {: 
   833     CHECKSLOTILLEGAL();
   834     CHECKDEST( sh4r.pr );
   835     sh4r.in_delay_slot = 1;
   836     sh4r.pc = sh4r.new_pc;
   837     sh4r.new_pc = sh4r.pr;
   838     TRACE_RETURN( pc, sh4r.new_pc );
   839     return TRUE;
   840 :}
   841 SLEEP {:
   842     if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
   843 	sh4r.sh4_state = SH4_STATE_STANDBY;
   844     } else {
   845 	sh4r.sh4_state = SH4_STATE_SLEEP;
   846     }
   847     return FALSE; /* Halt CPU */
   848 :}
   849 RTE {:
   850     CHECKPRIV();
   851     CHECKDEST( sh4r.spc );
   852     CHECKSLOTILLEGAL();
   853     sh4r.in_delay_slot = 1;
   854     sh4r.pc = sh4r.new_pc;
   855     sh4r.new_pc = sh4r.spc;
   856     sh4_write_sr( sh4r.ssr );
   857     return TRUE;
   858 :}
   859 JMP @Rn {:
   860     CHECKDEST( sh4r.r[Rn] );
   861     CHECKSLOTILLEGAL();
   862     sh4r.in_delay_slot = 1;
   863     sh4r.pc = sh4r.new_pc;
   864     sh4r.new_pc = sh4r.r[Rn];
   865     return TRUE;
   866 :}
   867 JSR @Rn {:
   868     CHECKDEST( sh4r.r[Rn] );
   869     CHECKSLOTILLEGAL();
   870     sh4r.in_delay_slot = 1;
   871     sh4r.pc = sh4r.new_pc;
   872     sh4r.new_pc = sh4r.r[Rn];
   873     sh4r.pr = pc + 4;
   874     TRACE_CALL( pc, sh4r.new_pc );
   875     return TRUE;
   876 :}
   877 STS MACH, Rn {: sh4r.r[Rn] = (sh4r.mac>>32); :}
   878 STS.L MACH, @-Rn {:
   879     CHECKWALIGN32( sh4r.r[Rn] );
   880     MEM_WRITE_LONG( sh4r.r[Rn]-4, (sh4r.mac>>32) );
   881     sh4r.r[Rn] -= 4;
   882 :}
   883 STC.L SR, @-Rn {:
   884     CHECKPRIV();
   885     CHECKWALIGN32( sh4r.r[Rn] );
   886     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4_read_sr() );
   887     sh4r.r[Rn] -= 4;
   888 :}
   889 LDS.L @Rm+, MACH {:
   890     CHECKRALIGN32( sh4r.r[Rm] );
   891     MEM_READ_LONG(sh4r.r[Rm], tmp);
   892     sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
   893 	(((uint64_t)tmp)<<32);
   894     sh4r.r[Rm] += 4;
   895 :}
   896 LDC.L @Rm+, SR {:
   897     CHECKSLOTILLEGAL();
   898     CHECKPRIV();
   899     CHECKWALIGN32( sh4r.r[Rm] );
   900     MEM_READ_LONG(sh4r.r[Rm], tmp);
   901     sh4_write_sr( tmp );
   902     sh4r.r[Rm] +=4;
   903 :}
   904 LDS Rm, MACH {:
   905     sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
   906                (((uint64_t)sh4r.r[Rm])<<32);
   907 :}
   908 LDC Rm, SR {:
   909     CHECKSLOTILLEGAL();
   910     CHECKPRIV();
   911     sh4_write_sr( sh4r.r[Rm] );
   912 :}
   913 LDC Rm, SGR {:
   914     CHECKPRIV();
   915     sh4r.sgr = sh4r.r[Rm];
   916 :}
   917 LDC.L @Rm+, SGR {:
   918     CHECKPRIV();
   919     CHECKRALIGN32( sh4r.r[Rm] );
   920     MEM_READ_LONG(sh4r.r[Rm], sh4r.sgr);
   921     sh4r.r[Rm] +=4;
   922 :}
   923 STS MACL, Rn {: sh4r.r[Rn] = (uint32_t)sh4r.mac; :}
   924 STS.L MACL, @-Rn {:
   925     CHECKWALIGN32( sh4r.r[Rn] );
   926     MEM_WRITE_LONG( sh4r.r[Rn]-4, (uint32_t)sh4r.mac );
   927     sh4r.r[Rn] -= 4;
   928 :}
   929 STC.L GBR, @-Rn {:
   930     CHECKWALIGN32( sh4r.r[Rn] );
   931     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.gbr );
   932     sh4r.r[Rn] -= 4;
   933 :}
   934 LDS.L @Rm+, MACL {:
   935     CHECKRALIGN32( sh4r.r[Rm] );
   936     MEM_READ_LONG(sh4r.r[Rm], tmp);
   937     sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
   938                (uint64_t)((uint32_t)tmp);
   939     sh4r.r[Rm] += 4;
   940 :}
   941 LDC.L @Rm+, GBR {:
   942     CHECKRALIGN32( sh4r.r[Rm] );
   943     MEM_READ_LONG(sh4r.r[Rm], sh4r.gbr);
   944     sh4r.r[Rm] +=4;
   945 :}
   946 LDS Rm, MACL {:
   947     sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
   948                (uint64_t)((uint32_t)(sh4r.r[Rm]));
   949 :}
   950 LDC Rm, GBR {: sh4r.gbr = sh4r.r[Rm]; :}
   951 STS PR, Rn {: sh4r.r[Rn] = sh4r.pr; :}
   952 STS.L PR, @-Rn {:
   953     CHECKWALIGN32( sh4r.r[Rn] );
   954     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.pr );
   955     sh4r.r[Rn] -= 4;
   956 :}
   957 STC.L VBR, @-Rn {:
   958     CHECKPRIV();
   959     CHECKWALIGN32( sh4r.r[Rn] );
   960     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.vbr );
   961     sh4r.r[Rn] -= 4;
   962 :}
   963 LDS.L @Rm+, PR {:
   964     CHECKRALIGN32( sh4r.r[Rm] );
   965     MEM_READ_LONG( sh4r.r[Rm], sh4r.pr );
   966     sh4r.r[Rm] += 4;
   967 :}
   968 LDC.L @Rm+, VBR {:
   969     CHECKPRIV();
   970     CHECKRALIGN32( sh4r.r[Rm] );
   971     MEM_READ_LONG(sh4r.r[Rm], sh4r.vbr);
   972     sh4r.r[Rm] +=4;
   973 :}
   974 LDS Rm, PR {: sh4r.pr = sh4r.r[Rm]; :}
   975 LDC Rm, VBR {:
   976     CHECKPRIV();
   977     sh4r.vbr = sh4r.r[Rm];
   978 :}
   979 STC SGR, Rn {:
   980     CHECKPRIV();
   981     sh4r.r[Rn] = sh4r.sgr;
   982 :}
   983 STC.L SGR, @-Rn {:
   984     CHECKPRIV();
   985     CHECKWALIGN32( sh4r.r[Rn] );
   986     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.sgr );
   987     sh4r.r[Rn] -= 4;
   988 :}
   989 STC.L SSR, @-Rn {:
   990     CHECKPRIV();
   991     CHECKWALIGN32( sh4r.r[Rn] );
   992     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.ssr );
   993     sh4r.r[Rn] -= 4;
   994 :}
   995 LDC.L @Rm+, SSR {:
   996     CHECKPRIV();
   997     CHECKRALIGN32( sh4r.r[Rm] );
   998     MEM_READ_LONG(sh4r.r[Rm], sh4r.ssr);
   999     sh4r.r[Rm] +=4;
  1000 :}
  1001 LDC Rm, SSR {:
  1002     CHECKPRIV();
  1003     sh4r.ssr = sh4r.r[Rm];
  1004 :}
  1005 STC.L SPC, @-Rn {:
  1006     CHECKPRIV();
  1007     CHECKWALIGN32( sh4r.r[Rn] );
  1008     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.spc );
  1009     sh4r.r[Rn] -= 4;
  1010 :}
  1011 LDC.L @Rm+, SPC {:
  1012     CHECKPRIV();
  1013     CHECKRALIGN32( sh4r.r[Rm] );
  1014     MEM_READ_LONG(sh4r.r[Rm], sh4r.spc);
  1015     sh4r.r[Rm] +=4;
  1016 :}
  1017 LDC Rm, SPC {:
  1018     CHECKPRIV();
  1019     sh4r.spc = sh4r.r[Rm];
  1020 :}
  1021 STS FPUL, Rn {: 
  1022     CHECKFPUEN();
  1023     sh4r.r[Rn] = FPULi; 
  1024 :}
  1025 STS.L FPUL, @-Rn {:
  1026     CHECKFPUEN();
  1027     CHECKWALIGN32( sh4r.r[Rn] );
  1028     MEM_WRITE_LONG( sh4r.r[Rn]-4, FPULi );
  1029     sh4r.r[Rn] -= 4;
  1030 :}
  1031 LDS.L @Rm+, FPUL {:
  1032     CHECKFPUEN();
  1033     CHECKRALIGN32( sh4r.r[Rm] );
  1034     MEM_READ_LONG(sh4r.r[Rm], FPULi);
  1035     sh4r.r[Rm] +=4;
  1036 :}
  1037 LDS Rm, FPUL {:
  1038     CHECKFPUEN();
  1039     FPULi = sh4r.r[Rm]; 
  1040 :}
  1041 STS FPSCR, Rn {: 
  1042     CHECKFPUEN();
  1043     sh4r.r[Rn] = sh4r.fpscr; 
  1044 :}
  1045 STS.L FPSCR, @-Rn {:
  1046     CHECKFPUEN();
  1047     CHECKWALIGN32( sh4r.r[Rn] );
  1048     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.fpscr );
  1049     sh4r.r[Rn] -= 4;
  1050 :}
  1051 LDS.L @Rm+, FPSCR {:
  1052     CHECKFPUEN();
  1053     CHECKRALIGN32( sh4r.r[Rm] );
  1054     MEM_READ_LONG(sh4r.r[Rm], tmp);
  1055     sh4r.r[Rm] +=4;
  1056     sh4_write_fpscr( tmp );
  1057 :}
  1058 LDS Rm, FPSCR {: 
  1059     CHECKFPUEN();
  1060     sh4_write_fpscr( sh4r.r[Rm] );
  1061 :}
  1062 STC DBR, Rn {: CHECKPRIV(); sh4r.r[Rn] = sh4r.dbr; :}
  1063 STC.L DBR, @-Rn {:
  1064     CHECKPRIV();
  1065     CHECKWALIGN32( sh4r.r[Rn] );
  1066     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.dbr );
  1067     sh4r.r[Rn] -= 4;
  1068 :}
  1069 LDC.L @Rm+, DBR {:
  1070     CHECKPRIV();
  1071     CHECKRALIGN32( sh4r.r[Rm] );
  1072     MEM_READ_LONG(sh4r.r[Rm], sh4r.dbr);
  1073     sh4r.r[Rm] +=4;
  1074 :}
  1075 LDC Rm, DBR {:
  1076     CHECKPRIV();
  1077     sh4r.dbr = sh4r.r[Rm];
  1078 :}
  1079 STC.L Rm_BANK, @-Rn {:
  1080     CHECKPRIV();
  1081     CHECKWALIGN32( sh4r.r[Rn] );
  1082     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.r_bank[Rm_BANK] );
  1083     sh4r.r[Rn] -= 4;
  1084 :}
  1085 LDC.L @Rm+, Rn_BANK {:
  1086     CHECKPRIV();
  1087     CHECKRALIGN32( sh4r.r[Rm] );
  1088     MEM_READ_LONG( sh4r.r[Rm], sh4r.r_bank[Rn_BANK] );
  1089     sh4r.r[Rm] += 4;
  1090 :}
  1091 LDC Rm, Rn_BANK {:
  1092     CHECKPRIV();
  1093     sh4r.r_bank[Rn_BANK] = sh4r.r[Rm];
  1094 :}
  1095 STC SR, Rn {: 
  1096     CHECKPRIV();
  1097     sh4r.r[Rn] = sh4_read_sr();
  1098 :}
  1099 STC GBR, Rn {:
  1100     sh4r.r[Rn] = sh4r.gbr;
  1101 :}
  1102 STC VBR, Rn {:
  1103     CHECKPRIV();
  1104     sh4r.r[Rn] = sh4r.vbr;
  1105 :}
  1106 STC SSR, Rn {:
  1107     CHECKPRIV();
  1108     sh4r.r[Rn] = sh4r.ssr;
  1109 :}
  1110 STC SPC, Rn {:
  1111     CHECKPRIV();
  1112     sh4r.r[Rn] = sh4r.spc;
  1113 :}
  1114 STC Rm_BANK, Rn {:
  1115     CHECKPRIV();
  1116     sh4r.r[Rn] = sh4r.r_bank[Rm_BANK];
  1117 :}
  1119 FADD FRm, FRn {:
  1120     CHECKFPUEN();
  1121     if( IS_FPU_DOUBLEPREC() ) {
  1122 	DR(FRn) += DR(FRm);
  1123     } else {
  1124 	FR(FRn) += FR(FRm);
  1126 :}
  1127 FSUB FRm, FRn {:
  1128     CHECKFPUEN();
  1129     if( IS_FPU_DOUBLEPREC() ) {
  1130 	DR(FRn) -= DR(FRm);
  1131     } else {
  1132 	FR(FRn) -= FR(FRm);
  1134 :}
  1136 FMUL FRm, FRn {:
  1137     CHECKFPUEN();
  1138     if( IS_FPU_DOUBLEPREC() ) {
  1139 	DR(FRn) *= DR(FRm);
  1140     } else {
  1141 	FR(FRn) *= FR(FRm);
  1143 :}
  1145 FDIV FRm, FRn {:
  1146     CHECKFPUEN();
  1147     if( IS_FPU_DOUBLEPREC() ) {
  1148 	DR(FRn) /= DR(FRm);
  1149     } else {
  1150 	FR(FRn) /= FR(FRm);
  1152 :}
  1154 FCMP/EQ FRm, FRn {:
  1155     CHECKFPUEN();
  1156     if( IS_FPU_DOUBLEPREC() ) {
  1157 	sh4r.t = ( DR(FRn) == DR(FRm) ? 1 : 0 );
  1158     } else {
  1159 	sh4r.t = ( FR(FRn) == FR(FRm) ? 1 : 0 );
  1161 :}
  1163 FCMP/GT FRm, FRn {:
  1164     CHECKFPUEN();
  1165     if( IS_FPU_DOUBLEPREC() ) {
  1166 	sh4r.t = ( DR(FRn) > DR(FRm) ? 1 : 0 );
  1167     } else {
  1168 	sh4r.t = ( FR(FRn) > FR(FRm) ? 1 : 0 );
  1170 :}
  1172 FSTS FPUL, FRn {: CHECKFPUEN(); FR(FRn) = FPULf; :}
  1173 FLDS FRm, FPUL {: CHECKFPUEN(); FPULf = FR(FRm); :}
  1174 FLOAT FPUL, FRn {: 
  1175     CHECKFPUEN();
  1176     if( IS_FPU_DOUBLEPREC() ) {
  1177 	if( FRn&1 ) { // No, really...
  1178 	    dtmp = (double)FPULi;
  1179 	    FR(FRn) = *(((float *)&dtmp)+1);
  1180 	} else {
  1181 	    DRF(FRn>>1) = (double)FPULi;
  1183     } else {
  1184 	FR(FRn) = (float)FPULi;
  1186 :}
  1187 FTRC FRm, FPUL {:
  1188     CHECKFPUEN();
  1189     if( IS_FPU_DOUBLEPREC() ) {
  1190 	if( FRm&1 ) {
  1191 	    dtmp = 0;
  1192 	    *(((float *)&dtmp)+1) = FR(FRm);
  1193 	} else {
  1194 	    dtmp = DRF(FRm>>1);
  1196         if( dtmp >= MAX_INTF )
  1197             FPULi = MAX_INT;
  1198         else if( dtmp <= MIN_INTF )
  1199             FPULi = MIN_INT;
  1200         else 
  1201             FPULi = (int32_t)dtmp;
  1202     } else {
  1203 	ftmp = FR(FRm);
  1204 	if( ftmp >= MAX_INTF )
  1205 	    FPULi = MAX_INT;
  1206 	else if( ftmp <= MIN_INTF )
  1207 	    FPULi = MIN_INT;
  1208 	else
  1209 	    FPULi = (int32_t)ftmp;
  1211 :}
  1212 FNEG FRn {:
  1213     CHECKFPUEN();
  1214     if( IS_FPU_DOUBLEPREC() ) {
  1215 	DR(FRn) = -DR(FRn);
  1216     } else {
  1217         FR(FRn) = -FR(FRn);
  1219 :}
  1220 FABS FRn {:
  1221     CHECKFPUEN();
  1222     if( IS_FPU_DOUBLEPREC() ) {
  1223 	DR(FRn) = fabs(DR(FRn));
  1224     } else {
  1225         FR(FRn) = fabsf(FR(FRn));
  1227 :}
  1228 FSQRT FRn {:
  1229     CHECKFPUEN();
  1230     if( IS_FPU_DOUBLEPREC() ) {
  1231 	DR(FRn) = sqrt(DR(FRn));
  1232     } else {
  1233         FR(FRn) = sqrtf(FR(FRn));
  1235 :}
  1236 FLDI0 FRn {:
  1237     CHECKFPUEN();
  1238     if( IS_FPU_DOUBLEPREC() ) {
  1239 	DR(FRn) = 0.0;
  1240     } else {
  1241         FR(FRn) = 0.0;
  1243 :}
  1244 FLDI1 FRn {:
  1245     CHECKFPUEN();
  1246     if( IS_FPU_DOUBLEPREC() ) {
  1247 	DR(FRn) = 1.0;
  1248     } else {
  1249         FR(FRn) = 1.0;
  1251 :}
  1252 FMAC FR0, FRm, FRn {:
  1253     CHECKFPUEN();
  1254     if( IS_FPU_DOUBLEPREC() ) {
  1255         DR(FRn) += DR(FRm)*DR(0);
  1256     } else {
  1257 	FR(FRn) += FR(FRm)*FR(0);
  1259 :}
  1260 FRCHG {: 
  1261     CHECKFPUEN(); 
  1262     sh4r.fpscr ^= FPSCR_FR; 
  1263     sh4_switch_fr_banks();
  1264 :}
  1265 FSCHG {: CHECKFPUEN(); sh4r.fpscr ^= FPSCR_SZ; :}
  1266 FCNVSD FPUL, FRn {:
  1267     CHECKFPUEN();
  1268     if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
  1269 	DR(FRn) = (double)FPULf;
  1271 :}
  1272 FCNVDS FRm, FPUL {:
  1273     CHECKFPUEN();
  1274     if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
  1275 	FPULf = (float)DR(FRm);
  1277 :}
  1279 FSRRA FRn {:
  1280     CHECKFPUEN();
  1281     if( !IS_FPU_DOUBLEPREC() ) {
  1282 	FR(FRn) = 1.0/sqrtf(FR(FRn));
  1284 :}
  1285 FIPR FVm, FVn {:
  1286     CHECKFPUEN();
  1287     if( !IS_FPU_DOUBLEPREC() ) {
  1288         int tmp2 = FVn<<2;
  1289         tmp = FVm<<2;
  1290         FR(tmp2+3) = FR(tmp)*FR(tmp2) +
  1291             FR(tmp+1)*FR(tmp2+1) +
  1292             FR(tmp+2)*FR(tmp2+2) +
  1293             FR(tmp+3)*FR(tmp2+3);
  1295 :}
  1296 FSCA FPUL, FRn {:
  1297     CHECKFPUEN();
  1298     if( !IS_FPU_DOUBLEPREC() ) {
  1299 	sh4_fsca( FPULi, (float *)&(DRF(FRn>>1)) );
  1301 :}
  1302 FTRV XMTRX, FVn {:
  1303     CHECKFPUEN();
  1304     if( !IS_FPU_DOUBLEPREC() ) {
  1305 	sh4_ftrv((float *)&(DRF(FVn<<1)) );
  1307 :}
  1308 UNDEF {:
  1309     UNDEF(ir);
  1310 :}
  1311 %%
  1312     sh4r.pc = sh4r.new_pc;
  1313     sh4r.new_pc += 2;
  1315 except:
  1316     sh4r.in_delay_slot = 0;
  1317     return TRUE;
.