lxdream 0.9.1| filename | test/sh4/tlb.s |
| changeset | 1065:bc1cc0c54917 |
| prev | 976:e57a25d9eb7d |
| prev | 555:309c97260912 |
| author | nkeynes |
| date | Sun Jul 05 13:52:50 2009 +1000 (14 years ago) |
| permissions | -rw-r--r-- |
| last change | No-op merge lxdream-mmu to remove head (actually merged long ago) |
| view | annotate | diff | log | raw |
1 .section .text
2 .include "sh4/inc.s"
3 !
4 ! Test for correct UTLB operation.
5 !
6 ! Note we don't test triggering a TLB multiple-hit exception - it's a reset
7 ! rather than a regular exception.
9 .global _test_tlb
10 _test_tlb:
11 start_test
13 ! Turn on AT, and flush the current TLB (if any)
14 ! Initialize to SV=0, SQMD=0, URB=URC=LRUI=0
15 mov.l test_tlb_mmucr, r0
16 mov #5, r1
17 mov.l r1, @r0
19 ! Privileged mode tests first (much easier)
20 add #1, r12
21 mov.l test_tlb1_pteh, r1
22 mov.l test_tlb_pteh, r2
23 mov.l r1, @r2
24 mov.l test_tlb1_ptel, r1
25 mov.l test_tlb_ptel, r2
26 mov.l r1, @r2
27 ldtlb
29 ! Simple read
30 mov.l test_tlb1_direct, r3
31 mov #42, r2
32 mov.l r2, @r3
33 mov.l test_tlb1_mmu, r0
34 mov.l @r0, r1
35 cmp/eq r1, r2
36 bt test_tlb_2
37 fail test_tlb_str_k
38 bra test_tlb_2
39 nop
40 test_tlb1_pteh:
41 .long 0x12345012
42 test_tlb1_ptel:
43 .long 0x005F8120
45 test_tlb_2:
46 ! Trigger an initial-page-write exception
47 add #1, r12
48 expect_exc 0x00000080
49 mov.l test_tlb1_mmu, r0
50 test_tlb2_exc:
51 mov.l r0, @r0
52 assert_tlb_exc_caught test_tlb_str_k test_tlb2_exc test_tlb1_mmu
54 test_tlb_3:
55 ! Trigger a missing page read exception by invalidation
56 add #1, r12
57 mov.l test_tlb3_addr, r1
58 mov.l test_tlb3_data, r2
59 mov.l r2, @r1
61 expect_exc 0x00000040
62 mov.l test_tlb1_mmu, r0
63 test_tlb3_exc:
64 mov.l @r0, r2
65 assert_tlb_exc_caught test_tlb_str_k, test_tlb3_exc, test_tlb1_mmu
66 bra test_tlb_4
67 nop
69 test_tlb3_addr:
70 .long 0xF6000F80
71 test_tlb3_data:
72 .long 0x12345212
74 test_tlb_4:
75 ! Test missing page write exception on the same page
76 add #1, r12
77 expect_exc 0x00000060
78 mov.l test_tlb1_mmu, r0
79 test_tlb4_exc:
80 mov.l r2, @r0
81 assert_tlb_exc_caught test_tlb_str_k, test_tlb4_exc, test_tlb1_mmu
83 test_tlb_5: ! Test initial write exception
84 add #1, r12
86 mov.l test_tlb5_addr, r1
87 mov.l test_tlb5_data, r2
88 mov.l r2, @r1
90 expect_exc 0x00000080
91 mov.l test_tlb1_mmu, r0
92 mov #63, r3
93 test_tlb5_exc:
94 mov.l r3, @r0
95 assert_tlb_exc_caught test_tlb_str_k, test_tlb5_exc, test_tlb1_mmu
96 mov.l test_tlb1_direct, r3
97 mov.l @r3, r4
98 mov #42, r2
99 cmp/eq r2, r4
100 bf test_tlb5_fail
101 mov.l test_tlb1_mmu, r0
102 mov.l @r0, r3
103 cmp/eq r2, r3
104 bt test_tlb_6
105 test_tlb5_fail:
106 fail test_tlb_str_k
107 bra test_tlb_6
108 nop
110 test_tlb5_addr:
111 .long 0xF6000000
112 test_tlb5_data:
113 .long 0x12345112
115 test_tlb_6:! Test successful write.
116 add #1, r12
118 mov.l test_tlb6_addr, r1
119 mov.l test_tlb6_data, r2
120 mov.l r2, @r1
122 mov.l test_tlb1_mmu, r0
123 mov #77, r3
124 mov.l r3, @r0
125 mov.l test_tlb1_direct, r1
126 mov.l @r1, r2
127 cmp/eq r2, r3
128 bt test_tlb_7
129 fail test_tlb_str_k
130 bra test_tlb_7
131 nop
133 test_tlb_7:
134 bra test_tlb_end
135 nop
137 test_tlb6_addr:
138 .long 0xF6000F80
139 test_tlb6_data:
140 .long 0x12345312
143 test_tlb1_mmu:
144 .long 0x12345040
145 test_tlb1_direct:
146 .long 0xA05F8040 ! Display border colour
148 test_tlb_end:
149 xor r0, r0
150 mov.l test_tlb_mmucr, r1
151 mov.l r0, @r1
153 end_test test_tlb_str_k
155 test_tlb_mmucr:
156 .long 0xFF000010
157 test_tlb_pteh:
158 .long 0xFF000000
159 test_tlb_ptel:
160 .long 0xFF000004
161 test_tlb_tea:
162 .long 0xFF00000C
163 test_tlb_str:
164 .string "TLB"
165 .align 4
166 test_tlb_str_k:
167 .long test_tlb_str
.