lxdream 0.9.1| filename | src/sh4/sh4core.c |
| changeset | 181:bc28fd93e233 |
| prev | 164:84f6b203cfe1 |
| next | 208:ad290228eea1 |
| author | nkeynes |
| date | Thu Jul 06 08:46:41 2006 +0000 (14 years ago) |
| permissions | -rw-r--r-- |
| last change | FSCA, FSRRA, FIPR, FTRV should be treated as no-ops when PR=1. At least according to the hardware |
| view | annotate | diff | log | raw |
1 /**
2 * $Id: sh4core.c,v 1.29 2006-07-06 08:46:41 nkeynes Exp $
3 *
4 * SH4 emulation core, and parent module for all the SH4 peripheral
5 * modules.
6 *
7 * Copyright (c) 2005 Nathan Keynes.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
20 #define MODULE sh4_module
21 #include <math.h>
22 #include "dream.h"
23 #include "sh4/sh4core.h"
24 #include "sh4/sh4mmio.h"
25 #include "sh4/intc.h"
26 #include "mem.h"
27 #include "clock.h"
28 #include "syscall.h"
30 #define SH4_CALLTRACE 1
32 #define MAX_INT 0x7FFFFFFF
33 #define MIN_INT 0x80000000
34 #define MAX_INTF 2147483647.0
35 #define MIN_INTF -2147483648.0
37 /* CPU-generated exception code/vector pairs */
38 #define EXC_POWER_RESET 0x000 /* vector special */
39 #define EXC_MANUAL_RESET 0x020
40 #define EXC_SLOT_ILLEGAL 0x1A0
41 #define EXC_ILLEGAL 0x180
42 #define EXV_ILLEGAL 0x100
43 #define EXC_TRAP 0x160
44 #define EXV_TRAP 0x100
45 #define EXC_FPDISABLE 0x800
46 #define EXV_FPDISABLE 0x100
48 /********************** SH4 Module Definition ****************************/
50 void sh4_init( void );
51 void sh4_reset( void );
52 uint32_t sh4_run_slice( uint32_t );
53 void sh4_start( void );
54 void sh4_stop( void );
55 void sh4_save_state( FILE *f );
56 int sh4_load_state( FILE *f );
58 struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset,
59 NULL, sh4_run_slice, sh4_stop,
60 sh4_save_state, sh4_load_state };
62 struct sh4_registers sh4r;
64 void sh4_init(void)
65 {
66 register_io_regions( mmio_list_sh4mmio );
67 mmu_init();
68 sh4_reset();
69 }
71 void sh4_reset(void)
72 {
73 /* zero everything out, for the sake of having a consistent state. */
74 memset( &sh4r, 0, sizeof(sh4r) );
76 /* Resume running if we were halted */
77 sh4r.sh4_state = SH4_STATE_RUNNING;
79 sh4r.pc = 0xA0000000;
80 sh4r.new_pc= 0xA0000002;
81 sh4r.vbr = 0x00000000;
82 sh4r.fpscr = 0x00040001;
83 sh4r.sr = 0x700000F0;
85 /* Mem reset will do this, but if we want to reset _just_ the SH4... */
86 MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
88 /* Peripheral modules */
89 INTC_reset();
90 TMU_reset();
91 SCIF_reset();
92 }
94 static struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
95 static int sh4_breakpoint_count = 0;
97 void sh4_set_breakpoint( uint32_t pc, int type )
98 {
99 sh4_breakpoints[sh4_breakpoint_count].address = pc;
100 sh4_breakpoints[sh4_breakpoint_count].type = type;
101 sh4_breakpoint_count++;
102 }
104 gboolean sh4_clear_breakpoint( uint32_t pc, int type )
105 {
106 int i;
108 for( i=0; i<sh4_breakpoint_count; i++ ) {
109 if( sh4_breakpoints[i].address == pc &&
110 sh4_breakpoints[i].type == type ) {
111 while( ++i < sh4_breakpoint_count ) {
112 sh4_breakpoints[i-1].address = sh4_breakpoints[i].address;
113 sh4_breakpoints[i-1].type = sh4_breakpoints[i].type;
114 }
115 sh4_breakpoint_count--;
116 return TRUE;
117 }
118 }
119 return FALSE;
120 }
122 int sh4_get_breakpoint( uint32_t pc )
123 {
124 int i;
125 for( i=0; i<sh4_breakpoint_count; i++ ) {
126 if( sh4_breakpoints[i].address == pc )
127 return sh4_breakpoints[i].type;
128 }
129 return 0;
130 }
132 uint32_t sh4_run_slice( uint32_t nanosecs )
133 {
134 int target = sh4r.icount + nanosecs / sh4_cpu_period;
135 int start = sh4r.icount;
136 int i;
138 if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
139 if( sh4r.int_pending != 0 )
140 sh4r.sh4_state = SH4_STATE_RUNNING;;
141 }
143 for( sh4r.slice_cycle = 0; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
144 if( !sh4_execute_instruction() )
145 break;
146 #ifdef ENABLE_DEBUG_MODE
147 for( i=0; i<sh4_breakpoint_count; i++ ) {
148 if( sh4_breakpoints[i].address == sh4r.pc ) {
149 break;
150 }
151 }
152 if( i != sh4_breakpoint_count ) {
153 dreamcast_stop();
154 if( sh4_breakpoints[i].type == BREAK_ONESHOT )
155 sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );
156 break;
157 }
158 #endif
159 }
161 /* If we aborted early, but the cpu is still technically running,
162 * we're doing a hard abort - cut the timeslice back to what we
163 * actually executed
164 */
165 if( sh4r.slice_cycle != nanosecs && sh4r.sh4_state == SH4_STATE_RUNNING ) {
166 nanosecs = sh4r.slice_cycle;
167 }
168 if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
169 TMU_run_slice( nanosecs );
170 SCIF_run_slice( nanosecs );
171 }
172 sh4r.icount += sh4r.slice_cycle / sh4_cpu_period;
173 return nanosecs;
174 }
176 void sh4_stop(void)
177 {
179 }
181 void sh4_save_state( FILE *f )
182 {
183 fwrite( &sh4r, sizeof(sh4r), 1, f );
184 INTC_save_state( f );
185 TMU_save_state( f );
186 SCIF_save_state( f );
187 }
189 int sh4_load_state( FILE * f )
190 {
191 fread( &sh4r, sizeof(sh4r), 1, f );
192 INTC_load_state( f );
193 TMU_load_state( f );
194 return SCIF_load_state( f );
195 }
197 /********************** SH4 emulation core ****************************/
199 void sh4_set_pc( int pc )
200 {
201 sh4r.pc = pc;
202 sh4r.new_pc = pc+2;
203 }
205 #define UNDEF(ir) do{ ERROR( "Raising exception on undefined instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)
206 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)
208 #if(SH4_CALLTRACE == 1)
209 #define MAX_CALLSTACK 32
210 static struct call_stack {
211 sh4addr_t call_addr;
212 sh4addr_t target_addr;
213 sh4addr_t stack_pointer;
214 } call_stack[MAX_CALLSTACK];
216 static int call_stack_depth = 0;
217 int sh4_call_trace_on = 0;
219 static inline trace_call( sh4addr_t source, sh4addr_t dest )
220 {
221 if( call_stack_depth < MAX_CALLSTACK ) {
222 call_stack[call_stack_depth].call_addr = source;
223 call_stack[call_stack_depth].target_addr = dest;
224 call_stack[call_stack_depth].stack_pointer = sh4r.r[15];
225 }
226 call_stack_depth++;
227 }
229 static inline trace_return( sh4addr_t source, sh4addr_t dest )
230 {
231 if( call_stack_depth > 0 ) {
232 call_stack_depth--;
233 }
234 }
236 void fprint_stack_trace( FILE *f )
237 {
238 int i = call_stack_depth -1;
239 if( i >= MAX_CALLSTACK )
240 i = MAX_CALLSTACK - 1;
241 for( ; i >= 0; i-- ) {
242 fprintf( f, "%d. Call from %08X => %08X, SP=%08X\n",
243 (call_stack_depth - i), call_stack[i].call_addr,
244 call_stack[i].target_addr, call_stack[i].stack_pointer );
245 }
246 }
248 #define TRACE_CALL( source, dest ) trace_call(source, dest)
249 #define TRACE_RETURN( source, dest ) trace_return(source, dest)
250 #else
251 #define TRACE_CALL( dest, rts )
252 #define TRACE_RETURN( source, dest )
253 #endif
255 #define RAISE( x, v ) do{ \
256 if( sh4r.vbr == 0 ) { \
257 ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
258 dreamcast_stop(); return FALSE; \
259 } else { \
260 sh4r.spc = sh4r.pc + 2; \
261 sh4r.ssr = sh4_read_sr(); \
262 sh4r.sgr = sh4r.r[15]; \
263 MMIO_WRITE(MMU,EXPEVT,x); \
264 sh4r.pc = sh4r.vbr + v; \
265 sh4r.new_pc = sh4r.pc + 2; \
266 sh4_load_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
267 } \
268 return TRUE; } while(0)
270 #define MEM_READ_BYTE( addr ) sh4_read_byte(addr)
271 #define MEM_READ_WORD( addr ) sh4_read_word(addr)
272 #define MEM_READ_LONG( addr ) sh4_read_long(addr)
273 #define MEM_WRITE_BYTE( addr, val ) sh4_write_byte(addr, val)
274 #define MEM_WRITE_WORD( addr, val ) sh4_write_word(addr, val)
275 #define MEM_WRITE_LONG( addr, val ) sh4_write_long(addr, val)
277 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
279 #define MEM_FP_READ( addr, reg ) sh4_read_float( addr, reg );
281 #define MEM_FP_WRITE( addr, reg ) sh4_write_float( addr, reg );
283 #define CHECK( x, c, v ) if( !x ) RAISE( c, v )
284 #define CHECKPRIV() CHECK( IS_SH4_PRIVMODE(), EXC_ILLEGAL, EXV_ILLEGAL )
285 #define CHECKFPUEN() CHECK( IS_FPU_ENABLED(), EXC_FPDISABLE, EXV_FPDISABLE )
286 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); dreamcast_stop(); return FALSE; }
287 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) { RAISE(EXC_SLOT_ILLEGAL,EXV_ILLEGAL); }
289 static void sh4_switch_banks( )
290 {
291 uint32_t tmp[8];
293 memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
294 memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
295 memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
296 }
298 static void sh4_load_sr( uint32_t newval )
299 {
300 if( (newval ^ sh4r.sr) & SR_RB )
301 sh4_switch_banks();
302 sh4r.sr = newval;
303 sh4r.t = (newval&SR_T) ? 1 : 0;
304 sh4r.s = (newval&SR_S) ? 1 : 0;
305 sh4r.m = (newval&SR_M) ? 1 : 0;
306 sh4r.q = (newval&SR_Q) ? 1 : 0;
307 intc_mask_changed();
308 }
310 static void sh4_write_float( uint32_t addr, int reg )
311 {
312 if( IS_FPU_DOUBLESIZE() ) {
313 if( reg & 1 ) {
314 sh4_write_long( addr, *((uint32_t *)&XF((reg)&0x0E)) );
315 sh4_write_long( addr+4, *((uint32_t *)&XF(reg)) );
316 } else {
317 sh4_write_long( addr, *((uint32_t *)&FR(reg)) );
318 sh4_write_long( addr+4, *((uint32_t *)&FR((reg)|0x01)) );
319 }
320 } else {
321 sh4_write_long( addr, *((uint32_t *)&FR((reg))) );
322 }
323 }
325 static void sh4_read_float( uint32_t addr, int reg )
326 {
327 if( IS_FPU_DOUBLESIZE() ) {
328 if( reg & 1 ) {
329 *((uint32_t *)&XF((reg) & 0x0E)) = sh4_read_long(addr);
330 *((uint32_t *)&XF(reg)) = sh4_read_long(addr+4);
331 } else {
332 *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
333 *((uint32_t *)&FR((reg) | 0x01)) = sh4_read_long(addr+4);
334 }
335 } else {
336 *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
337 }
338 }
340 static uint32_t sh4_read_sr( void )
341 {
342 /* synchronize sh4r.sr with the various bitflags */
343 sh4r.sr &= SR_MQSTMASK;
344 if( sh4r.t ) sh4r.sr |= SR_T;
345 if( sh4r.s ) sh4r.sr |= SR_S;
346 if( sh4r.m ) sh4r.sr |= SR_M;
347 if( sh4r.q ) sh4r.sr |= SR_Q;
348 return sh4r.sr;
349 }
350 /* function for external use */
351 void sh4_raise_exception( int code, int vector )
352 {
353 RAISE(code, vector);
354 }
356 static void sh4_accept_interrupt( void )
357 {
358 uint32_t code = intc_accept_interrupt();
359 sh4r.ssr = sh4_read_sr();
360 sh4r.spc = sh4r.pc;
361 sh4r.sgr = sh4r.r[15];
362 sh4_load_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
363 MMIO_WRITE( MMU, INTEVT, code );
364 sh4r.pc = sh4r.vbr + 0x600;
365 sh4r.new_pc = sh4r.pc + 2;
366 // WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
367 }
369 gboolean sh4_execute_instruction( void )
370 {
371 uint32_t pc;
372 unsigned short ir;
373 uint32_t tmp;
374 uint64_t tmpl;
375 float ftmp;
376 double dtmp;
378 #define R0 sh4r.r[0]
379 #define FR0 FR(0)
380 #define DR0 DR(0)
381 #define RN(ir) sh4r.r[(ir&0x0F00)>>8]
382 #define RN_BANK(ir) sh4r.r_bank[(ir&0x0070)>>4]
383 #define RM(ir) sh4r.r[(ir&0x00F0)>>4]
384 #define DISP4(ir) (ir&0x000F) /* 4-bit displacements are *NOT* sign-extended */
385 #define DISP8(ir) (ir&0x00FF)
386 #define PCDISP8(ir) SIGNEXT8(ir&0x00FF)
387 #define IMM8(ir) SIGNEXT8(ir&0x00FF)
388 #define UIMM8(ir) (ir&0x00FF) /* Unsigned immmediate */
389 #define DISP12(ir) SIGNEXT12(ir&0x0FFF)
390 #define FRNn(ir) ((ir&0x0F00)>>8)
391 #define FRMn(ir) ((ir&0x00F0)>>4)
392 #define DRNn(ir) ((ir&0x0E00)>>9)
393 #define DRMn(ir) ((ir&0x00E0)>>5)
394 #define FVN(ir) ((ir&0x0C00)>>8)
395 #define FVM(ir) ((ir&0x0300)>>6)
396 #define FRN(ir) FR(FRNn(ir))
397 #define FRM(ir) FR(FRMn(ir))
398 #define FRNi(ir) (*((uint32_t *)&FR(FRNn(ir))))
399 #define FRMi(ir) (*((uint32_t *)&FR(FRMn(ir))))
400 #define DRN(ir) DRb(DRNn(ir), ir&0x0100)
401 #define DRM(ir) DRb(DRMn(ir),ir&0x0010)
402 #define DRNi(ir) (*((uint64_t *)&DR(FRNn(ir))))
403 #define DRMi(ir) (*((uint64_t *)&DR(FRMn(ir))))
404 #define FPULf *((float *)&sh4r.fpul)
405 #define FPULi (sh4r.fpul)
407 if( SH4_INT_PENDING() )
408 sh4_accept_interrupt();
410 pc = sh4r.pc;
411 if( pc > 0xFFFFFF00 ) {
412 /* SYSCALL Magic */
413 syscall_invoke( pc );
414 sh4r.in_delay_slot = 0;
415 pc = sh4r.pc = sh4r.pr;
416 sh4r.new_pc = sh4r.pc + 2;
417 }
418 ir = MEM_READ_WORD(pc);
419 sh4r.icount++;
421 switch( (ir&0xF000)>>12 ) {
422 case 0: /* 0000nnnnmmmmxxxx */
423 switch( ir&0x000F ) {
424 case 2:
425 switch( (ir&0x00F0)>>4 ) {
426 case 0: /* STC SR, Rn */
427 CHECKPRIV();
428 RN(ir) = sh4_read_sr();
429 break;
430 case 1: /* STC GBR, Rn */
431 RN(ir) = sh4r.gbr;
432 break;
433 case 2: /* STC VBR, Rn */
434 CHECKPRIV();
435 RN(ir) = sh4r.vbr;
436 break;
437 case 3: /* STC SSR, Rn */
438 CHECKPRIV();
439 RN(ir) = sh4r.ssr;
440 break;
441 case 4: /* STC SPC, Rn */
442 CHECKPRIV();
443 RN(ir) = sh4r.spc;
444 break;
445 case 8: case 9: case 10: case 11: case 12: case 13:
446 case 14: case 15:/* STC Rm_bank, Rn */
447 CHECKPRIV();
448 RN(ir) = RN_BANK(ir);
449 break;
450 default: UNDEF(ir);
451 }
452 break;
453 case 3:
454 switch( (ir&0x00F0)>>4 ) {
455 case 0: /* BSRF Rn */
456 CHECKDEST( pc + 4 + RN(ir) );
457 CHECKSLOTILLEGAL();
458 sh4r.in_delay_slot = 1;
459 sh4r.pr = sh4r.pc + 4;
460 sh4r.pc = sh4r.new_pc;
461 sh4r.new_pc = pc + 4 + RN(ir);
462 TRACE_CALL( pc, sh4r.new_pc );
463 return TRUE;
464 case 2: /* BRAF Rn */
465 CHECKDEST( pc + 4 + RN(ir) );
466 CHECKSLOTILLEGAL();
467 sh4r.in_delay_slot = 1;
468 sh4r.pc = sh4r.new_pc;
469 sh4r.new_pc = pc + 4 + RN(ir);
470 return TRUE;
471 case 8: /* PREF [Rn] */
472 tmp = RN(ir);
473 if( (tmp & 0xFC000000) == 0xE0000000 ) {
474 /* Store queue operation */
475 int queue = (tmp&0x20)>>2;
476 int32_t *src = &sh4r.store_queue[queue];
477 uint32_t hi = (MMIO_READ( MMU, (queue == 0 ? QACR0 : QACR1) ) & 0x1C) << 24;
478 uint32_t target = tmp&0x03FFFFE0 | hi;
479 mem_copy_to_sh4( target, src, 32 );
480 }
481 break;
482 case 9: /* OCBI [Rn] */
483 case 10:/* OCBP [Rn] */
484 case 11:/* OCBWB [Rn] */
485 /* anything? */
486 break;
487 case 12:/* MOVCA.L R0, [Rn] */
488 tmp = RN(ir);
489 MEM_WRITE_LONG( tmp, R0 );
490 break;
491 default: UNDEF(ir);
492 }
493 break;
494 case 4: /* MOV.B Rm, [R0 + Rn] */
495 MEM_WRITE_BYTE( R0 + RN(ir), RM(ir) );
496 break;
497 case 5: /* MOV.W Rm, [R0 + Rn] */
498 MEM_WRITE_WORD( R0 + RN(ir), RM(ir) );
499 break;
500 case 6: /* MOV.L Rm, [R0 + Rn] */
501 MEM_WRITE_LONG( R0 + RN(ir), RM(ir) );
502 break;
503 case 7: /* MUL.L Rm, Rn */
504 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
505 (RM(ir) * RN(ir));
506 break;
507 case 8:
508 switch( (ir&0x0FF0)>>4 ) {
509 case 0: /* CLRT */
510 sh4r.t = 0;
511 break;
512 case 1: /* SETT */
513 sh4r.t = 1;
514 break;
515 case 2: /* CLRMAC */
516 sh4r.mac = 0;
517 break;
518 case 3: /* LDTLB */
519 break;
520 case 4: /* CLRS */
521 sh4r.s = 0;
522 break;
523 case 5: /* SETS */
524 sh4r.s = 1;
525 break;
526 default: UNDEF(ir);
527 }
528 break;
529 case 9:
530 if( (ir&0x00F0) == 0x20 ) /* MOVT Rn */
531 RN(ir) = sh4r.t;
532 else if( ir == 0x0019 ) /* DIV0U */
533 sh4r.m = sh4r.q = sh4r.t = 0;
534 else if( ir == 0x0009 )
535 /* NOP */;
536 else UNDEF(ir);
537 break;
538 case 10:
539 switch( (ir&0x00F0) >> 4 ) {
540 case 0: /* STS MACH, Rn */
541 RN(ir) = sh4r.mac >> 32;
542 break;
543 case 1: /* STS MACL, Rn */
544 RN(ir) = (uint32_t)sh4r.mac;
545 break;
546 case 2: /* STS PR, Rn */
547 RN(ir) = sh4r.pr;
548 break;
549 case 3: /* STC SGR, Rn */
550 CHECKPRIV();
551 RN(ir) = sh4r.sgr;
552 break;
553 case 5:/* STS FPUL, Rn */
554 RN(ir) = sh4r.fpul;
555 break;
556 case 6: /* STS FPSCR, Rn */
557 RN(ir) = sh4r.fpscr;
558 break;
559 case 15:/* STC DBR, Rn */
560 CHECKPRIV();
561 RN(ir) = sh4r.dbr;
562 break;
563 default: UNDEF(ir);
564 }
565 break;
566 case 11:
567 switch( (ir&0x0FF0)>>4 ) {
568 case 0: /* RTS */
569 CHECKDEST( sh4r.pr );
570 CHECKSLOTILLEGAL();
571 sh4r.in_delay_slot = 1;
572 sh4r.pc = sh4r.new_pc;
573 sh4r.new_pc = sh4r.pr;
574 TRACE_RETURN( pc, sh4r.new_pc );
575 return TRUE;
576 case 1: /* SLEEP */
577 if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
578 sh4r.sh4_state = SH4_STATE_STANDBY;
579 } else {
580 sh4r.sh4_state = SH4_STATE_SLEEP;
581 }
582 return FALSE; /* Halt CPU */
583 case 2: /* RTE */
584 CHECKPRIV();
585 CHECKDEST( sh4r.spc );
586 CHECKSLOTILLEGAL();
587 sh4r.in_delay_slot = 1;
588 sh4r.pc = sh4r.new_pc;
589 sh4r.new_pc = sh4r.spc;
590 sh4_load_sr( sh4r.ssr );
591 return TRUE;
592 default:UNDEF(ir);
593 }
594 break;
595 case 12:/* MOV.B [R0+R%d], R%d */
596 RN(ir) = MEM_READ_BYTE( R0 + RM(ir) );
597 break;
598 case 13:/* MOV.W [R0+R%d], R%d */
599 RN(ir) = MEM_READ_WORD( R0 + RM(ir) );
600 break;
601 case 14:/* MOV.L [R0+R%d], R%d */
602 RN(ir) = MEM_READ_LONG( R0 + RM(ir) );
603 break;
604 case 15:/* MAC.L [Rm++], [Rn++] */
605 tmpl = ( SIGNEXT32(MEM_READ_LONG(RM(ir))) *
606 SIGNEXT32(MEM_READ_LONG(RN(ir))) );
607 if( sh4r.s ) {
608 /* 48-bit Saturation. Yuch */
609 tmpl += SIGNEXT48(sh4r.mac);
610 if( tmpl < 0xFFFF800000000000LL )
611 tmpl = 0xFFFF800000000000LL;
612 else if( tmpl > 0x00007FFFFFFFFFFFLL )
613 tmpl = 0x00007FFFFFFFFFFFLL;
614 sh4r.mac = (sh4r.mac&0xFFFF000000000000LL) |
615 (tmpl&0x0000FFFFFFFFFFFFLL);
616 } else sh4r.mac = tmpl;
618 RM(ir) += 4;
619 RN(ir) += 4;
621 break;
622 default: UNDEF(ir);
623 }
624 break;
625 case 1: /* 0001nnnnmmmmdddd */
626 /* MOV.L Rm, [Rn + disp4*4] */
627 MEM_WRITE_LONG( RN(ir) + (DISP4(ir)<<2), RM(ir) );
628 break;
629 case 2: /* 0010nnnnmmmmxxxx */
630 switch( ir&0x000F ) {
631 case 0: /* MOV.B Rm, [Rn] */
632 MEM_WRITE_BYTE( RN(ir), RM(ir) );
633 break;
634 case 1: /* MOV.W Rm, [Rn] */
635 MEM_WRITE_WORD( RN(ir), RM(ir) );
636 break;
637 case 2: /* MOV.L Rm, [Rn] */
638 MEM_WRITE_LONG( RN(ir), RM(ir) );
639 break;
640 case 3: UNDEF(ir);
641 break;
642 case 4: /* MOV.B Rm, [--Rn] */
643 RN(ir) --;
644 MEM_WRITE_BYTE( RN(ir), RM(ir) );
645 break;
646 case 5: /* MOV.W Rm, [--Rn] */
647 RN(ir) -= 2;
648 MEM_WRITE_WORD( RN(ir), RM(ir) );
649 break;
650 case 6: /* MOV.L Rm, [--Rn] */
651 RN(ir) -= 4;
652 MEM_WRITE_LONG( RN(ir), RM(ir) );
653 break;
654 case 7: /* DIV0S Rm, Rn */
655 sh4r.q = RN(ir)>>31;
656 sh4r.m = RM(ir)>>31;
657 sh4r.t = sh4r.q ^ sh4r.m;
658 break;
659 case 8: /* TST Rm, Rn */
660 sh4r.t = (RN(ir)&RM(ir) ? 0 : 1);
661 break;
662 case 9: /* AND Rm, Rn */
663 RN(ir) &= RM(ir);
664 break;
665 case 10:/* XOR Rm, Rn */
666 RN(ir) ^= RM(ir);
667 break;
668 case 11:/* OR Rm, Rn */
669 RN(ir) |= RM(ir);
670 break;
671 case 12:/* CMP/STR Rm, Rn */
672 /* set T = 1 if any byte in RM & RN is the same */
673 tmp = RM(ir) ^ RN(ir);
674 sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
675 (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
676 break;
677 case 13:/* XTRCT Rm, Rn */
678 RN(ir) = (RN(ir)>>16) | (RM(ir)<<16);
679 break;
680 case 14:/* MULU.W Rm, Rn */
681 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
682 (uint32_t)((RM(ir)&0xFFFF) * (RN(ir)&0xFFFF));
683 break;
684 case 15:/* MULS.W Rm, Rn */
685 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
686 (uint32_t)(SIGNEXT32(RM(ir)&0xFFFF) * SIGNEXT32(RN(ir)&0xFFFF));
687 break;
688 }
689 break;
690 case 3: /* 0011nnnnmmmmxxxx */
691 switch( ir&0x000F ) {
692 case 0: /* CMP/EQ Rm, Rn */
693 sh4r.t = ( RM(ir) == RN(ir) ? 1 : 0 );
694 break;
695 case 2: /* CMP/HS Rm, Rn */
696 sh4r.t = ( RN(ir) >= RM(ir) ? 1 : 0 );
697 break;
698 case 3: /* CMP/GE Rm, Rn */
699 sh4r.t = ( ((int32_t)RN(ir)) >= ((int32_t)RM(ir)) ? 1 : 0 );
700 break;
701 case 4: { /* DIV1 Rm, Rn */
702 /* This is just from the sh4p manual with some
703 * simplifications (someone want to check it's correct? :)
704 * Why they couldn't just provide a real DIV instruction...
705 * Please oh please let the translator batch these things
706 * up into a single DIV... */
707 uint32_t tmp0, tmp1, tmp2, dir;
709 dir = sh4r.q ^ sh4r.m;
710 sh4r.q = (RN(ir) >> 31);
711 tmp2 = RM(ir);
712 RN(ir) = (RN(ir) << 1) | sh4r.t;
713 tmp0 = RN(ir);
714 if( dir ) {
715 RN(ir) += tmp2;
716 tmp1 = (RN(ir)<tmp0 ? 1 : 0 );
717 } else {
718 RN(ir) -= tmp2;
719 tmp1 = (RN(ir)>tmp0 ? 1 : 0 );
720 }
721 sh4r.q ^= sh4r.m ^ tmp1;
722 sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
723 break; }
724 case 5: /* DMULU.L Rm, Rn */
725 sh4r.mac = ((uint64_t)RM(ir)) * ((uint64_t)RN(ir));
726 break;
727 case 6: /* CMP/HI Rm, Rn */
728 sh4r.t = ( RN(ir) > RM(ir) ? 1 : 0 );
729 break;
730 case 7: /* CMP/GT Rm, Rn */
731 sh4r.t = ( ((int32_t)RN(ir)) > ((int32_t)RM(ir)) ? 1 : 0 );
732 break;
733 case 8: /* SUB Rm, Rn */
734 RN(ir) -= RM(ir);
735 break;
736 case 10:/* SUBC Rm, Rn */
737 tmp = RN(ir);
738 RN(ir) = RN(ir) - RM(ir) - sh4r.t;
739 sh4r.t = (RN(ir) > tmp || (RN(ir) == tmp && sh4r.t == 1));
740 break;
741 case 11:/* SUBV Rm, Rn */
742 UNIMP(ir);
743 break;
744 case 12:/* ADD Rm, Rn */
745 RN(ir) += RM(ir);
746 break;
747 case 13:/* DMULS.L Rm, Rn */
748 sh4r.mac = SIGNEXT32(RM(ir)) * SIGNEXT32(RN(ir));
749 break;
750 case 14:/* ADDC Rm, Rn */
751 tmp = RN(ir);
752 RN(ir) += RM(ir) + sh4r.t;
753 sh4r.t = ( RN(ir) < tmp || (RN(ir) == tmp && sh4r.t != 0) ? 1 : 0 );
754 break;
755 case 15:/* ADDV Rm, Rn */
756 UNIMP(ir);
757 break;
758 default: UNDEF(ir);
759 }
760 break;
761 case 4: /* 0100nnnnxxxxxxxx */
762 switch( ir&0x00FF ) {
763 case 0x00: /* SHLL Rn */
764 sh4r.t = RN(ir) >> 31;
765 RN(ir) <<= 1;
766 break;
767 case 0x01: /* SHLR Rn */
768 sh4r.t = RN(ir) & 0x00000001;
769 RN(ir) >>= 1;
770 break;
771 case 0x02: /* STS.L MACH, [--Rn] */
772 RN(ir) -= 4;
773 MEM_WRITE_LONG( RN(ir), (sh4r.mac>>32) );
774 break;
775 case 0x03: /* STC.L SR, [--Rn] */
776 CHECKPRIV();
777 RN(ir) -= 4;
778 MEM_WRITE_LONG( RN(ir), sh4_read_sr() );
779 break;
780 case 0x04: /* ROTL Rn */
781 sh4r.t = RN(ir) >> 31;
782 RN(ir) <<= 1;
783 RN(ir) |= sh4r.t;
784 break;
785 case 0x05: /* ROTR Rn */
786 sh4r.t = RN(ir) & 0x00000001;
787 RN(ir) >>= 1;
788 RN(ir) |= (sh4r.t << 31);
789 break;
790 case 0x06: /* LDS.L [Rn++], MACH */
791 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
792 (((uint64_t)MEM_READ_LONG(RN(ir)))<<32);
793 RN(ir) += 4;
794 break;
795 case 0x07: /* LDC.L [Rn++], SR */
796 CHECKPRIV();
797 sh4_load_sr( MEM_READ_LONG(RN(ir)) );
798 RN(ir) +=4;
799 break;
800 case 0x08: /* SHLL2 Rn */
801 RN(ir) <<= 2;
802 break;
803 case 0x09: /* SHLR2 Rn */
804 RN(ir) >>= 2;
805 break;
806 case 0x0A: /* LDS Rn, MACH */
807 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
808 (((uint64_t)RN(ir))<<32);
809 break;
810 case 0x0B: /* JSR [Rn] */
811 CHECKDEST( RN(ir) );
812 CHECKSLOTILLEGAL();
813 sh4r.in_delay_slot = 1;
814 sh4r.pc = sh4r.new_pc;
815 sh4r.new_pc = RN(ir);
816 sh4r.pr = pc + 4;
817 TRACE_CALL( pc, sh4r.new_pc );
818 return TRUE;
819 case 0x0E: /* LDC Rn, SR */
820 CHECKPRIV();
821 sh4_load_sr( RN(ir) );
822 break;
823 case 0x10: /* DT Rn */
824 RN(ir) --;
825 sh4r.t = ( RN(ir) == 0 ? 1 : 0 );
826 break;
827 case 0x11: /* CMP/PZ Rn */
828 sh4r.t = ( ((int32_t)RN(ir)) >= 0 ? 1 : 0 );
829 break;
830 case 0x12: /* STS.L MACL, [--Rn] */
831 RN(ir) -= 4;
832 MEM_WRITE_LONG( RN(ir), (uint32_t)sh4r.mac );
833 break;
834 case 0x13: /* STC.L GBR, [--Rn] */
835 RN(ir) -= 4;
836 MEM_WRITE_LONG( RN(ir), sh4r.gbr );
837 break;
838 case 0x15: /* CMP/PL Rn */
839 sh4r.t = ( ((int32_t)RN(ir)) > 0 ? 1 : 0 );
840 break;
841 case 0x16: /* LDS.L [Rn++], MACL */
842 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
843 (uint64_t)((uint32_t)MEM_READ_LONG(RN(ir)));
844 RN(ir) += 4;
845 break;
846 case 0x17: /* LDC.L [Rn++], GBR */
847 sh4r.gbr = MEM_READ_LONG(RN(ir));
848 RN(ir) +=4;
849 break;
850 case 0x18: /* SHLL8 Rn */
851 RN(ir) <<= 8;
852 break;
853 case 0x19: /* SHLR8 Rn */
854 RN(ir) >>= 8;
855 break;
856 case 0x1A: /* LDS Rn, MACL */
857 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
858 (uint64_t)((uint32_t)(RN(ir)));
859 break;
860 case 0x1B: /* TAS.B [Rn] */
861 tmp = MEM_READ_BYTE( RN(ir) );
862 sh4r.t = ( tmp == 0 ? 1 : 0 );
863 MEM_WRITE_BYTE( RN(ir), tmp | 0x80 );
864 break;
865 case 0x1E: /* LDC Rn, GBR */
866 sh4r.gbr = RN(ir);
867 break;
868 case 0x20: /* SHAL Rn */
869 sh4r.t = RN(ir) >> 31;
870 RN(ir) <<= 1;
871 break;
872 case 0x21: /* SHAR Rn */
873 sh4r.t = RN(ir) & 0x00000001;
874 RN(ir) = ((int32_t)RN(ir)) >> 1;
875 break;
876 case 0x22: /* STS.L PR, [--Rn] */
877 RN(ir) -= 4;
878 MEM_WRITE_LONG( RN(ir), sh4r.pr );
879 break;
880 case 0x23: /* STC.L VBR, [--Rn] */
881 CHECKPRIV();
882 RN(ir) -= 4;
883 MEM_WRITE_LONG( RN(ir), sh4r.vbr );
884 break;
885 case 0x24: /* ROTCL Rn */
886 tmp = RN(ir) >> 31;
887 RN(ir) <<= 1;
888 RN(ir) |= sh4r.t;
889 sh4r.t = tmp;
890 break;
891 case 0x25: /* ROTCR Rn */
892 tmp = RN(ir) & 0x00000001;
893 RN(ir) >>= 1;
894 RN(ir) |= (sh4r.t << 31 );
895 sh4r.t = tmp;
896 break;
897 case 0x26: /* LDS.L [Rn++], PR */
898 sh4r.pr = MEM_READ_LONG( RN(ir) );
899 RN(ir) += 4;
900 break;
901 case 0x27: /* LDC.L [Rn++], VBR */
902 CHECKPRIV();
903 sh4r.vbr = MEM_READ_LONG(RN(ir));
904 RN(ir) +=4;
905 break;
906 case 0x28: /* SHLL16 Rn */
907 RN(ir) <<= 16;
908 break;
909 case 0x29: /* SHLR16 Rn */
910 RN(ir) >>= 16;
911 break;
912 case 0x2A: /* LDS Rn, PR */
913 sh4r.pr = RN(ir);
914 break;
915 case 0x2B: /* JMP [Rn] */
916 CHECKDEST( RN(ir) );
917 CHECKSLOTILLEGAL();
918 sh4r.in_delay_slot = 1;
919 sh4r.pc = sh4r.new_pc;
920 sh4r.new_pc = RN(ir);
921 return TRUE;
922 case 0x2E: /* LDC Rn, VBR */
923 CHECKPRIV();
924 sh4r.vbr = RN(ir);
925 break;
926 case 0x32: /* STC.L SGR, [--Rn] */
927 CHECKPRIV();
928 RN(ir) -= 4;
929 MEM_WRITE_LONG( RN(ir), sh4r.sgr );
930 break;
931 case 0x33: /* STC.L SSR, [--Rn] */
932 CHECKPRIV();
933 RN(ir) -= 4;
934 MEM_WRITE_LONG( RN(ir), sh4r.ssr );
935 break;
936 case 0x37: /* LDC.L [Rn++], SSR */
937 CHECKPRIV();
938 sh4r.ssr = MEM_READ_LONG(RN(ir));
939 RN(ir) +=4;
940 break;
941 case 0x3E: /* LDC Rn, SSR */
942 CHECKPRIV();
943 sh4r.ssr = RN(ir);
944 break;
945 case 0x43: /* STC.L SPC, [--Rn] */
946 CHECKPRIV();
947 RN(ir) -= 4;
948 MEM_WRITE_LONG( RN(ir), sh4r.spc );
949 break;
950 case 0x47: /* LDC.L [Rn++], SPC */
951 CHECKPRIV();
952 sh4r.spc = MEM_READ_LONG(RN(ir));
953 RN(ir) +=4;
954 break;
955 case 0x4E: /* LDC Rn, SPC */
956 CHECKPRIV();
957 sh4r.spc = RN(ir);
958 break;
959 case 0x52: /* STS.L FPUL, [--Rn] */
960 RN(ir) -= 4;
961 MEM_WRITE_LONG( RN(ir), sh4r.fpul );
962 break;
963 case 0x56: /* LDS.L [Rn++], FPUL */
964 sh4r.fpul = MEM_READ_LONG(RN(ir));
965 RN(ir) +=4;
966 break;
967 case 0x5A: /* LDS Rn, FPUL */
968 sh4r.fpul = RN(ir);
969 break;
970 case 0x62: /* STS.L FPSCR, [--Rn] */
971 RN(ir) -= 4;
972 MEM_WRITE_LONG( RN(ir), sh4r.fpscr );
973 break;
974 case 0x66: /* LDS.L [Rn++], FPSCR */
975 sh4r.fpscr = MEM_READ_LONG(RN(ir));
976 RN(ir) +=4;
977 break;
978 case 0x6A: /* LDS Rn, FPSCR */
979 sh4r.fpscr = RN(ir);
980 break;
981 case 0xF2: /* STC.L DBR, [--Rn] */
982 CHECKPRIV();
983 RN(ir) -= 4;
984 MEM_WRITE_LONG( RN(ir), sh4r.dbr );
985 break;
986 case 0xF6: /* LDC.L [Rn++], DBR */
987 CHECKPRIV();
988 sh4r.dbr = MEM_READ_LONG(RN(ir));
989 RN(ir) +=4;
990 break;
991 case 0xFA: /* LDC Rn, DBR */
992 CHECKPRIV();
993 sh4r.dbr = RN(ir);
994 break;
995 case 0x83: case 0x93: case 0xA3: case 0xB3: case 0xC3:
996 case 0xD3: case 0xE3: case 0xF3: /* STC.L Rn_BANK, [--Rn] */
997 CHECKPRIV();
998 RN(ir) -= 4;
999 MEM_WRITE_LONG( RN(ir), RN_BANK(ir) );
1000 break;
1001 case 0x87: case 0x97: case 0xA7: case 0xB7: case 0xC7:
1002 case 0xD7: case 0xE7: case 0xF7: /* LDC.L [Rn++], Rn_BANK */
1003 CHECKPRIV();
1004 RN_BANK(ir) = MEM_READ_LONG( RN(ir) );
1005 RN(ir) += 4;
1006 break;
1007 case 0x8E: case 0x9E: case 0xAE: case 0xBE: case 0xCE:
1008 case 0xDE: case 0xEE: case 0xFE: /* LDC Rm, Rn_BANK */
1009 CHECKPRIV();
1010 RN_BANK(ir) = RM(ir);
1011 break;
1012 default:
1013 if( (ir&0x000F) == 0x0F ) {
1014 /* MAC.W [Rm++], [Rn++] */
1015 tmp = SIGNEXT16(MEM_READ_WORD(RM(ir))) *
1016 SIGNEXT16(MEM_READ_WORD(RN(ir)));
1017 if( sh4r.s ) {
1018 /* FIXME */
1019 UNIMP(ir);
1020 } else sh4r.mac += SIGNEXT32(tmp);
1021 RM(ir) += 2;
1022 RN(ir) += 2;
1023 } else if( (ir&0x000F) == 0x0C ) {
1024 /* SHAD Rm, Rn */
1025 tmp = RM(ir);
1026 if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);
1027 else if( (tmp & 0x1F) == 0 )
1028 RN(ir) = ((int32_t)RN(ir)) >> 31;
1029 else
1030 RN(ir) = ((int32_t)RN(ir)) >> (((~RM(ir)) & 0x1F)+1);
1031 } else if( (ir&0x000F) == 0x0D ) {
1032 /* SHLD Rm, Rn */
1033 tmp = RM(ir);
1034 if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);
1035 else if( (tmp & 0x1F) == 0 ) RN(ir) = 0;
1036 else RN(ir) >>= (((~tmp) & 0x1F)+1);
1037 } else UNDEF(ir);
1038 }
1039 break;
1040 case 5: /* 0101nnnnmmmmdddd */
1041 /* MOV.L [Rm + disp4*4], Rn */
1042 RN(ir) = MEM_READ_LONG( RM(ir) + (DISP4(ir)<<2) );
1043 break;
1044 case 6: /* 0110xxxxxxxxxxxx */
1045 switch( ir&0x000f ) {
1046 case 0: /* MOV.B [Rm], Rn */
1047 RN(ir) = MEM_READ_BYTE( RM(ir) );
1048 break;
1049 case 1: /* MOV.W [Rm], Rn */
1050 RN(ir) = MEM_READ_WORD( RM(ir) );
1051 break;
1052 case 2: /* MOV.L [Rm], Rn */
1053 RN(ir) = MEM_READ_LONG( RM(ir) );
1054 break;
1055 case 3: /* MOV Rm, Rn */
1056 RN(ir) = RM(ir);
1057 break;
1058 case 4: /* MOV.B [Rm++], Rn */
1059 RN(ir) = MEM_READ_BYTE( RM(ir) );
1060 RM(ir) ++;
1061 break;
1062 case 5: /* MOV.W [Rm++], Rn */
1063 RN(ir) = MEM_READ_WORD( RM(ir) );
1064 RM(ir) += 2;
1065 break;
1066 case 6: /* MOV.L [Rm++], Rn */
1067 RN(ir) = MEM_READ_LONG( RM(ir) );
1068 RM(ir) += 4;
1069 break;
1070 case 7: /* NOT Rm, Rn */
1071 RN(ir) = ~RM(ir);
1072 break;
1073 case 8: /* SWAP.B Rm, Rn */
1074 RN(ir) = (RM(ir)&0xFFFF0000) | ((RM(ir)&0x0000FF00)>>8) |
1075 ((RM(ir)&0x000000FF)<<8);
1076 break;
1077 case 9: /* SWAP.W Rm, Rn */
1078 RN(ir) = (RM(ir)>>16) | (RM(ir)<<16);
1079 break;
1080 case 10:/* NEGC Rm, Rn */
1081 tmp = 0 - RM(ir);
1082 RN(ir) = tmp - sh4r.t;
1083 sh4r.t = ( 0<tmp || tmp<RN(ir) ? 1 : 0 );
1084 break;
1085 case 11:/* NEG Rm, Rn */
1086 RN(ir) = 0 - RM(ir);
1087 break;
1088 case 12:/* EXTU.B Rm, Rn */
1089 RN(ir) = RM(ir)&0x000000FF;
1090 break;
1091 case 13:/* EXTU.W Rm, Rn */
1092 RN(ir) = RM(ir)&0x0000FFFF;
1093 break;
1094 case 14:/* EXTS.B Rm, Rn */
1095 RN(ir) = SIGNEXT8( RM(ir)&0x000000FF );
1096 break;
1097 case 15:/* EXTS.W Rm, Rn */
1098 RN(ir) = SIGNEXT16( RM(ir)&0x0000FFFF );
1099 break;
1100 }
1101 break;
1102 case 7: /* 0111nnnniiiiiiii */
1103 /* ADD imm8, Rn */
1104 RN(ir) += IMM8(ir);
1105 break;
1106 case 8: /* 1000xxxxxxxxxxxx */
1107 switch( (ir&0x0F00) >> 8 ) {
1108 case 0: /* MOV.B R0, [Rm + disp4] */
1109 MEM_WRITE_BYTE( RM(ir) + DISP4(ir), R0 );
1110 break;
1111 case 1: /* MOV.W R0, [Rm + disp4*2] */
1112 MEM_WRITE_WORD( RM(ir) + (DISP4(ir)<<1), R0 );
1113 break;
1114 case 4: /* MOV.B [Rm + disp4], R0 */
1115 R0 = MEM_READ_BYTE( RM(ir) + DISP4(ir) );
1116 break;
1117 case 5: /* MOV.W [Rm + disp4*2], R0 */
1118 R0 = MEM_READ_WORD( RM(ir) + (DISP4(ir)<<1) );
1119 break;
1120 case 8: /* CMP/EQ imm, R0 */
1121 sh4r.t = ( R0 == IMM8(ir) ? 1 : 0 );
1122 break;
1123 case 9: /* BT disp8 */
1124 CHECKSLOTILLEGAL()
1125 if( sh4r.t ) {
1126 CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
1127 sh4r.pc += (PCDISP8(ir)<<1) + 4;
1128 sh4r.new_pc = sh4r.pc + 2;
1129 return TRUE;
1130 }
1131 break;
1132 case 11:/* BF disp8 */
1133 CHECKSLOTILLEGAL()
1134 if( !sh4r.t ) {
1135 CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
1136 sh4r.pc += (PCDISP8(ir)<<1) + 4;
1137 sh4r.new_pc = sh4r.pc + 2;
1138 return TRUE;
1139 }
1140 break;
1141 case 13:/* BT/S disp8 */
1142 CHECKSLOTILLEGAL()
1143 if( sh4r.t ) {
1144 CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
1145 sh4r.in_delay_slot = 1;
1146 sh4r.pc = sh4r.new_pc;
1147 sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;
1148 sh4r.in_delay_slot = 1;
1149 return TRUE;
1150 }
1151 break;
1152 case 15:/* BF/S disp8 */
1153 CHECKSLOTILLEGAL()
1154 if( !sh4r.t ) {
1155 CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
1156 sh4r.in_delay_slot = 1;
1157 sh4r.pc = sh4r.new_pc;
1158 sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;
1159 return TRUE;
1160 }
1161 break;
1162 default: UNDEF(ir);
1163 }
1164 break;
1165 case 9: /* 1001xxxxxxxxxxxx */
1166 /* MOV.W [disp8*2 + pc + 4], Rn */
1167 RN(ir) = MEM_READ_WORD( pc + 4 + (DISP8(ir)<<1) );
1168 break;
1169 case 10:/* 1010dddddddddddd */
1170 /* BRA disp12 */
1171 CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 )
1172 CHECKSLOTILLEGAL()
1173 sh4r.in_delay_slot = 1;
1174 sh4r.pc = sh4r.new_pc;
1175 sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);
1176 return TRUE;
1177 case 11:/* 1011dddddddddddd */
1178 /* BSR disp12 */
1179 CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 )
1180 CHECKSLOTILLEGAL()
1181 sh4r.in_delay_slot = 1;
1182 sh4r.pr = pc + 4;
1183 sh4r.pc = sh4r.new_pc;
1184 sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);
1185 TRACE_CALL( pc, sh4r.new_pc );
1186 return TRUE;
1187 case 12:/* 1100xxxxdddddddd */
1188 switch( (ir&0x0F00)>>8 ) {
1189 case 0: /* MOV.B R0, [GBR + disp8] */
1190 MEM_WRITE_BYTE( sh4r.gbr + DISP8(ir), R0 );
1191 break;
1192 case 1: /* MOV.W R0, [GBR + disp8*2] */
1193 MEM_WRITE_WORD( sh4r.gbr + (DISP8(ir)<<1), R0 );
1194 break;
1195 case 2: /*MOV.L R0, [GBR + disp8*4] */
1196 MEM_WRITE_LONG( sh4r.gbr + (DISP8(ir)<<2), R0 );
1197 break;
1198 case 3: /* TRAPA imm8 */
1199 CHECKSLOTILLEGAL()
1200 sh4r.in_delay_slot = 1;
1201 MMIO_WRITE( MMU, TRA, UIMM8(ir)<<2 );
1202 RAISE( EXC_TRAP, EXV_TRAP );
1203 break;
1204 case 4: /* MOV.B [GBR + disp8], R0 */
1205 R0 = MEM_READ_BYTE( sh4r.gbr + DISP8(ir) );
1206 break;
1207 case 5: /* MOV.W [GBR + disp8*2], R0 */
1208 R0 = MEM_READ_WORD( sh4r.gbr + (DISP8(ir)<<1) );
1209 break;
1210 case 6: /* MOV.L [GBR + disp8*4], R0 */
1211 R0 = MEM_READ_LONG( sh4r.gbr + (DISP8(ir)<<2) );
1212 break;
1213 case 7: /* MOVA disp8 + pc&~3 + 4, R0 */
1214 R0 = (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4;
1215 break;
1216 case 8: /* TST imm8, R0 */
1217 sh4r.t = (R0 & UIMM8(ir) ? 0 : 1);
1218 break;
1219 case 9: /* AND imm8, R0 */
1220 R0 &= UIMM8(ir);
1221 break;
1222 case 10:/* XOR imm8, R0 */
1223 R0 ^= UIMM8(ir);
1224 break;
1225 case 11:/* OR imm8, R0 */
1226 R0 |= UIMM8(ir);
1227 break;
1228 case 12:/* TST.B imm8, [R0+GBR] */
1229 sh4r.t = ( MEM_READ_BYTE(R0 + sh4r.gbr) & UIMM8(ir) ? 0 : 1 );
1230 break;
1231 case 13:/* AND.B imm8, [R0+GBR] */
1232 MEM_WRITE_BYTE( R0 + sh4r.gbr,
1233 UIMM8(ir) & MEM_READ_BYTE(R0 + sh4r.gbr) );
1234 break;
1235 case 14:/* XOR.B imm8, [R0+GBR] */
1236 MEM_WRITE_BYTE( R0 + sh4r.gbr,
1237 UIMM8(ir) ^ MEM_READ_BYTE(R0 + sh4r.gbr) );
1238 break;
1239 case 15:/* OR.B imm8, [R0+GBR] */
1240 MEM_WRITE_BYTE( R0 + sh4r.gbr,
1241 UIMM8(ir) | MEM_READ_BYTE(R0 + sh4r.gbr) );
1242 break;
1243 }
1244 break;
1245 case 13:/* 1101nnnndddddddd */
1246 /* MOV.L [disp8*4 + pc&~3 + 4], Rn */
1247 RN(ir) = MEM_READ_LONG( (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4 );
1248 break;
1249 case 14:/* 1110nnnniiiiiiii */
1250 /* MOV imm8, Rn */
1251 RN(ir) = IMM8(ir);
1252 break;
1253 case 15:/* 1111xxxxxxxxxxxx */
1254 CHECKFPUEN();
1255 if( IS_FPU_DOUBLEPREC() ) {
1256 switch( ir&0x000F ) {
1257 case 0: /* FADD FRm, FRn */
1258 DRN(ir) += DRM(ir);
1259 break;
1260 case 1: /* FSUB FRm, FRn */
1261 DRN(ir) -= DRM(ir);
1262 break;
1263 case 2: /* FMUL FRm, FRn */
1264 DRN(ir) = DRN(ir) * DRM(ir);
1265 break;
1266 case 3: /* FDIV FRm, FRn */
1267 DRN(ir) = DRN(ir) / DRM(ir);
1268 break;
1269 case 4: /* FCMP/EQ FRm, FRn */
1270 sh4r.t = ( DRN(ir) == DRM(ir) ? 1 : 0 );
1271 break;
1272 case 5: /* FCMP/GT FRm, FRn */
1273 sh4r.t = ( DRN(ir) > DRM(ir) ? 1 : 0 );
1274 break;
1275 case 6: /* FMOV.S [Rm+R0], FRn */
1276 MEM_FP_READ( RM(ir) + R0, FRNn(ir) );
1277 break;
1278 case 7: /* FMOV.S FRm, [Rn+R0] */
1279 MEM_FP_WRITE( RN(ir) + R0, FRMn(ir) );
1280 break;
1281 case 8: /* FMOV.S [Rm], FRn */
1282 MEM_FP_READ( RM(ir), FRNn(ir) );
1283 break;
1284 case 9: /* FMOV.S [Rm++], FRn */
1285 MEM_FP_READ( RM(ir), FRNn(ir) );
1286 RM(ir) += FP_WIDTH;
1287 break;
1288 case 10:/* FMOV.S FRm, [Rn] */
1289 MEM_FP_WRITE( RN(ir), FRMn(ir) );
1290 break;
1291 case 11:/* FMOV.S FRm, [--Rn] */
1292 RN(ir) -= FP_WIDTH;
1293 MEM_FP_WRITE( RN(ir), FRMn(ir) );
1294 break;
1295 case 12:/* FMOV FRm, FRn */
1296 if( IS_FPU_DOUBLESIZE() )
1297 DRN(ir) = DRM(ir);
1298 else
1299 FRN(ir) = FRM(ir);
1300 break;
1301 case 13:
1302 switch( (ir&0x00F0) >> 4 ) {
1303 case 0: /* FSTS FPUL, FRn */
1304 FRN(ir) = FPULf;
1305 break;
1306 case 1: /* FLDS FRn,FPUL */
1307 FPULf = FRN(ir);
1308 break;
1309 case 2: /* FLOAT FPUL, FRn */
1310 DRN(ir) = (float)FPULi;
1311 break;
1312 case 3: /* FTRC FRn, FPUL */
1313 dtmp = DRN(ir);
1314 if( dtmp >= MAX_INTF )
1315 FPULi = MAX_INT;
1316 else if( dtmp <= MIN_INTF )
1317 FPULi = MIN_INT;
1318 else
1319 FPULi = (int32_t)dtmp;
1320 break;
1321 case 4: /* FNEG FRn */
1322 DRN(ir) = -DRN(ir);
1323 break;
1324 case 5: /* FABS FRn */
1325 DRN(ir) = fabs(DRN(ir));
1326 break;
1327 case 6: /* FSQRT FRn */
1328 DRN(ir) = sqrt(DRN(ir));
1329 break;
1330 case 7: /* FSRRA FRn */
1331 /* NO-OP when PR=1 */
1332 break;
1333 case 8: /* FLDI0 FRn */
1334 DRN(ir) = 0.0;
1335 break;
1336 case 9: /* FLDI1 FRn */
1337 DRN(ir) = 1.0;
1338 break;
1339 case 10: /* FCNVSD FPUL, DRn */
1340 if( ! IS_FPU_DOUBLESIZE() )
1341 DRN(ir) = (double)FPULf;
1342 break;
1343 case 11: /* FCNVDS DRn, FPUL */
1344 if( ! IS_FPU_DOUBLESIZE() )
1345 FPULf = (float)DRN(ir);
1346 break;
1347 case 14:/* FIPR FVm, FVn */
1348 /* NO-OP when PR=1 */
1349 break;
1350 case 15:
1351 if( (ir&0x0300) == 0x0100 ) { /* FTRV XMTRX,FVn */
1352 /* NO-OP when PR=1 */
1353 break;
1354 }
1355 else if( (ir&0x0100) == 0 ) { /* FSCA FPUL, DRn */
1356 /* NO-OP when PR=1 */
1357 break;
1358 }
1359 else if( ir == 0xFBFD ) {
1360 /* FRCHG */
1361 sh4r.fpscr ^= FPSCR_FR;
1362 break;
1363 }
1364 else if( ir == 0xF3FD ) {
1365 /* FSCHG */
1366 sh4r.fpscr ^= FPSCR_SZ;
1367 break;
1368 }
1369 default: UNDEF(ir);
1370 }
1371 break;
1372 case 14:/* FMAC FR0, FRm, FRn */
1373 DRN(ir) += DRM(ir)*DR0;
1374 break;
1375 default: UNDEF(ir);
1376 }
1377 } else { /* Single precision */
1378 switch( ir&0x000F ) {
1379 case 0: /* FADD FRm, FRn */
1380 FRN(ir) += FRM(ir);
1381 break;
1382 case 1: /* FSUB FRm, FRn */
1383 FRN(ir) -= FRM(ir);
1384 break;
1385 case 2: /* FMUL FRm, FRn */
1386 FRN(ir) = FRN(ir) * FRM(ir);
1387 break;
1388 case 3: /* FDIV FRm, FRn */
1389 FRN(ir) = FRN(ir) / FRM(ir);
1390 break;
1391 case 4: /* FCMP/EQ FRm, FRn */
1392 sh4r.t = ( FRN(ir) == FRM(ir) ? 1 : 0 );
1393 break;
1394 case 5: /* FCMP/GT FRm, FRn */
1395 sh4r.t = ( FRN(ir) > FRM(ir) ? 1 : 0 );
1396 break;
1397 case 6: /* FMOV.S [Rm+R0], FRn */
1398 MEM_FP_READ( RM(ir) + R0, FRNn(ir) );
1399 break;
1400 case 7: /* FMOV.S FRm, [Rn+R0] */
1401 MEM_FP_WRITE( RN(ir) + R0, FRMn(ir) );
1402 break;
1403 case 8: /* FMOV.S [Rm], FRn */
1404 MEM_FP_READ( RM(ir), FRNn(ir) );
1405 break;
1406 case 9: /* FMOV.S [Rm++], FRn */
1407 MEM_FP_READ( RM(ir), FRNn(ir) );
1408 RM(ir) += FP_WIDTH;
1409 break;
1410 case 10:/* FMOV.S FRm, [Rn] */
1411 MEM_FP_WRITE( RN(ir), FRMn(ir) );
1412 break;
1413 case 11:/* FMOV.S FRm, [--Rn] */
1414 RN(ir) -= FP_WIDTH;
1415 MEM_FP_WRITE( RN(ir), FRMn(ir) );
1416 break;
1417 case 12:/* FMOV FRm, FRn */
1418 if( IS_FPU_DOUBLESIZE() )
1419 DRN(ir) = DRM(ir);
1420 else
1421 FRN(ir) = FRM(ir);
1422 break;
1423 case 13:
1424 switch( (ir&0x00F0) >> 4 ) {
1425 case 0: /* FSTS FPUL, FRn */
1426 FRN(ir) = FPULf;
1427 break;
1428 case 1: /* FLDS FRn,FPUL */
1429 FPULf = FRN(ir);
1430 break;
1431 case 2: /* FLOAT FPUL, FRn */
1432 FRN(ir) = (float)FPULi;
1433 break;
1434 case 3: /* FTRC FRn, FPUL */
1435 ftmp = FRN(ir);
1436 if( ftmp >= MAX_INTF )
1437 FPULi = MAX_INT;
1438 else if( ftmp <= MIN_INTF )
1439 FPULi = MIN_INT;
1440 else
1441 FPULi = (int32_t)ftmp;
1442 break;
1443 case 4: /* FNEG FRn */
1444 FRN(ir) = -FRN(ir);
1445 break;
1446 case 5: /* FABS FRn */
1447 FRN(ir) = fabsf(FRN(ir));
1448 break;
1449 case 6: /* FSQRT FRn */
1450 FRN(ir) = sqrtf(FRN(ir));
1451 break;
1452 case 7: /* FSRRA FRn */
1453 FRN(ir) = 1.0/sqrtf(FRN(ir));
1454 break;
1455 case 8: /* FLDI0 FRn */
1456 FRN(ir) = 0.0;
1457 break;
1458 case 9: /* FLDI1 FRn */
1459 FRN(ir) = 1.0;
1460 break;
1461 case 10: /* FCNVSD FPUL, DRn */
1462 break;
1463 case 11: /* FCNVDS DRn, FPUL */
1464 break;
1465 case 14:/* FIPR FVm, FVn */
1466 /* FIXME: This is not going to be entirely accurate
1467 * as the SH4 instruction is less precise. Also
1468 * need to check for 0s and infinities.
1469 */
1470 {
1471 int tmp2 = FVN(ir);
1472 tmp = FVM(ir);
1473 FR(tmp2+3) = FR(tmp)*FR(tmp2) +
1474 FR(tmp+1)*FR(tmp2+1) +
1475 FR(tmp+2)*FR(tmp2+2) +
1476 FR(tmp+3)*FR(tmp2+3);
1477 break;
1478 }
1479 case 15:
1480 if( (ir&0x0300) == 0x0100 ) { /* FTRV XMTRX,FVn */
1481 tmp = FVN(ir);
1482 float fv[4] = { FR(tmp), FR(tmp+1), FR(tmp+2), FR(tmp+3) };
1483 FR(tmp) = XF(0) * fv[0] + XF(4)*fv[1] +
1484 XF(8)*fv[2] + XF(12)*fv[3];
1485 FR(tmp+1) = XF(1) * fv[0] + XF(5)*fv[1] +
1486 XF(9)*fv[2] + XF(13)*fv[3];
1487 FR(tmp+2) = XF(2) * fv[0] + XF(6)*fv[1] +
1488 XF(10)*fv[2] + XF(14)*fv[3];
1489 FR(tmp+3) = XF(3) * fv[0] + XF(7)*fv[1] +
1490 XF(11)*fv[2] + XF(15)*fv[3];
1491 break;
1492 }
1493 else if( (ir&0x0100) == 0 ) { /* FSCA FPUL, DRn */
1494 float angle = (((float)(short)(FPULi>>16)) +
1495 (((float)(FPULi&0xFFFF))/65536.0)) *
1496 2 * M_PI;
1497 int reg = FRNn(ir);
1498 FR(reg) = sinf(angle);
1499 FR(reg+1) = cosf(angle);
1500 break;
1501 }
1502 else if( ir == 0xFBFD ) {
1503 /* FRCHG */
1504 sh4r.fpscr ^= FPSCR_FR;
1505 break;
1506 }
1507 else if( ir == 0xF3FD ) {
1508 /* FSCHG */
1509 sh4r.fpscr ^= FPSCR_SZ;
1510 break;
1511 }
1512 default: UNDEF(ir);
1513 }
1514 break;
1515 case 14:/* FMAC FR0, FRm, FRn */
1516 FRN(ir) += FRM(ir)*FR0;
1517 break;
1518 default: UNDEF(ir);
1519 }
1520 }
1521 break;
1522 }
1523 sh4r.pc = sh4r.new_pc;
1524 sh4r.new_pc += 2;
1525 sh4r.in_delay_slot = 0;
1526 }
.