2 * $Id: sh4core.c,v 1.41 2007-08-23 12:33:27 nkeynes Exp $
4 * SH4 emulation core, and parent module for all the SH4 peripheral
7 * Copyright (c) 2005 Nathan Keynes.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
20 #define MODULE sh4_module
23 #include "sh4/sh4core.h"
24 #include "sh4/sh4mmio.h"
30 #define SH4_CALLTRACE 1
32 #define MAX_INT 0x7FFFFFFF
33 #define MIN_INT 0x80000000
34 #define MAX_INTF 2147483647.0
35 #define MIN_INTF -2147483648.0
37 /* CPU-generated exception code/vector pairs */
38 #define EXC_POWER_RESET 0x000 /* vector special */
39 #define EXC_MANUAL_RESET 0x020
40 #define EXC_READ_ADDR_ERR 0x0E0
41 #define EXC_WRITE_ADDR_ERR 0x100
42 #define EXC_SLOT_ILLEGAL 0x1A0
43 #define EXC_ILLEGAL 0x180
44 #define EXC_TRAP 0x160
45 #define EXC_FPDISABLE 0x800
46 #define EXC_SLOT_FPDISABLE 0x820
48 #define EXV_EXCEPTION 0x100 /* General exception vector */
49 #define EXV_TLBMISS 0x400 /* TLB-miss exception vector */
50 #define EXV_INTERRUPT 0x600 /* External interrupt vector */
52 /********************** SH4 Module Definition ****************************/
54 void sh4_init( void );
55 void sh4_reset( void );
56 uint32_t sh4_run_slice( uint32_t );
57 void sh4_start( void );
58 void sh4_stop( void );
59 void sh4_save_state( FILE *f );
60 int sh4_load_state( FILE *f );
61 void sh4_accept_interrupt( void );
63 struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset,
64 NULL, sh4_run_slice, sh4_stop,
65 sh4_save_state, sh4_load_state };
67 struct sh4_registers sh4r;
71 register_io_regions( mmio_list_sh4mmio );
78 /* zero everything out, for the sake of having a consistent state. */
79 memset( &sh4r, 0, sizeof(sh4r) );
81 /* Resume running if we were halted */
82 sh4r.sh4_state = SH4_STATE_RUNNING;
85 sh4r.new_pc= 0xA0000002;
86 sh4r.vbr = 0x00000000;
87 sh4r.fpscr = 0x00040001;
90 /* Mem reset will do this, but if we want to reset _just_ the SH4... */
91 MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
93 /* Peripheral modules */
101 static struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
102 static int sh4_breakpoint_count = 0;
103 static uint16_t *sh4_icache = NULL;
104 static uint32_t sh4_icache_addr = 0;
106 void sh4_set_breakpoint( uint32_t pc, int type )
108 sh4_breakpoints[sh4_breakpoint_count].address = pc;
109 sh4_breakpoints[sh4_breakpoint_count].type = type;
110 sh4_breakpoint_count++;
113 gboolean sh4_clear_breakpoint( uint32_t pc, int type )
117 for( i=0; i<sh4_breakpoint_count; i++ ) {
118 if( sh4_breakpoints[i].address == pc &&
119 sh4_breakpoints[i].type == type ) {
120 while( ++i < sh4_breakpoint_count ) {
121 sh4_breakpoints[i-1].address = sh4_breakpoints[i].address;
122 sh4_breakpoints[i-1].type = sh4_breakpoints[i].type;
124 sh4_breakpoint_count--;
131 int sh4_get_breakpoint( uint32_t pc )
134 for( i=0; i<sh4_breakpoint_count; i++ ) {
135 if( sh4_breakpoints[i].address == pc )
136 return sh4_breakpoints[i].type;
141 uint32_t sh4_run_slice( uint32_t nanosecs )
144 sh4r.slice_cycle = 0;
146 if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
147 if( sh4r.event_pending < nanosecs ) {
148 sh4r.sh4_state = SH4_STATE_RUNNING;
149 sh4r.slice_cycle = sh4r.event_pending;
153 if( sh4_breakpoint_count == 0 ) {
154 for( ; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
155 if( SH4_EVENT_PENDING() ) {
156 if( sh4r.event_types & PENDING_EVENT ) {
159 /* Eventq execute may (quite likely) deliver an immediate IRQ */
160 if( sh4r.event_types & PENDING_IRQ ) {
161 sh4_accept_interrupt();
164 if( !sh4_execute_instruction() ) {
169 for( ;sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
170 if( SH4_EVENT_PENDING() ) {
171 if( sh4r.event_types & PENDING_EVENT ) {
174 /* Eventq execute may (quite likely) deliver an immediate IRQ */
175 if( sh4r.event_types & PENDING_IRQ ) {
176 sh4_accept_interrupt();
180 if( !sh4_execute_instruction() )
182 #ifdef ENABLE_DEBUG_MODE
183 for( i=0; i<sh4_breakpoint_count; i++ ) {
184 if( sh4_breakpoints[i].address == sh4r.pc ) {
188 if( i != sh4_breakpoint_count ) {
190 if( sh4_breakpoints[i].type == BREAK_ONESHOT )
191 sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );
198 /* If we aborted early, but the cpu is still technically running,
199 * we're doing a hard abort - cut the timeslice back to what we
202 if( sh4r.slice_cycle != nanosecs && sh4r.sh4_state == SH4_STATE_RUNNING ) {
203 nanosecs = sh4r.slice_cycle;
205 if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
206 TMU_run_slice( nanosecs );
207 SCIF_run_slice( nanosecs );
217 void sh4_save_state( FILE *f )
219 fwrite( &sh4r, sizeof(sh4r), 1, f );
221 INTC_save_state( f );
223 SCIF_save_state( f );
226 int sh4_load_state( FILE * f )
228 fread( &sh4r, sizeof(sh4r), 1, f );
230 INTC_load_state( f );
232 return SCIF_load_state( f );
235 /********************** SH4 emulation core ****************************/
237 void sh4_set_pc( int pc )
243 #define UNDEF(ir) return sh4_raise_slot_exception(EXC_ILLEGAL, EXC_SLOT_ILLEGAL)
244 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)
246 #if(SH4_CALLTRACE == 1)
247 #define MAX_CALLSTACK 32
248 static struct call_stack {
250 sh4addr_t target_addr;
251 sh4addr_t stack_pointer;
252 } call_stack[MAX_CALLSTACK];
254 static int call_stack_depth = 0;
255 int sh4_call_trace_on = 0;
257 static inline trace_call( sh4addr_t source, sh4addr_t dest )
259 if( call_stack_depth < MAX_CALLSTACK ) {
260 call_stack[call_stack_depth].call_addr = source;
261 call_stack[call_stack_depth].target_addr = dest;
262 call_stack[call_stack_depth].stack_pointer = sh4r.r[15];
267 static inline trace_return( sh4addr_t source, sh4addr_t dest )
269 if( call_stack_depth > 0 ) {
274 void fprint_stack_trace( FILE *f )
276 int i = call_stack_depth -1;
277 if( i >= MAX_CALLSTACK )
278 i = MAX_CALLSTACK - 1;
279 for( ; i >= 0; i-- ) {
280 fprintf( f, "%d. Call from %08X => %08X, SP=%08X\n",
281 (call_stack_depth - i), call_stack[i].call_addr,
282 call_stack[i].target_addr, call_stack[i].stack_pointer );
286 #define TRACE_CALL( source, dest ) trace_call(source, dest)
287 #define TRACE_RETURN( source, dest ) trace_return(source, dest)
289 #define TRACE_CALL( dest, rts )
290 #define TRACE_RETURN( source, dest )
293 #define RAISE( x, v ) do{ \
294 if( sh4r.vbr == 0 ) { \
295 ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
296 dreamcast_stop(); return FALSE; \
298 sh4r.spc = sh4r.pc; \
299 sh4r.ssr = sh4_read_sr(); \
300 sh4r.sgr = sh4r.r[15]; \
301 MMIO_WRITE(MMU,EXPEVT,x); \
302 sh4r.pc = sh4r.vbr + v; \
303 sh4r.new_pc = sh4r.pc + 2; \
304 sh4_load_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
305 if( sh4r.in_delay_slot ) { \
306 sh4r.in_delay_slot = 0; \
310 return TRUE; } while(0)
312 #define MEM_READ_BYTE( addr ) sh4_read_byte(addr)
313 #define MEM_READ_WORD( addr ) sh4_read_word(addr)
314 #define MEM_READ_LONG( addr ) sh4_read_long(addr)
315 #define MEM_WRITE_BYTE( addr, val ) sh4_write_byte(addr, val)
316 #define MEM_WRITE_WORD( addr, val ) sh4_write_word(addr, val)
317 #define MEM_WRITE_LONG( addr, val ) sh4_write_long(addr, val)
319 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
321 #define MEM_FP_READ( addr, reg ) sh4_read_float( addr, reg );
322 #define MEM_FP_WRITE( addr, reg ) sh4_write_float( addr, reg );
324 #define CHECKPRIV() if( !IS_SH4_PRIVMODE() ) return sh4_raise_slot_exception( EXC_ILLEGAL, EXC_SLOT_ILLEGAL )
325 #define CHECKRALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_READ_ADDR_ERR )
326 #define CHECKRALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_READ_ADDR_ERR )
327 #define CHECKWALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_WRITE_ADDR_ERR )
328 #define CHECKWALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_WRITE_ADDR_ERR )
330 #define CHECKFPUEN() if( !IS_FPU_ENABLED() ) { if( ir == 0xFFFD ) { UNDEF(ir); } else { return sh4_raise_slot_exception( EXC_FPDISABLE, EXC_SLOT_FPDISABLE ); } }
331 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); dreamcast_stop(); return FALSE; }
332 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) return sh4_raise_exception(EXC_SLOT_ILLEGAL)
334 static void sh4_switch_banks( )
338 memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
339 memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
340 memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
343 static void sh4_load_sr( uint32_t newval )
345 if( (newval ^ sh4r.sr) & SR_RB )
348 sh4r.t = (newval&SR_T) ? 1 : 0;
349 sh4r.s = (newval&SR_S) ? 1 : 0;
350 sh4r.m = (newval&SR_M) ? 1 : 0;
351 sh4r.q = (newval&SR_Q) ? 1 : 0;
355 static void sh4_write_float( uint32_t addr, int reg )
357 if( IS_FPU_DOUBLESIZE() ) {
359 sh4_write_long( addr, *((uint32_t *)&XF((reg)&0x0E)) );
360 sh4_write_long( addr+4, *((uint32_t *)&XF(reg)) );
362 sh4_write_long( addr, *((uint32_t *)&FR(reg)) );
363 sh4_write_long( addr+4, *((uint32_t *)&FR((reg)|0x01)) );
366 sh4_write_long( addr, *((uint32_t *)&FR((reg))) );
370 static void sh4_read_float( uint32_t addr, int reg )
372 if( IS_FPU_DOUBLESIZE() ) {
374 *((uint32_t *)&XF((reg) & 0x0E)) = sh4_read_long(addr);
375 *((uint32_t *)&XF(reg)) = sh4_read_long(addr+4);
377 *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
378 *((uint32_t *)&FR((reg) | 0x01)) = sh4_read_long(addr+4);
381 *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
385 static uint32_t sh4_read_sr( void )
387 /* synchronize sh4r.sr with the various bitflags */
388 sh4r.sr &= SR_MQSTMASK;
389 if( sh4r.t ) sh4r.sr |= SR_T;
390 if( sh4r.s ) sh4r.sr |= SR_S;
391 if( sh4r.m ) sh4r.sr |= SR_M;
392 if( sh4r.q ) sh4r.sr |= SR_Q;
397 * Raise a general CPU exception for the specified exception code.
398 * (NOT for TRAPA or TLB exceptions)
400 gboolean sh4_raise_exception( int code )
402 RAISE( code, EXV_EXCEPTION );
405 gboolean sh4_raise_slot_exception( int normal_code, int slot_code ) {
406 if( sh4r.in_delay_slot ) {
407 return sh4_raise_exception(slot_code);
409 return sh4_raise_exception(normal_code);
413 gboolean sh4_raise_tlb_exception( int code )
415 RAISE( code, EXV_TLBMISS );
418 void sh4_accept_interrupt( void )
420 uint32_t code = intc_accept_interrupt();
421 sh4r.ssr = sh4_read_sr();
423 sh4r.sgr = sh4r.r[15];
424 sh4_load_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
425 MMIO_WRITE( MMU, INTEVT, code );
426 sh4r.pc = sh4r.vbr + 0x600;
427 sh4r.new_pc = sh4r.pc + 2;
428 // WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
431 gboolean sh4_execute_instruction( void )
441 if( pc > 0xFFFFFF00 ) {
443 syscall_invoke( pc );
444 sh4r.in_delay_slot = 0;
445 pc = sh4r.pc = sh4r.pr;
446 sh4r.new_pc = sh4r.pc + 2;
450 /* Read instruction */
451 uint32_t pageaddr = pc >> 12;
452 if( sh4_icache != NULL && pageaddr == sh4_icache_addr ) {
453 ir = sh4_icache[(pc&0xFFF)>>1];
455 sh4_icache = (uint16_t *)mem_get_page(pc);
456 if( ((uint32_t)sh4_icache) < MAX_IO_REGIONS ) {
457 /* If someone's actually been so daft as to try to execute out of an IO
458 * region, fallback on the full-blown memory read
461 ir = MEM_READ_WORD(pc);
463 sh4_icache_addr = pageaddr;
464 ir = sh4_icache[(pc&0xFFF)>>1];
467 switch( (ir&0xF000) >> 12 ) {
471 switch( (ir&0x80) >> 7 ) {
473 switch( (ir&0x70) >> 4 ) {
476 uint32_t Rn = ((ir>>8)&0xF);
478 sh4r.r[Rn] = sh4_read_sr();
483 uint32_t Rn = ((ir>>8)&0xF);
485 sh4r.r[Rn] = sh4r.gbr;
490 uint32_t Rn = ((ir>>8)&0xF);
492 sh4r.r[Rn] = sh4r.vbr;
497 uint32_t Rn = ((ir>>8)&0xF);
499 sh4r.r[Rn] = sh4r.ssr;
504 uint32_t Rn = ((ir>>8)&0xF);
506 sh4r.r[Rn] = sh4r.spc;
515 { /* STC Rm_BANK, Rn */
516 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7);
518 sh4r.r[Rn] = sh4r.r_bank[Rm_BANK];
524 switch( (ir&0xF0) >> 4 ) {
527 uint32_t Rn = ((ir>>8)&0xF);
529 CHECKDEST( pc + 4 + sh4r.r[Rn] );
530 sh4r.in_delay_slot = 1;
531 sh4r.pr = sh4r.pc + 4;
532 sh4r.pc = sh4r.new_pc;
533 sh4r.new_pc = pc + 4 + sh4r.r[Rn];
534 TRACE_CALL( pc, sh4r.new_pc );
540 uint32_t Rn = ((ir>>8)&0xF);
542 CHECKDEST( pc + 4 + sh4r.r[Rn] );
543 sh4r.in_delay_slot = 1;
544 sh4r.pc = sh4r.new_pc;
545 sh4r.new_pc = pc + 4 + sh4r.r[Rn];
551 uint32_t Rn = ((ir>>8)&0xF);
553 if( (tmp & 0xFC000000) == 0xE0000000 ) {
554 /* Store queue operation */
555 int queue = (tmp&0x20)>>2;
556 int32_t *src = &sh4r.store_queue[queue];
557 uint32_t hi = (MMIO_READ( MMU, (queue == 0 ? QACR0 : QACR1) ) & 0x1C) << 24;
558 uint32_t target = tmp&0x03FFFFE0 | hi;
559 mem_copy_to_sh4( target, src, 32 );
565 uint32_t Rn = ((ir>>8)&0xF);
570 uint32_t Rn = ((ir>>8)&0xF);
575 uint32_t Rn = ((ir>>8)&0xF);
579 { /* MOVCA.L R0, @Rn */
580 uint32_t Rn = ((ir>>8)&0xF);
583 MEM_WRITE_LONG( tmp, R0 );
592 { /* MOV.B Rm, @(R0, Rn) */
593 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
594 MEM_WRITE_BYTE( R0 + sh4r.r[Rn], sh4r.r[Rm] );
598 { /* MOV.W Rm, @(R0, Rn) */
599 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
600 CHECKWALIGN16( R0 + sh4r.r[Rn] );
601 MEM_WRITE_WORD( R0 + sh4r.r[Rn], sh4r.r[Rm] );
605 { /* MOV.L Rm, @(R0, Rn) */
606 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
607 CHECKWALIGN32( R0 + sh4r.r[Rn] );
608 MEM_WRITE_LONG( R0 + sh4r.r[Rn], sh4r.r[Rm] );
613 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
614 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
615 (sh4r.r[Rm] * sh4r.r[Rn]);
619 switch( (ir&0xFF0) >> 4 ) {
656 switch( (ir&0xF0) >> 4 ) {
664 sh4r.m = sh4r.q = sh4r.t = 0;
669 uint32_t Rn = ((ir>>8)&0xF);
679 switch( (ir&0xF0) >> 4 ) {
682 uint32_t Rn = ((ir>>8)&0xF);
683 sh4r.r[Rn] = (sh4r.mac>>32);
688 uint32_t Rn = ((ir>>8)&0xF);
689 sh4r.r[Rn] = (uint32_t)sh4r.mac;
694 uint32_t Rn = ((ir>>8)&0xF);
695 sh4r.r[Rn] = sh4r.pr;
700 uint32_t Rn = ((ir>>8)&0xF);
702 sh4r.r[Rn] = sh4r.sgr;
707 uint32_t Rn = ((ir>>8)&0xF);
708 sh4r.r[Rn] = sh4r.fpul;
712 { /* STS FPSCR, Rn */
713 uint32_t Rn = ((ir>>8)&0xF);
714 sh4r.r[Rn] = sh4r.fpscr;
719 uint32_t Rn = ((ir>>8)&0xF);
720 CHECKPRIV(); sh4r.r[Rn] = sh4r.dbr;
729 switch( (ir&0xFF0) >> 4 ) {
733 CHECKDEST( sh4r.pr );
734 sh4r.in_delay_slot = 1;
735 sh4r.pc = sh4r.new_pc;
736 sh4r.new_pc = sh4r.pr;
737 TRACE_RETURN( pc, sh4r.new_pc );
743 if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
744 sh4r.sh4_state = SH4_STATE_STANDBY;
746 sh4r.sh4_state = SH4_STATE_SLEEP;
748 return FALSE; /* Halt CPU */
754 CHECKDEST( sh4r.spc );
756 sh4r.in_delay_slot = 1;
757 sh4r.pc = sh4r.new_pc;
758 sh4r.new_pc = sh4r.spc;
759 sh4_load_sr( sh4r.ssr );
769 { /* MOV.B @(R0, Rm), Rn */
770 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
771 sh4r.r[Rn] = MEM_READ_BYTE( R0 + sh4r.r[Rm] );
775 { /* MOV.W @(R0, Rm), Rn */
776 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
777 CHECKRALIGN16( R0 + sh4r.r[Rm] );
778 sh4r.r[Rn] = MEM_READ_WORD( R0 + sh4r.r[Rm] );
782 { /* MOV.L @(R0, Rm), Rn */
783 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
784 CHECKRALIGN32( R0 + sh4r.r[Rm] );
785 sh4r.r[Rn] = MEM_READ_LONG( R0 + sh4r.r[Rm] );
789 { /* MAC.L @Rm+, @Rn+ */
790 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
791 CHECKRALIGN32( sh4r.r[Rm] );
792 CHECKRALIGN32( sh4r.r[Rn] );
793 int64_t tmpl = SIGNEXT32(MEM_READ_LONG(sh4r.r[Rn]));
795 tmpl = tmpl * SIGNEXT32(MEM_READ_LONG(sh4r.r[Rm])) + sh4r.mac;
798 /* 48-bit Saturation. Yuch */
799 if( tmpl < (int64_t)0xFFFF800000000000LL )
800 tmpl = 0xFFFF800000000000LL;
801 else if( tmpl > (int64_t)0x00007FFFFFFFFFFFLL )
802 tmpl = 0x00007FFFFFFFFFFFLL;
813 { /* MOV.L Rm, @(disp, Rn) */
814 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2;
815 tmp = sh4r.r[Rn] + disp;
816 CHECKWALIGN32( tmp );
817 MEM_WRITE_LONG( tmp, sh4r.r[Rm] );
823 { /* MOV.B Rm, @Rn */
824 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
825 MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] );
829 { /* MOV.W Rm, @Rn */
830 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
831 CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] );
835 { /* MOV.L Rm, @Rn */
836 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
837 CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] );
841 { /* MOV.B Rm, @-Rn */
842 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
843 sh4r.r[Rn] --; MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] );
847 { /* MOV.W Rm, @-Rn */
848 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
849 sh4r.r[Rn] -= 2; CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] );
853 { /* MOV.L Rm, @-Rn */
854 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
855 sh4r.r[Rn] -= 4; CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] );
860 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
861 sh4r.q = sh4r.r[Rn]>>31;
862 sh4r.m = sh4r.r[Rm]>>31;
863 sh4r.t = sh4r.q ^ sh4r.m;
868 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
869 sh4r.t = (sh4r.r[Rn]&sh4r.r[Rm] ? 0 : 1);
874 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
875 sh4r.r[Rn] &= sh4r.r[Rm];
880 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
881 sh4r.r[Rn] ^= sh4r.r[Rm];
886 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
887 sh4r.r[Rn] |= sh4r.r[Rm];
891 { /* CMP/STR Rm, Rn */
892 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
893 /* set T = 1 if any byte in RM & RN is the same */
894 tmp = sh4r.r[Rm] ^ sh4r.r[Rn];
895 sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
896 (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
901 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
902 sh4r.r[Rn] = (sh4r.r[Rn]>>16) | (sh4r.r[Rm]<<16);
906 { /* MULU.W Rm, Rn */
907 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
908 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
909 (uint32_t)((sh4r.r[Rm]&0xFFFF) * (sh4r.r[Rn]&0xFFFF));
913 { /* MULS.W Rm, Rn */
914 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
915 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
916 (uint32_t)(SIGNEXT32(sh4r.r[Rm]&0xFFFF) * SIGNEXT32(sh4r.r[Rn]&0xFFFF));
927 { /* CMP/EQ Rm, Rn */
928 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
929 sh4r.t = ( sh4r.r[Rm] == sh4r.r[Rn] ? 1 : 0 );
933 { /* CMP/HS Rm, Rn */
934 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
935 sh4r.t = ( sh4r.r[Rn] >= sh4r.r[Rm] ? 1 : 0 );
939 { /* CMP/GE Rm, Rn */
940 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
941 sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= ((int32_t)sh4r.r[Rm]) ? 1 : 0 );
946 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
947 /* This is just from the sh4p manual with some
948 * simplifications (someone want to check it's correct? :)
949 * Why they couldn't just provide a real DIV instruction...
951 uint32_t tmp0, tmp1, tmp2, dir;
953 dir = sh4r.q ^ sh4r.m;
954 sh4r.q = (sh4r.r[Rn] >> 31);
956 sh4r.r[Rn] = (sh4r.r[Rn] << 1) | sh4r.t;
960 tmp1 = (sh4r.r[Rn]<tmp0 ? 1 : 0 );
963 tmp1 = (sh4r.r[Rn]>tmp0 ? 1 : 0 );
965 sh4r.q ^= sh4r.m ^ tmp1;
966 sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
970 { /* DMULU.L Rm, Rn */
971 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
972 sh4r.mac = ((uint64_t)sh4r.r[Rm]) * ((uint64_t)sh4r.r[Rn]);
976 { /* CMP/HI Rm, Rn */
977 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
978 sh4r.t = ( sh4r.r[Rn] > sh4r.r[Rm] ? 1 : 0 );
982 { /* CMP/GT Rm, Rn */
983 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
984 sh4r.t = ( ((int32_t)sh4r.r[Rn]) > ((int32_t)sh4r.r[Rm]) ? 1 : 0 );
989 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
990 sh4r.r[Rn] -= sh4r.r[Rm];
995 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
997 sh4r.r[Rn] = sh4r.r[Rn] - sh4r.r[Rm] - sh4r.t;
998 sh4r.t = (sh4r.r[Rn] > tmp || (sh4r.r[Rn] == tmp && sh4r.t == 1));
1002 UNIMP(ir); /* SUBV Rm, Rn */
1006 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1007 sh4r.r[Rn] += sh4r.r[Rm];
1011 { /* DMULS.L Rm, Rn */
1012 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1013 sh4r.mac = SIGNEXT32(sh4r.r[Rm]) * SIGNEXT32(sh4r.r[Rn]);
1018 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1020 sh4r.r[Rn] += sh4r.r[Rm] + sh4r.t;
1021 sh4r.t = ( sh4r.r[Rn] < tmp || (sh4r.r[Rn] == tmp && sh4r.t != 0) ? 1 : 0 );
1026 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1027 tmp = sh4r.r[Rn] + sh4r.r[Rm];
1028 sh4r.t = ( (sh4r.r[Rn]>>31) == (sh4r.r[Rm]>>31) && ((sh4r.r[Rn]>>31) != (tmp>>31)) );
1040 switch( (ir&0xF0) >> 4 ) {
1043 uint32_t Rn = ((ir>>8)&0xF);
1044 sh4r.t = sh4r.r[Rn] >> 31; sh4r.r[Rn] <<= 1;
1049 uint32_t Rn = ((ir>>8)&0xF);
1051 sh4r.t = ( sh4r.r[Rn] == 0 ? 1 : 0 );
1056 uint32_t Rn = ((ir>>8)&0xF);
1057 sh4r.t = sh4r.r[Rn] >> 31;
1067 switch( (ir&0xF0) >> 4 ) {
1070 uint32_t Rn = ((ir>>8)&0xF);
1071 sh4r.t = sh4r.r[Rn] & 0x00000001; sh4r.r[Rn] >>= 1;
1076 uint32_t Rn = ((ir>>8)&0xF);
1077 sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= 0 ? 1 : 0 );
1082 uint32_t Rn = ((ir>>8)&0xF);
1083 sh4r.t = sh4r.r[Rn] & 0x00000001;
1084 sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 1;
1093 switch( (ir&0xF0) >> 4 ) {
1095 { /* STS.L MACH, @-Rn */
1096 uint32_t Rn = ((ir>>8)&0xF);
1098 CHECKWALIGN32( sh4r.r[Rn] );
1099 MEM_WRITE_LONG( sh4r.r[Rn], (sh4r.mac>>32) );
1103 { /* STS.L MACL, @-Rn */
1104 uint32_t Rn = ((ir>>8)&0xF);
1106 CHECKWALIGN32( sh4r.r[Rn] );
1107 MEM_WRITE_LONG( sh4r.r[Rn], (uint32_t)sh4r.mac );
1111 { /* STS.L PR, @-Rn */
1112 uint32_t Rn = ((ir>>8)&0xF);
1114 CHECKWALIGN32( sh4r.r[Rn] );
1115 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.pr );
1119 { /* STC.L SGR, @-Rn */
1120 uint32_t Rn = ((ir>>8)&0xF);
1123 CHECKWALIGN32( sh4r.r[Rn] );
1124 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.sgr );
1128 { /* STS.L FPUL, @-Rn */
1129 uint32_t Rn = ((ir>>8)&0xF);
1131 CHECKWALIGN32( sh4r.r[Rn] );
1132 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.fpul );
1136 { /* STS.L FPSCR, @-Rn */
1137 uint32_t Rn = ((ir>>8)&0xF);
1139 CHECKWALIGN32( sh4r.r[Rn] );
1140 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.fpscr );
1144 { /* STC.L DBR, @-Rn */
1145 uint32_t Rn = ((ir>>8)&0xF);
1148 CHECKWALIGN32( sh4r.r[Rn] );
1149 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.dbr );
1158 switch( (ir&0x80) >> 7 ) {
1160 switch( (ir&0x70) >> 4 ) {
1162 { /* STC.L SR, @-Rn */
1163 uint32_t Rn = ((ir>>8)&0xF);
1166 CHECKWALIGN32( sh4r.r[Rn] );
1167 MEM_WRITE_LONG( sh4r.r[Rn], sh4_read_sr() );
1171 { /* STC.L GBR, @-Rn */
1172 uint32_t Rn = ((ir>>8)&0xF);
1174 CHECKWALIGN32( sh4r.r[Rn] );
1175 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.gbr );
1179 { /* STC.L VBR, @-Rn */
1180 uint32_t Rn = ((ir>>8)&0xF);
1183 CHECKWALIGN32( sh4r.r[Rn] );
1184 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.vbr );
1188 { /* STC.L SSR, @-Rn */
1189 uint32_t Rn = ((ir>>8)&0xF);
1192 CHECKWALIGN32( sh4r.r[Rn] );
1193 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.ssr );
1197 { /* STC.L SPC, @-Rn */
1198 uint32_t Rn = ((ir>>8)&0xF);
1201 CHECKWALIGN32( sh4r.r[Rn] );
1202 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.spc );
1211 { /* STC.L Rm_BANK, @-Rn */
1212 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7);
1215 CHECKWALIGN32( sh4r.r[Rn] );
1216 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r_bank[Rm_BANK] );
1222 switch( (ir&0xF0) >> 4 ) {
1225 uint32_t Rn = ((ir>>8)&0xF);
1226 sh4r.t = sh4r.r[Rn] >> 31;
1228 sh4r.r[Rn] |= sh4r.t;
1233 uint32_t Rn = ((ir>>8)&0xF);
1234 tmp = sh4r.r[Rn] >> 31;
1236 sh4r.r[Rn] |= sh4r.t;
1246 switch( (ir&0xF0) >> 4 ) {
1249 uint32_t Rn = ((ir>>8)&0xF);
1250 sh4r.t = sh4r.r[Rn] & 0x00000001;
1252 sh4r.r[Rn] |= (sh4r.t << 31);
1257 uint32_t Rn = ((ir>>8)&0xF);
1258 sh4r.t = ( ((int32_t)sh4r.r[Rn]) > 0 ? 1 : 0 );
1263 uint32_t Rn = ((ir>>8)&0xF);
1264 tmp = sh4r.r[Rn] & 0x00000001;
1266 sh4r.r[Rn] |= (sh4r.t << 31 );
1276 switch( (ir&0xF0) >> 4 ) {
1278 { /* LDS.L @Rm+, MACH */
1279 uint32_t Rm = ((ir>>8)&0xF);
1280 CHECKRALIGN32( sh4r.r[Rm] );
1281 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
1282 (((uint64_t)MEM_READ_LONG(sh4r.r[Rm]))<<32);
1287 { /* LDS.L @Rm+, MACL */
1288 uint32_t Rm = ((ir>>8)&0xF);
1289 CHECKRALIGN32( sh4r.r[Rm] );
1290 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
1291 (uint64_t)((uint32_t)MEM_READ_LONG(sh4r.r[Rm]));
1296 { /* LDS.L @Rm+, PR */
1297 uint32_t Rm = ((ir>>8)&0xF);
1298 CHECKRALIGN32( sh4r.r[Rm] );
1299 sh4r.pr = MEM_READ_LONG( sh4r.r[Rm] );
1304 { /* LDC.L @Rm+, SGR */
1305 uint32_t Rm = ((ir>>8)&0xF);
1307 CHECKRALIGN32( sh4r.r[Rm] );
1308 sh4r.sgr = MEM_READ_LONG(sh4r.r[Rm]);
1313 { /* LDS.L @Rm+, FPUL */
1314 uint32_t Rm = ((ir>>8)&0xF);
1315 CHECKRALIGN32( sh4r.r[Rm] );
1316 sh4r.fpul = MEM_READ_LONG(sh4r.r[Rm]);
1321 { /* LDS.L @Rm+, FPSCR */
1322 uint32_t Rm = ((ir>>8)&0xF);
1323 CHECKRALIGN32( sh4r.r[Rm] );
1324 sh4r.fpscr = MEM_READ_LONG(sh4r.r[Rm]);
1329 { /* LDC.L @Rm+, DBR */
1330 uint32_t Rm = ((ir>>8)&0xF);
1332 CHECKRALIGN32( sh4r.r[Rm] );
1333 sh4r.dbr = MEM_READ_LONG(sh4r.r[Rm]);
1343 switch( (ir&0x80) >> 7 ) {
1345 switch( (ir&0x70) >> 4 ) {
1347 { /* LDC.L @Rm+, SR */
1348 uint32_t Rm = ((ir>>8)&0xF);
1351 CHECKWALIGN32( sh4r.r[Rm] );
1352 sh4_load_sr( MEM_READ_LONG(sh4r.r[Rm]) );
1357 { /* LDC.L @Rm+, GBR */
1358 uint32_t Rm = ((ir>>8)&0xF);
1359 CHECKRALIGN32( sh4r.r[Rm] );
1360 sh4r.gbr = MEM_READ_LONG(sh4r.r[Rm]);
1365 { /* LDC.L @Rm+, VBR */
1366 uint32_t Rm = ((ir>>8)&0xF);
1368 CHECKRALIGN32( sh4r.r[Rm] );
1369 sh4r.vbr = MEM_READ_LONG(sh4r.r[Rm]);
1374 { /* LDC.L @Rm+, SSR */
1375 uint32_t Rm = ((ir>>8)&0xF);
1377 CHECKRALIGN32( sh4r.r[Rm] );
1378 sh4r.ssr = MEM_READ_LONG(sh4r.r[Rm]);
1383 { /* LDC.L @Rm+, SPC */
1384 uint32_t Rm = ((ir>>8)&0xF);
1386 CHECKRALIGN32( sh4r.r[Rm] );
1387 sh4r.spc = MEM_READ_LONG(sh4r.r[Rm]);
1397 { /* LDC.L @Rm+, Rn_BANK */
1398 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7);
1400 CHECKRALIGN32( sh4r.r[Rm] );
1401 sh4r.r_bank[Rn_BANK] = MEM_READ_LONG( sh4r.r[Rm] );
1408 switch( (ir&0xF0) >> 4 ) {
1411 uint32_t Rn = ((ir>>8)&0xF);
1417 uint32_t Rn = ((ir>>8)&0xF);
1423 uint32_t Rn = ((ir>>8)&0xF);
1433 switch( (ir&0xF0) >> 4 ) {
1436 uint32_t Rn = ((ir>>8)&0xF);
1442 uint32_t Rn = ((ir>>8)&0xF);
1448 uint32_t Rn = ((ir>>8)&0xF);
1458 switch( (ir&0xF0) >> 4 ) {
1460 { /* LDS Rm, MACH */
1461 uint32_t Rm = ((ir>>8)&0xF);
1462 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
1463 (((uint64_t)sh4r.r[Rm])<<32);
1467 { /* LDS Rm, MACL */
1468 uint32_t Rm = ((ir>>8)&0xF);
1469 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
1470 (uint64_t)((uint32_t)(sh4r.r[Rm]));
1475 uint32_t Rm = ((ir>>8)&0xF);
1476 sh4r.pr = sh4r.r[Rm];
1481 uint32_t Rm = ((ir>>8)&0xF);
1483 sh4r.sgr = sh4r.r[Rm];
1487 { /* LDS Rm, FPUL */
1488 uint32_t Rm = ((ir>>8)&0xF);
1489 sh4r.fpul = sh4r.r[Rm];
1493 { /* LDS Rm, FPSCR */
1494 uint32_t Rm = ((ir>>8)&0xF);
1495 sh4r.fpscr = sh4r.r[Rm];
1500 uint32_t Rm = ((ir>>8)&0xF);
1502 sh4r.dbr = sh4r.r[Rm];
1511 switch( (ir&0xF0) >> 4 ) {
1514 uint32_t Rn = ((ir>>8)&0xF);
1515 CHECKDEST( sh4r.r[Rn] );
1517 sh4r.in_delay_slot = 1;
1518 sh4r.pc = sh4r.new_pc;
1519 sh4r.new_pc = sh4r.r[Rn];
1521 TRACE_CALL( pc, sh4r.new_pc );
1527 uint32_t Rn = ((ir>>8)&0xF);
1528 tmp = MEM_READ_BYTE( sh4r.r[Rn] );
1529 sh4r.t = ( tmp == 0 ? 1 : 0 );
1530 MEM_WRITE_BYTE( sh4r.r[Rn], tmp | 0x80 );
1535 uint32_t Rn = ((ir>>8)&0xF);
1536 CHECKDEST( sh4r.r[Rn] );
1538 sh4r.in_delay_slot = 1;
1539 sh4r.pc = sh4r.new_pc;
1540 sh4r.new_pc = sh4r.r[Rn];
1551 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1553 if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
1554 else if( (tmp & 0x1F) == 0 )
1555 sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 31;
1557 sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> (((~sh4r.r[Rm]) & 0x1F)+1);
1562 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1564 if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
1565 else if( (tmp & 0x1F) == 0 ) sh4r.r[Rn] = 0;
1566 else sh4r.r[Rn] >>= (((~tmp) & 0x1F)+1);
1570 switch( (ir&0x80) >> 7 ) {
1572 switch( (ir&0x70) >> 4 ) {
1575 uint32_t Rm = ((ir>>8)&0xF);
1578 sh4_load_sr( sh4r.r[Rm] );
1583 uint32_t Rm = ((ir>>8)&0xF);
1584 sh4r.gbr = sh4r.r[Rm];
1589 uint32_t Rm = ((ir>>8)&0xF);
1591 sh4r.vbr = sh4r.r[Rm];
1596 uint32_t Rm = ((ir>>8)&0xF);
1598 sh4r.ssr = sh4r.r[Rm];
1603 uint32_t Rm = ((ir>>8)&0xF);
1605 sh4r.spc = sh4r.r[Rm];
1614 { /* LDC Rm, Rn_BANK */
1615 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7);
1617 sh4r.r_bank[Rn_BANK] = sh4r.r[Rm];
1623 { /* MAC.W @Rm+, @Rn+ */
1624 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1625 CHECKRALIGN16( sh4r.r[Rn] );
1626 CHECKRALIGN16( sh4r.r[Rm] );
1627 int32_t stmp = SIGNEXT16(MEM_READ_WORD(sh4r.r[Rn]));
1629 stmp = stmp * SIGNEXT16(MEM_READ_WORD(sh4r.r[Rm]));
1632 int64_t tmpl = (int64_t)((int32_t)sh4r.mac) + (int64_t)stmp;
1633 if( tmpl > (int64_t)0x000000007FFFFFFFLL ) {
1634 sh4r.mac = 0x000000017FFFFFFFLL;
1635 } else if( tmpl < (int64_t)0xFFFFFFFF80000000LL ) {
1636 sh4r.mac = 0x0000000180000000LL;
1638 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
1639 ((uint32_t)(sh4r.mac + stmp));
1642 sh4r.mac += SIGNEXT32(stmp);
1649 { /* MOV.L @(disp, Rm), Rn */
1650 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2;
1651 tmp = sh4r.r[Rm] + disp;
1652 CHECKRALIGN32( tmp );
1653 sh4r.r[Rn] = MEM_READ_LONG( tmp );
1659 { /* MOV.B @Rm, Rn */
1660 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1661 sh4r.r[Rn] = MEM_READ_BYTE( sh4r.r[Rm] );
1665 { /* MOV.W @Rm, Rn */
1666 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1667 CHECKRALIGN16( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_WORD( sh4r.r[Rm] );
1671 { /* MOV.L @Rm, Rn */
1672 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1673 CHECKRALIGN32( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_LONG( sh4r.r[Rm] );
1678 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1679 sh4r.r[Rn] = sh4r.r[Rm];
1683 { /* MOV.B @Rm+, Rn */
1684 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1685 sh4r.r[Rn] = MEM_READ_BYTE( sh4r.r[Rm] ); sh4r.r[Rm] ++;
1689 { /* MOV.W @Rm+, Rn */
1690 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1691 CHECKRALIGN16( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_WORD( sh4r.r[Rm] ); sh4r.r[Rm] += 2;
1695 { /* MOV.L @Rm+, Rn */
1696 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1697 CHECKRALIGN32( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_LONG( sh4r.r[Rm] ); sh4r.r[Rm] += 4;
1702 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1703 sh4r.r[Rn] = ~sh4r.r[Rm];
1707 { /* SWAP.B Rm, Rn */
1708 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1709 sh4r.r[Rn] = (sh4r.r[Rm]&0xFFFF0000) | ((sh4r.r[Rm]&0x0000FF00)>>8) | ((sh4r.r[Rm]&0x000000FF)<<8);
1713 { /* SWAP.W Rm, Rn */
1714 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1715 sh4r.r[Rn] = (sh4r.r[Rm]>>16) | (sh4r.r[Rm]<<16);
1720 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1721 tmp = 0 - sh4r.r[Rm];
1722 sh4r.r[Rn] = tmp - sh4r.t;
1723 sh4r.t = ( 0<tmp || tmp<sh4r.r[Rn] ? 1 : 0 );
1728 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1729 sh4r.r[Rn] = 0 - sh4r.r[Rm];
1733 { /* EXTU.B Rm, Rn */
1734 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1735 sh4r.r[Rn] = sh4r.r[Rm]&0x000000FF;
1739 { /* EXTU.W Rm, Rn */
1740 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1741 sh4r.r[Rn] = sh4r.r[Rm]&0x0000FFFF;
1745 { /* EXTS.B Rm, Rn */
1746 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1747 sh4r.r[Rn] = SIGNEXT8( sh4r.r[Rm]&0x000000FF );
1751 { /* EXTS.W Rm, Rn */
1752 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1753 sh4r.r[Rn] = SIGNEXT16( sh4r.r[Rm]&0x0000FFFF );
1759 { /* ADD #imm, Rn */
1760 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF);
1765 switch( (ir&0xF00) >> 8 ) {
1767 { /* MOV.B R0, @(disp, Rn) */
1768 uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF);
1769 MEM_WRITE_BYTE( sh4r.r[Rn] + disp, R0 );
1773 { /* MOV.W R0, @(disp, Rn) */
1774 uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1;
1775 tmp = sh4r.r[Rn] + disp;
1776 CHECKWALIGN16( tmp );
1777 MEM_WRITE_WORD( tmp, R0 );
1781 { /* MOV.B @(disp, Rm), R0 */
1782 uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF);
1783 R0 = MEM_READ_BYTE( sh4r.r[Rm] + disp );
1787 { /* MOV.W @(disp, Rm), R0 */
1788 uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1;
1789 tmp = sh4r.r[Rm] + disp;
1790 CHECKRALIGN16( tmp );
1791 R0 = MEM_READ_WORD( tmp );
1795 { /* CMP/EQ #imm, R0 */
1796 int32_t imm = SIGNEXT8(ir&0xFF);
1797 sh4r.t = ( R0 == imm ? 1 : 0 );
1802 int32_t disp = SIGNEXT8(ir&0xFF)<<1;
1805 CHECKDEST( sh4r.pc + disp + 4 )
1806 sh4r.pc += disp + 4;
1807 sh4r.new_pc = sh4r.pc + 2;
1814 int32_t disp = SIGNEXT8(ir&0xFF)<<1;
1817 CHECKDEST( sh4r.pc + disp + 4 )
1818 sh4r.pc += disp + 4;
1819 sh4r.new_pc = sh4r.pc + 2;
1826 int32_t disp = SIGNEXT8(ir&0xFF)<<1;
1829 CHECKDEST( sh4r.pc + disp + 4 )
1830 sh4r.in_delay_slot = 1;
1831 sh4r.pc = sh4r.new_pc;
1832 sh4r.new_pc = pc + disp + 4;
1833 sh4r.in_delay_slot = 1;
1840 int32_t disp = SIGNEXT8(ir&0xFF)<<1;
1843 CHECKDEST( sh4r.pc + disp + 4 )
1844 sh4r.in_delay_slot = 1;
1845 sh4r.pc = sh4r.new_pc;
1846 sh4r.new_pc = pc + disp + 4;
1857 { /* MOV.W @(disp, PC), Rn */
1858 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1;
1860 tmp = pc + 4 + disp;
1861 sh4r.r[Rn] = MEM_READ_WORD( tmp );
1866 int32_t disp = SIGNEXT12(ir&0xFFF)<<1;
1868 CHECKDEST( sh4r.pc + disp + 4 );
1869 sh4r.in_delay_slot = 1;
1870 sh4r.pc = sh4r.new_pc;
1871 sh4r.new_pc = pc + 4 + disp;
1877 int32_t disp = SIGNEXT12(ir&0xFFF)<<1;
1878 CHECKDEST( sh4r.pc + disp + 4 );
1880 sh4r.in_delay_slot = 1;
1882 sh4r.pc = sh4r.new_pc;
1883 sh4r.new_pc = pc + 4 + disp;
1884 TRACE_CALL( pc, sh4r.new_pc );
1889 switch( (ir&0xF00) >> 8 ) {
1891 { /* MOV.B R0, @(disp, GBR) */
1892 uint32_t disp = (ir&0xFF);
1893 MEM_WRITE_BYTE( sh4r.gbr + disp, R0 );
1897 { /* MOV.W R0, @(disp, GBR) */
1898 uint32_t disp = (ir&0xFF)<<1;
1899 tmp = sh4r.gbr + disp;
1900 CHECKWALIGN16( tmp );
1901 MEM_WRITE_WORD( tmp, R0 );
1905 { /* MOV.L R0, @(disp, GBR) */
1906 uint32_t disp = (ir&0xFF)<<2;
1907 tmp = sh4r.gbr + disp;
1908 CHECKWALIGN32( tmp );
1909 MEM_WRITE_LONG( tmp, R0 );
1914 uint32_t imm = (ir&0xFF);
1916 MMIO_WRITE( MMU, TRA, imm<<2 );
1918 sh4_raise_exception( EXC_TRAP );
1922 { /* MOV.B @(disp, GBR), R0 */
1923 uint32_t disp = (ir&0xFF);
1924 R0 = MEM_READ_BYTE( sh4r.gbr + disp );
1928 { /* MOV.W @(disp, GBR), R0 */
1929 uint32_t disp = (ir&0xFF)<<1;
1930 tmp = sh4r.gbr + disp;
1931 CHECKRALIGN16( tmp );
1932 R0 = MEM_READ_WORD( tmp );
1936 { /* MOV.L @(disp, GBR), R0 */
1937 uint32_t disp = (ir&0xFF)<<2;
1938 tmp = sh4r.gbr + disp;
1939 CHECKRALIGN32( tmp );
1940 R0 = MEM_READ_LONG( tmp );
1944 { /* MOVA @(disp, PC), R0 */
1945 uint32_t disp = (ir&0xFF)<<2;
1947 R0 = (pc&0xFFFFFFFC) + disp + 4;
1951 { /* TST #imm, R0 */
1952 uint32_t imm = (ir&0xFF);
1953 sh4r.t = (R0 & imm ? 0 : 1);
1957 { /* AND #imm, R0 */
1958 uint32_t imm = (ir&0xFF);
1963 { /* XOR #imm, R0 */
1964 uint32_t imm = (ir&0xFF);
1970 uint32_t imm = (ir&0xFF);
1975 { /* TST.B #imm, @(R0, GBR) */
1976 uint32_t imm = (ir&0xFF);
1977 sh4r.t = ( MEM_READ_BYTE(R0 + sh4r.gbr) & imm ? 0 : 1 );
1981 { /* AND.B #imm, @(R0, GBR) */
1982 uint32_t imm = (ir&0xFF);
1983 MEM_WRITE_BYTE( R0 + sh4r.gbr, imm & MEM_READ_BYTE(R0 + sh4r.gbr) );
1987 { /* XOR.B #imm, @(R0, GBR) */
1988 uint32_t imm = (ir&0xFF);
1989 MEM_WRITE_BYTE( R0 + sh4r.gbr, imm ^ MEM_READ_BYTE(R0 + sh4r.gbr) );
1993 { /* OR.B #imm, @(R0, GBR) */
1994 uint32_t imm = (ir&0xFF);
1995 MEM_WRITE_BYTE( R0 + sh4r.gbr, imm | MEM_READ_BYTE(R0 + sh4r.gbr) );
2001 { /* MOV.L @(disp, PC), Rn */
2002 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<2;
2004 tmp = (pc&0xFFFFFFFC) + disp + 4;
2005 sh4r.r[Rn] = MEM_READ_LONG( tmp );
2009 { /* MOV #imm, Rn */
2010 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF);
2017 { /* FADD FRm, FRn */
2018 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
2020 if( IS_FPU_DOUBLEPREC() ) {
2028 { /* FSUB FRm, FRn */
2029 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
2031 if( IS_FPU_DOUBLEPREC() ) {
2039 { /* FMUL FRm, FRn */
2040 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
2042 if( IS_FPU_DOUBLEPREC() ) {
2050 { /* FDIV FRm, FRn */
2051 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
2053 if( IS_FPU_DOUBLEPREC() ) {
2061 { /* FCMP/EQ FRm, FRn */
2062 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
2064 if( IS_FPU_DOUBLEPREC() ) {
2065 sh4r.t = ( DR(FRn) == DR(FRm) ? 1 : 0 );
2067 sh4r.t = ( FR(FRn) == FR(FRm) ? 1 : 0 );
2072 { /* FCMP/GT FRm, FRn */
2073 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
2075 if( IS_FPU_DOUBLEPREC() ) {
2076 sh4r.t = ( DR(FRn) > DR(FRm) ? 1 : 0 );
2078 sh4r.t = ( FR(FRn) > FR(FRm) ? 1 : 0 );
2083 { /* FMOV @(R0, Rm), FRn */
2084 uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
2085 MEM_FP_READ( sh4r.r[Rm] + R0, FRn );
2089 { /* FMOV FRm, @(R0, Rn) */
2090 uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
2091 MEM_FP_WRITE( sh4r.r[Rn] + R0, FRm );
2095 { /* FMOV @Rm, FRn */
2096 uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
2097 MEM_FP_READ( sh4r.r[Rm], FRn );
2101 { /* FMOV @Rm+, FRn */
2102 uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
2103 MEM_FP_READ( sh4r.r[Rm], FRn ); sh4r.r[Rm] += FP_WIDTH;
2107 { /* FMOV FRm, @Rn */
2108 uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
2109 MEM_FP_WRITE( sh4r.r[Rn], FRm );
2113 { /* FMOV FRm, @-Rn */
2114 uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
2115 sh4r.r[Rn] -= FP_WIDTH; MEM_FP_WRITE( sh4r.r[Rn], FRm );
2119 { /* FMOV FRm, FRn */
2120 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
2121 if( IS_FPU_DOUBLESIZE() )
2128 switch( (ir&0xF0) >> 4 ) {
2130 { /* FSTS FPUL, FRn */
2131 uint32_t FRn = ((ir>>8)&0xF);
2132 CHECKFPUEN(); FR(FRn) = FPULf;
2136 { /* FLDS FRm, FPUL */
2137 uint32_t FRm = ((ir>>8)&0xF);
2138 CHECKFPUEN(); FPULf = FR(FRm);
2142 { /* FLOAT FPUL, FRn */
2143 uint32_t FRn = ((ir>>8)&0xF);
2145 if( IS_FPU_DOUBLEPREC() )
2146 DR(FRn) = (float)FPULi;
2148 FR(FRn) = (float)FPULi;
2152 { /* FTRC FRm, FPUL */
2153 uint32_t FRm = ((ir>>8)&0xF);
2155 if( IS_FPU_DOUBLEPREC() ) {
2157 if( dtmp >= MAX_INTF )
2159 else if( dtmp <= MIN_INTF )
2162 FPULi = (int32_t)dtmp;
2165 if( ftmp >= MAX_INTF )
2167 else if( ftmp <= MIN_INTF )
2170 FPULi = (int32_t)ftmp;
2176 uint32_t FRn = ((ir>>8)&0xF);
2178 if( IS_FPU_DOUBLEPREC() ) {
2187 uint32_t FRn = ((ir>>8)&0xF);
2189 if( IS_FPU_DOUBLEPREC() ) {
2190 DR(FRn) = fabs(DR(FRn));
2192 FR(FRn) = fabsf(FR(FRn));
2198 uint32_t FRn = ((ir>>8)&0xF);
2200 if( IS_FPU_DOUBLEPREC() ) {
2201 DR(FRn) = sqrt(DR(FRn));
2203 FR(FRn) = sqrtf(FR(FRn));
2209 uint32_t FRn = ((ir>>8)&0xF);
2211 if( !IS_FPU_DOUBLEPREC() ) {
2212 FR(FRn) = 1.0/sqrtf(FR(FRn));
2218 uint32_t FRn = ((ir>>8)&0xF);
2220 if( IS_FPU_DOUBLEPREC() ) {
2229 uint32_t FRn = ((ir>>8)&0xF);
2231 if( IS_FPU_DOUBLEPREC() ) {
2239 { /* FCNVSD FPUL, FRn */
2240 uint32_t FRn = ((ir>>8)&0xF);
2242 if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
2243 DR(FRn) = (double)FPULf;
2248 { /* FCNVDS FRm, FPUL */
2249 uint32_t FRm = ((ir>>8)&0xF);
2251 if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
2252 FPULf = (float)DR(FRm);
2257 { /* FIPR FVm, FVn */
2258 uint32_t FVn = ((ir>>10)&0x3); uint32_t FVm = ((ir>>8)&0x3);
2260 if( !IS_FPU_DOUBLEPREC() ) {
2263 FR(tmp2+3) = FR(tmp)*FR(tmp2) +
2264 FR(tmp+1)*FR(tmp2+1) +
2265 FR(tmp+2)*FR(tmp2+2) +
2266 FR(tmp+3)*FR(tmp2+3);
2271 switch( (ir&0x100) >> 8 ) {
2273 { /* FSCA FPUL, FRn */
2274 uint32_t FRn = ((ir>>9)&0x7)<<1;
2276 if( !IS_FPU_DOUBLEPREC() ) {
2277 float angle = (((float)(FPULi&0xFFFF))/65536.0) * 2 * M_PI;
2278 FR(FRn) = sinf(angle);
2279 FR((FRn)+1) = cosf(angle);
2284 switch( (ir&0x200) >> 9 ) {
2286 { /* FTRV XMTRX, FVn */
2287 uint32_t FVn = ((ir>>10)&0x3);
2289 if( !IS_FPU_DOUBLEPREC() ) {
2291 float fv[4] = { FR(tmp), FR(tmp+1), FR(tmp+2), FR(tmp+3) };
2292 FR(tmp) = XF(0) * fv[0] + XF(4)*fv[1] +
2293 XF(8)*fv[2] + XF(12)*fv[3];
2294 FR(tmp+1) = XF(1) * fv[0] + XF(5)*fv[1] +
2295 XF(9)*fv[2] + XF(13)*fv[3];
2296 FR(tmp+2) = XF(2) * fv[0] + XF(6)*fv[1] +
2297 XF(10)*fv[2] + XF(14)*fv[3];
2298 FR(tmp+3) = XF(3) * fv[0] + XF(7)*fv[1] +
2299 XF(11)*fv[2] + XF(15)*fv[3];
2304 switch( (ir&0xC00) >> 10 ) {
2307 CHECKFPUEN(); sh4r.fpscr ^= FPSCR_SZ;
2312 CHECKFPUEN(); sh4r.fpscr ^= FPSCR_FR;
2335 { /* FMAC FR0, FRm, FRn */
2336 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
2338 if( IS_FPU_DOUBLEPREC() ) {
2339 DR(FRn) += DR(FRm)*DR(0);
2341 FR(FRn) += FR(FRm)*FR(0);
2352 sh4r.pc = sh4r.new_pc;
2354 sh4r.in_delay_slot = 0;
.