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lxdream.org :: lxdream/src/asic.c
lxdream 0.9.1
released Jun 29
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filename src/asic.c
changeset 155:be61d1a20937
prev137:41907543d890
next158:a0a82246b44e
author nkeynes
date Wed May 24 11:50:19 2006 +0000 (14 years ago)
permissions -rw-r--r--
last change Add load/save/reset state, and general tidy up
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     1 /**
     2  * $Id: asic.c,v 1.15 2006-05-24 11:50:19 nkeynes Exp $
     3  *
     4  * Support for the miscellaneous ASIC functions (Primarily event multiplexing,
     5  * and DMA). 
     6  *
     7  * Copyright (c) 2005 Nathan Keynes.
     8  *
     9  * This program is free software; you can redistribute it and/or modify
    10  * it under the terms of the GNU General Public License as published by
    11  * the Free Software Foundation; either version 2 of the License, or
    12  * (at your option) any later version.
    13  *
    14  * This program is distributed in the hope that it will be useful,
    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17  * GNU General Public License for more details.
    18  */
    20 #define MODULE asic_module
    22 #include <assert.h>
    23 #include <stdlib.h>
    24 #include "dream.h"
    25 #include "mem.h"
    26 #include "sh4/intc.h"
    27 #include "sh4/dmac.h"
    28 #include "dreamcast.h"
    29 #include "maple/maple.h"
    30 #include "gdrom/ide.h"
    31 #include "asic.h"
    32 #define MMIO_IMPL
    33 #include "asic.h"
    34 /*
    35  * Open questions:
    36  *   1) Does changing the mask after event occurance result in the
    37  *      interrupt being delivered immediately?
    38  * TODO: Logic diagram of ASIC event/interrupt logic.
    39  *
    40  * ... don't even get me started on the "EXTDMA" page, about which, apparently,
    41  * practically nothing is publicly known...
    42  */
    44 static void asic_check_cleared_events( void );
    45 static void asic_init( void );
    46 static void asic_reset( void );
    47 static void asic_save_state( FILE *f );
    48 static int asic_load_state( FILE *f );
    50 struct dreamcast_module asic_module = { "ASIC", asic_init, asic_reset, NULL, NULL,
    51 					NULL, asic_save_state, asic_load_state };
    53 #define G2_BIT5_TICKS 8
    54 #define G2_BIT4_TICKS 16
    55 #define G2_BIT0_ON_TICKS 24
    56 #define G2_BIT0_OFF_TICKS 24
    58 struct asic_g2_state {
    59     unsigned int bit5_off_timer;
    60     unsigned int bit4_on_timer;
    61     unsigned int bit4_off_timer;
    62     unsigned int bit0_on_timer;
    63     unsigned int bit0_off_timer;
    64 };
    66 static struct asic_g2_state g2_state;
    68 static void asic_init( void )
    69 {
    70     register_io_region( &mmio_region_ASIC );
    71     register_io_region( &mmio_region_EXTDMA );
    72     mmio_region_ASIC.trace_flag = 0; /* Because this is called so often */
    73     asic_reset();
    74 }
    76 static void asic_reset( void )
    77 {
    78     memset( &g2_state, 0, sizeof(g2_state) );
    79 }    
    81 static void asic_save_state( FILE *f )
    82 {
    83     fwrite( &g2_state, sizeof(g2_state), 1, f );
    84 }
    86 static int asic_load_state( FILE *f )
    87 {
    88     if( fread( &g2_state, sizeof(g2_state), 1, f ) != 1 )
    89 	return 1;
    90     else
    91 	return 0;
    92 }
    95 /* FIXME: Handle rollover */
    96 void asic_g2_write_word()
    97 {
    98     g2_state.bit5_off_timer = sh4r.icount + G2_BIT5_TICKS;
    99     if( g2_state.bit4_off_timer < sh4r.icount )
   100 	g2_state.bit4_on_timer = sh4r.icount + G2_BIT5_TICKS;
   101     g2_state.bit4_off_timer = max(sh4r.icount,g2_state.bit4_off_timer) + G2_BIT4_TICKS;
   102     if( g2_state.bit0_off_timer < sh4r.icount ) {
   103 	g2_state.bit0_on_timer = sh4r.icount + G2_BIT0_ON_TICKS;
   104 	g2_state.bit0_off_timer = g2_state.bit0_on_timer + G2_BIT0_OFF_TICKS;
   105     } else {
   106 	g2_state.bit0_off_timer += G2_BIT0_OFF_TICKS;
   107     }
   108     MMIO_WRITE( ASIC, G2STATUS, MMIO_READ(ASIC, G2STATUS) | 0x20 );
   109 }
   111 static uint32_t g2_read_status()
   112 {
   113     uint32_t val = MMIO_READ( ASIC, G2STATUS );
   114     if( g2_state.bit5_off_timer <= sh4r.icount )
   115 	val = val & (~0x20);
   116     if( g2_state.bit4_off_timer <= sh4r.icount )
   117 	val = val & (~0x10);
   118     else if( g2_state.bit4_on_timer <= sh4r.icount )
   119 	val = val | 0x10;
   120     if( g2_state.bit0_off_timer <= sh4r.icount )
   121 	val = val & (~0x01);
   122     else if( g2_state.bit0_on_timer <= sh4r.icount )
   123 	val = val | 0x01;
   124     return val | 0x0E;
   125 }   
   128 void asic_event( int event )
   129 {
   130     int offset = ((event&0x60)>>3);
   131     int result = (MMIO_READ(ASIC, PIRQ0 + offset))  |=  (1<<(event&0x1F));
   133     if( result & MMIO_READ(ASIC, IRQA0 + offset) )
   134         intc_raise_interrupt( INT_IRQ13 );
   135     if( result & MMIO_READ(ASIC, IRQB0 + offset) )
   136         intc_raise_interrupt( INT_IRQ11 );
   137     if( result & MMIO_READ(ASIC, IRQC0 + offset) )
   138         intc_raise_interrupt( INT_IRQ9 );
   139 }
   141 void asic_clear_event( int event ) {
   142     int offset = ((event&0x60)>>3);
   143     uint32_t result = MMIO_READ(ASIC, PIRQ0 + offset)  & (~(1<<(event&0x1F)));
   144     MMIO_WRITE( ASIC, PIRQ0 + offset, result );
   146     asic_check_cleared_events();
   147 }
   149 void asic_check_cleared_events( )
   150 {
   151     int i, setA = 0, setB = 0, setC = 0;
   152     uint32_t bits;
   153     for( i=0; i<3; i++ ) {
   154 	bits = MMIO_READ( ASIC, PIRQ0 + i );
   155 	setA |= (bits & MMIO_READ(ASIC, IRQA0 + i ));
   156 	setB |= (bits & MMIO_READ(ASIC, IRQB0 + i ));
   157 	setC |= (bits & MMIO_READ(ASIC, IRQC0 + i ));
   158     }
   159     if( setA == 0 )
   160 	intc_clear_interrupt( INT_IRQ13 );
   161     if( setB == 0 )
   162 	intc_clear_interrupt( INT_IRQ11 );
   163     if( setC == 0 )
   164 	intc_clear_interrupt( INT_IRQ9 );
   165 }
   168 void asic_ide_dma_transfer( )
   169 {	
   170     if( MMIO_READ( EXTDMA, IDEDMACTL2 ) == 1 &&
   171 	MMIO_READ( EXTDMA, IDEDMACTL1 ) == 0 ) {
   172 	uint32_t addr = MMIO_READ( EXTDMA, IDEDMASH4 );
   173 	uint32_t length = MMIO_READ( EXTDMA, IDEDMASIZ );
   174 	int dir = MMIO_READ( EXTDMA, IDEDMADIR );
   176 	uint32_t xfer = ide_read_data_dma( addr, length );
   177 	if( xfer != 0 ) {
   178 	    MMIO_WRITE( EXTDMA, IDEDMASH4, addr + xfer );
   179 	    MMIO_WRITE( EXTDMA, IDEDMASIZ, length - xfer );
   180 	    if( xfer == length ) {
   181 		MMIO_WRITE( EXTDMA, IDEDMACTL2, 0 );
   182 		asic_event( EVENT_IDE_DMA );
   183 	    }
   184 	}
   185     }
   187 }
   190 void mmio_region_ASIC_write( uint32_t reg, uint32_t val )
   191 {
   192     switch( reg ) {
   193     case PIRQ1:
   194 	val = val & 0xFFFFFFFE; /* Prevent the IDE event from clearing */
   195 	/* fallthrough */
   196     case PIRQ0:
   197     case PIRQ2:
   198 	/* Clear any interrupts */
   199 	MMIO_WRITE( ASIC, reg, MMIO_READ(ASIC, reg)&~val );
   200 	asic_check_cleared_events();
   201 	break;
   202     case MAPLE_STATE:
   203 	MMIO_WRITE( ASIC, reg, val );
   204 	if( val & 1 ) {
   205 	    uint32_t maple_addr = MMIO_READ( ASIC, MAPLE_DMA) &0x1FFFFFE0;
   206 	    // WARN( "Maple request initiated at %08X, halting", maple_addr );
   207 	    maple_handle_buffer( maple_addr );
   208 	    MMIO_WRITE( ASIC, reg, 0 );
   209 	}
   210 	break;
   211     case PVRDMACTL: /* Initiate PVR DMA transfer */
   212 	MMIO_WRITE( ASIC, reg, val );
   213 	if( val & 1 ) {
   214 	    uint32_t dest_addr = MMIO_READ( ASIC, PVRDMADEST) &0x1FFFFFE0;
   215 	    uint32_t count = MMIO_READ( ASIC, PVRDMACNT );
   216 	    char *data = alloca( count );
   217 	    uint32_t rcount = DMAC_get_buffer( 2, data, count );
   218 	    if( rcount != count )
   219 		WARN( "PVR received %08X bytes from DMA, expected %08X", rcount, count );
   220 	    mem_copy_to_sh4( dest_addr, data, rcount );
   221 	    asic_event( EVENT_PVR_DMA );
   222 	}
   223 	break;
   224     default:
   225 	MMIO_WRITE( ASIC, reg, val );
   226 	WARN( "Write to ASIC (%03X <= %08X) [%s: %s]",
   227 	      reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );
   228     }
   229 }
   231 int32_t mmio_region_ASIC_read( uint32_t reg )
   232 {
   233     int32_t val;
   234     switch( reg ) {
   235         /*
   236         case 0x89C:
   237             sh4_stop();
   238             return 0x000000B;
   239         */     
   240     case PIRQ0:
   241     case PIRQ1:
   242     case PIRQ2:
   243     case IRQA0:
   244     case IRQA1:
   245     case IRQA2:
   246     case IRQB0:
   247     case IRQB1:
   248     case IRQB2:
   249     case IRQC0:
   250     case IRQC1:
   251     case IRQC2:
   252 	val = MMIO_READ(ASIC, reg);
   253 	//            WARN( "Read from ASIC (%03X => %08X) [%s: %s]",
   254 	//                  reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );
   255 	return val;            
   256     case G2STATUS:
   257 	return g2_read_status();
   258     default:
   259 	val = MMIO_READ(ASIC, reg);
   260 	WARN( "Read from ASIC (%03X => %08X) [%s: %s]",
   261 	      reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );
   262 	return val;
   263     }
   265 }
   267 MMIO_REGION_WRITE_FN( EXTDMA, reg, val )
   268 {
   269     WARN( "EXTDMA write %08X <= %08X", reg, val );
   271     switch( reg ) {
   272     case IDEALTSTATUS: /* Device control */
   273 	ide_write_control( val );
   274 	break;
   275     case IDEDATA:
   276 	ide_write_data_pio( val );
   277 	break;
   278     case IDEFEAT:
   279 	if( ide_can_write_regs() )
   280 	    idereg.feature = (uint8_t)val;
   281 	break;
   282     case IDECOUNT:
   283 	if( ide_can_write_regs() )
   284 	    idereg.count = (uint8_t)val;
   285 	break;
   286     case IDELBA0:
   287 	if( ide_can_write_regs() )
   288 	    idereg.lba0 = (uint8_t)val;
   289 	break;
   290     case IDELBA1:
   291 	if( ide_can_write_regs() )
   292 	    idereg.lba1 = (uint8_t)val;
   293 	break;
   294     case IDELBA2:
   295 	if( ide_can_write_regs() )
   296 	    idereg.lba2 = (uint8_t)val;
   297 	break;
   298     case IDEDEV:
   299 	if( ide_can_write_regs() )
   300 	    idereg.device = (uint8_t)val;
   301 	break;
   302     case IDECMD:
   303 	if( ide_can_write_regs() ) {
   304 	    ide_write_command( (uint8_t)val );
   305 	}
   306 	break;
   307     case IDEDMACTL1:
   308 	MMIO_WRITE( EXTDMA, reg, val );
   309     case IDEDMACTL2:
   310 	MMIO_WRITE( EXTDMA, reg, val );
   311 	asic_ide_dma_transfer( );
   312 	break;
   313     default:
   314             MMIO_WRITE( EXTDMA, reg, val );
   315     }
   316 }
   318 MMIO_REGION_READ_FN( EXTDMA, reg )
   319 {
   320     uint32_t val;
   321     switch( reg ) {
   322         case IDEALTSTATUS: return idereg.status;
   323         case IDEDATA: return ide_read_data_pio( );
   324         case IDEFEAT: return idereg.error;
   325         case IDECOUNT:return idereg.count;
   326         case IDELBA0: return idereg.disc;
   327         case IDELBA1: return idereg.lba1;
   328         case IDELBA2: return idereg.lba2;
   329         case IDEDEV: return idereg.device;
   330         case IDECMD:
   331 	    return ide_read_status();
   332         default:
   333 	    val = MMIO_READ( EXTDMA, reg );
   334 	    //DEBUG( "EXTDMA read %08X => %08X", reg, val );
   335 	    return val;
   336     }
   337 }
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