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lxdream.org :: lxdream/src/sh4/sh4core.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4core.c
changeset 32:bf0bc2c524b8
prev30:89b30313d757
next35:21a4be098304
author nkeynes
date Mon Dec 26 03:10:23 2005 +0000 (14 years ago)
permissions -rw-r--r--
last change Reset SCIF properly on SH4 reset
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     1 /**
     2  * $Id: sh4core.c,v 1.12 2005-12-26 03:10:23 nkeynes Exp $
     3  * 
     4  * SH4 emulation core, and parent module for all the SH4 peripheral
     5  * modules.
     6  *
     7  * Copyright (c) 2005 Nathan Keynes.
     8  *
     9  * This program is free software; you can redistribute it and/or modify
    10  * it under the terms of the GNU General Public License as published by
    11  * the Free Software Foundation; either version 2 of the License, or
    12  * (at your option) any later version.
    13  *
    14  * This program is distributed in the hope that it will be useful,
    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17  * GNU General Public License for more details.
    18  */
    20 #include <math.h>
    21 #include "dream.h"
    22 #include "modules.h"
    23 #include "sh4core.h"
    24 #include "sh4mmio.h"
    25 #include "mem.h"
    26 #include "clock.h"
    27 #include "intc.h"
    29 /* CPU-generated exception code/vector pairs */
    30 #define EXC_POWER_RESET  0x000 /* vector special */
    31 #define EXC_MANUAL_RESET 0x020
    32 #define EXC_SLOT_ILLEGAL 0x1A0
    33 #define EXC_ILLEGAL      0x180
    34 #define EXV_ILLEGAL      0x100
    35 #define EXC_TRAP         0x160
    36 #define EXV_TRAP         0x100
    37 #define EXC_FPDISABLE    0x800
    38 #define EXV_FPDISABLE    0x100
    40 uint32_t sh4_freq = SH4_BASE_RATE;
    41 uint32_t sh4_bus_freq = SH4_BASE_RATE;
    42 uint32_t sh4_peripheral_freq = SH4_BASE_RATE / 2;
    44 uint32_t sh4_cpu_period = 1000 / SH4_BASE_RATE; /* in nanoseconds */
    45 uint32_t sh4_bus_period = 1000 / SH4_BASE_RATE;
    46 uint32_t sh4_peripheral_period = 2000 / SH4_BASE_RATE;
    48 /********************** SH4 Module Definition ****************************/
    50 void sh4_init( void );
    51 void sh4_reset( void );
    52 uint32_t sh4_run_slice( uint32_t );
    53 void sh4_start( void );
    54 void sh4_stop( void );
    55 void sh4_save_state( FILE *f );
    56 int sh4_load_state( FILE *f );
    58 struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset, 
    59 				       NULL, sh4_run_slice, sh4_stop,
    60 				       sh4_save_state, sh4_load_state };
    62 struct sh4_registers sh4r;
    64 void sh4_init(void)
    65 {
    66     register_io_regions( mmio_list_sh4mmio );
    67     mmu_init();
    68     sh4_reset();
    69 }
    71 void sh4_reset(void)
    72 {
    73     /* zero everything out, for the sake of having a consistent state. */
    74     memset( &sh4r, 0, sizeof(sh4r) );
    76     /* Resume running if we were halted */
    77     sh4r.sh4_state = SH4_STATE_RUNNING;
    79     sh4r.pc    = 0xA0000000;
    80     sh4r.new_pc= 0xA0000002;
    81     sh4r.vbr   = 0x00000000;
    82     sh4r.fpscr = 0x00040001;
    83     sh4r.sr    = 0x700000F0;
    85     /* Mem reset will do this, but if we want to reset _just_ the SH4... */
    86     MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
    88     /* Peripheral modules */
    89     intc_reset();
    90     SCIF_reset();
    91 }
    93 uint32_t sh4_run_slice( uint32_t nanosecs ) 
    94 {
    95     int target = sh4r.icount + nanosecs / sh4_cpu_period;
    96     int start = sh4r.icount;
    97     int i;
    99     if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
   100 	if( sh4r.int_pending != 0 )
   101 	    sh4r.sh4_state = SH4_STATE_RUNNING;;
   102     }
   104     while( sh4r.icount < target && sh4r.sh4_state == SH4_STATE_RUNNING ) {
   105 	sh4r.icount++;
   106 	if( !sh4_execute_instruction() )
   107 	    break;
   108     }
   110     /* If we aborted early, but the cpu is still technically running,
   111      * we're doing a hard abort - cut the timeslice back to what we
   112      * actually executed
   113      */
   114     if( target != sh4r.icount && sh4r.sh4_state == SH4_STATE_RUNNING ) {
   115 	/* Halted - compute time actually executed */
   116 	nanosecs = (sh4r.icount - start) * sh4_cpu_period;
   117     }
   118     if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
   119 	TMU_run_slice( nanosecs );
   120 	SCIF_run_slice( nanosecs );
   121     }
   122     return nanosecs;
   123 }
   125 void sh4_stop(void)
   126 {
   128 }
   130 void sh4_save_state( FILE *f )
   131 {
   132     fwrite( &sh4r, sizeof(sh4r), 1, f );
   133     SCIF_save_state( f );
   134 }
   136 int sh4_load_state( FILE * f )
   137 {
   138     fread( &sh4r, sizeof(sh4r), 1, f );
   139     return SCIF_load_state( f );
   140 }
   142 /********************** SH4 emulation core  ****************************/
   144 void sh4_set_pc( int pc )
   145 {
   146     sh4r.pc = pc;
   147     sh4r.new_pc = pc+2;
   148 }
   150 void sh4_set_breakpoint( uint32_t pc, int type )
   151 {
   153 }
   155 #define UNDEF(ir) do{ ERROR( "Raising exception on undefined instruction at %08x, opcode = %04x", sh4r.pc, ir ); RAISE( EXC_ILLEGAL, EXV_ILLEGAL ); }while(0)
   156 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)
   158 #define RAISE( x, v ) do{ \
   159     if( sh4r.vbr == 0 ) { \
   160         ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
   161         sh4_stop(); \
   162     } else { \
   163         sh4r.spc = sh4r.pc + 2; \
   164         sh4r.ssr = sh4_read_sr(); \
   165         sh4r.sgr = sh4r.r[15]; \
   166         MMIO_WRITE(MMU,EXPEVT,x); \
   167         sh4r.pc = sh4r.vbr + v; \
   168         sh4r.new_pc = sh4r.pc + 2; \
   169         sh4_load_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
   170     } \
   171     return TRUE; } while(0)
   173 #define MEM_READ_BYTE( addr ) sh4_read_byte(addr)
   174 #define MEM_READ_WORD( addr ) sh4_read_word(addr)
   175 #define MEM_READ_LONG( addr ) sh4_read_long(addr)
   176 #define MEM_WRITE_BYTE( addr, val ) sh4_write_byte(addr, val)
   177 #define MEM_WRITE_WORD( addr, val ) sh4_write_word(addr, val)
   178 #define MEM_WRITE_LONG( addr, val ) sh4_write_long(addr, val)
   180 #define MEM_FP_READ( addr, reg ) if( IS_FPU_DOUBLESIZE() ) { \
   181     ((uint32_t *)FR)[(reg)&0xE0] = sh4_read_long(addr); \
   182     ((uint32_t *)FR)[(reg)|1] = sh4_read_long(addr+4); \
   183 } else ((uint32_t *)FR)[reg] = sh4_read_long(addr)
   185 #define MEM_FP_WRITE( addr, reg ) if( IS_FPU_DOUBLESIZE() ) { \
   186     sh4_write_long( addr, ((uint32_t *)FR)[(reg)&0xE0] ); \
   187     sh4_write_long( addr+4, ((uint32_t *)FR)[(reg)|1] ); \
   188 } else sh4_write_long( addr, ((uint32_t *)FR)[reg] )
   190 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
   192 #define CHECK( x, c, v ) if( !x ) RAISE( c, v )
   193 #define CHECKPRIV() CHECK( IS_SH4_PRIVMODE(), EXC_ILLEGAL, EXV_ILLEGAL )
   194 #define CHECKFPUEN() CHECK( IS_FPU_ENABLED(), EXC_FPDISABLE, EXV_FPDISABLE )
   195 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); sh4_stop(); return; }
   196 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) { RAISE(EXC_SLOT_ILLEGAL,EXV_ILLEGAL); }
   198 static void sh4_switch_banks( )
   199 {
   200     uint32_t tmp[8];
   202     memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
   203     memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
   204     memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
   205 }
   207 static void sh4_load_sr( uint32_t newval )
   208 {
   209     if( (newval ^ sh4r.sr) & SR_RB )
   210         sh4_switch_banks();
   211     sh4r.sr = newval;
   212     sh4r.t = (newval&SR_T) ? 1 : 0;
   213     sh4r.s = (newval&SR_S) ? 1 : 0;
   214     sh4r.m = (newval&SR_M) ? 1 : 0;
   215     sh4r.q = (newval&SR_Q) ? 1 : 0;
   216     intc_mask_changed();
   217 }
   219 static uint32_t sh4_read_sr( void )
   220 {
   221     /* synchronize sh4r.sr with the various bitflags */
   222     sh4r.sr &= SR_MQSTMASK;
   223     if( sh4r.t ) sh4r.sr |= SR_T;
   224     if( sh4r.s ) sh4r.sr |= SR_S;
   225     if( sh4r.m ) sh4r.sr |= SR_M;
   226     if( sh4r.q ) sh4r.sr |= SR_Q;
   227     return sh4r.sr;
   228 }
   229 /* function for external use */
   230 void sh4_raise_exception( int code, int vector )
   231 {
   232     RAISE(code, vector);
   233 }
   235 static void sh4_accept_interrupt( void )
   236 {
   237     uint32_t code = intc_accept_interrupt();
   238     sh4r.ssr = sh4_read_sr();
   239     sh4r.spc = sh4r.pc;
   240     sh4r.sgr = sh4r.r[15];
   241     sh4_load_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
   242     MMIO_WRITE( MMU, INTEVT, code );
   243     sh4r.pc = sh4r.vbr + 0x600;
   244     sh4r.new_pc = sh4r.pc + 2;
   245     WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
   246 }
   248 gboolean sh4_execute_instruction( void )
   249 {
   250     int pc;
   251     unsigned short ir;
   252     uint32_t tmp;
   253     uint64_t tmpl;
   255 #define R0 sh4r.r[0]
   256 #define FR0 (FR[0])
   257 #define RN(ir) sh4r.r[(ir&0x0F00)>>8]
   258 #define RN_BANK(ir) sh4r.r_bank[(ir&0x0070)>>4]
   259 #define RM(ir) sh4r.r[(ir&0x00F0)>>4]
   260 #define DISP4(ir) (ir&0x000F) /* 4-bit displacements are *NOT* sign-extended */
   261 #define DISP8(ir) (ir&0x00FF)
   262 #define PCDISP8(ir) SIGNEXT8(ir&0x00FF)
   263 #define IMM8(ir) SIGNEXT8(ir&0x00FF)
   264 #define UIMM8(ir) (ir&0x00FF) /* Unsigned immmediate */
   265 #define DISP12(ir) SIGNEXT12(ir&0x0FFF)
   266 #define FVN(ir) ((ir&0x0C00)>>8)
   267 #define FVM(ir) ((ir&0x0300)>>6)
   268 #define FRN(ir) (FR[(ir&0x0F00)>>8])
   269 #define FRM(ir) (FR[(ir&0x00F0)>>4])
   270 #define FRNi(ir) (((uint32_t *)FR)[(ir&0x0F00)>>8])
   271 #define FRMi(ir) (((uint32_t *)FR)[(ir&0x00F0)>>4])
   272 #define DRN(ir) (((double *)FR)[(ir&0x0E00)>>9])
   273 #define DRM(ir) (((double *)FR)[(ir&0x00E0)>>5])
   274 #define DRNi(ir) (((uint64_t *)FR)[(ir&0x0E00)>>9])
   275 #define DRMi(ir) (((uint64_t *)FR)[(ir&0x00E0)>>5])
   276 #define FRNn(ir) ((ir&0x0F00)>>8)
   277 #define FRMn(ir) ((ir&0x00F0)>>4)
   278 #define FPULf   *((float *)&sh4r.fpul)
   279 #define FPULi    (sh4r.fpul)
   281     if( SH4_INT_PENDING() ) 
   282         sh4_accept_interrupt();
   284     pc = sh4r.pc;
   285     ir = MEM_READ_WORD(pc);
   286     sh4r.icount++;
   288     switch( (ir&0xF000)>>12 ) {
   289         case 0: /* 0000nnnnmmmmxxxx */
   290             switch( ir&0x000F ) {
   291                 case 2:
   292                     switch( (ir&0x00F0)>>4 ) {
   293                         case 0: /* STC     SR, Rn */
   294                             CHECKPRIV();
   295                             RN(ir) = sh4_read_sr();
   296                             break;
   297                         case 1: /* STC     GBR, Rn */
   298                             RN(ir) = sh4r.gbr;
   299                             break;
   300                         case 2: /* STC     VBR, Rn */
   301                             CHECKPRIV();
   302                             RN(ir) = sh4r.vbr;
   303                             break;
   304                         case 3: /* STC     SSR, Rn */
   305                             CHECKPRIV();
   306                             RN(ir) = sh4r.ssr;
   307                             break;
   308                         case 4: /* STC     SPC, Rn */
   309                             CHECKPRIV();
   310                             RN(ir) = sh4r.spc;
   311                             break;
   312                         case 8: case 9: case 10: case 11: case 12: case 13:
   313                         case 14: case 15:/* STC     Rm_bank, Rn */
   314                             CHECKPRIV();
   315                             RN(ir) = RN_BANK(ir);
   316                             break;
   317                         default: UNDEF(ir);
   318                     }
   319                     break;
   320                 case 3:
   321                     switch( (ir&0x00F0)>>4 ) {
   322                         case 0: /* BSRF    Rn */
   323                             CHECKDEST( pc + 4 + RN(ir) );
   324                             CHECKSLOTILLEGAL();
   325                             sh4r.in_delay_slot = 1;
   326                             sh4r.pr = sh4r.pc + 4;
   327                             sh4r.pc = sh4r.new_pc;
   328                             sh4r.new_pc = pc + 4 + RN(ir);
   329                             return TRUE;
   330                         case 2: /* BRAF    Rn */
   331                             CHECKDEST( pc + 4 + RN(ir) );
   332                             CHECKSLOTILLEGAL();
   333                             sh4r.in_delay_slot = 1;
   334                             sh4r.pc = sh4r.new_pc;
   335                             sh4r.new_pc = pc + 4 + RN(ir);
   336                             return TRUE;
   337                         case 8: /* PREF    [Rn] */
   338                             tmp = RN(ir);
   339                             if( (tmp & 0xFC000000) == 0xE0000000 ) {
   340                                 /* Store queue operation */
   341                                 int queue = (tmp&0x20)>>2;
   342                                 int32_t *src = &sh4r.store_queue[queue];
   343                                 uint32_t hi = (MMIO_READ( MMU, (queue == 0 ? QACR0 : QACR1) ) & 0x1C) << 24;
   344                                 uint32_t target = tmp&0x03FFFFE0 | hi;
   345                                 mem_copy_to_sh4( target, src, 32 );
   346                                 WARN( "Executed SQ%c => %08X",
   347                                       (queue == 0 ? '0' : '1'), target );
   348                             }
   349                             break;
   350                         case 9: /* OCBI    [Rn] */
   351                         case 10:/* OCBP    [Rn] */
   352                         case 11:/* OCBWB   [Rn] */
   353                             /* anything? */
   354                             break;
   355                         case 12:/* MOVCA.L R0, [Rn] */
   356                             UNIMP(ir);
   357                         default: UNDEF(ir);
   358                     }
   359                     break;
   360                 case 4: /* MOV.B   Rm, [R0 + Rn] */
   361                     MEM_WRITE_BYTE( R0 + RN(ir), RM(ir) );
   362                     break;
   363                 case 5: /* MOV.W   Rm, [R0 + Rn] */
   364                     MEM_WRITE_WORD( R0 + RN(ir), RM(ir) );
   365                     break;
   366                 case 6: /* MOV.L   Rm, [R0 + Rn] */
   367                     MEM_WRITE_LONG( R0 + RN(ir), RM(ir) );
   368                     break;
   369                 case 7: /* MUL.L   Rm, Rn */
   370                     sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   371                         (RM(ir) * RN(ir));
   372                     break;
   373                 case 8: 
   374                     switch( (ir&0x0FF0)>>4 ) {
   375                         case 0: /* CLRT    */
   376                             sh4r.t = 0;
   377                             break;
   378                         case 1: /* SETT    */
   379                             sh4r.t = 1;
   380                             break;
   381                         case 2: /* CLRMAC  */
   382                             sh4r.mac = 0;
   383                             break;
   384                         case 3: /* LDTLB   */
   385                             break;
   386                         case 4: /* CLRS    */
   387                             sh4r.s = 0;
   388                             break;
   389                         case 5: /* SETS    */
   390                             sh4r.s = 1;
   391                             break;
   392                         default: UNDEF(ir);
   393                     }
   394                     break;
   395                 case 9: 
   396                     if( (ir&0x00F0) == 0x20 ) /* MOVT    Rn */
   397                         RN(ir) = sh4r.t;
   398                     else if( ir == 0x0019 ) /* DIV0U   */
   399                         sh4r.m = sh4r.q = sh4r.t = 0;
   400                     else if( ir == 0x0009 )
   401                         /* NOP     */;
   402                     else UNDEF(ir);
   403                     break;
   404                 case 10:
   405                     switch( (ir&0x00F0) >> 4 ) {
   406                         case 0: /* STS     MACH, Rn */
   407                             RN(ir) = sh4r.mac >> 32;
   408                             break;
   409                         case 1: /* STS     MACL, Rn */
   410                             RN(ir) = (uint32_t)sh4r.mac;
   411                             break;
   412                         case 2: /* STS     PR, Rn */
   413                             RN(ir) = sh4r.pr;
   414                             break;
   415                         case 3: /* STC     SGR, Rn */
   416                             CHECKPRIV();
   417                             RN(ir) = sh4r.sgr;
   418                             break;
   419                         case 5:/* STS      FPUL, Rn */
   420                             RN(ir) = sh4r.fpul;
   421                             break;
   422                         case 6: /* STS     FPSCR, Rn */
   423                             RN(ir) = sh4r.fpscr;
   424                             break;
   425                         case 15:/* STC     DBR, Rn */
   426                             CHECKPRIV();
   427                             RN(ir) = sh4r.dbr;
   428                             break;
   429                         default: UNDEF(ir);
   430                     }
   431                     break;
   432                 case 11:
   433                     switch( (ir&0x0FF0)>>4 ) {
   434                         case 0: /* RTS     */
   435                             CHECKDEST( sh4r.pr );
   436                             CHECKSLOTILLEGAL();
   437                             sh4r.in_delay_slot = 1;
   438                             sh4r.pc = sh4r.new_pc;
   439                             sh4r.new_pc = sh4r.pr;
   440                             return TRUE;
   441                         case 1: /* SLEEP   */
   442 			    if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
   443 				sh4r.sh4_state = SH4_STATE_STANDBY;
   444 			    } else {
   445 				sh4r.sh4_state = SH4_STATE_SLEEP;
   446 			    }
   447 			    return FALSE; /* Halt CPU */
   448                         case 2: /* RTE     */
   449                             CHECKPRIV();
   450                             CHECKDEST( sh4r.spc );
   451                             CHECKSLOTILLEGAL();
   452                             sh4r.in_delay_slot = 1;
   453                             sh4r.pc = sh4r.new_pc;
   454                             sh4r.new_pc = sh4r.spc;
   455                             sh4_load_sr( sh4r.ssr );
   456                             WARN( "RTE => %08X", sh4r.new_pc );
   457                             return TRUE;
   458                         default:UNDEF(ir);
   459                     }
   460                     break;
   461                 case 12:/* MOV.B   [R0+R%d], R%d */
   462                     RN(ir) = MEM_READ_BYTE( R0 + RM(ir) );
   463                     break;
   464                 case 13:/* MOV.W   [R0+R%d], R%d */
   465                     RN(ir) = MEM_READ_WORD( R0 + RM(ir) );
   466                     break;
   467                 case 14:/* MOV.L   [R0+R%d], R%d */
   468                     RN(ir) = MEM_READ_LONG( R0 + RM(ir) );
   469                     break;
   470                 case 15:/* MAC.L   [Rm++], [Rn++] */
   471                     tmpl = ( SIGNEXT32(MEM_READ_LONG(RM(ir))) *
   472                                   SIGNEXT32(MEM_READ_LONG(RN(ir))) );
   473                     if( sh4r.s ) {
   474                         /* 48-bit Saturation. Yuch */
   475                         tmpl += SIGNEXT48(sh4r.mac);
   476                         if( tmpl < 0xFFFF800000000000LL )
   477                             tmpl = 0xFFFF800000000000LL;
   478                         else if( tmpl > 0x00007FFFFFFFFFFFLL )
   479                             tmpl = 0x00007FFFFFFFFFFFLL;
   480                         sh4r.mac = (sh4r.mac&0xFFFF000000000000LL) |
   481                             (tmpl&0x0000FFFFFFFFFFFFLL);
   482                     } else sh4r.mac = tmpl;
   484                     RM(ir) += 4;
   485                     RN(ir) += 4;
   487                     break;
   488                 default: UNDEF(ir);
   489             }
   490             break;
   491         case 1: /* 0001nnnnmmmmdddd */
   492             /* MOV.L   Rm, [Rn + disp4*4] */
   493             MEM_WRITE_LONG( RN(ir) + (DISP4(ir)<<2), RM(ir) );
   494             break;
   495         case 2: /* 0010nnnnmmmmxxxx */
   496             switch( ir&0x000F ) {
   497                 case 0: /* MOV.B   Rm, [Rn] */
   498                     MEM_WRITE_BYTE( RN(ir), RM(ir) );
   499                     break;
   500                 case 1: /* MOV.W   Rm, [Rn] */
   501                     MEM_WRITE_WORD( RN(ir), RM(ir) );
   502                     break;
   503                 case 2: /* MOV.L   Rm, [Rn] */
   504                     MEM_WRITE_LONG( RN(ir), RM(ir) );
   505                     break;
   506                 case 3: UNDEF(ir);
   507                     break;
   508                 case 4: /* MOV.B   Rm, [--Rn] */
   509                     RN(ir) --;
   510                     MEM_WRITE_BYTE( RN(ir), RM(ir) );
   511                     break;
   512                 case 5: /* MOV.W   Rm, [--Rn] */
   513                     RN(ir) -= 2;
   514                     MEM_WRITE_WORD( RN(ir), RM(ir) );
   515                     break;
   516                 case 6: /* MOV.L   Rm, [--Rn] */
   517                     RN(ir) -= 4;
   518                     MEM_WRITE_LONG( RN(ir), RM(ir) );
   519                     break;
   520                 case 7: /* DIV0S   Rm, Rn */
   521                     sh4r.q = RN(ir)>>31;
   522                     sh4r.m = RM(ir)>>31;
   523                     sh4r.t = sh4r.q ^ sh4r.m;
   524                     break;
   525                 case 8: /* TST     Rm, Rn */
   526                     sh4r.t = (RN(ir)&RM(ir) ? 0 : 1);
   527                     break;
   528                 case 9: /* AND     Rm, Rn */
   529                     RN(ir) &= RM(ir);
   530                     break;
   531                 case 10:/* XOR     Rm, Rn */
   532                     RN(ir) ^= RM(ir);
   533                     break;
   534                 case 11:/* OR      Rm, Rn */
   535                     RN(ir) |= RM(ir);
   536                     break;
   537                 case 12:/* CMP/STR Rm, Rn */
   538                     /* set T = 1 if any byte in RM & RN is the same */
   539                     tmp = RM(ir) ^ RN(ir);
   540                     sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
   541                               (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
   542                     break;
   543                 case 13:/* XTRCT   Rm, Rn */
   544                     RN(ir) = (RN(ir)>>16) | (RM(ir)<<16);
   545                     break;
   546                 case 14:/* MULU.W  Rm, Rn */
   547                     sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   548                         (uint32_t)((RM(ir)&0xFFFF) * (RN(ir)&0xFFFF));
   549                     break;
   550                 case 15:/* MULS.W  Rm, Rn */
   551                     sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   552                         (uint32_t)(SIGNEXT32(RM(ir)&0xFFFF) * SIGNEXT32(RN(ir)&0xFFFF));
   553                     break;
   554             }
   555             break;
   556         case 3: /* 0011nnnnmmmmxxxx */
   557             switch( ir&0x000F ) {
   558                 case 0: /* CMP/EQ  Rm, Rn */
   559                     sh4r.t = ( RM(ir) == RN(ir) ? 1 : 0 );
   560                     break;
   561                 case 2: /* CMP/HS  Rm, Rn */
   562                     sh4r.t = ( RN(ir) >= RM(ir) ? 1 : 0 );
   563                     break;
   564                 case 3: /* CMP/GE  Rm, Rn */
   565                     sh4r.t = ( ((int32_t)RN(ir)) >= ((int32_t)RM(ir)) ? 1 : 0 );
   566                     break;
   567                 case 4: { /* DIV1    Rm, Rn */
   568                     /* This is just from the sh4p manual with some
   569                      * simplifications (someone want to check it's correct? :)
   570                      * Why they couldn't just provide a real DIV instruction...
   571                      * Please oh please let the translator batch these things
   572                      * up into a single DIV... */
   573                     uint32_t tmp0, tmp1, tmp2, dir;
   575                     dir = sh4r.q ^ sh4r.m;
   576                     sh4r.q = (RN(ir) >> 31);
   577                     tmp2 = RM(ir);
   578                     RN(ir) = (RN(ir) << 1) | sh4r.t;
   579                     tmp0 = RN(ir);
   580                     if( dir ) {
   581                         RN(ir) += tmp2;
   582                         tmp1 = (RN(ir)<tmp0 ? 1 : 0 );
   583                     } else {
   584                         RN(ir) -= tmp2;
   585                         tmp1 = (RN(ir)>tmp0 ? 1 : 0 );
   586                     }
   587                     sh4r.q ^= sh4r.m ^ tmp1;
   588                     sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
   589                     break; }
   590                 case 5: /* DMULU.L Rm, Rn */
   591                     sh4r.mac = ((uint64_t)RM(ir)) * ((uint64_t)RN(ir));
   592                     break;
   593                 case 6: /* CMP/HI  Rm, Rn */
   594                     sh4r.t = ( RN(ir) > RM(ir) ? 1 : 0 );
   595                     break;
   596                 case 7: /* CMP/GT  Rm, Rn */
   597                     sh4r.t = ( ((int32_t)RN(ir)) > ((int32_t)RM(ir)) ? 1 : 0 );
   598                     break;
   599                 case 8: /* SUB     Rm, Rn */
   600                     RN(ir) -= RM(ir);
   601                     break;
   602                 case 10:/* SUBC    Rm, Rn */
   603                     tmp = RN(ir);
   604                     RN(ir) = RN(ir) - RM(ir) - sh4r.t;
   605                     sh4r.t = (RN(ir) > tmp || (RN(ir) == tmp && sh4r.t == 1));
   606                     break;
   607                 case 11:/* SUBV    Rm, Rn */
   608                     UNIMP(ir);
   609                     break;
   610                 case 12:/* ADD     Rm, Rn */
   611                     RN(ir) += RM(ir);
   612                     break;
   613                 case 13:/* DMULS.L Rm, Rn */
   614                     sh4r.mac = SIGNEXT32(RM(ir)) * SIGNEXT32(RN(ir));
   615                     break;
   616                 case 14:/* ADDC    Rm, Rn */
   617                     tmp = RN(ir);
   618                     RN(ir) += RM(ir) + sh4r.t;
   619                     sh4r.t = ( RN(ir) < tmp || (RN(ir) == tmp && sh4r.t != 0) ? 1 : 0 );
   620                     break;
   621                 case 15:/* ADDV    Rm, Rn */
   622                     UNIMP(ir);
   623                     break;
   624                 default: UNDEF(ir);
   625             }
   626             break;
   627         case 4: /* 0100nnnnxxxxxxxx */
   628             switch( ir&0x00FF ) {
   629                 case 0x00: /* SHLL    Rn */
   630                     sh4r.t = RN(ir) >> 31;
   631                     RN(ir) <<= 1;
   632                     break;
   633                 case 0x01: /* SHLR    Rn */
   634                     sh4r.t = RN(ir) & 0x00000001;
   635                     RN(ir) >>= 1;
   636                     break;
   637                 case 0x02: /* STS.L   MACH, [--Rn] */
   638                     RN(ir) -= 4;
   639                     MEM_WRITE_LONG( RN(ir), (sh4r.mac>>32) );
   640                     break;
   641                 case 0x03: /* STC.L   SR, [--Rn] */
   642                     CHECKPRIV();
   643                     RN(ir) -= 4;
   644                     MEM_WRITE_LONG( RN(ir), sh4_read_sr() );
   645                     break;
   646                 case 0x04: /* ROTL    Rn */
   647                     sh4r.t = RN(ir) >> 31;
   648                     RN(ir) <<= 1;
   649                     RN(ir) |= sh4r.t;
   650                     break;
   651                 case 0x05: /* ROTR    Rn */
   652                     sh4r.t = RN(ir) & 0x00000001;
   653                     RN(ir) >>= 1;
   654                     RN(ir) |= (sh4r.t << 31);
   655                     break;
   656                 case 0x06: /* LDS.L   [Rn++], MACH */
   657                     sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
   658                         (((uint64_t)MEM_READ_LONG(RN(ir)))<<32);
   659                     RN(ir) += 4;
   660                     break;
   661                 case 0x07: /* LDC.L   [Rn++], SR */
   662                     CHECKPRIV();
   663                     sh4_load_sr( MEM_READ_LONG(RN(ir)) );
   664                     RN(ir) +=4;
   665                     break;
   666                 case 0x08: /* SHLL2   Rn */
   667                     RN(ir) <<= 2;
   668                     break;
   669                 case 0x09: /* SHLR2   Rn */
   670                     RN(ir) >>= 2;
   671                     break;
   672                 case 0x0A: /* LDS     Rn, MACH */
   673                     sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
   674                         (((uint64_t)RN(ir))<<32);
   675                     break;
   676                 case 0x0B: /* JSR     [Rn] */
   677                     CHECKDEST( RN(ir) );
   678                     CHECKSLOTILLEGAL();
   679                     sh4r.in_delay_slot = 1;
   680                     sh4r.pc = sh4r.new_pc;
   681                     sh4r.new_pc = RN(ir);
   682                     sh4r.pr = pc + 4;
   683                     return TRUE;
   684                 case 0x0E: /* LDC     Rn, SR */
   685                     CHECKPRIV();
   686                     sh4_load_sr( RN(ir) );
   687                     break;
   688                 case 0x10: /* DT      Rn */
   689                     RN(ir) --;
   690                     sh4r.t = ( RN(ir) == 0 ? 1 : 0 );
   691                     break;
   692                 case 0x11: /* CMP/PZ  Rn */
   693                     sh4r.t = ( ((int32_t)RN(ir)) >= 0 ? 1 : 0 );
   694                     break;
   695                 case 0x12: /* STS.L   MACL, [--Rn] */
   696                     RN(ir) -= 4;
   697                     MEM_WRITE_LONG( RN(ir), (uint32_t)sh4r.mac );
   698                     break;
   699                 case 0x13: /* STC.L   GBR, [--Rn] */
   700                     RN(ir) -= 4;
   701                     MEM_WRITE_LONG( RN(ir), sh4r.gbr );
   702                     break;
   703                 case 0x15: /* CMP/PL  Rn */
   704                     sh4r.t = ( ((int32_t)RN(ir)) > 0 ? 1 : 0 );
   705                     break;
   706                 case 0x16: /* LDS.L   [Rn++], MACL */
   707                     sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
   708                         (uint64_t)((uint32_t)MEM_READ_LONG(RN(ir)));
   709                     RN(ir) += 4;
   710                     break;
   711                 case 0x17: /* LDC.L   [Rn++], GBR */
   712                     sh4r.gbr = MEM_READ_LONG(RN(ir));
   713                     RN(ir) +=4;
   714                     break;
   715                 case 0x18: /* SHLL8   Rn */
   716                     RN(ir) <<= 8;
   717                     break;
   718                 case 0x19: /* SHLR8   Rn */
   719                     RN(ir) >>= 8;
   720                     break;
   721                 case 0x1A: /* LDS     Rn, MACL */
   722                     sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
   723                         (uint64_t)((uint32_t)(RN(ir)));
   724                     break;
   725                 case 0x1B: /* TAS.B   [Rn] */
   726                     tmp = MEM_READ_BYTE( RN(ir) );
   727                     sh4r.t = ( tmp == 0 ? 1 : 0 );
   728                     MEM_WRITE_BYTE( RN(ir), tmp | 0x80 );
   729                     break;
   730                 case 0x1E: /* LDC     Rn, GBR */
   731                     sh4r.gbr = RN(ir);
   732                     break;
   733                 case 0x20: /* SHAL    Rn */
   734                     sh4r.t = RN(ir) >> 31;
   735                     RN(ir) <<= 1;
   736                     break;
   737                 case 0x21: /* SHAR    Rn */
   738                     sh4r.t = RN(ir) & 0x00000001;
   739                     RN(ir) = ((int32_t)RN(ir)) >> 1;
   740                     break;
   741                 case 0x22: /* STS.L   PR, [--Rn] */
   742                     RN(ir) -= 4;
   743                     MEM_WRITE_LONG( RN(ir), sh4r.pr );
   744                     break;
   745                 case 0x23: /* STC.L   VBR, [--Rn] */
   746                     CHECKPRIV();
   747                     RN(ir) -= 4;
   748                     MEM_WRITE_LONG( RN(ir), sh4r.vbr );
   749                     break;
   750                 case 0x24: /* ROTCL   Rn */
   751                     tmp = RN(ir) >> 31;
   752                     RN(ir) <<= 1;
   753                     RN(ir) |= sh4r.t;
   754                     sh4r.t = tmp;
   755                     break;
   756                 case 0x25: /* ROTCR   Rn */
   757                     tmp = RN(ir) & 0x00000001;
   758                     RN(ir) >>= 1;
   759                     RN(ir) |= (sh4r.t << 31 );
   760                     sh4r.t = tmp;
   761                     break;
   762                 case 0x26: /* LDS.L   [Rn++], PR */
   763                     sh4r.pr = MEM_READ_LONG( RN(ir) );
   764                     RN(ir) += 4;
   765                     break;
   766                 case 0x27: /* LDC.L   [Rn++], VBR */
   767                     CHECKPRIV();
   768                     sh4r.vbr = MEM_READ_LONG(RN(ir));
   769                     RN(ir) +=4;
   770                     break;
   771                 case 0x28: /* SHLL16  Rn */
   772                     RN(ir) <<= 16;
   773                     break;
   774                 case 0x29: /* SHLR16  Rn */
   775                     RN(ir) >>= 16;
   776                     break;
   777                 case 0x2A: /* LDS     Rn, PR */
   778                     sh4r.pr = RN(ir);
   779                     break;
   780                 case 0x2B: /* JMP     [Rn] */
   781                     CHECKDEST( RN(ir) );
   782                     CHECKSLOTILLEGAL();
   783                     sh4r.in_delay_slot = 1;
   784                     sh4r.pc = sh4r.new_pc;
   785                     sh4r.new_pc = RN(ir);
   786                     return TRUE;
   787                 case 0x2E: /* LDC     Rn, VBR */
   788                     CHECKPRIV();
   789                     sh4r.vbr = RN(ir);
   790                     break;
   791                 case 0x32: /* STC.L   SGR, [--Rn] */
   792                     CHECKPRIV();
   793                     RN(ir) -= 4;
   794                     MEM_WRITE_LONG( RN(ir), sh4r.sgr );
   795                     break;
   796                 case 0x33: /* STC.L   SSR, [--Rn] */
   797                     CHECKPRIV();
   798                     RN(ir) -= 4;
   799                     MEM_WRITE_LONG( RN(ir), sh4r.ssr );
   800                     break;
   801                 case 0x37: /* LDC.L   [Rn++], SSR */
   802                     CHECKPRIV();
   803                     sh4r.ssr = MEM_READ_LONG(RN(ir));
   804                     RN(ir) +=4;
   805                     break;
   806                 case 0x3E: /* LDC     Rn, SSR */
   807                     CHECKPRIV();
   808                     sh4r.ssr = RN(ir);
   809                     break;
   810                 case 0x43: /* STC.L   SPC, [--Rn] */
   811                     CHECKPRIV();
   812                     RN(ir) -= 4;
   813                     MEM_WRITE_LONG( RN(ir), sh4r.spc );
   814                     break;
   815                 case 0x47: /* LDC.L   [Rn++], SPC */
   816                     CHECKPRIV();
   817                     sh4r.spc = MEM_READ_LONG(RN(ir));
   818                     RN(ir) +=4;
   819                     break;
   820                 case 0x4E: /* LDC     Rn, SPC */
   821                     CHECKPRIV();
   822                     sh4r.spc = RN(ir);
   823                     break;
   824                 case 0x52: /* STS.L   FPUL, [--Rn] */
   825                     RN(ir) -= 4;
   826                     MEM_WRITE_LONG( RN(ir), sh4r.fpul );
   827                     break;
   828                 case 0x56: /* LDS.L   [Rn++], FPUL */
   829                     sh4r.fpul = MEM_READ_LONG(RN(ir));
   830                     RN(ir) +=4;
   831                     break;
   832                 case 0x5A: /* LDS     Rn, FPUL */
   833                     sh4r.fpul = RN(ir);
   834                     break;
   835                 case 0x62: /* STS.L   FPSCR, [--Rn] */
   836                     RN(ir) -= 4;
   837                     MEM_WRITE_LONG( RN(ir), sh4r.fpscr );
   838                     break;
   839                 case 0x66: /* LDS.L   [Rn++], FPSCR */
   840                     sh4r.fpscr = MEM_READ_LONG(RN(ir));
   841                     RN(ir) +=4;
   842                     break;
   843                 case 0x6A: /* LDS     Rn, FPSCR */
   844                     sh4r.fpscr = RN(ir);
   845                     break;
   846                 case 0xF2: /* STC.L   DBR, [--Rn] */
   847                     CHECKPRIV();
   848                     RN(ir) -= 4;
   849                     MEM_WRITE_LONG( RN(ir), sh4r.dbr );
   850                     break;
   851                 case 0xF6: /* LDC.L   [Rn++], DBR */
   852                     CHECKPRIV();
   853                     sh4r.dbr = MEM_READ_LONG(RN(ir));
   854                     RN(ir) +=4;
   855                     break;
   856                 case 0xFA: /* LDC     Rn, DBR */
   857                     CHECKPRIV();
   858                     sh4r.dbr = RN(ir);
   859                     break;
   860                 case 0x83: case 0x93: case 0xA3: case 0xB3: case 0xC3:
   861                 case 0xD3: case 0xE3: case 0xF3: /* STC.L   Rn_BANK, [--Rn] */
   862                     CHECKPRIV();
   863                     RN(ir) -= 4;
   864                     MEM_WRITE_LONG( RN(ir), RN_BANK(ir) );
   865                     break;
   866                 case 0x87: case 0x97: case 0xA7: case 0xB7: case 0xC7:
   867                 case 0xD7: case 0xE7: case 0xF7: /* LDC.L   [Rn++], Rn_BANK */
   868                     CHECKPRIV();
   869                     RN_BANK(ir) = MEM_READ_LONG( RN(ir) );
   870                     RN(ir) += 4;
   871                     break;
   872                 case 0x8E: case 0x9E: case 0xAE: case 0xBE: case 0xCE:
   873                 case 0xDE: case 0xEE: case 0xFE: /* LDC     Rm, Rn_BANK */
   874                     CHECKPRIV();
   875                     RN_BANK(ir) = RM(ir);
   876                     break;
   877                 default:
   878                     if( (ir&0x000F) == 0x0F ) {
   879                         /* MAC.W   [Rm++], [Rn++] */
   880                         tmp = SIGNEXT16(MEM_READ_WORD(RM(ir))) *
   881                             SIGNEXT16(MEM_READ_WORD(RN(ir)));
   882                         if( sh4r.s ) {
   883                             /* FIXME */
   884                             UNIMP(ir);
   885                         } else sh4r.mac += SIGNEXT32(tmp);
   886                         RM(ir) += 2;
   887                         RN(ir) += 2;
   888                     } else if( (ir&0x000F) == 0x0C ) {
   889                         /* SHAD    Rm, Rn */
   890                         tmp = RM(ir);
   891                         if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);
   892                         else if( (tmp & 0x1F) == 0 )  
   893 			  RN(ir) = ((int32_t)RN(ir)) >> 31;
   894                         else 
   895 			  RN(ir) = ((int32_t)RN(ir)) >> (((~RM(ir)) & 0x1F)+1);
   896                     } else if( (ir&0x000F) == 0x0D ) {
   897                         /* SHLD    Rm, Rn */
   898                         tmp = RM(ir);
   899                         if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);
   900                         else if( (tmp & 0x1F) == 0 ) RN(ir) = 0;
   901                         else RN(ir) >>= (((~tmp) & 0x1F)+1);
   902                     } else UNDEF(ir);
   903             }
   904             break;
   905         case 5: /* 0101nnnnmmmmdddd */
   906             /* MOV.L   [Rm + disp4*4], Rn */
   907             RN(ir) = MEM_READ_LONG( RM(ir) + (DISP4(ir)<<2) );
   908             break;
   909         case 6: /* 0110xxxxxxxxxxxx */
   910             switch( ir&0x000f ) {
   911                 case 0: /* MOV.B   [Rm], Rn */
   912                     RN(ir) = MEM_READ_BYTE( RM(ir) );
   913                     break;
   914                 case 1: /* MOV.W   [Rm], Rn */
   915                     RN(ir) = MEM_READ_WORD( RM(ir) );
   916                     break;
   917                 case 2: /* MOV.L   [Rm], Rn */
   918                     RN(ir) = MEM_READ_LONG( RM(ir) );
   919                     break;
   920                 case 3: /* MOV     Rm, Rn */
   921                     RN(ir) = RM(ir);
   922                     break;
   923                 case 4: /* MOV.B   [Rm++], Rn */
   924                     RN(ir) = MEM_READ_BYTE( RM(ir) );
   925                     RM(ir) ++;
   926                     break;
   927                 case 5: /* MOV.W   [Rm++], Rn */
   928                     RN(ir) = MEM_READ_WORD( RM(ir) );
   929                     RM(ir) += 2;
   930                     break;
   931                 case 6: /* MOV.L   [Rm++], Rn */
   932                     RN(ir) = MEM_READ_LONG( RM(ir) );
   933                     RM(ir) += 4;
   934                     break;
   935                 case 7: /* NOT     Rm, Rn */
   936                     RN(ir) = ~RM(ir);
   937                     break;
   938                 case 8: /* SWAP.B  Rm, Rn */
   939                     RN(ir) = (RM(ir)&0xFFFF0000) | ((RM(ir)&0x0000FF00)>>8) |
   940                         ((RM(ir)&0x000000FF)<<8);
   941                     break;
   942                 case 9: /* SWAP.W  Rm, Rn */
   943                     RN(ir) = (RM(ir)>>16) | (RM(ir)<<16);
   944                     break;
   945                 case 10:/* NEGC    Rm, Rn */
   946                     tmp = 0 - RM(ir);
   947                     RN(ir) = tmp - sh4r.t;
   948                     sh4r.t = ( 0<tmp || tmp<RN(ir) ? 1 : 0 );
   949                     break;
   950                 case 11:/* NEG     Rm, Rn */
   951                     RN(ir) = 0 - RM(ir);
   952                     break;
   953                 case 12:/* EXTU.B  Rm, Rn */
   954                     RN(ir) = RM(ir)&0x000000FF;
   955                     break;
   956                 case 13:/* EXTU.W  Rm, Rn */
   957                     RN(ir) = RM(ir)&0x0000FFFF;
   958                     break;
   959                 case 14:/* EXTS.B  Rm, Rn */
   960                     RN(ir) = SIGNEXT8( RM(ir)&0x000000FF );
   961                     break;
   962                 case 15:/* EXTS.W  Rm, Rn */
   963                     RN(ir) = SIGNEXT16( RM(ir)&0x0000FFFF );
   964                     break;
   965             }
   966             break;
   967         case 7: /* 0111nnnniiiiiiii */
   968             /* ADD    imm8, Rn */
   969             RN(ir) += IMM8(ir);
   970             break;
   971         case 8: /* 1000xxxxxxxxxxxx */
   972             switch( (ir&0x0F00) >> 8 ) {
   973                 case 0: /* MOV.B   R0, [Rm + disp4] */
   974                     MEM_WRITE_BYTE( RM(ir) + DISP4(ir), R0 );
   975                     break;
   976                 case 1: /* MOV.W   R0, [Rm + disp4*2] */
   977                     MEM_WRITE_WORD( RM(ir) + (DISP4(ir)<<1), R0 );
   978                     break;
   979                 case 4: /* MOV.B   [Rm + disp4], R0 */
   980                     R0 = MEM_READ_BYTE( RM(ir) + DISP4(ir) );
   981                     break;
   982                 case 5: /* MOV.W   [Rm + disp4*2], R0 */
   983                     R0 = MEM_READ_WORD( RM(ir) + (DISP4(ir)<<1) );
   984                     break;
   985                 case 8: /* CMP/EQ  imm, R0 */
   986                     sh4r.t = ( R0 == IMM8(ir) ? 1 : 0 );
   987                     break;
   988                 case 9: /* BT      disp8 */
   989                     CHECKSLOTILLEGAL()
   990                     if( sh4r.t ) {
   991                         CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
   992                         sh4r.pc += (PCDISP8(ir)<<1) + 4;
   993                         sh4r.new_pc = sh4r.pc + 2;
   994                         return TRUE;
   995                     }
   996                     break;
   997                 case 11:/* BF      disp8 */
   998                     CHECKSLOTILLEGAL()
   999                     if( !sh4r.t ) {
  1000                         CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
  1001                         sh4r.pc += (PCDISP8(ir)<<1) + 4;
  1002                         sh4r.new_pc = sh4r.pc + 2;
  1003                         return TRUE;
  1005                     break;
  1006                 case 13:/* BT/S    disp8 */
  1007                     CHECKSLOTILLEGAL()
  1008                     if( sh4r.t ) {
  1009                         CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
  1010                         sh4r.in_delay_slot = 1;
  1011                         sh4r.pc = sh4r.new_pc;
  1012                         sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;
  1013                         sh4r.in_delay_slot = 1;
  1014                         return TRUE;
  1016                     break;
  1017                 case 15:/* BF/S    disp8 */
  1018                     CHECKSLOTILLEGAL()
  1019                     if( !sh4r.t ) {
  1020                         CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
  1021                         sh4r.in_delay_slot = 1;
  1022                         sh4r.pc = sh4r.new_pc;
  1023                         sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;
  1024                         return TRUE;
  1026                     break;
  1027                 default: UNDEF(ir);
  1029             break;
  1030         case 9: /* 1001xxxxxxxxxxxx */
  1031             /* MOV.W   [disp8*2 + pc + 4], Rn */
  1032             RN(ir) = MEM_READ_WORD( pc + 4 + (DISP8(ir)<<1) );
  1033             break;
  1034         case 10:/* 1010dddddddddddd */
  1035             /* BRA     disp12 */
  1036             CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 )
  1037             CHECKSLOTILLEGAL()
  1038             sh4r.in_delay_slot = 1;
  1039             sh4r.pc = sh4r.new_pc;
  1040             sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);
  1041             return TRUE;
  1042         case 11:/* 1011dddddddddddd */
  1043             /* BSR     disp12 */
  1044             CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 )
  1045             CHECKSLOTILLEGAL()
  1046             sh4r.in_delay_slot = 1;
  1047             sh4r.pr = pc + 4;
  1048             sh4r.pc = sh4r.new_pc;
  1049             sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);
  1050             return TRUE;
  1051         case 12:/* 1100xxxxdddddddd */
  1052         switch( (ir&0x0F00)>>8 ) {
  1053                 case 0: /* MOV.B  R0, [GBR + disp8] */
  1054                     MEM_WRITE_BYTE( sh4r.gbr + DISP8(ir), R0 );
  1055                     break;
  1056                 case 1: /* MOV.W  R0, [GBR + disp8*2] */
  1057                     MEM_WRITE_WORD( sh4r.gbr + (DISP8(ir)<<1), R0 );
  1058                     break;
  1059                 case  2: /*MOV.L   R0, [GBR + disp8*4] */
  1060                     MEM_WRITE_LONG( sh4r.gbr + (DISP8(ir)<<2), R0 );
  1061                     break;
  1062                 case 3: /* TRAPA   imm8 */
  1063                     CHECKSLOTILLEGAL()
  1064                     sh4r.in_delay_slot = 1;
  1065                     MMIO_WRITE( MMU, TRA, UIMM8(ir) );
  1066                     sh4r.pc = sh4r.new_pc;  /* RAISE ends the instruction */
  1067                     sh4r.new_pc += 2;
  1068                     RAISE( EXC_TRAP, EXV_TRAP );
  1069                     break;
  1070                 case 4: /* MOV.B   [GBR + disp8], R0 */
  1071                     R0 = MEM_READ_BYTE( sh4r.gbr + DISP8(ir) );
  1072                     break;
  1073                 case 5: /* MOV.W   [GBR + disp8*2], R0 */
  1074                     R0 = MEM_READ_WORD( sh4r.gbr + (DISP8(ir)<<1) );
  1075                     break;
  1076                 case 6: /* MOV.L   [GBR + disp8*4], R0 */
  1077                     R0 = MEM_READ_LONG( sh4r.gbr + (DISP8(ir)<<2) );
  1078                     break;
  1079                 case 7: /* MOVA    disp8 + pc&~3 + 4, R0 */
  1080                     R0 = (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4;
  1081                     break;
  1082                 case 8: /* TST     imm8, R0 */
  1083                     sh4r.t = (R0 & UIMM8(ir) ? 0 : 1);
  1084                     break;
  1085                 case 9: /* AND     imm8, R0 */
  1086                     R0 &= UIMM8(ir);
  1087                     break;
  1088                 case 10:/* XOR     imm8, R0 */
  1089                     R0 ^= UIMM8(ir);
  1090                     break;
  1091                 case 11:/* OR      imm8, R0 */
  1092                     R0 |= UIMM8(ir);
  1093                     break;
  1094                 case 12:/* TST.B   imm8, [R0+GBR] */
  1095                     sh4r.t = ( MEM_READ_BYTE(R0 + sh4r.gbr) & UIMM8(ir) ? 0 : 1 );
  1096                     break;
  1097                 case 13:/* AND.B   imm8, [R0+GBR] */
  1098                     MEM_WRITE_BYTE( R0 + sh4r.gbr,
  1099                                     UIMM8(ir) & MEM_READ_BYTE(R0 + sh4r.gbr) );
  1100                     break;
  1101                 case 14:/* XOR.B   imm8, [R0+GBR] */
  1102                     MEM_WRITE_BYTE( R0 + sh4r.gbr,
  1103                                     UIMM8(ir) ^ MEM_READ_BYTE(R0 + sh4r.gbr) );
  1104                     break;
  1105                 case 15:/* OR.B    imm8, [R0+GBR] */
  1106                     MEM_WRITE_BYTE( R0 + sh4r.gbr,
  1107                                     UIMM8(ir) | MEM_READ_BYTE(R0 + sh4r.gbr) );
  1108                     break;
  1110             break;
  1111         case 13:/* 1101nnnndddddddd */
  1112             /* MOV.L   [disp8*4 + pc&~3 + 4], Rn */
  1113             RN(ir) = MEM_READ_LONG( (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4 );
  1114             break;
  1115         case 14:/* 1110nnnniiiiiiii */
  1116             /* MOV     imm8, Rn */
  1117             RN(ir) = IMM8(ir);
  1118             break;
  1119         case 15:/* 1111xxxxxxxxxxxx */
  1120             CHECKFPUEN();
  1121             switch( ir&0x000F ) {
  1122                 case 0: /* FADD    FRm, FRn */
  1123                     FRN(ir) += FRM(ir);
  1124                     break;
  1125                 case 1: /* FSUB    FRm, FRn */
  1126                     FRN(ir) -= FRM(ir);
  1127                     break;
  1128                 case 2: /* FMUL    FRm, FRn */
  1129                     FRN(ir) = FRN(ir) * FRM(ir);
  1130                     break;
  1131                 case 3: /* FDIV    FRm, FRn */
  1132                     FRN(ir) = FRN(ir) / FRM(ir);
  1133                     break;
  1134                 case 4: /* FCMP/EQ FRm, FRn */
  1135                     sh4r.t = ( FRN(ir) == FRM(ir) ? 1 : 0 );
  1136                     break;
  1137                 case 5: /* FCMP/GT FRm, FRn */
  1138                     sh4r.t = ( FRN(ir) > FRM(ir) ? 1 : 0 );
  1139                     break;
  1140                 case 6: /* FMOV.S  [Rm+R0], FRn */
  1141                     MEM_FP_READ( RM(ir) + R0, FRNn(ir) );
  1142                     break;
  1143                 case 7: /* FMOV.S  FRm, [Rn+R0] */
  1144                     MEM_FP_WRITE( RN(ir) + R0, FRMn(ir) );
  1145                     break;
  1146                 case 8: /* FMOV.S  [Rm], FRn */
  1147                     MEM_FP_READ( RM(ir), FRNn(ir) );
  1148                     break;
  1149                 case 9: /* FMOV.S  [Rm++], FRn */
  1150                     MEM_FP_READ( RM(ir), FRNn(ir) );
  1151                     RM(ir) += FP_WIDTH;
  1152                     break;
  1153                 case 10:/* FMOV.S  FRm, [Rn] */
  1154                     MEM_FP_WRITE( RN(ir), FRMn(ir) );
  1155                     break;
  1156                 case 11:/* FMOV.S  FRm, [--Rn] */
  1157                     RN(ir) -= FP_WIDTH;
  1158                     MEM_FP_WRITE( RN(ir), FRMn(ir) );
  1159                     break;
  1160                 case 12:/* FMOV    FRm, FRn */
  1161                     if( IS_FPU_DOUBLESIZE() ) {
  1162                         DRN(ir) = DRM(ir);
  1163                     } else {
  1164                         FRN(ir) = FRM(ir);
  1166                     break;
  1167                 case 13:
  1168                     switch( (ir&0x00F0) >> 4 ) {
  1169                         case 0: /* FSTS    FPUL, FRn */
  1170                             FRN(ir) = FPULf;
  1171                             break;
  1172                         case 1: /* FLDS    FRn, FPUL */
  1173                             FPULf = FRN(ir);
  1174                             break;
  1175                         case 2: /* FLOAT   FPUL, FRn */
  1176                             FRN(ir) = (float)FPULi;
  1177                             break;
  1178                         case 3: /* FTRC    FRn, FPUL */
  1179                             FPULi = (uint32_t)FRN(ir);
  1180                             /* FIXME: is this sufficient? */
  1181                             break;
  1182                         case 4: /* FNEG    FRn */
  1183                             FRN(ir) = -FRN(ir);
  1184                             break;
  1185                         case 5: /* FABS    FRn */
  1186                             FRN(ir) = fabsf(FRN(ir));
  1187                             break;
  1188                         case 6: /* FSQRT   FRn */
  1189                             FRN(ir) = sqrtf(FRN(ir));
  1190                             break;
  1191                         case 7: /* FSRRA FRn */
  1192                             FRN(ir) = 1.0/sqrtf(FRN(ir));
  1193                             break;
  1194                         case 8: /* FLDI0   FRn */
  1195                             FRN(ir) = 0.0;
  1196                             break;
  1197                         case 9: /* FLDI1   FRn */
  1198                             FRN(ir) = 1.0;
  1199                             break;
  1200                         case 10: /* FCNVSD FPUL, DRn */
  1201                             if( IS_FPU_DOUBLEPREC() )
  1202                                 DRN(ir) = (double)FPULf;
  1203                             else UNDEF(ir);
  1204                             break;
  1205                         case 11: /* FCNVDS DRn, FPUL */
  1206                             if( IS_FPU_DOUBLEPREC() ) 
  1207                                 FPULf = (float)DRN(ir);
  1208                             else UNDEF(ir);
  1209                             break;
  1210                         case 14:/* FIPR    FVm, FVn */
  1211                             /* FIXME: This is not going to be entirely accurate
  1212                              * as the SH4 instruction is less precise. Also
  1213                              * need to check for 0s and infinities.
  1214                              */
  1216                             float *fr_bank = FR;
  1217                             int tmp2 = FVN(ir);
  1218                             tmp = FVM(ir);
  1219                             fr_bank[tmp2+3] = fr_bank[tmp]*fr_bank[tmp2] +
  1220                                 fr_bank[tmp+1]*fr_bank[tmp2+1] +
  1221                                 fr_bank[tmp+2]*fr_bank[tmp2+2] +
  1222                                 fr_bank[tmp+3]*fr_bank[tmp2+3];
  1223                             break;
  1225                         case 15:
  1226                             if( (ir&0x0300) == 0x0100 ) { /* FTRV    XMTRX,FVn */
  1227                                 float *fvout = FR+FVN(ir);
  1228                                 float *xm = XF;
  1229                                 float fv[4] = { fvout[0], fvout[1], fvout[2], fvout[3] };
  1230                                 fvout[0] = xm[0] * fv[0] + xm[4]*fv[1] +
  1231                                     xm[8]*fv[2] + xm[12]*fv[3];
  1232                                 fvout[1] = xm[1] * fv[0] + xm[5]*fv[1] +
  1233                                     xm[9]*fv[2] + xm[13]*fv[3];
  1234                                 fvout[2] = xm[2] * fv[0] + xm[6]*fv[1] +
  1235                                     xm[10]*fv[2] + xm[14]*fv[3];
  1236                                 fvout[3] = xm[3] * fv[0] + xm[7]*fv[1] +
  1237                                     xm[11]*fv[2] + xm[15]*fv[3];
  1238                                 break;
  1240                             else if( (ir&0x0100) == 0 ) { /* FSCA    FPUL, DRn */
  1241                                 float angle = (((float)(short)(FPULi>>16)) +
  1242                                                ((float)(FPULi&16)/65536.0)) *
  1243                                     2 * M_PI;
  1244                                 int reg = FRNn(ir);
  1245                                 FR[reg] = sinf(angle);
  1246                                 FR[reg+1] = cosf(angle);
  1247                                 break;
  1249                             else if( ir == 0xFBFD ) {
  1250                                 /* FRCHG   */
  1251                                 sh4r.fpscr ^= FPSCR_FR;
  1252                                 break;
  1254                             else if( ir == 0xF3FD ) {
  1255                                 /* FSCHG   */
  1256                                 sh4r.fpscr ^= FPSCR_SZ;
  1257                                 break;
  1259                         default: UNDEF(ir);
  1261                     break;
  1262                 case 14:/* FMAC    FR0, FRm, FRn */
  1263                     FRN(ir) += FRM(ir)*FR0;
  1264                     break;
  1265                 default: UNDEF(ir);
  1267             break;
  1269     sh4r.pc = sh4r.new_pc;
  1270     sh4r.new_pc += 2;
  1271     sh4r.in_delay_slot = 0;
.