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lxdream.org :: lxdream/src/sh4/sh4mmio.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4mmio.c
changeset 413:bff683bc5228
prev336:c3455be86ee2
next428:338966c8aed0
author nkeynes
date Tue Oct 02 08:48:27 2007 +0000 (13 years ago)
permissions -rw-r--r--
last change Abort if MMUAT is turned on
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     1 /**
     2  * $Id: sh4mmio.c,v 1.13 2007-10-02 08:48:27 nkeynes Exp $
     3  * 
     4  * Miscellaneous and not-really-implemented SH4 peripheral modules. Also
     5  * responsible for including the IMPL side of the SH4 MMIO pages.
     6  * Most of these will eventually be split off into their own files.
     7  *
     8  * Copyright (c) 2005 Nathan Keynes.
     9  *
    10  * This program is free software; you can redistribute it and/or modify
    11  * it under the terms of the GNU General Public License as published by
    12  * the Free Software Foundation; either version 2 of the License, or
    13  * (at your option) any later version.
    14  *
    15  * This program is distributed in the hope that it will be useful,
    16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    18  * GNU General Public License for more details.
    19  */
    20 #define MODULE sh4_module
    22 #include "dream.h"
    23 #include "mem.h"
    24 #include "clock.h"
    25 #include "sh4core.h"
    26 #include "sh4mmio.h"
    27 #define MMIO_IMPL
    28 #include "sh4mmio.h"
    30 /********************************* MMU *************************************/
    32 MMIO_REGION_READ_DEFFN( MMU )
    34 #define OCRAM_START (0x1C000000>>PAGE_BITS)
    35 #define OCRAM_END   (0x20000000>>PAGE_BITS)
    37 static char *cache = NULL;
    39 void mmio_region_MMU_write( uint32_t reg, uint32_t val )
    40 {
    41     switch(reg) {
    42     case MMUCR:
    43 	if( val & MMUCR_AT ) {
    44 	    ERROR( "MMU Address translation not implemented!" );
    45 	    dreamcast_stop();
    46 	}
    47 	break;
    48     case CCR:
    49 	mmu_set_cache_mode( val & (CCR_OIX|CCR_ORA) );
    50 	break;
    51     default:
    52 	break;
    53     }
    54     MMIO_WRITE( MMU, reg, val );
    55 }
    58 void MMU_init() 
    59 {
    60     cache = mem_alloc_pages(2);
    61 }
    63 void MMU_reset()
    64 {
    65     mmio_region_MMU_write( CCR, 0 );
    66 }
    68 void MMU_save_state( FILE *f )
    69 {
    70     fwrite( cache, 4096, 2, f );
    71 }
    73 int MMU_load_state( FILE *f )
    74 {
    75     /* Setup the cache mode according to the saved register value
    76      * (mem_load runs before this point to load all MMIO data)
    77      */
    78     mmio_region_MMU_write( CCR, MMIO_READ(MMU, CCR) );
    79     if( fread( cache, 4096, 2, f ) != 2 ) {
    80 	return 1;
    81     }
    82     return 0;
    83 }
    85 void mmu_set_cache_mode( int mode )
    86 {
    87     uint32_t i;
    88     switch( mode ) {
    89         case MEM_OC_INDEX0: /* OIX=0 */
    90             for( i=OCRAM_START; i<OCRAM_END; i++ )
    91                 page_map[i] = cache + ((i&0x02)<<(PAGE_BITS-1));
    92             break;
    93         case MEM_OC_INDEX1: /* OIX=1 */
    94             for( i=OCRAM_START; i<OCRAM_END; i++ )
    95                 page_map[i] = cache + ((i&0x02000000)>>(25-PAGE_BITS));
    96             break;
    97         default: /* disabled */
    98             for( i=OCRAM_START; i<OCRAM_END; i++ )
    99                 page_map[i] = NULL;
   100             break;
   101     }
   102 }
   105 /********************************* BSC *************************************/
   107 uint32_t bsc_input = 0x0300;
   109 uint16_t bsc_read_pdtra()
   110 {
   111     int i;
   112     uint32_t pctra = MMIO_READ( BSC, PCTRA );
   113     uint16_t output = MMIO_READ( BSC, PDTRA );
   114     uint16_t input_mask = 0, output_mask = 0;
   115     for( i=0; i<16; i++ ) {
   116 	int bits = (pctra >> (i<<1)) & 0x03;
   117 	if( bits == 2 ) input_mask |= (1<<i);
   118 	else if( bits != 0 ) output_mask |= (1<<i);
   119     }
   121     /* ??? */
   122     if( ((output | (~output_mask)) & 0x03) == 3 ) {
   123         output |= 0x03;
   124     } else {
   125         output &= ~0x03;
   126     }
   128     return (bsc_input & input_mask) | output;
   129 }
   131 uint32_t bsc_read_pdtrb()
   132 {
   133     int i;
   134     uint32_t pctrb = MMIO_READ( BSC, PCTRB );
   135     uint16_t output = MMIO_READ( BSC, PDTRB );
   136     uint16_t input_mask = 0, output_mask = 0;
   137     for( i=0; i<4; i++ ) {
   138 	int bits = (pctrb >> (i<<1)) & 0x03;
   139 	if( bits == 2 ) input_mask |= (1<<i);
   140 	else if( bits != 0 ) output_mask |= (1<<i);
   141     }
   143     return ((bsc_input>>16) & input_mask) | output;
   145 }
   147 MMIO_REGION_WRITE_DEFFN(BSC)
   149 int32_t mmio_region_BSC_read( uint32_t reg )
   150 {
   151     int32_t val;
   152     int i;
   153     switch( reg ) {
   154         case PDTRA:
   155 	    val = bsc_read_pdtra();
   156 	    break;
   157         case PDTRB:
   158 	    val = bsc_read_pdtrb();
   159 	    break;
   160         default:
   161             val = MMIO_READ( BSC, reg );
   162     }
   163     return val;
   164 }
   166 /********************************* UBC *************************************/
   168 MMIO_REGION_STUBFNS( UBC )
   171 /********************************** SCI *************************************/
   173 MMIO_REGION_STUBFNS( SCI )
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