lxdream 0.9.1| filename | src/pvr2/pvr2.c |
| changeset | 871:c0b7e21cb62b |
| prev | 867:3af8840d5d8c |
| next | 890:a9896953e9a1 |
| author | nkeynes |
| date | Fri Oct 10 00:13:39 2008 +0000 (15 years ago) |
| permissions | -rw-r--r-- |
| last change | Skip the texcache render-buffer alloc for now (due to various texture-format complications), and write the buffer straight back to vram after rendering. |
| view | annotate | diff | log | raw |
1 /**
2 * $Id$
3 *
4 * PVR2 (Video) Core module implementation and MMIO registers.
5 *
6 * Copyright (c) 2005 Nathan Keynes.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18 #define MODULE pvr2_module
20 #include <assert.h>
21 #include "dream.h"
22 #include "eventq.h"
23 #include "display.h"
24 #include "mem.h"
25 #include "asic.h"
26 #include "clock.h"
27 #include "pvr2/pvr2.h"
28 #include "pvr2/pvr2mmio.h"
29 #include "pvr2/scene.h"
30 #include "sh4/sh4.h"
31 #define MMIO_IMPL
32 #include "pvr2/pvr2mmio.h"
34 unsigned char *video_base;
36 #define MAX_RENDER_BUFFERS 4
38 #define HPOS_PER_FRAME 0
39 #define HPOS_PER_LINECOUNT 1
41 static void pvr2_init( void );
42 static void pvr2_reset( void );
43 static uint32_t pvr2_run_slice( uint32_t );
44 static void pvr2_save_state( FILE *f );
45 static int pvr2_load_state( FILE *f );
46 static void pvr2_update_raster_posn( uint32_t nanosecs );
47 static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int line_time_ns );
48 static render_buffer_t pvr2_get_render_buffer( frame_buffer_t frame );
49 static render_buffer_t pvr2_next_render_buffer( );
50 static render_buffer_t pvr2_frame_buffer_to_render_buffer( frame_buffer_t frame );
51 uint32_t pvr2_get_sync_status();
53 void pvr2_display_frame( void );
55 static int output_colour_formats[] = { COLFMT_BGRA1555, COLFMT_RGB565, COLFMT_BGR888, COLFMT_BGRA8888 };
56 static int render_colour_formats[8] = {
57 COLFMT_BGRA1555, COLFMT_RGB565, COLFMT_BGRA4444, COLFMT_BGRA1555,
58 COLFMT_BGR888, COLFMT_BGRA8888, COLFMT_BGRA8888, COLFMT_BGRA4444 };
61 struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, pvr2_reset, NULL,
62 pvr2_run_slice, NULL,
63 pvr2_save_state, pvr2_load_state };
66 display_driver_t display_driver = NULL;
68 struct pvr2_state {
69 uint32_t frame_count;
70 uint32_t line_count;
71 uint32_t line_remainder;
72 uint32_t cycles_run; /* Cycles already executed prior to main time slice */
73 uint32_t irq_hpos_line;
74 uint32_t irq_hpos_line_count;
75 uint32_t irq_hpos_mode;
76 uint32_t irq_hpos_time_ns; /* Time within the line */
77 uint32_t irq_vpos1;
78 uint32_t irq_vpos2;
79 uint32_t odd_even_field; /* 1 = odd, 0 = even */
80 int32_t palette_changed; /* TRUE if palette has changed since last render */
81 /* timing */
82 uint32_t dot_clock;
83 uint32_t total_lines;
84 uint32_t line_size;
85 uint32_t line_time_ns;
86 uint32_t vsync_lines;
87 uint32_t hsync_width_ns;
88 uint32_t front_porch_ns;
89 uint32_t back_porch_ns;
90 uint32_t retrace_start_line;
91 uint32_t retrace_end_line;
92 int32_t interlaced;
93 } pvr2_state;
95 static gchar *save_next_render_filename;
96 static render_buffer_t render_buffers[MAX_RENDER_BUFFERS];
97 static uint32_t render_buffer_count = 0;
98 static render_buffer_t displayed_render_buffer = NULL;
99 static uint32_t displayed_border_colour = 0;
101 /**
102 * Event handler for the hpos callback
103 */
104 static void pvr2_hpos_callback( int eventid ) {
105 asic_event( eventid );
106 pvr2_update_raster_posn(sh4r.slice_cycle);
107 if( pvr2_state.irq_hpos_mode == HPOS_PER_LINECOUNT ) {
108 pvr2_state.irq_hpos_line += pvr2_state.irq_hpos_line_count;
109 while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {
110 pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);
111 }
112 }
113 pvr2_schedule_scanline_event( eventid, pvr2_state.irq_hpos_line, 1,
114 pvr2_state.irq_hpos_time_ns );
115 }
117 /**
118 * Event handler for the scanline callbacks. Fires the corresponding
119 * ASIC event, and resets the timer for the next field.
120 */
121 static void pvr2_scanline_callback( int eventid )
122 {
123 asic_event( eventid );
124 pvr2_update_raster_posn(sh4r.slice_cycle);
125 if( eventid == EVENT_SCANLINE1 ) {
126 pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos1, 1, 0 );
127 } else {
128 pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos2, 1, 0 );
129 }
130 }
132 static void pvr2_gunpos_callback( int eventid )
133 {
134 pvr2_update_raster_posn(sh4r.slice_cycle);
135 int hpos = pvr2_state.line_remainder * pvr2_state.dot_clock / 1000000;
136 MMIO_WRITE( PVR2, GUNPOS, ((pvr2_state.line_count<<16)|(hpos&0x3FF)) );
137 asic_event( EVENT_MAPLE_DMA );
138 }
140 static void pvr2_init( void )
141 {
142 int i;
143 register_io_region( &mmio_region_PVR2 );
144 register_io_region( &mmio_region_PVR2PAL );
145 register_io_region( &mmio_region_PVR2TA );
146 register_event_callback( EVENT_HPOS, pvr2_hpos_callback );
147 register_event_callback( EVENT_SCANLINE1, pvr2_scanline_callback );
148 register_event_callback( EVENT_SCANLINE2, pvr2_scanline_callback );
149 register_event_callback( EVENT_GUNPOS, pvr2_gunpos_callback );
150 video_base = mem_get_region_by_name( MEM_REGION_VIDEO );
151 texcache_init();
152 pvr2_reset();
153 pvr2_ta_reset();
154 save_next_render_filename = NULL;
155 for( i=0; i<MAX_RENDER_BUFFERS; i++ ) {
156 render_buffers[i] = NULL;
157 }
158 render_buffer_count = 0;
159 displayed_render_buffer = NULL;
160 displayed_border_colour = 0;
161 }
163 static void pvr2_reset( void )
164 {
165 int i;
166 pvr2_state.line_count = 0;
167 pvr2_state.line_remainder = 0;
168 pvr2_state.cycles_run = 0;
169 pvr2_state.irq_vpos1 = 0;
170 pvr2_state.irq_vpos2 = 0;
171 pvr2_state.dot_clock = PVR2_DOT_CLOCK;
172 pvr2_state.back_porch_ns = 4000;
173 pvr2_state.palette_changed = FALSE;
174 mmio_region_PVR2_write( DISP_TOTAL, 0x0270035F );
175 mmio_region_PVR2_write( DISP_SYNCTIME, 0x07D6A53F );
176 mmio_region_PVR2_write( YUV_ADDR, 0 );
177 mmio_region_PVR2_write( YUV_CFG, 0 );
179 pvr2_ta_init();
180 texcache_flush();
181 if( display_driver ) {
182 display_driver->display_blank(0);
183 for( i=0; i<render_buffer_count; i++ ) {
184 display_driver->destroy_render_buffer(render_buffers[i]);
185 render_buffers[i] = NULL;
186 }
187 render_buffer_count = 0;
188 }
189 }
191 void pvr2_save_render_buffer( FILE *f, render_buffer_t buffer )
192 {
193 struct frame_buffer fbuf;
195 fbuf.width = buffer->width;
196 fbuf.height = buffer->height;
197 fbuf.rowstride = fbuf.width*3;
198 fbuf.colour_format = COLFMT_BGR888;
199 fbuf.inverted = buffer->inverted;
200 fbuf.data = g_malloc0( buffer->width * buffer->height * 3 );
202 display_driver->read_render_buffer( fbuf.data, buffer, fbuf.rowstride, COLFMT_BGR888 );
203 write_png_to_stream( f, &fbuf );
204 g_free( fbuf.data );
206 fwrite( &buffer->rowstride, sizeof(buffer->rowstride), 1, f );
207 fwrite( &buffer->colour_format, sizeof(buffer->colour_format), 1, f );
208 fwrite( &buffer->address, sizeof(buffer->address), 1, f );
209 fwrite( &buffer->scale, sizeof(buffer->scale), 1, f );
210 int32_t flushed = (int32_t)buffer->flushed; // Force to 32-bits for save-file consistency
211 fwrite( &flushed, sizeof(flushed), 1, f );
213 }
215 render_buffer_t pvr2_load_render_buffer( FILE *f )
216 {
217 frame_buffer_t frame = read_png_from_stream( f );
218 if( frame == NULL ) {
219 return NULL;
220 }
222 render_buffer_t buffer = pvr2_frame_buffer_to_render_buffer(frame);
223 if( buffer != NULL ) {
224 int32_t flushed;
225 fread( &buffer->rowstride, sizeof(buffer->rowstride), 1, f );
226 fread( &buffer->colour_format, sizeof(buffer->colour_format), 1, f );
227 fread( &buffer->address, sizeof(buffer->address), 1, f );
228 fread( &buffer->scale, sizeof(buffer->scale), 1, f );
229 fread( &flushed, sizeof(flushed), 1, f );
230 buffer->flushed = (gboolean)flushed;
231 } else {
232 fseek( f, sizeof(buffer->rowstride)+sizeof(buffer->colour_format)+
233 sizeof(buffer->address)+sizeof(buffer->scale)+
234 sizeof(int32_t), SEEK_CUR );
235 }
236 return buffer;
237 }
242 void pvr2_save_render_buffers( FILE *f )
243 {
244 int i;
245 uint32_t has_frontbuffer;
246 fwrite( &render_buffer_count, sizeof(render_buffer_count), 1, f );
247 if( displayed_render_buffer != NULL ) {
248 has_frontbuffer = 1;
249 fwrite( &has_frontbuffer, sizeof(has_frontbuffer), 1, f );
250 pvr2_save_render_buffer( f, displayed_render_buffer );
251 } else {
252 has_frontbuffer = 0;
253 fwrite( &has_frontbuffer, sizeof(has_frontbuffer), 1, f );
254 }
256 for( i=0; i<render_buffer_count; i++ ) {
257 if( render_buffers[i] != displayed_render_buffer && render_buffers[i] != NULL ) {
258 pvr2_save_render_buffer( f, render_buffers[i] );
259 }
260 }
261 }
263 gboolean pvr2_load_render_buffers( FILE *f )
264 {
265 uint32_t count, has_frontbuffer;
266 int i;
268 fread( &count, sizeof(count), 1, f );
269 if( count > MAX_RENDER_BUFFERS ) {
270 return FALSE;
271 }
272 fread( &has_frontbuffer, sizeof(has_frontbuffer), 1, f );
273 for( i=0; i<render_buffer_count; i++ ) {
274 display_driver->destroy_render_buffer(render_buffers[i]);
275 render_buffers[i] = NULL;
276 }
277 render_buffer_count = 0;
279 if( has_frontbuffer ) {
280 displayed_render_buffer = pvr2_load_render_buffer(f);
281 if( displayed_render_buffer == NULL )
282 return FALSE;
283 display_driver->display_render_buffer( displayed_render_buffer );
284 count--;
285 }
287 for( i=0; i<count; i++ ) {
288 if( pvr2_load_render_buffer( f ) == NULL )
289 return FALSE;
290 }
291 return TRUE;
292 }
295 static void pvr2_save_state( FILE *f )
296 {
297 pvr2_save_render_buffers( f );
298 fwrite( &pvr2_state, sizeof(pvr2_state), 1, f );
299 pvr2_ta_save_state( f );
300 pvr2_yuv_save_state( f );
301 }
303 static int pvr2_load_state( FILE *f )
304 {
305 if( !pvr2_load_render_buffers(f) )
306 return 1;
307 if( fread( &pvr2_state, sizeof(pvr2_state), 1, f ) != 1 )
308 return 1;
309 if( pvr2_ta_load_state(f) ) {
310 return 1;
311 }
312 return pvr2_yuv_load_state(f);
313 }
315 /**
316 * Update the current raster position to the given number of nanoseconds,
317 * relative to the last time slice. (ie the raster will be adjusted forward
318 * by nanosecs - nanosecs_already_run_this_timeslice)
319 */
320 static void pvr2_update_raster_posn( uint32_t nanosecs )
321 {
322 uint32_t old_line_count = pvr2_state.line_count;
323 if( pvr2_state.line_time_ns == 0 ) {
324 return; /* do nothing */
325 }
326 pvr2_state.line_remainder += (nanosecs - pvr2_state.cycles_run);
327 pvr2_state.cycles_run = nanosecs;
328 while( pvr2_state.line_remainder >= pvr2_state.line_time_ns ) {
329 pvr2_state.line_count ++;
330 pvr2_state.line_remainder -= pvr2_state.line_time_ns;
331 }
333 if( pvr2_state.line_count >= pvr2_state.total_lines ) {
334 pvr2_state.line_count -= pvr2_state.total_lines;
335 if( pvr2_state.interlaced ) {
336 pvr2_state.odd_even_field = !pvr2_state.odd_even_field;
337 }
338 }
339 if( pvr2_state.line_count >= pvr2_state.retrace_end_line &&
340 (old_line_count < pvr2_state.retrace_end_line ||
341 old_line_count > pvr2_state.line_count) ) {
342 pvr2_state.frame_count++;
343 pvr2_display_frame();
344 }
345 }
347 static uint32_t pvr2_run_slice( uint32_t nanosecs )
348 {
349 pvr2_update_raster_posn( nanosecs );
350 pvr2_state.cycles_run = 0;
351 return nanosecs;
352 }
354 int pvr2_get_frame_count()
355 {
356 return pvr2_state.frame_count;
357 }
359 void pvr2_redraw_display()
360 {
361 if( display_driver != NULL ) {
362 if( displayed_render_buffer == NULL ) {
363 display_driver->display_blank(displayed_border_colour);
364 } else {
365 display_driver->display_render_buffer(displayed_render_buffer);
366 }
367 }
368 }
370 gboolean pvr2_save_next_scene( const gchar *filename )
371 {
372 if( save_next_render_filename != NULL ) {
373 g_free( save_next_render_filename );
374 }
375 save_next_render_filename = g_strdup(filename);
376 return TRUE;
377 }
381 /**
382 * Display the next frame, copying the current contents of video ram to
383 * the window. If the video configuration has changed, first recompute the
384 * new frame size/depth.
385 */
386 void pvr2_display_frame( void )
387 {
388 int dispmode = MMIO_READ( PVR2, DISP_MODE );
389 int vidcfg = MMIO_READ( PVR2, DISP_SYNCCFG );
390 gboolean bEnabled = (dispmode & DISPMODE_ENABLE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE;
392 if( display_driver == NULL ) {
393 return; /* can't really do anything much */
394 } else if( !bEnabled ) {
395 /* Output disabled == black */
396 displayed_render_buffer = NULL;
397 displayed_border_colour = 0;
398 display_driver->display_blank( 0 );
399 } else if( MMIO_READ( PVR2, DISP_CFG2 ) & 0x08 ) {
400 /* Enabled but blanked - border colour */
401 displayed_border_colour = MMIO_READ( PVR2, DISP_BORDER );
402 displayed_render_buffer = NULL;
403 display_driver->display_blank( displayed_border_colour );
404 } else {
405 /* Real output - determine dimensions etc */
406 struct frame_buffer fbuf;
407 uint32_t dispsize = MMIO_READ( PVR2, DISP_SIZE );
408 int vid_stride = (((dispsize & DISPSIZE_MODULO) >> 20) - 1);
409 int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
411 fbuf.colour_format = output_colour_formats[(dispmode & DISPMODE_COLFMT) >> 2];
412 fbuf.width = vid_ppl << 2 / colour_formats[fbuf.colour_format].bpp;
413 fbuf.height = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
414 fbuf.size = vid_ppl << 2 * fbuf.height;
415 fbuf.rowstride = (vid_ppl + vid_stride) << 2;
417 /* Determine the field to display, and deinterlace if possible */
418 if( pvr2_state.interlaced ) {
419 if( vid_ppl == vid_stride ) { /* Magic deinterlace */
420 fbuf.height = fbuf.height << 1;
421 fbuf.rowstride = vid_ppl << 2;
422 fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
423 } else {
424 /* Just display the field as is, folks. This is slightly tricky -
425 * we pick the field based on which frame is about to come through,
426 * which may not be the same as the odd_even_field.
427 */
428 gboolean oddfield = pvr2_state.odd_even_field;
429 if( pvr2_state.line_count >= pvr2_state.retrace_start_line ) {
430 oddfield = !oddfield;
431 }
432 if( oddfield ) {
433 fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
434 } else {
435 fbuf.address = MMIO_READ( PVR2, DISP_ADDR2 );
436 }
437 }
438 } else {
439 fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
440 }
441 fbuf.address = (fbuf.address & 0x00FFFFFF) + PVR2_RAM_BASE;
442 fbuf.inverted = FALSE;
443 fbuf.data = video_base + (fbuf.address&0x00FFFFFF);
445 render_buffer_t rbuf = pvr2_get_render_buffer( &fbuf );
446 if( rbuf == NULL ) {
447 rbuf = pvr2_frame_buffer_to_render_buffer( &fbuf );
448 }
449 displayed_render_buffer = rbuf;
450 if( rbuf != NULL ) {
451 display_driver->display_render_buffer( rbuf );
452 }
453 }
454 }
456 /**
457 * This has to handle every single register individually as they all get masked
458 * off differently (and its easier to do it at write time)
459 */
460 void mmio_region_PVR2_write( uint32_t reg, uint32_t val )
461 {
462 if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
463 MMIO_WRITE( PVR2, reg, val );
464 return;
465 }
467 switch(reg) {
468 case PVRID:
469 case PVRVER:
470 case GUNPOS: /* Read only registers */
471 break;
472 case PVRRESET:
473 val &= 0x00000007; /* Do stuff? */
474 MMIO_WRITE( PVR2, reg, val );
475 break;
476 case RENDER_START: /* Don't really care what value */
477 if( save_next_render_filename != NULL ) {
478 if( pvr2_render_save_scene(save_next_render_filename) == 0 ) {
479 INFO( "Saved scene to %s", save_next_render_filename);
480 }
481 g_free( save_next_render_filename );
482 save_next_render_filename = NULL;
483 }
484 pvr2_scene_read();
485 render_buffer_t buffer = pvr2_next_render_buffer();
486 if( buffer != NULL ) {
487 pvr2_scene_render( buffer );
488 pvr2_finish_render_buffer( buffer );
489 if( buffer->address < PVR2_RAM_BASE ) {
490 // Flush immediately - optimize this later. Otherwise this gets
491 // complicated very quickly trying to second-guess how it's
492 // going to be used as a texture.
493 pvr2_render_buffer_copy_to_sh4( buffer );
494 }
495 }
496 asic_event( EVENT_PVR_RENDER_DONE );
497 break;
498 case RENDER_POLYBASE:
499 MMIO_WRITE( PVR2, reg, val&0x00F00000 );
500 break;
501 case RENDER_TSPCFG:
502 MMIO_WRITE( PVR2, reg, val&0x00010101 );
503 break;
504 case DISP_BORDER:
505 MMIO_WRITE( PVR2, reg, val&0x01FFFFFF );
506 break;
507 case DISP_MODE:
508 MMIO_WRITE( PVR2, reg, val&0x00FFFF7F );
509 break;
510 case RENDER_MODE:
511 MMIO_WRITE( PVR2, reg, val&0x00FFFF0F );
512 break;
513 case RENDER_SIZE:
514 MMIO_WRITE( PVR2, reg, val&0x000001FF );
515 break;
516 case DISP_ADDR1:
517 val &= 0x00FFFFFC;
518 MMIO_WRITE( PVR2, reg, val );
519 pvr2_update_raster_posn(sh4r.slice_cycle);
520 break;
521 case DISP_ADDR2:
522 MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
523 pvr2_update_raster_posn(sh4r.slice_cycle);
524 break;
525 case DISP_SIZE:
526 MMIO_WRITE( PVR2, reg, val&0x3FFFFFFF );
527 break;
528 case RENDER_ADDR1:
529 case RENDER_ADDR2:
530 MMIO_WRITE( PVR2, reg, val&0x01FFFFFC );
531 break;
532 case RENDER_HCLIP:
533 MMIO_WRITE( PVR2, reg, val&0x07FF07FF );
534 break;
535 case RENDER_VCLIP:
536 MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
537 break;
538 case DISP_HPOSIRQ:
539 MMIO_WRITE( PVR2, reg, val&0x03FF33FF );
540 pvr2_state.irq_hpos_line = val & 0x03FF;
541 pvr2_state.irq_hpos_time_ns = 2000000*((val>>16)&0x03FF)/pvr2_state.dot_clock;
542 pvr2_state.irq_hpos_mode = (val >> 12) & 0x03;
543 switch( pvr2_state.irq_hpos_mode ) {
544 case 3: /* Reserved - treat as 0 */
545 case 0: /* Once per frame at specified line */
546 pvr2_state.irq_hpos_mode = HPOS_PER_FRAME;
547 break;
548 case 2: /* Once per line - as per-line-count */
549 pvr2_state.irq_hpos_line = 1;
550 pvr2_state.irq_hpos_mode = 1;
551 case 1: /* Once per N lines */
552 pvr2_state.irq_hpos_line_count = pvr2_state.irq_hpos_line;
553 pvr2_state.irq_hpos_line = (pvr2_state.line_count >> 1) +
554 pvr2_state.irq_hpos_line_count;
555 while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {
556 pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);
557 }
558 pvr2_state.irq_hpos_mode = HPOS_PER_LINECOUNT;
559 }
560 pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0,
561 pvr2_state.irq_hpos_time_ns );
562 break;
563 case DISP_VPOSIRQ:
564 val = val & 0x03FF03FF;
565 pvr2_state.irq_vpos1 = (val >> 16);
566 pvr2_state.irq_vpos2 = val & 0x03FF;
567 pvr2_update_raster_posn(sh4r.slice_cycle);
568 pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );
569 pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );
570 MMIO_WRITE( PVR2, reg, val );
571 break;
572 case RENDER_NEARCLIP:
573 MMIO_WRITE( PVR2, reg, val & 0x7FFFFFFF );
574 break;
575 case RENDER_SHADOW:
576 MMIO_WRITE( PVR2, reg, val&0x000001FF );
577 break;
578 case RENDER_OBJCFG:
579 MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
580 break;
581 case RENDER_TSPCLIP:
582 MMIO_WRITE( PVR2, reg, val&0x7FFFFFFF );
583 break;
584 case RENDER_FARCLIP:
585 MMIO_WRITE( PVR2, reg, val&0xFFFFFFF0 );
586 break;
587 case RENDER_BGPLANE:
588 MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
589 break;
590 case RENDER_ISPCFG:
591 MMIO_WRITE( PVR2, reg, val&0x00FFFFF9 );
592 break;
593 case VRAM_CFG1:
594 MMIO_WRITE( PVR2, reg, val&0x000000FF );
595 break;
596 case VRAM_CFG2:
597 MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
598 break;
599 case VRAM_CFG3:
600 MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
601 break;
602 case RENDER_FOGTBLCOL:
603 case RENDER_FOGVRTCOL:
604 MMIO_WRITE( PVR2, reg, val&0x00FFFFFF );
605 break;
606 case RENDER_FOGCOEFF:
607 MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
608 break;
609 case RENDER_CLAMPHI:
610 case RENDER_CLAMPLO:
611 MMIO_WRITE( PVR2, reg, val );
612 break;
613 case RENDER_TEXSIZE:
614 MMIO_WRITE( PVR2, reg, val&0x00031F1F );
615 break;
616 case RENDER_PALETTE:
617 MMIO_WRITE( PVR2, reg, val&0x00000003 );
618 break;
619 case RENDER_ALPHA_REF:
620 MMIO_WRITE( PVR2, reg, val&0x000000FF );
621 break;
622 /********** CRTC registers *************/
623 case DISP_HBORDER:
624 case DISP_VBORDER:
625 MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
626 break;
627 case DISP_TOTAL:
628 val = val & 0x03FF03FF;
629 MMIO_WRITE( PVR2, reg, val );
630 pvr2_update_raster_posn(sh4r.slice_cycle);
631 pvr2_state.total_lines = (val >> 16) + 1;
632 pvr2_state.line_size = (val & 0x03FF) + 1;
633 pvr2_state.line_time_ns = 1000000 * pvr2_state.line_size / pvr2_state.dot_clock;
634 pvr2_state.retrace_end_line = 0x2A;
635 pvr2_state.retrace_start_line = pvr2_state.total_lines - 6;
636 pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );
637 pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );
638 pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0,
639 pvr2_state.irq_hpos_time_ns );
640 break;
641 case DISP_SYNCCFG:
642 MMIO_WRITE( PVR2, reg, val&0x000003FF );
643 pvr2_state.interlaced = (val & 0x0010) ? TRUE : FALSE;
644 break;
645 case DISP_SYNCTIME:
646 pvr2_state.vsync_lines = (val >> 8) & 0x0F;
647 pvr2_state.hsync_width_ns = ((val & 0x7F) + 1) * 2000000 / pvr2_state.dot_clock;
648 MMIO_WRITE( PVR2, reg, val&0xFFFFFF7F );
649 break;
650 case DISP_CFG2:
651 MMIO_WRITE( PVR2, reg, val&0x003F01FF );
652 break;
653 case DISP_HPOS:
654 val = val & 0x03FF;
655 pvr2_state.front_porch_ns = (val + 1) * 1000000 / pvr2_state.dot_clock;
656 MMIO_WRITE( PVR2, reg, val );
657 break;
658 case DISP_VPOS:
659 MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
660 break;
662 /*********** Tile accelerator registers ***********/
663 case TA_POLYPOS:
664 case TA_LISTPOS:
665 /* Readonly registers */
666 break;
667 case TA_TILEBASE:
668 case TA_LISTEND:
669 case TA_LISTBASE:
670 MMIO_WRITE( PVR2, reg, val&0x00FFFFE0 );
671 break;
672 case RENDER_TILEBASE:
673 case TA_POLYBASE:
674 case TA_POLYEND:
675 MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
676 break;
677 case TA_TILESIZE:
678 MMIO_WRITE( PVR2, reg, val&0x000F003F );
679 break;
680 case TA_TILECFG:
681 MMIO_WRITE( PVR2, reg, val&0x00133333 );
682 break;
683 case TA_INIT:
684 if( val & 0x80000000 )
685 pvr2_ta_init();
686 break;
687 case TA_REINIT:
688 break;
689 /**************** Scaler registers? ****************/
690 case RENDER_SCALER:
691 MMIO_WRITE( PVR2, reg, val&0x0007FFFF );
692 break;
694 case YUV_ADDR:
695 val = val & 0x00FFFFF8;
696 MMIO_WRITE( PVR2, reg, val );
697 pvr2_yuv_init( val );
698 break;
699 case YUV_CFG:
700 MMIO_WRITE( PVR2, reg, val&0x01013F3F );
701 pvr2_yuv_set_config(val);
702 break;
704 /**************** Unknowns ***************/
705 case PVRUNK1:
706 MMIO_WRITE( PVR2, reg, val&0x000007FF );
707 break;
708 case PVRUNK2:
709 MMIO_WRITE( PVR2, reg, val&0x00000007 );
710 break;
711 case PVRUNK3:
712 MMIO_WRITE( PVR2, reg, val&0x000FFF3F );
713 break;
714 case PVRUNK5:
715 MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
716 break;
717 case PVRUNK7:
718 MMIO_WRITE( PVR2, reg, val&0x00000001 );
719 break;
720 case PVRUNK8:
721 MMIO_WRITE( PVR2, reg, val&0x0300FFFF );
722 break;
723 }
724 }
726 /**
727 * Calculate the current read value of the syncstat register, using
728 * the current SH4 clock time as an offset from the last timeslice.
729 * The register reads (LSB to MSB) as:
730 * 0..9 Current scan line
731 * 10 Odd/even field (1 = odd, 0 = even)
732 * 11 Display active (including border and overscan)
733 * 12 Horizontal sync off
734 * 13 Vertical sync off
735 * Note this method is probably incorrect for anything other than straight
736 * interlaced PAL/NTSC, and needs further testing.
737 */
738 uint32_t pvr2_get_sync_status()
739 {
740 pvr2_update_raster_posn(sh4r.slice_cycle);
741 uint32_t result = pvr2_state.line_count;
743 if( pvr2_state.odd_even_field ) {
744 result |= 0x0400;
745 }
746 if( (pvr2_state.line_count & 0x01) == pvr2_state.odd_even_field ) {
747 if( pvr2_state.line_remainder > pvr2_state.hsync_width_ns ) {
748 result |= 0x1000; /* !HSYNC */
749 }
750 if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
751 if( pvr2_state.line_remainder > pvr2_state.front_porch_ns ) {
752 result |= 0x2800; /* Display active */
753 } else {
754 result |= 0x2000; /* Front porch */
755 }
756 }
757 } else {
758 if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
759 if( pvr2_state.line_remainder < (pvr2_state.line_time_ns - pvr2_state.back_porch_ns)) {
760 result |= 0x3800; /* Display active */
761 } else {
762 result |= 0x3000;
763 }
764 } else {
765 result |= 0x1000; /* Back porch */
766 }
767 }
768 return result;
769 }
771 /**
772 * Schedule a "scanline" event. This actually goes off at
773 * 2 * line in even fields and 2 * line + 1 in odd fields.
774 * Otherwise this behaves as per pvr2_schedule_line_event().
775 * The raster position should be updated before calling this
776 * method.
777 * @param eventid Event to fire at the specified time
778 * @param line Line on which to fire the event (this is 2n/2n+1 for interlaced
779 * displays).
780 * @param hpos_ns Nanoseconds into the line at which to fire.
781 */
782 static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int hpos_ns )
783 {
784 uint32_t field = pvr2_state.odd_even_field;
785 if( line <= pvr2_state.line_count && pvr2_state.interlaced ) {
786 field = !field;
787 }
788 if( hpos_ns > pvr2_state.line_time_ns ) {
789 hpos_ns = pvr2_state.line_time_ns;
790 }
792 line <<= 1;
793 if( field ) {
794 line += 1;
795 }
797 if( line < pvr2_state.total_lines ) {
798 uint32_t lines;
799 uint32_t time;
800 if( line <= pvr2_state.line_count ) {
801 lines = (pvr2_state.total_lines - pvr2_state.line_count + line);
802 } else {
803 lines = (line - pvr2_state.line_count);
804 }
805 if( lines <= minimum_lines ) {
806 lines += pvr2_state.total_lines;
807 }
808 time = (lines * pvr2_state.line_time_ns) - pvr2_state.line_remainder + hpos_ns;
809 event_schedule( eventid, time );
810 } else {
811 event_cancel( eventid );
812 }
813 }
815 void pvr2_queue_gun_event( int xpos, int ypos )
816 {
817 pvr2_update_raster_posn(sh4r.slice_cycle);
818 pvr2_schedule_scanline_event( EVENT_GUNPOS, (ypos >> 1) + pvr2_state.vsync_lines, 0,
819 (1000000 * xpos / pvr2_state.dot_clock) + pvr2_state.hsync_width_ns );
820 }
822 MMIO_REGION_READ_FN( PVR2, reg )
823 {
824 switch( reg ) {
825 case DISP_SYNCSTAT:
826 return pvr2_get_sync_status();
827 default:
828 return MMIO_READ( PVR2, reg );
829 }
830 }
832 MMIO_REGION_WRITE_FN( PVR2PAL, reg, val )
833 {
834 MMIO_WRITE( PVR2PAL, reg, val );
835 pvr2_state.palette_changed = TRUE;
836 }
838 void pvr2_check_palette_changed()
839 {
840 if( pvr2_state.palette_changed ) {
841 texcache_invalidate_palette();
842 pvr2_state.palette_changed = FALSE;
843 }
844 }
846 MMIO_REGION_READ_DEFFN( PVR2PAL );
848 void pvr2_set_base_address( uint32_t base )
849 {
850 mmio_region_PVR2_write( DISP_ADDR1, base );
851 }
856 int32_t mmio_region_PVR2TA_read( uint32_t reg )
857 {
858 return 0xFFFFFFFF;
859 }
861 void mmio_region_PVR2TA_write( uint32_t reg, uint32_t val )
862 {
863 pvr2_ta_write( (unsigned char *)&val, sizeof(uint32_t) );
864 }
866 render_buffer_t pvr2_create_render_buffer( sh4addr_t addr, int width, int height, GLuint tex_id )
867 {
868 if( display_driver != NULL && display_driver->create_render_buffer != NULL ) {
869 render_buffer_t buffer = display_driver->create_render_buffer(width,height,tex_id);
870 buffer->address = addr;
871 return buffer;
872 }
873 return NULL;
874 }
876 void pvr2_destroy_render_buffer( render_buffer_t buffer )
877 {
878 if( !buffer->flushed )
879 pvr2_render_buffer_copy_to_sh4( buffer );
880 display_driver->destroy_render_buffer( buffer );
881 }
883 void pvr2_finish_render_buffer( render_buffer_t buffer )
884 {
885 display_driver->finish_render( buffer );
886 }
888 /**
889 * Find the render buffer corresponding to the requested output frame
890 * (does not consider texture renders).
891 * @return the render_buffer if found, or null if no such buffer.
892 *
893 * Note: Currently does not consider "partial matches", ie partial
894 * frame overlap - it probably needs to do this.
895 */
896 render_buffer_t pvr2_get_render_buffer( frame_buffer_t frame )
897 {
898 int i;
899 for( i=0; i<render_buffer_count; i++ ) {
900 if( render_buffers[i] != NULL && render_buffers[i]->address == frame->address ) {
901 return render_buffers[i];
902 }
903 }
904 return NULL;
905 }
907 /**
908 * Allocate a render buffer with the requested parameters.
909 * The order of preference is:
910 * 1. An existing buffer with the same address. (not flushed unless the new
911 * size is smaller than the old one).
912 * 2. An existing buffer with the same size chosen by LRU order. Old buffer
913 * is flushed to vram.
914 * 3. A new buffer if one can be created.
915 * 4. The current display buff
916 * Note: The current display field(s) will never be overwritten except as a last
917 * resort.
918 */
919 render_buffer_t pvr2_alloc_render_buffer( sh4addr_t render_addr, int width, int height )
920 {
921 int i;
922 render_buffer_t result = NULL;
924 /* Check existing buffers for an available buffer */
925 for( i=0; i<render_buffer_count; i++ ) {
926 if( render_buffers[i]->width == width && render_buffers[i]->height == height ) {
927 /* needs to be the right dimensions */
928 if( render_buffers[i]->address == render_addr ) {
929 if( displayed_render_buffer == render_buffers[i] ) {
930 /* Same address, but we can't use it because the
931 * display has it. Mark it as unaddressed for later.
932 */
933 render_buffers[i]->address = -1;
934 } else {
935 /* perfect */
936 result = render_buffers[i];
937 break;
938 }
939 } else if( render_buffers[i]->address == -1 && result == NULL &&
940 displayed_render_buffer != render_buffers[i] ) {
941 result = render_buffers[i];
942 }
944 } else if( render_buffers[i]->address == render_addr ) {
945 /* right address, wrong size - if it's larger, flush it, otherwise
946 * nuke it quietly */
947 if( render_buffers[i]->width * render_buffers[i]->height >
948 width*height ) {
949 pvr2_render_buffer_copy_to_sh4( render_buffers[i] );
950 }
951 render_buffers[i]->address = -1;
952 }
953 }
955 /* Nothing available - make one */
956 if( result == NULL ) {
957 if( render_buffer_count == MAX_RENDER_BUFFERS ) {
958 /* maximum buffers reached - need to throw one away */
959 uint32_t field1_addr = MMIO_READ( PVR2, DISP_ADDR1 );
960 uint32_t field2_addr = MMIO_READ( PVR2, DISP_ADDR2 );
961 for( i=0; i<render_buffer_count; i++ ) {
962 if( render_buffers[i]->address != field1_addr &&
963 render_buffers[i]->address != field2_addr &&
964 render_buffers[i] != displayed_render_buffer ) {
965 /* Never throw away the current "front buffer(s)" */
966 result = render_buffers[i];
967 if( !result->flushed && result->address != -1 ) {
968 pvr2_render_buffer_copy_to_sh4( result );
969 }
970 if( result->width != width || result->height != height ) {
971 display_driver->destroy_render_buffer(render_buffers[i]);
972 result = display_driver->create_render_buffer(width,height,0);
973 render_buffers[i] = result;
974 }
975 break;
976 }
977 }
978 } else {
979 result = display_driver->create_render_buffer(width,height,0);
980 if( result != NULL ) {
981 render_buffers[render_buffer_count++] = result;
982 }
983 }
984 }
986 if( result != NULL ) {
987 result->address = render_addr;
988 }
989 return result;
990 }
992 /**
993 * Allocate a render buffer based on the current rendering settings
994 */
995 render_buffer_t pvr2_next_render_buffer()
996 {
997 render_buffer_t result = NULL;
998 uint32_t render_addr = MMIO_READ( PVR2, RENDER_ADDR1 );
999 uint32_t render_mode = MMIO_READ( PVR2, RENDER_MODE );
1000 uint32_t render_scale = MMIO_READ( PVR2, RENDER_SCALER );
1001 uint32_t render_stride = MMIO_READ( PVR2, RENDER_SIZE ) << 3;
1003 int width = pvr2_scene_buffer_width();
1004 int height = pvr2_scene_buffer_height();
1005 int colour_format = render_colour_formats[render_mode&0x07];
1007 if( render_addr & 0x01000000 ) { /* vram64 */
1008 render_addr = (render_addr & 0x00FFFFFF) + PVR2_RAM_BASE_INT;
1009 } else { /* vram32 */
1010 render_addr = (render_addr & 0x00FFFFFF) + PVR2_RAM_BASE;
1011 }
1012 result = pvr2_alloc_render_buffer( render_addr, width, height );
1014 /* Setup the buffer */
1015 if( result != NULL ) {
1016 result->rowstride = render_stride;
1017 result->colour_format = colour_format;
1018 result->scale = render_scale;
1019 result->size = width * height * colour_formats[colour_format].bpp;
1020 result->flushed = FALSE;
1021 result->inverted = TRUE; // render buffers are inverted normally
1022 }
1023 return result;
1024 }
1026 static render_buffer_t pvr2_frame_buffer_to_render_buffer( frame_buffer_t frame )
1027 {
1028 render_buffer_t result = pvr2_alloc_render_buffer( frame->address, frame->width, frame->height );
1029 if( result != NULL ) {
1030 int bpp = colour_formats[frame->colour_format].bpp;
1031 result->rowstride = frame->rowstride;
1032 result->colour_format = frame->colour_format;
1033 result->scale = 0x400;
1034 result->size = frame->width * frame->height * bpp;
1035 result->flushed = TRUE;
1036 result->inverted = frame->inverted;
1037 display_driver->load_frame_buffer( frame, result );
1038 }
1039 return result;
1040 }
1043 /**
1044 * Invalidate any caching on the supplied address. Specifically, if it falls
1045 * within any of the render buffers, flush the buffer back to PVR2 ram.
1046 */
1047 gboolean pvr2_render_buffer_invalidate( sh4addr_t address, gboolean isWrite )
1048 {
1049 int i;
1050 address = address & 0x1FFFFFFF;
1051 for( i=0; i<render_buffer_count; i++ ) {
1052 uint32_t bufaddr = render_buffers[i]->address;
1053 if( bufaddr != -1 && bufaddr <= address &&
1054 (bufaddr + render_buffers[i]->size) > address ) {
1055 if( !render_buffers[i]->flushed ) {
1056 pvr2_render_buffer_copy_to_sh4( render_buffers[i] );
1057 }
1058 if( isWrite ) {
1059 render_buffers[i]->address = -1; /* Invalid */
1060 }
1061 return TRUE; /* should never have overlapping buffers */
1062 }
1063 }
1064 return FALSE;
1065 }
.