Search
lxdream.org :: lxdream/src/sh4/sh4mmio.c
lxdream 0.9.1
released Jun 29
Download Now
filename src/sh4/sh4mmio.c
changeset 336:c3455be86ee2
prev323:067583c1a704
next413:bff683bc5228
author nkeynes
date Sat Jan 27 12:04:22 2007 +0000 (13 years ago)
permissions -rw-r--r--
last change Remove BSC stub warnings
view annotate diff log raw
     1 /**
     2  * $Id: sh4mmio.c,v 1.12 2007-01-27 12:04:22 nkeynes Exp $
     3  * 
     4  * Miscellaneous and not-really-implemented SH4 peripheral modules. Also
     5  * responsible for including the IMPL side of the SH4 MMIO pages.
     6  * Most of these will eventually be split off into their own files.
     7  *
     8  * Copyright (c) 2005 Nathan Keynes.
     9  *
    10  * This program is free software; you can redistribute it and/or modify
    11  * it under the terms of the GNU General Public License as published by
    12  * the Free Software Foundation; either version 2 of the License, or
    13  * (at your option) any later version.
    14  *
    15  * This program is distributed in the hope that it will be useful,
    16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    18  * GNU General Public License for more details.
    19  */
    20 #define MODULE sh4_module
    22 #include "dream.h"
    23 #include "mem.h"
    24 #include "clock.h"
    25 #include "sh4core.h"
    26 #include "sh4mmio.h"
    27 #define MMIO_IMPL
    28 #include "sh4mmio.h"
    30 /********************************* MMU *************************************/
    32 MMIO_REGION_READ_DEFFN( MMU )
    34 #define OCRAM_START (0x1C000000>>PAGE_BITS)
    35 #define OCRAM_END   (0x20000000>>PAGE_BITS)
    37 static char *cache = NULL;
    39 void mmio_region_MMU_write( uint32_t reg, uint32_t val )
    40 {
    41     switch(reg) {
    42         case CCR:
    43             mmu_set_cache_mode( val & (CCR_OIX|CCR_ORA) );
    44             break;
    45         default:
    46             break;
    47     }
    48     MMIO_WRITE( MMU, reg, val );
    49 }
    52 void MMU_init() 
    53 {
    54     cache = mem_alloc_pages(2);
    55 }
    57 void MMU_reset()
    58 {
    59     mmio_region_MMU_write( CCR, 0 );
    60 }
    62 void MMU_save_state( FILE *f )
    63 {
    64     fwrite( cache, 4096, 2, f );
    65 }
    67 int MMU_load_state( FILE *f )
    68 {
    69     /* Setup the cache mode according to the saved register value
    70      * (mem_load runs before this point to load all MMIO data)
    71      */
    72     mmio_region_MMU_write( CCR, MMIO_READ(MMU, CCR) );
    73     if( fread( cache, 4096, 2, f ) != 2 ) {
    74 	return 1;
    75     }
    76     return 0;
    77 }
    79 void mmu_set_cache_mode( int mode )
    80 {
    81     uint32_t i;
    82     switch( mode ) {
    83         case MEM_OC_INDEX0: /* OIX=0 */
    84             for( i=OCRAM_START; i<OCRAM_END; i++ )
    85                 page_map[i] = cache + ((i&0x02)<<(PAGE_BITS-1));
    86             break;
    87         case MEM_OC_INDEX1: /* OIX=1 */
    88             for( i=OCRAM_START; i<OCRAM_END; i++ )
    89                 page_map[i] = cache + ((i&0x02000000)>>(25-PAGE_BITS));
    90             break;
    91         default: /* disabled */
    92             for( i=OCRAM_START; i<OCRAM_END; i++ )
    93                 page_map[i] = NULL;
    94             break;
    95     }
    96 }
    99 /********************************* BSC *************************************/
   101 uint32_t bsc_input = 0x0300;
   103 uint16_t bsc_read_pdtra()
   104 {
   105     int i;
   106     uint32_t pctra = MMIO_READ( BSC, PCTRA );
   107     uint16_t output = MMIO_READ( BSC, PDTRA );
   108     uint16_t input_mask = 0, output_mask = 0;
   109     for( i=0; i<16; i++ ) {
   110 	int bits = (pctra >> (i<<1)) & 0x03;
   111 	if( bits == 2 ) input_mask |= (1<<i);
   112 	else if( bits != 0 ) output_mask |= (1<<i);
   113     }
   115     /* ??? */
   116     if( ((output | (~output_mask)) & 0x03) == 3 ) {
   117         output |= 0x03;
   118     } else {
   119         output &= ~0x03;
   120     }
   122     return (bsc_input & input_mask) | output;
   123 }
   125 uint32_t bsc_read_pdtrb()
   126 {
   127     int i;
   128     uint32_t pctrb = MMIO_READ( BSC, PCTRB );
   129     uint16_t output = MMIO_READ( BSC, PDTRB );
   130     uint16_t input_mask = 0, output_mask = 0;
   131     for( i=0; i<4; i++ ) {
   132 	int bits = (pctrb >> (i<<1)) & 0x03;
   133 	if( bits == 2 ) input_mask |= (1<<i);
   134 	else if( bits != 0 ) output_mask |= (1<<i);
   135     }
   137     return ((bsc_input>>16) & input_mask) | output;
   139 }
   141 MMIO_REGION_WRITE_DEFFN(BSC)
   143 int32_t mmio_region_BSC_read( uint32_t reg )
   144 {
   145     int32_t val;
   146     int i;
   147     switch( reg ) {
   148         case PDTRA:
   149 	    val = bsc_read_pdtra();
   150 	    break;
   151         case PDTRB:
   152 	    val = bsc_read_pdtrb();
   153 	    break;
   154         default:
   155             val = MMIO_READ( BSC, reg );
   156     }
   157     return val;
   158 }
   160 /********************************* UBC *************************************/
   162 MMIO_REGION_STUBFNS( UBC )
   165 /********************************** SCI *************************************/
   167 MMIO_REGION_STUBFNS( SCI )
.