Search
lxdream.org :: lxdream/src/sh4/sh4.c
lxdream 0.9.1
released Jun 29
Download Now
filename src/sh4/sh4.c
changeset 502:c4ecae2b1b5e
prev472:8a3ae91eb215
next526:ba3da45b5754
author nkeynes
date Thu Nov 08 11:54:16 2007 +0000 (12 years ago)
permissions -rw-r--r--
last change Add sh4ptr_t type, start converting bare pointer refs to it
view annotate diff log raw
     1 /**
     2  * $Id: sh4.c,v 1.7 2007-11-08 11:54:16 nkeynes Exp $
     3  * 
     4  * SH4 parent module for all CPU modes and SH4 peripheral
     5  * modules.
     6  *
     7  * Copyright (c) 2005 Nathan Keynes.
     8  *
     9  * This program is free software; you can redistribute it and/or modify
    10  * it under the terms of the GNU General Public License as published by
    11  * the Free Software Foundation; either version 2 of the License, or
    12  * (at your option) any later version.
    13  *
    14  * This program is distributed in the hope that it will be useful,
    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17  * GNU General Public License for more details.
    18  */
    20 #define MODULE sh4_module
    21 #include <math.h>
    22 #include "dream.h"
    23 #include "dreamcast.h"
    24 #include "sh4/sh4core.h"
    25 #include "sh4/sh4mmio.h"
    26 #include "sh4/intc.h"
    27 #include "sh4/xltcache.h"
    28 #include "sh4/sh4stat.h"
    29 #include "mem.h"
    30 #include "clock.h"
    31 #include "syscall.h"
    33 #define EXV_EXCEPTION    0x100  /* General exception vector */
    34 #define EXV_TLBMISS      0x400  /* TLB-miss exception vector */
    35 #define EXV_INTERRUPT    0x600  /* External interrupt vector */
    37 void sh4_init( void );
    38 void sh4_x86_init( void );
    39 void sh4_reset( void );
    40 void sh4_start( void );
    41 void sh4_stop( void );
    42 void sh4_save_state( FILE *f );
    43 int sh4_load_state( FILE *f );
    45 uint32_t sh4_run_slice( uint32_t );
    46 uint32_t sh4_xlat_run_slice( uint32_t );
    48 struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset, 
    49 				       NULL, sh4_run_slice, sh4_stop,
    50 				       sh4_save_state, sh4_load_state };
    52 struct sh4_registers sh4r;
    53 struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
    54 int sh4_breakpoint_count = 0;
    55 extern sh4ptr_t sh4_main_ram;
    57 void sh4_set_use_xlat( gboolean use )
    58 {
    59     if( use ) {
    60 	xlat_cache_init();
    61 	sh4_x86_init();
    62 	sh4_module.run_time_slice = sh4_xlat_run_slice;
    63     } else {
    64 	sh4_module.run_time_slice = sh4_run_slice;
    65     }
    66 }
    68 void sh4_init(void)
    69 {
    70     register_io_regions( mmio_list_sh4mmio );
    71     sh4_main_ram = mem_get_region_by_name(MEM_REGION_MAIN);
    72     MMU_init();
    73     sh4_reset();
    74 }
    76 void sh4_reset(void)
    77 {
    78     if(	sh4_module.run_time_slice == sh4_xlat_run_slice ) {
    79 	xlat_flush_cache();
    80     }
    82     /* zero everything out, for the sake of having a consistent state. */
    83     memset( &sh4r, 0, sizeof(sh4r) );
    85     /* Resume running if we were halted */
    86     sh4r.sh4_state = SH4_STATE_RUNNING;
    88     sh4r.pc    = 0xA0000000;
    89     sh4r.new_pc= 0xA0000002;
    90     sh4r.vbr   = 0x00000000;
    91     sh4r.fpscr = 0x00040001;
    92     sh4r.sr    = 0x700000F0;
    93     sh4r.fr_bank = &sh4r.fr[0][0];
    95     /* Mem reset will do this, but if we want to reset _just_ the SH4... */
    96     MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
    98     /* Peripheral modules */
    99     CPG_reset();
   100     INTC_reset();
   101     MMU_reset();
   102     TMU_reset();
   103     SCIF_reset();
   104     sh4_stats_reset();
   105 }
   107 void sh4_stop(void)
   108 {
   109     if(	sh4_module.run_time_slice == sh4_xlat_run_slice ) {
   110 	/* If we were running with the translator, update new_pc and in_delay_slot */
   111 	sh4r.new_pc = sh4r.pc+2;
   112 	sh4r.in_delay_slot = FALSE;
   113     }
   115 }
   117 void sh4_save_state( FILE *f )
   118 {
   119     if(	sh4_module.run_time_slice == sh4_xlat_run_slice ) {
   120 	/* If we were running with the translator, update new_pc and in_delay_slot */
   121 	sh4r.new_pc = sh4r.pc+2;
   122 	sh4r.in_delay_slot = FALSE;
   123     }
   125     fwrite( &sh4r, sizeof(sh4r), 1, f );
   126     MMU_save_state( f );
   127     INTC_save_state( f );
   128     TMU_save_state( f );
   129     SCIF_save_state( f );
   130 }
   132 int sh4_load_state( FILE * f )
   133 {
   134     if(	sh4_module.run_time_slice == sh4_xlat_run_slice ) {
   135 	xlat_flush_cache();
   136     }
   137     fread( &sh4r, sizeof(sh4r), 1, f );
   138     sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0]; // Fixup internal FR pointer
   139     MMU_load_state( f );
   140     INTC_load_state( f );
   141     TMU_load_state( f );
   142     return SCIF_load_state( f );
   143 }
   146 void sh4_set_breakpoint( uint32_t pc, int type )
   147 {
   148     sh4_breakpoints[sh4_breakpoint_count].address = pc;
   149     sh4_breakpoints[sh4_breakpoint_count].type = type;
   150     sh4_breakpoint_count++;
   151 }
   153 gboolean sh4_clear_breakpoint( uint32_t pc, int type )
   154 {
   155     int i;
   157     for( i=0; i<sh4_breakpoint_count; i++ ) {
   158 	if( sh4_breakpoints[i].address == pc && 
   159 	    sh4_breakpoints[i].type == type ) {
   160 	    while( ++i < sh4_breakpoint_count ) {
   161 		sh4_breakpoints[i-1].address = sh4_breakpoints[i].address;
   162 		sh4_breakpoints[i-1].type = sh4_breakpoints[i].type;
   163 	    }
   164 	    sh4_breakpoint_count--;
   165 	    return TRUE;
   166 	}
   167     }
   168     return FALSE;
   169 }
   171 int sh4_get_breakpoint( uint32_t pc )
   172 {
   173     int i;
   174     for( i=0; i<sh4_breakpoint_count; i++ ) {
   175 	if( sh4_breakpoints[i].address == pc )
   176 	    return sh4_breakpoints[i].type;
   177     }
   178     return 0;
   179 }
   181 void sh4_set_pc( int pc )
   182 {
   183     sh4r.pc = pc;
   184     sh4r.new_pc = pc+2;
   185 }
   188 /******************************* Support methods ***************************/
   190 static void sh4_switch_banks( )
   191 {
   192     uint32_t tmp[8];
   194     memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
   195     memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
   196     memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
   197 }
   199 void sh4_write_sr( uint32_t newval )
   200 {
   201     if( (newval ^ sh4r.sr) & SR_RB )
   202         sh4_switch_banks();
   203     sh4r.sr = newval;
   204     sh4r.t = (newval&SR_T) ? 1 : 0;
   205     sh4r.s = (newval&SR_S) ? 1 : 0;
   206     sh4r.m = (newval&SR_M) ? 1 : 0;
   207     sh4r.q = (newval&SR_Q) ? 1 : 0;
   208     intc_mask_changed();
   209 }
   211 uint32_t sh4_read_sr( void )
   212 {
   213     /* synchronize sh4r.sr with the various bitflags */
   214     sh4r.sr &= SR_MQSTMASK;
   215     if( sh4r.t ) sh4r.sr |= SR_T;
   216     if( sh4r.s ) sh4r.sr |= SR_S;
   217     if( sh4r.m ) sh4r.sr |= SR_M;
   218     if( sh4r.q ) sh4r.sr |= SR_Q;
   219     return sh4r.sr;
   220 }
   224 #define RAISE( x, v ) do{			\
   225     if( sh4r.vbr == 0 ) { \
   226         ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
   227         dreamcast_stop(); return FALSE;	\
   228     } else { \
   229         sh4r.spc = sh4r.pc;	\
   230         sh4r.ssr = sh4_read_sr(); \
   231         sh4r.sgr = sh4r.r[15]; \
   232         MMIO_WRITE(MMU,EXPEVT,x); \
   233         sh4r.pc = sh4r.vbr + v; \
   234         sh4r.new_pc = sh4r.pc + 2; \
   235         sh4_write_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
   236 	if( sh4r.in_delay_slot ) { \
   237 	    sh4r.in_delay_slot = 0; \
   238 	    sh4r.spc -= 2; \
   239 	} \
   240     } \
   241     return TRUE; } while(0)
   243 /**
   244  * Raise a general CPU exception for the specified exception code.
   245  * (NOT for TRAPA or TLB exceptions)
   246  */
   247 gboolean sh4_raise_exception( int code )
   248 {
   249     RAISE( code, EXV_EXCEPTION );
   250 }
   252 gboolean sh4_raise_trap( int trap )
   253 {
   254     MMIO_WRITE( MMU, TRA, trap<<2 );
   255     return sh4_raise_exception( EXC_TRAP );
   256 }
   258 gboolean sh4_raise_slot_exception( int normal_code, int slot_code ) {
   259     if( sh4r.in_delay_slot ) {
   260 	return sh4_raise_exception(slot_code);
   261     } else {
   262 	return sh4_raise_exception(normal_code);
   263     }
   264 }
   266 gboolean sh4_raise_tlb_exception( int code )
   267 {
   268     RAISE( code, EXV_TLBMISS );
   269 }
   271 void sh4_accept_interrupt( void )
   272 {
   273     uint32_t code = intc_accept_interrupt();
   274     sh4r.ssr = sh4_read_sr();
   275     sh4r.spc = sh4r.pc;
   276     sh4r.sgr = sh4r.r[15];
   277     sh4_write_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
   278     MMIO_WRITE( MMU, INTEVT, code );
   279     sh4r.pc = sh4r.vbr + 0x600;
   280     sh4r.new_pc = sh4r.pc + 2;
   281     //    WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
   282 }
   284 void signsat48( void )
   285 {
   286     if( ((int64_t)sh4r.mac) < (int64_t)0xFFFF800000000000LL )
   287 	sh4r.mac = 0xFFFF800000000000LL;
   288     else if( ((int64_t)sh4r.mac) > (int64_t)0x00007FFFFFFFFFFFLL )
   289 	sh4r.mac = 0x00007FFFFFFFFFFFLL;
   290 }
   292 void sh4_fsca( uint32_t anglei, float *fr )
   293 {
   294     float angle = (((float)(anglei&0xFFFF))/65536.0) * 2 * M_PI;
   295     *fr++ = cosf(angle);
   296     *fr = sinf(angle);
   297 }
   299 void sh4_sleep(void)
   300 {
   301     if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
   302 	sh4r.sh4_state = SH4_STATE_STANDBY;
   303     } else {
   304 	sh4r.sh4_state = SH4_STATE_SLEEP;
   305     }
   306 }
   308 /**
   309  * Compute the matrix tranform of fv given the matrix xf.
   310  * Both fv and xf are word-swapped as per the sh4r.fr banks
   311  */
   312 void sh4_ftrv( float *target, float *xf )
   313 {
   314     float fv[4] = { target[1], target[0], target[3], target[2] };
   315     target[1] = xf[1] * fv[0] + xf[5]*fv[1] +
   316 	xf[9]*fv[2] + xf[13]*fv[3];
   317     target[0] = xf[0] * fv[0] + xf[4]*fv[1] +
   318 	xf[8]*fv[2] + xf[12]*fv[3];
   319     target[3] = xf[3] * fv[0] + xf[7]*fv[1] +
   320 	xf[11]*fv[2] + xf[15]*fv[3];
   321     target[2] = xf[2] * fv[0] + xf[6]*fv[1] +
   322 	xf[10]*fv[2] + xf[14]*fv[3];
   323 }
.