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lxdream.org :: lxdream/src/sh4/sh4mmio.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4mmio.c
changeset 502:c4ecae2b1b5e
prev428:338966c8aed0
next550:a27e31340147
author nkeynes
date Thu Nov 08 11:54:16 2007 +0000 (12 years ago)
permissions -rw-r--r--
last change Add sh4ptr_t type, start converting bare pointer refs to it
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     1 /**
     2  * $Id: sh4mmio.c,v 1.15 2007-11-08 11:54:16 nkeynes Exp $
     3  * 
     4  * Miscellaneous and not-really-implemented SH4 peripheral modules. Also
     5  * responsible for including the IMPL side of the SH4 MMIO pages.
     6  * Most of these will eventually be split off into their own files.
     7  *
     8  * Copyright (c) 2005 Nathan Keynes.
     9  *
    10  * This program is free software; you can redistribute it and/or modify
    11  * it under the terms of the GNU General Public License as published by
    12  * the Free Software Foundation; either version 2 of the License, or
    13  * (at your option) any later version.
    14  *
    15  * This program is distributed in the hope that it will be useful,
    16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    18  * GNU General Public License for more details.
    19  */
    20 #define MODULE sh4_module
    22 #include "dream.h"
    23 #include "dreamcast.h"
    24 #include "mem.h"
    25 #include "clock.h"
    26 #include "sh4/sh4core.h"
    27 #include "sh4/sh4mmio.h"
    28 #define MMIO_IMPL
    29 #include "sh4/sh4mmio.h"
    31 /********************************* MMU *************************************/
    33 MMIO_REGION_READ_DEFFN( MMU )
    35 #define OCRAM_START (0x1C000000>>PAGE_BITS)
    36 #define OCRAM_END   (0x20000000>>PAGE_BITS)
    38 static sh4ptr_t cache = NULL;
    40 void mmio_region_MMU_write( uint32_t reg, uint32_t val )
    41 {
    42     switch(reg) {
    43     case MMUCR:
    44 	if( val & MMUCR_AT ) {
    45 	    ERROR( "MMU Address translation not implemented!" );
    46 	    dreamcast_stop();
    47 	}
    48 	break;
    49     case CCR:
    50 	mmu_set_cache_mode( val & (CCR_OIX|CCR_ORA) );
    51 	break;
    52     default:
    53 	break;
    54     }
    55     MMIO_WRITE( MMU, reg, val );
    56 }
    59 void MMU_init() 
    60 {
    61     cache = mem_alloc_pages(2);
    62 }
    64 void MMU_reset()
    65 {
    66     mmio_region_MMU_write( CCR, 0 );
    67 }
    69 void MMU_save_state( FILE *f )
    70 {
    71     fwrite( cache, 4096, 2, f );
    72 }
    74 int MMU_load_state( FILE *f )
    75 {
    76     /* Setup the cache mode according to the saved register value
    77      * (mem_load runs before this point to load all MMIO data)
    78      */
    79     mmio_region_MMU_write( CCR, MMIO_READ(MMU, CCR) );
    80     if( fread( cache, 4096, 2, f ) != 2 ) {
    81 	return 1;
    82     }
    83     return 0;
    84 }
    86 void mmu_set_cache_mode( int mode )
    87 {
    88     uint32_t i;
    89     switch( mode ) {
    90         case MEM_OC_INDEX0: /* OIX=0 */
    91             for( i=OCRAM_START; i<OCRAM_END; i++ )
    92                 page_map[i] = cache + ((i&0x02)<<(PAGE_BITS-1));
    93             break;
    94         case MEM_OC_INDEX1: /* OIX=1 */
    95             for( i=OCRAM_START; i<OCRAM_END; i++ )
    96                 page_map[i] = cache + ((i&0x02000000)>>(25-PAGE_BITS));
    97             break;
    98         default: /* disabled */
    99             for( i=OCRAM_START; i<OCRAM_END; i++ )
   100                 page_map[i] = NULL;
   101             break;
   102     }
   103 }
   106 /********************************* BSC *************************************/
   108 uint32_t bsc_input = 0x0300;
   110 uint16_t bsc_read_pdtra()
   111 {
   112     int i;
   113     uint32_t pctra = MMIO_READ( BSC, PCTRA );
   114     uint16_t output = MMIO_READ( BSC, PDTRA );
   115     uint16_t input_mask = 0, output_mask = 0;
   116     for( i=0; i<16; i++ ) {
   117 	int bits = (pctra >> (i<<1)) & 0x03;
   118 	if( bits == 2 ) input_mask |= (1<<i);
   119 	else if( bits != 0 ) output_mask |= (1<<i);
   120     }
   122     /* ??? */
   123     if( ((output | (~output_mask)) & 0x03) == 3 ) {
   124         output |= 0x03;
   125     } else {
   126         output &= ~0x03;
   127     }
   129     return (bsc_input & input_mask) | output;
   130 }
   132 uint32_t bsc_read_pdtrb()
   133 {
   134     int i;
   135     uint32_t pctrb = MMIO_READ( BSC, PCTRB );
   136     uint16_t output = MMIO_READ( BSC, PDTRB );
   137     uint16_t input_mask = 0, output_mask = 0;
   138     for( i=0; i<4; i++ ) {
   139 	int bits = (pctrb >> (i<<1)) & 0x03;
   140 	if( bits == 2 ) input_mask |= (1<<i);
   141 	else if( bits != 0 ) output_mask |= (1<<i);
   142     }
   144     return ((bsc_input>>16) & input_mask) | output;
   146 }
   148 MMIO_REGION_WRITE_DEFFN(BSC)
   150 int32_t mmio_region_BSC_read( uint32_t reg )
   151 {
   152     int32_t val;
   153     switch( reg ) {
   154         case PDTRA:
   155 	    val = bsc_read_pdtra();
   156 	    break;
   157         case PDTRB:
   158 	    val = bsc_read_pdtrb();
   159 	    break;
   160         default:
   161             val = MMIO_READ( BSC, reg );
   162     }
   163     return val;
   164 }
   166 /********************************* UBC *************************************/
   168 MMIO_REGION_STUBFNS( UBC )
   171 /********************************** SCI *************************************/
   173 MMIO_REGION_STUBFNS( SCI )
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