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lxdream.org :: lxdream/src/sh4/sh4core.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4core.c
changeset 359:c588dce7ebde
prev312:2c34bdc36cbd
next367:9c52dcbad3fb
author nkeynes
date Thu Aug 23 12:33:27 2007 +0000 (13 years ago)
permissions -rw-r--r--
last change Commit decoder generator
Translator work in progress
Fix mac.l, mac.w in emu core
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     1 /**
     2  * $Id: sh4core.c,v 1.41 2007-08-23 12:33:27 nkeynes Exp $
     3  * 
     4  * SH4 emulation core, and parent module for all the SH4 peripheral
     5  * modules.
     6  *
     7  * Copyright (c) 2005 Nathan Keynes.
     8  *
     9  * This program is free software; you can redistribute it and/or modify
    10  * it under the terms of the GNU General Public License as published by
    11  * the Free Software Foundation; either version 2 of the License, or
    12  * (at your option) any later version.
    13  *
    14  * This program is distributed in the hope that it will be useful,
    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17  * GNU General Public License for more details.
    18  */
    20 #define MODULE sh4_module
    21 #include <math.h>
    22 #include "dream.h"
    23 #include "sh4/sh4core.h"
    24 #include "sh4/sh4mmio.h"
    25 #include "sh4/intc.h"
    26 #include "mem.h"
    27 #include "clock.h"
    28 #include "syscall.h"
    30 #define SH4_CALLTRACE 1
    32 #define MAX_INT 0x7FFFFFFF
    33 #define MIN_INT 0x80000000
    34 #define MAX_INTF 2147483647.0
    35 #define MIN_INTF -2147483648.0
    37 /* CPU-generated exception code/vector pairs */
    38 #define EXC_POWER_RESET  0x000 /* vector special */
    39 #define EXC_MANUAL_RESET 0x020
    40 #define EXC_READ_ADDR_ERR 0x0E0
    41 #define EXC_WRITE_ADDR_ERR 0x100
    42 #define EXC_SLOT_ILLEGAL 0x1A0
    43 #define EXC_ILLEGAL      0x180
    44 #define EXC_TRAP         0x160
    45 #define EXC_FPDISABLE    0x800
    46 #define EXC_SLOT_FPDISABLE 0x820
    48 #define EXV_EXCEPTION    0x100  /* General exception vector */
    49 #define EXV_TLBMISS      0x400  /* TLB-miss exception vector */
    50 #define EXV_INTERRUPT    0x600  /* External interrupt vector */
    52 /********************** SH4 Module Definition ****************************/
    54 void sh4_init( void );
    55 void sh4_reset( void );
    56 uint32_t sh4_run_slice( uint32_t );
    57 void sh4_start( void );
    58 void sh4_stop( void );
    59 void sh4_save_state( FILE *f );
    60 int sh4_load_state( FILE *f );
    61 void sh4_accept_interrupt( void );
    63 struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset, 
    64 				       NULL, sh4_run_slice, sh4_stop,
    65 				       sh4_save_state, sh4_load_state };
    67 struct sh4_registers sh4r;
    69 void sh4_init(void)
    70 {
    71     register_io_regions( mmio_list_sh4mmio );
    72     MMU_init();
    73     sh4_reset();
    74 }
    76 void sh4_reset(void)
    77 {
    78     /* zero everything out, for the sake of having a consistent state. */
    79     memset( &sh4r, 0, sizeof(sh4r) );
    81     /* Resume running if we were halted */
    82     sh4r.sh4_state = SH4_STATE_RUNNING;
    84     sh4r.pc    = 0xA0000000;
    85     sh4r.new_pc= 0xA0000002;
    86     sh4r.vbr   = 0x00000000;
    87     sh4r.fpscr = 0x00040001;
    88     sh4r.sr    = 0x700000F0;
    90     /* Mem reset will do this, but if we want to reset _just_ the SH4... */
    91     MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
    93     /* Peripheral modules */
    94     CPG_reset();
    95     INTC_reset();
    96     MMU_reset();
    97     TMU_reset();
    98     SCIF_reset();
    99 }
   101 static struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
   102 static int sh4_breakpoint_count = 0;
   103 static uint16_t *sh4_icache = NULL;
   104 static uint32_t sh4_icache_addr = 0;
   106 void sh4_set_breakpoint( uint32_t pc, int type )
   107 {
   108     sh4_breakpoints[sh4_breakpoint_count].address = pc;
   109     sh4_breakpoints[sh4_breakpoint_count].type = type;
   110     sh4_breakpoint_count++;
   111 }
   113 gboolean sh4_clear_breakpoint( uint32_t pc, int type )
   114 {
   115     int i;
   117     for( i=0; i<sh4_breakpoint_count; i++ ) {
   118 	if( sh4_breakpoints[i].address == pc && 
   119 	    sh4_breakpoints[i].type == type ) {
   120 	    while( ++i < sh4_breakpoint_count ) {
   121 		sh4_breakpoints[i-1].address = sh4_breakpoints[i].address;
   122 		sh4_breakpoints[i-1].type = sh4_breakpoints[i].type;
   123 	    }
   124 	    sh4_breakpoint_count--;
   125 	    return TRUE;
   126 	}
   127     }
   128     return FALSE;
   129 }
   131 int sh4_get_breakpoint( uint32_t pc )
   132 {
   133     int i;
   134     for( i=0; i<sh4_breakpoint_count; i++ ) {
   135 	if( sh4_breakpoints[i].address == pc )
   136 	    return sh4_breakpoints[i].type;
   137     }
   138     return 0;
   139 }
   141 uint32_t sh4_run_slice( uint32_t nanosecs ) 
   142 {
   143     int i;
   144     sh4r.slice_cycle = 0;
   146     if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
   147 	if( sh4r.event_pending < nanosecs ) {
   148 	    sh4r.sh4_state = SH4_STATE_RUNNING;
   149 	    sh4r.slice_cycle = sh4r.event_pending;
   150 	}
   151     }
   153     if( sh4_breakpoint_count == 0 ) {
   154 	for( ; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
   155 	    if( SH4_EVENT_PENDING() ) {
   156 		if( sh4r.event_types & PENDING_EVENT ) {
   157 		    event_execute();
   158 		}
   159 		/* Eventq execute may (quite likely) deliver an immediate IRQ */
   160 		if( sh4r.event_types & PENDING_IRQ ) {
   161 		    sh4_accept_interrupt();
   162 		}
   163 	    }
   164 	    if( !sh4_execute_instruction() ) {
   165 		break;
   166 	    }
   167 	}
   168     } else {
   169 	for( ;sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
   170 	    if( SH4_EVENT_PENDING() ) {
   171 		if( sh4r.event_types & PENDING_EVENT ) {
   172 		    event_execute();
   173 		}
   174 		/* Eventq execute may (quite likely) deliver an immediate IRQ */
   175 		if( sh4r.event_types & PENDING_IRQ ) {
   176 		    sh4_accept_interrupt();
   177 		}
   178 	    }
   180 	    if( !sh4_execute_instruction() )
   181 		break;
   182 #ifdef ENABLE_DEBUG_MODE
   183 	    for( i=0; i<sh4_breakpoint_count; i++ ) {
   184 		if( sh4_breakpoints[i].address == sh4r.pc ) {
   185 		    break;
   186 		}
   187 	    }
   188 	    if( i != sh4_breakpoint_count ) {
   189 		dreamcast_stop();
   190 		if( sh4_breakpoints[i].type == BREAK_ONESHOT )
   191 		    sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );
   192 		break;
   193 	    }
   194 #endif	
   195 	}
   196     }
   198     /* If we aborted early, but the cpu is still technically running,
   199      * we're doing a hard abort - cut the timeslice back to what we
   200      * actually executed
   201      */
   202     if( sh4r.slice_cycle != nanosecs && sh4r.sh4_state == SH4_STATE_RUNNING ) {
   203 	nanosecs = sh4r.slice_cycle;
   204     }
   205     if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
   206 	TMU_run_slice( nanosecs );
   207 	SCIF_run_slice( nanosecs );
   208     }
   209     return nanosecs;
   210 }
   212 void sh4_stop(void)
   213 {
   215 }
   217 void sh4_save_state( FILE *f )
   218 {
   219     fwrite( &sh4r, sizeof(sh4r), 1, f );
   220     MMU_save_state( f );
   221     INTC_save_state( f );
   222     TMU_save_state( f );
   223     SCIF_save_state( f );
   224 }
   226 int sh4_load_state( FILE * f )
   227 {
   228     fread( &sh4r, sizeof(sh4r), 1, f );
   229     MMU_load_state( f );
   230     INTC_load_state( f );
   231     TMU_load_state( f );
   232     return SCIF_load_state( f );
   233 }
   235 /********************** SH4 emulation core  ****************************/
   237 void sh4_set_pc( int pc )
   238 {
   239     sh4r.pc = pc;
   240     sh4r.new_pc = pc+2;
   241 }
   243 #define UNDEF(ir) return sh4_raise_slot_exception(EXC_ILLEGAL, EXC_SLOT_ILLEGAL)
   244 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)
   246 #if(SH4_CALLTRACE == 1)
   247 #define MAX_CALLSTACK 32
   248 static struct call_stack {
   249     sh4addr_t call_addr;
   250     sh4addr_t target_addr;
   251     sh4addr_t stack_pointer;
   252 } call_stack[MAX_CALLSTACK];
   254 static int call_stack_depth = 0;
   255 int sh4_call_trace_on = 0;
   257 static inline trace_call( sh4addr_t source, sh4addr_t dest ) 
   258 {
   259     if( call_stack_depth < MAX_CALLSTACK ) {
   260 	call_stack[call_stack_depth].call_addr = source;
   261 	call_stack[call_stack_depth].target_addr = dest;
   262 	call_stack[call_stack_depth].stack_pointer = sh4r.r[15];
   263     }
   264     call_stack_depth++;
   265 }
   267 static inline trace_return( sh4addr_t source, sh4addr_t dest )
   268 {
   269     if( call_stack_depth > 0 ) {
   270 	call_stack_depth--;
   271     }
   272 }
   274 void fprint_stack_trace( FILE *f )
   275 {
   276     int i = call_stack_depth -1;
   277     if( i >= MAX_CALLSTACK )
   278 	i = MAX_CALLSTACK - 1;
   279     for( ; i >= 0; i-- ) {
   280 	fprintf( f, "%d. Call from %08X => %08X, SP=%08X\n", 
   281 		 (call_stack_depth - i), call_stack[i].call_addr,
   282 		 call_stack[i].target_addr, call_stack[i].stack_pointer );
   283     }
   284 }
   286 #define TRACE_CALL( source, dest ) trace_call(source, dest)
   287 #define TRACE_RETURN( source, dest ) trace_return(source, dest)
   288 #else
   289 #define TRACE_CALL( dest, rts ) 
   290 #define TRACE_RETURN( source, dest )
   291 #endif
   293 #define RAISE( x, v ) do{			\
   294     if( sh4r.vbr == 0 ) { \
   295         ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
   296         dreamcast_stop(); return FALSE;	\
   297     } else { \
   298         sh4r.spc = sh4r.pc;	\
   299         sh4r.ssr = sh4_read_sr(); \
   300         sh4r.sgr = sh4r.r[15]; \
   301         MMIO_WRITE(MMU,EXPEVT,x); \
   302         sh4r.pc = sh4r.vbr + v; \
   303         sh4r.new_pc = sh4r.pc + 2; \
   304         sh4_load_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
   305 	if( sh4r.in_delay_slot ) { \
   306 	    sh4r.in_delay_slot = 0; \
   307 	    sh4r.spc -= 2; \
   308 	} \
   309     } \
   310     return TRUE; } while(0)
   312 #define MEM_READ_BYTE( addr ) sh4_read_byte(addr)
   313 #define MEM_READ_WORD( addr ) sh4_read_word(addr)
   314 #define MEM_READ_LONG( addr ) sh4_read_long(addr)
   315 #define MEM_WRITE_BYTE( addr, val ) sh4_write_byte(addr, val)
   316 #define MEM_WRITE_WORD( addr, val ) sh4_write_word(addr, val)
   317 #define MEM_WRITE_LONG( addr, val ) sh4_write_long(addr, val)
   319 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
   321 #define MEM_FP_READ( addr, reg ) sh4_read_float( addr, reg );
   322 #define MEM_FP_WRITE( addr, reg ) sh4_write_float( addr, reg );
   324 #define CHECKPRIV() if( !IS_SH4_PRIVMODE() ) return sh4_raise_slot_exception( EXC_ILLEGAL, EXC_SLOT_ILLEGAL )
   325 #define CHECKRALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_READ_ADDR_ERR )
   326 #define CHECKRALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_READ_ADDR_ERR )
   327 #define CHECKWALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_WRITE_ADDR_ERR )
   328 #define CHECKWALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_WRITE_ADDR_ERR )
   330 #define CHECKFPUEN() if( !IS_FPU_ENABLED() ) { if( ir == 0xFFFD ) { UNDEF(ir); } else { return sh4_raise_slot_exception( EXC_FPDISABLE, EXC_SLOT_FPDISABLE ); } }
   331 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); dreamcast_stop(); return FALSE; }
   332 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) return sh4_raise_exception(EXC_SLOT_ILLEGAL)
   334 static void sh4_switch_banks( )
   335 {
   336     uint32_t tmp[8];
   338     memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
   339     memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
   340     memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
   341 }
   343 static void sh4_load_sr( uint32_t newval )
   344 {
   345     if( (newval ^ sh4r.sr) & SR_RB )
   346         sh4_switch_banks();
   347     sh4r.sr = newval;
   348     sh4r.t = (newval&SR_T) ? 1 : 0;
   349     sh4r.s = (newval&SR_S) ? 1 : 0;
   350     sh4r.m = (newval&SR_M) ? 1 : 0;
   351     sh4r.q = (newval&SR_Q) ? 1 : 0;
   352     intc_mask_changed();
   353 }
   355 static void sh4_write_float( uint32_t addr, int reg )
   356 {
   357     if( IS_FPU_DOUBLESIZE() ) {
   358 	if( reg & 1 ) {
   359 	    sh4_write_long( addr, *((uint32_t *)&XF((reg)&0x0E)) );
   360 	    sh4_write_long( addr+4, *((uint32_t *)&XF(reg)) );
   361 	} else {
   362 	    sh4_write_long( addr, *((uint32_t *)&FR(reg)) ); 
   363 	    sh4_write_long( addr+4, *((uint32_t *)&FR((reg)|0x01)) );
   364 	}
   365     } else {
   366 	sh4_write_long( addr, *((uint32_t *)&FR((reg))) );
   367     }
   368 }
   370 static void sh4_read_float( uint32_t addr, int reg )
   371 {
   372     if( IS_FPU_DOUBLESIZE() ) {
   373 	if( reg & 1 ) {
   374 	    *((uint32_t *)&XF((reg) & 0x0E)) = sh4_read_long(addr);
   375 	    *((uint32_t *)&XF(reg)) = sh4_read_long(addr+4);
   376 	} else {
   377 	    *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
   378 	    *((uint32_t *)&FR((reg) | 0x01)) = sh4_read_long(addr+4);
   379 	}
   380     } else {
   381 	*((uint32_t *)&FR(reg)) = sh4_read_long(addr);
   382     }
   383 }
   385 static uint32_t sh4_read_sr( void )
   386 {
   387     /* synchronize sh4r.sr with the various bitflags */
   388     sh4r.sr &= SR_MQSTMASK;
   389     if( sh4r.t ) sh4r.sr |= SR_T;
   390     if( sh4r.s ) sh4r.sr |= SR_S;
   391     if( sh4r.m ) sh4r.sr |= SR_M;
   392     if( sh4r.q ) sh4r.sr |= SR_Q;
   393     return sh4r.sr;
   394 }
   396 /**
   397  * Raise a general CPU exception for the specified exception code.
   398  * (NOT for TRAPA or TLB exceptions)
   399  */
   400 gboolean sh4_raise_exception( int code )
   401 {
   402     RAISE( code, EXV_EXCEPTION );
   403 }
   405 gboolean sh4_raise_slot_exception( int normal_code, int slot_code ) {
   406     if( sh4r.in_delay_slot ) {
   407 	return sh4_raise_exception(slot_code);
   408     } else {
   409 	return sh4_raise_exception(normal_code);
   410     }
   411 }
   413 gboolean sh4_raise_tlb_exception( int code )
   414 {
   415     RAISE( code, EXV_TLBMISS );
   416 }
   418 void sh4_accept_interrupt( void )
   419 {
   420     uint32_t code = intc_accept_interrupt();
   421     sh4r.ssr = sh4_read_sr();
   422     sh4r.spc = sh4r.pc;
   423     sh4r.sgr = sh4r.r[15];
   424     sh4_load_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
   425     MMIO_WRITE( MMU, INTEVT, code );
   426     sh4r.pc = sh4r.vbr + 0x600;
   427     sh4r.new_pc = sh4r.pc + 2;
   428     //    WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
   429 }
   431 gboolean sh4_execute_instruction( void )
   432 {
   433     uint32_t pc;
   434     unsigned short ir;
   435     uint32_t tmp;
   436     float ftmp;
   437     double dtmp;
   439 #define R0 sh4r.r[0]
   440     pc = sh4r.pc;
   441     if( pc > 0xFFFFFF00 ) {
   442 	/* SYSCALL Magic */
   443 	syscall_invoke( pc );
   444 	sh4r.in_delay_slot = 0;
   445 	pc = sh4r.pc = sh4r.pr;
   446 	sh4r.new_pc = sh4r.pc + 2;
   447     }
   448     CHECKRALIGN16(pc);
   450     /* Read instruction */
   451     uint32_t pageaddr = pc >> 12;
   452     if( sh4_icache != NULL && pageaddr == sh4_icache_addr ) {
   453 	ir = sh4_icache[(pc&0xFFF)>>1];
   454     } else {
   455 	sh4_icache = (uint16_t *)mem_get_page(pc);
   456 	if( ((uint32_t)sh4_icache) < MAX_IO_REGIONS ) {
   457 	    /* If someone's actually been so daft as to try to execute out of an IO
   458 	     * region, fallback on the full-blown memory read
   459 	     */
   460 	    sh4_icache = NULL;
   461 	    ir = MEM_READ_WORD(pc);
   462 	} else {
   463 	    sh4_icache_addr = pageaddr;
   464 	    ir = sh4_icache[(pc&0xFFF)>>1];
   465 	}
   466     }
   467         switch( (ir&0xF000) >> 12 ) {
   468             case 0x0:
   469                 switch( ir&0xF ) {
   470                     case 0x2:
   471                         switch( (ir&0x80) >> 7 ) {
   472                             case 0x0:
   473                                 switch( (ir&0x70) >> 4 ) {
   474                                     case 0x0:
   475                                         { /* STC SR, Rn */
   476                                         uint32_t Rn = ((ir>>8)&0xF); 
   477                                         CHECKPRIV();
   478                                         sh4r.r[Rn] = sh4_read_sr();
   479                                         }
   480                                         break;
   481                                     case 0x1:
   482                                         { /* STC GBR, Rn */
   483                                         uint32_t Rn = ((ir>>8)&0xF); 
   484                                         CHECKPRIV();
   485                                         sh4r.r[Rn] = sh4r.gbr;
   486                                         }
   487                                         break;
   488                                     case 0x2:
   489                                         { /* STC VBR, Rn */
   490                                         uint32_t Rn = ((ir>>8)&0xF); 
   491                                         CHECKPRIV();
   492                                         sh4r.r[Rn] = sh4r.vbr;
   493                                         }
   494                                         break;
   495                                     case 0x3:
   496                                         { /* STC SSR, Rn */
   497                                         uint32_t Rn = ((ir>>8)&0xF); 
   498                                         CHECKPRIV();
   499                                         sh4r.r[Rn] = sh4r.ssr;
   500                                         }
   501                                         break;
   502                                     case 0x4:
   503                                         { /* STC SPC, Rn */
   504                                         uint32_t Rn = ((ir>>8)&0xF); 
   505                                         CHECKPRIV();
   506                                         sh4r.r[Rn] = sh4r.spc;
   507                                         }
   508                                         break;
   509                                     default:
   510                                         UNDEF();
   511                                         break;
   512                                 }
   513                                 break;
   514                             case 0x1:
   515                                 { /* STC Rm_BANK, Rn */
   516                                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
   517                                 CHECKPRIV();
   518                                 sh4r.r[Rn] = sh4r.r_bank[Rm_BANK];
   519                                 }
   520                                 break;
   521                         }
   522                         break;
   523                     case 0x3:
   524                         switch( (ir&0xF0) >> 4 ) {
   525                             case 0x0:
   526                                 { /* BSRF Rn */
   527                                 uint32_t Rn = ((ir>>8)&0xF); 
   528                                 CHECKSLOTILLEGAL();
   529                                 CHECKDEST( pc + 4 + sh4r.r[Rn] );
   530                                 sh4r.in_delay_slot = 1;
   531                                 sh4r.pr = sh4r.pc + 4;
   532                                 sh4r.pc = sh4r.new_pc;
   533                                 sh4r.new_pc = pc + 4 + sh4r.r[Rn];
   534                                 TRACE_CALL( pc, sh4r.new_pc );
   535                                 return TRUE;
   536                                 }
   537                                 break;
   538                             case 0x2:
   539                                 { /* BRAF Rn */
   540                                 uint32_t Rn = ((ir>>8)&0xF); 
   541                                 CHECKSLOTILLEGAL();
   542                                 CHECKDEST( pc + 4 + sh4r.r[Rn] );
   543                                 sh4r.in_delay_slot = 1;
   544                                 sh4r.pc = sh4r.new_pc;
   545                                 sh4r.new_pc = pc + 4 + sh4r.r[Rn];
   546                                 return TRUE;
   547                                 }
   548                                 break;
   549                             case 0x8:
   550                                 { /* PREF @Rn */
   551                                 uint32_t Rn = ((ir>>8)&0xF); 
   552                                 tmp = sh4r.r[Rn];
   553                                 if( (tmp & 0xFC000000) == 0xE0000000 ) {
   554                            	 /* Store queue operation */
   555                            	 int queue = (tmp&0x20)>>2;
   556                            	 int32_t *src = &sh4r.store_queue[queue];
   557                            	 uint32_t hi = (MMIO_READ( MMU, (queue == 0 ? QACR0 : QACR1) ) & 0x1C) << 24;
   558                            	 uint32_t target = tmp&0x03FFFFE0 | hi;
   559                            	 mem_copy_to_sh4( target, src, 32 );
   560                                 }
   561                                 }
   562                                 break;
   563                             case 0x9:
   564                                 { /* OCBI @Rn */
   565                                 uint32_t Rn = ((ir>>8)&0xF); 
   566                                 }
   567                                 break;
   568                             case 0xA:
   569                                 { /* OCBP @Rn */
   570                                 uint32_t Rn = ((ir>>8)&0xF); 
   571                                 }
   572                                 break;
   573                             case 0xB:
   574                                 { /* OCBWB @Rn */
   575                                 uint32_t Rn = ((ir>>8)&0xF); 
   576                                 }
   577                                 break;
   578                             case 0xC:
   579                                 { /* MOVCA.L R0, @Rn */
   580                                 uint32_t Rn = ((ir>>8)&0xF); 
   581                                 tmp = sh4r.r[Rn];
   582                                 CHECKWALIGN32(tmp);
   583                                 MEM_WRITE_LONG( tmp, R0 );
   584                                 }
   585                                 break;
   586                             default:
   587                                 UNDEF();
   588                                 break;
   589                         }
   590                         break;
   591                     case 0x4:
   592                         { /* MOV.B Rm, @(R0, Rn) */
   593                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   594                         MEM_WRITE_BYTE( R0 + sh4r.r[Rn], sh4r.r[Rm] );
   595                         }
   596                         break;
   597                     case 0x5:
   598                         { /* MOV.W Rm, @(R0, Rn) */
   599                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   600                         CHECKWALIGN16( R0 + sh4r.r[Rn] );
   601                         MEM_WRITE_WORD( R0 + sh4r.r[Rn], sh4r.r[Rm] );
   602                         }
   603                         break;
   604                     case 0x6:
   605                         { /* MOV.L Rm, @(R0, Rn) */
   606                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   607                         CHECKWALIGN32( R0 + sh4r.r[Rn] );
   608                         MEM_WRITE_LONG( R0 + sh4r.r[Rn], sh4r.r[Rm] );
   609                         }
   610                         break;
   611                     case 0x7:
   612                         { /* MUL.L Rm, Rn */
   613                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   614                         sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   615                                                (sh4r.r[Rm] * sh4r.r[Rn]);
   616                         }
   617                         break;
   618                     case 0x8:
   619                         switch( (ir&0xFF0) >> 4 ) {
   620                             case 0x0:
   621                                 { /* CLRT */
   622                                 sh4r.t = 0;
   623                                 }
   624                                 break;
   625                             case 0x1:
   626                                 { /* SETT */
   627                                 sh4r.t = 1;
   628                                 }
   629                                 break;
   630                             case 0x2:
   631                                 { /* CLRMAC */
   632                                 sh4r.mac = 0;
   633                                 }
   634                                 break;
   635                             case 0x3:
   636                                 { /* LDTLB */
   637                                 /* TODO */
   638                                 }
   639                                 break;
   640                             case 0x4:
   641                                 { /* CLRS */
   642                                 sh4r.s = 0;
   643                                 }
   644                                 break;
   645                             case 0x5:
   646                                 { /* SETS */
   647                                 sh4r.s = 1;
   648                                 }
   649                                 break;
   650                             default:
   651                                 UNDEF();
   652                                 break;
   653                         }
   654                         break;
   655                     case 0x9:
   656                         switch( (ir&0xF0) >> 4 ) {
   657                             case 0x0:
   658                                 { /* NOP */
   659                                 /* NOP */
   660                                 }
   661                                 break;
   662                             case 0x1:
   663                                 { /* DIV0U */
   664                                 sh4r.m = sh4r.q = sh4r.t = 0;
   665                                 }
   666                                 break;
   667                             case 0x2:
   668                                 { /* MOVT Rn */
   669                                 uint32_t Rn = ((ir>>8)&0xF); 
   670                                 sh4r.r[Rn] = sh4r.t;
   671                                 }
   672                                 break;
   673                             default:
   674                                 UNDEF();
   675                                 break;
   676                         }
   677                         break;
   678                     case 0xA:
   679                         switch( (ir&0xF0) >> 4 ) {
   680                             case 0x0:
   681                                 { /* STS MACH, Rn */
   682                                 uint32_t Rn = ((ir>>8)&0xF); 
   683                                 sh4r.r[Rn] = (sh4r.mac>>32);
   684                                 }
   685                                 break;
   686                             case 0x1:
   687                                 { /* STS MACL, Rn */
   688                                 uint32_t Rn = ((ir>>8)&0xF); 
   689                                 sh4r.r[Rn] = (uint32_t)sh4r.mac;
   690                                 }
   691                                 break;
   692                             case 0x2:
   693                                 { /* STS PR, Rn */
   694                                 uint32_t Rn = ((ir>>8)&0xF); 
   695                                 sh4r.r[Rn] = sh4r.pr;
   696                                 }
   697                                 break;
   698                             case 0x3:
   699                                 { /* STC SGR, Rn */
   700                                 uint32_t Rn = ((ir>>8)&0xF); 
   701                                 CHECKPRIV();
   702                                 sh4r.r[Rn] = sh4r.sgr;
   703                                 }
   704                                 break;
   705                             case 0x5:
   706                                 { /* STS FPUL, Rn */
   707                                 uint32_t Rn = ((ir>>8)&0xF); 
   708                                 sh4r.r[Rn] = sh4r.fpul;
   709                                 }
   710                                 break;
   711                             case 0x6:
   712                                 { /* STS FPSCR, Rn */
   713                                 uint32_t Rn = ((ir>>8)&0xF); 
   714                                 sh4r.r[Rn] = sh4r.fpscr;
   715                                 }
   716                                 break;
   717                             case 0xF:
   718                                 { /* STC DBR, Rn */
   719                                 uint32_t Rn = ((ir>>8)&0xF); 
   720                                 CHECKPRIV(); sh4r.r[Rn] = sh4r.dbr;
   721                                 }
   722                                 break;
   723                             default:
   724                                 UNDEF();
   725                                 break;
   726                         }
   727                         break;
   728                     case 0xB:
   729                         switch( (ir&0xFF0) >> 4 ) {
   730                             case 0x0:
   731                                 { /* RTS */
   732                                 CHECKSLOTILLEGAL();
   733                                 CHECKDEST( sh4r.pr );
   734                                 sh4r.in_delay_slot = 1;
   735                                 sh4r.pc = sh4r.new_pc;
   736                                 sh4r.new_pc = sh4r.pr;
   737                                 TRACE_RETURN( pc, sh4r.new_pc );
   738                                 return TRUE;
   739                                 }
   740                                 break;
   741                             case 0x1:
   742                                 { /* SLEEP */
   743                                 if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
   744                             	sh4r.sh4_state = SH4_STATE_STANDBY;
   745                                 } else {
   746                             	sh4r.sh4_state = SH4_STATE_SLEEP;
   747                                 }
   748                                 return FALSE; /* Halt CPU */
   749                                 }
   750                                 break;
   751                             case 0x2:
   752                                 { /* RTE */
   753                                 CHECKPRIV();
   754                                 CHECKDEST( sh4r.spc );
   755                                 CHECKSLOTILLEGAL();
   756                                 sh4r.in_delay_slot = 1;
   757                                 sh4r.pc = sh4r.new_pc;
   758                                 sh4r.new_pc = sh4r.spc;
   759                                 sh4_load_sr( sh4r.ssr );
   760                                 return TRUE;
   761                                 }
   762                                 break;
   763                             default:
   764                                 UNDEF();
   765                                 break;
   766                         }
   767                         break;
   768                     case 0xC:
   769                         { /* MOV.B @(R0, Rm), Rn */
   770                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   771                         sh4r.r[Rn] = MEM_READ_BYTE( R0 + sh4r.r[Rm] );
   772                         }
   773                         break;
   774                     case 0xD:
   775                         { /* MOV.W @(R0, Rm), Rn */
   776                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   777                         CHECKRALIGN16( R0 + sh4r.r[Rm] );
   778                                            sh4r.r[Rn] = MEM_READ_WORD( R0 + sh4r.r[Rm] );
   779                         }
   780                         break;
   781                     case 0xE:
   782                         { /* MOV.L @(R0, Rm), Rn */
   783                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   784                         CHECKRALIGN32( R0 + sh4r.r[Rm] );
   785                                            sh4r.r[Rn] = MEM_READ_LONG( R0 + sh4r.r[Rm] );
   786                         }
   787                         break;
   788                     case 0xF:
   789                         { /* MAC.L @Rm+, @Rn+ */
   790                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   791                         CHECKRALIGN32( sh4r.r[Rm] );
   792                         CHECKRALIGN32( sh4r.r[Rn] );
   793                         int64_t tmpl = SIGNEXT32(MEM_READ_LONG(sh4r.r[Rn]));
   794                         sh4r.r[Rn] += 4;
   795                         tmpl = tmpl * SIGNEXT32(MEM_READ_LONG(sh4r.r[Rm])) + sh4r.mac;
   796                         sh4r.r[Rm] += 4;
   797                         if( sh4r.s ) {
   798                             /* 48-bit Saturation. Yuch */
   799                             if( tmpl < (int64_t)0xFFFF800000000000LL )
   800                                 tmpl = 0xFFFF800000000000LL;
   801                             else if( tmpl > (int64_t)0x00007FFFFFFFFFFFLL )
   802                                 tmpl = 0x00007FFFFFFFFFFFLL;
   803                         }
   804                         sh4r.mac = tmpl;
   805                         }
   806                         break;
   807                     default:
   808                         UNDEF();
   809                         break;
   810                 }
   811                 break;
   812             case 0x1:
   813                 { /* MOV.L Rm, @(disp, Rn) */
   814                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
   815                 tmp = sh4r.r[Rn] + disp;
   816                 CHECKWALIGN32( tmp );
   817                 MEM_WRITE_LONG( tmp, sh4r.r[Rm] );
   818                 }
   819                 break;
   820             case 0x2:
   821                 switch( ir&0xF ) {
   822                     case 0x0:
   823                         { /* MOV.B Rm, @Rn */
   824                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   825                         MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] );
   826                         }
   827                         break;
   828                     case 0x1:
   829                         { /* MOV.W Rm, @Rn */
   830                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   831                         CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] );
   832                         }
   833                         break;
   834                     case 0x2:
   835                         { /* MOV.L Rm, @Rn */
   836                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   837                         CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] );
   838                         }
   839                         break;
   840                     case 0x4:
   841                         { /* MOV.B Rm, @-Rn */
   842                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   843                         sh4r.r[Rn] --; MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] );
   844                         }
   845                         break;
   846                     case 0x5:
   847                         { /* MOV.W Rm, @-Rn */
   848                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   849                         sh4r.r[Rn] -= 2; CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] );
   850                         }
   851                         break;
   852                     case 0x6:
   853                         { /* MOV.L Rm, @-Rn */
   854                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   855                         sh4r.r[Rn] -= 4; CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] );
   856                         }
   857                         break;
   858                     case 0x7:
   859                         { /* DIV0S Rm, Rn */
   860                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   861                         sh4r.q = sh4r.r[Rn]>>31;
   862                         sh4r.m = sh4r.r[Rm]>>31;
   863                         sh4r.t = sh4r.q ^ sh4r.m;
   864                         }
   865                         break;
   866                     case 0x8:
   867                         { /* TST Rm, Rn */
   868                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   869                         sh4r.t = (sh4r.r[Rn]&sh4r.r[Rm] ? 0 : 1);
   870                         }
   871                         break;
   872                     case 0x9:
   873                         { /* AND Rm, Rn */
   874                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   875                         sh4r.r[Rn] &= sh4r.r[Rm];
   876                         }
   877                         break;
   878                     case 0xA:
   879                         { /* XOR Rm, Rn */
   880                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   881                         sh4r.r[Rn] ^= sh4r.r[Rm];
   882                         }
   883                         break;
   884                     case 0xB:
   885                         { /* OR Rm, Rn */
   886                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   887                         sh4r.r[Rn] |= sh4r.r[Rm];
   888                         }
   889                         break;
   890                     case 0xC:
   891                         { /* CMP/STR Rm, Rn */
   892                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   893                         /* set T = 1 if any byte in RM & RN is the same */
   894                         tmp = sh4r.r[Rm] ^ sh4r.r[Rn];
   895                         sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
   896                                  (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
   897                         }
   898                         break;
   899                     case 0xD:
   900                         { /* XTRCT Rm, Rn */
   901                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   902                         sh4r.r[Rn] = (sh4r.r[Rn]>>16) | (sh4r.r[Rm]<<16);
   903                         }
   904                         break;
   905                     case 0xE:
   906                         { /* MULU.W Rm, Rn */
   907                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   908                         sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   909                                    (uint32_t)((sh4r.r[Rm]&0xFFFF) * (sh4r.r[Rn]&0xFFFF));
   910                         }
   911                         break;
   912                     case 0xF:
   913                         { /* MULS.W Rm, Rn */
   914                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   915                         sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   916                                    (uint32_t)(SIGNEXT32(sh4r.r[Rm]&0xFFFF) * SIGNEXT32(sh4r.r[Rn]&0xFFFF));
   917                         }
   918                         break;
   919                     default:
   920                         UNDEF();
   921                         break;
   922                 }
   923                 break;
   924             case 0x3:
   925                 switch( ir&0xF ) {
   926                     case 0x0:
   927                         { /* CMP/EQ Rm, Rn */
   928                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   929                         sh4r.t = ( sh4r.r[Rm] == sh4r.r[Rn] ? 1 : 0 );
   930                         }
   931                         break;
   932                     case 0x2:
   933                         { /* CMP/HS Rm, Rn */
   934                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   935                         sh4r.t = ( sh4r.r[Rn] >= sh4r.r[Rm] ? 1 : 0 );
   936                         }
   937                         break;
   938                     case 0x3:
   939                         { /* CMP/GE Rm, Rn */
   940                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   941                         sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= ((int32_t)sh4r.r[Rm]) ? 1 : 0 );
   942                         }
   943                         break;
   944                     case 0x4:
   945                         { /* DIV1 Rm, Rn */
   946                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   947                         /* This is just from the sh4p manual with some
   948                          * simplifications (someone want to check it's correct? :)
   949                          * Why they couldn't just provide a real DIV instruction...
   950                          */
   951                         uint32_t tmp0, tmp1, tmp2, dir;
   953                         dir = sh4r.q ^ sh4r.m;
   954                         sh4r.q = (sh4r.r[Rn] >> 31);
   955                         tmp2 = sh4r.r[Rm];
   956                         sh4r.r[Rn] = (sh4r.r[Rn] << 1) | sh4r.t;
   957                         tmp0 = sh4r.r[Rn];
   958                         if( dir ) {
   959                              sh4r.r[Rn] += tmp2;
   960                              tmp1 = (sh4r.r[Rn]<tmp0 ? 1 : 0 );
   961                         } else {
   962                              sh4r.r[Rn] -= tmp2;
   963                              tmp1 = (sh4r.r[Rn]>tmp0 ? 1 : 0 );
   964                         }
   965                         sh4r.q ^= sh4r.m ^ tmp1;
   966                         sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
   967                         }
   968                         break;
   969                     case 0x5:
   970                         { /* DMULU.L Rm, Rn */
   971                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   972                         sh4r.mac = ((uint64_t)sh4r.r[Rm]) * ((uint64_t)sh4r.r[Rn]);
   973                         }
   974                         break;
   975                     case 0x6:
   976                         { /* CMP/HI Rm, Rn */
   977                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   978                         sh4r.t = ( sh4r.r[Rn] > sh4r.r[Rm] ? 1 : 0 );
   979                         }
   980                         break;
   981                     case 0x7:
   982                         { /* CMP/GT Rm, Rn */
   983                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   984                         sh4r.t = ( ((int32_t)sh4r.r[Rn]) > ((int32_t)sh4r.r[Rm]) ? 1 : 0 );
   985                         }
   986                         break;
   987                     case 0x8:
   988                         { /* SUB Rm, Rn */
   989                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   990                         sh4r.r[Rn] -= sh4r.r[Rm];
   991                         }
   992                         break;
   993                     case 0xA:
   994                         { /* SUBC Rm, Rn */
   995                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   996                         tmp = sh4r.r[Rn];
   997                         sh4r.r[Rn] = sh4r.r[Rn] - sh4r.r[Rm] - sh4r.t;
   998                         sh4r.t = (sh4r.r[Rn] > tmp || (sh4r.r[Rn] == tmp && sh4r.t == 1));
   999                         }
  1000                         break;
  1001                     case 0xB:
  1002                         UNIMP(ir); /* SUBV Rm, Rn */
  1003                         break;
  1004                     case 0xC:
  1005                         { /* ADD Rm, Rn */
  1006                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1007                         sh4r.r[Rn] += sh4r.r[Rm];
  1009                         break;
  1010                     case 0xD:
  1011                         { /* DMULS.L Rm, Rn */
  1012                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1013                         sh4r.mac = SIGNEXT32(sh4r.r[Rm]) * SIGNEXT32(sh4r.r[Rn]);
  1015                         break;
  1016                     case 0xE:
  1017                         { /* ADDC Rm, Rn */
  1018                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1019                         tmp = sh4r.r[Rn];
  1020                         sh4r.r[Rn] += sh4r.r[Rm] + sh4r.t;
  1021                         sh4r.t = ( sh4r.r[Rn] < tmp || (sh4r.r[Rn] == tmp && sh4r.t != 0) ? 1 : 0 );
  1023                         break;
  1024                     case 0xF:
  1025                         { /* ADDV Rm, Rn */
  1026                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1027                         tmp = sh4r.r[Rn] + sh4r.r[Rm];
  1028                         sh4r.t = ( (sh4r.r[Rn]>>31) == (sh4r.r[Rm]>>31) && ((sh4r.r[Rn]>>31) != (tmp>>31)) );
  1029                         sh4r.r[Rn] = tmp;
  1031                         break;
  1032                     default:
  1033                         UNDEF();
  1034                         break;
  1036                 break;
  1037             case 0x4:
  1038                 switch( ir&0xF ) {
  1039                     case 0x0:
  1040                         switch( (ir&0xF0) >> 4 ) {
  1041                             case 0x0:
  1042                                 { /* SHLL Rn */
  1043                                 uint32_t Rn = ((ir>>8)&0xF); 
  1044                                 sh4r.t = sh4r.r[Rn] >> 31; sh4r.r[Rn] <<= 1;
  1046                                 break;
  1047                             case 0x1:
  1048                                 { /* DT Rn */
  1049                                 uint32_t Rn = ((ir>>8)&0xF); 
  1050                                 sh4r.r[Rn] --;
  1051                                 sh4r.t = ( sh4r.r[Rn] == 0 ? 1 : 0 );
  1053                                 break;
  1054                             case 0x2:
  1055                                 { /* SHAL Rn */
  1056                                 uint32_t Rn = ((ir>>8)&0xF); 
  1057                                 sh4r.t = sh4r.r[Rn] >> 31;
  1058                                 sh4r.r[Rn] <<= 1;
  1060                                 break;
  1061                             default:
  1062                                 UNDEF();
  1063                                 break;
  1065                         break;
  1066                     case 0x1:
  1067                         switch( (ir&0xF0) >> 4 ) {
  1068                             case 0x0:
  1069                                 { /* SHLR Rn */
  1070                                 uint32_t Rn = ((ir>>8)&0xF); 
  1071                                 sh4r.t = sh4r.r[Rn] & 0x00000001; sh4r.r[Rn] >>= 1;
  1073                                 break;
  1074                             case 0x1:
  1075                                 { /* CMP/PZ Rn */
  1076                                 uint32_t Rn = ((ir>>8)&0xF); 
  1077                                 sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= 0 ? 1 : 0 );
  1079                                 break;
  1080                             case 0x2:
  1081                                 { /* SHAR Rn */
  1082                                 uint32_t Rn = ((ir>>8)&0xF); 
  1083                                 sh4r.t = sh4r.r[Rn] & 0x00000001;
  1084                                 sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 1;
  1086                                 break;
  1087                             default:
  1088                                 UNDEF();
  1089                                 break;
  1091                         break;
  1092                     case 0x2:
  1093                         switch( (ir&0xF0) >> 4 ) {
  1094                             case 0x0:
  1095                                 { /* STS.L MACH, @-Rn */
  1096                                 uint32_t Rn = ((ir>>8)&0xF); 
  1097                                 sh4r.r[Rn] -= 4;
  1098                                 CHECKWALIGN32( sh4r.r[Rn] );
  1099                                 MEM_WRITE_LONG( sh4r.r[Rn], (sh4r.mac>>32) );
  1101                                 break;
  1102                             case 0x1:
  1103                                 { /* STS.L MACL, @-Rn */
  1104                                 uint32_t Rn = ((ir>>8)&0xF); 
  1105                                 sh4r.r[Rn] -= 4;
  1106                                 CHECKWALIGN32( sh4r.r[Rn] );
  1107                                 MEM_WRITE_LONG( sh4r.r[Rn], (uint32_t)sh4r.mac );
  1109                                 break;
  1110                             case 0x2:
  1111                                 { /* STS.L PR, @-Rn */
  1112                                 uint32_t Rn = ((ir>>8)&0xF); 
  1113                                 sh4r.r[Rn] -= 4;
  1114                                 CHECKWALIGN32( sh4r.r[Rn] );
  1115                                 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.pr );
  1117                                 break;
  1118                             case 0x3:
  1119                                 { /* STC.L SGR, @-Rn */
  1120                                 uint32_t Rn = ((ir>>8)&0xF); 
  1121                                 CHECKPRIV();
  1122                                 sh4r.r[Rn] -= 4;
  1123                                 CHECKWALIGN32( sh4r.r[Rn] );
  1124                                 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.sgr );
  1126                                 break;
  1127                             case 0x5:
  1128                                 { /* STS.L FPUL, @-Rn */
  1129                                 uint32_t Rn = ((ir>>8)&0xF); 
  1130                                 sh4r.r[Rn] -= 4;
  1131                                 CHECKWALIGN32( sh4r.r[Rn] );
  1132                                 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.fpul );
  1134                                 break;
  1135                             case 0x6:
  1136                                 { /* STS.L FPSCR, @-Rn */
  1137                                 uint32_t Rn = ((ir>>8)&0xF); 
  1138                                 sh4r.r[Rn] -= 4;
  1139                                 CHECKWALIGN32( sh4r.r[Rn] );
  1140                                 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.fpscr );
  1142                                 break;
  1143                             case 0xF:
  1144                                 { /* STC.L DBR, @-Rn */
  1145                                 uint32_t Rn = ((ir>>8)&0xF); 
  1146                                 CHECKPRIV();
  1147                                 sh4r.r[Rn] -= 4;
  1148                                 CHECKWALIGN32( sh4r.r[Rn] );
  1149                                 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.dbr );
  1151                                 break;
  1152                             default:
  1153                                 UNDEF();
  1154                                 break;
  1156                         break;
  1157                     case 0x3:
  1158                         switch( (ir&0x80) >> 7 ) {
  1159                             case 0x0:
  1160                                 switch( (ir&0x70) >> 4 ) {
  1161                                     case 0x0:
  1162                                         { /* STC.L SR, @-Rn */
  1163                                         uint32_t Rn = ((ir>>8)&0xF); 
  1164                                         CHECKPRIV();
  1165                                         sh4r.r[Rn] -= 4;
  1166                                         CHECKWALIGN32( sh4r.r[Rn] );
  1167                                         MEM_WRITE_LONG( sh4r.r[Rn], sh4_read_sr() );
  1169                                         break;
  1170                                     case 0x1:
  1171                                         { /* STC.L GBR, @-Rn */
  1172                                         uint32_t Rn = ((ir>>8)&0xF); 
  1173                                         sh4r.r[Rn] -= 4;
  1174                                         CHECKWALIGN32( sh4r.r[Rn] );
  1175                                         MEM_WRITE_LONG( sh4r.r[Rn], sh4r.gbr );
  1177                                         break;
  1178                                     case 0x2:
  1179                                         { /* STC.L VBR, @-Rn */
  1180                                         uint32_t Rn = ((ir>>8)&0xF); 
  1181                                         CHECKPRIV();
  1182                                         sh4r.r[Rn] -= 4;
  1183                                         CHECKWALIGN32( sh4r.r[Rn] );
  1184                                         MEM_WRITE_LONG( sh4r.r[Rn], sh4r.vbr );
  1186                                         break;
  1187                                     case 0x3:
  1188                                         { /* STC.L SSR, @-Rn */
  1189                                         uint32_t Rn = ((ir>>8)&0xF); 
  1190                                         CHECKPRIV();
  1191                                         sh4r.r[Rn] -= 4;
  1192                                         CHECKWALIGN32( sh4r.r[Rn] );
  1193                                         MEM_WRITE_LONG( sh4r.r[Rn], sh4r.ssr );
  1195                                         break;
  1196                                     case 0x4:
  1197                                         { /* STC.L SPC, @-Rn */
  1198                                         uint32_t Rn = ((ir>>8)&0xF); 
  1199                                         CHECKPRIV();
  1200                                         sh4r.r[Rn] -= 4;
  1201                                         CHECKWALIGN32( sh4r.r[Rn] );
  1202                                         MEM_WRITE_LONG( sh4r.r[Rn], sh4r.spc );
  1204                                         break;
  1205                                     default:
  1206                                         UNDEF();
  1207                                         break;
  1209                                 break;
  1210                             case 0x1:
  1211                                 { /* STC.L Rm_BANK, @-Rn */
  1212                                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
  1213                                 CHECKPRIV();
  1214                                 sh4r.r[Rn] -= 4;
  1215                                 CHECKWALIGN32( sh4r.r[Rn] );
  1216                                 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r_bank[Rm_BANK] );
  1218                                 break;
  1220                         break;
  1221                     case 0x4:
  1222                         switch( (ir&0xF0) >> 4 ) {
  1223                             case 0x0:
  1224                                 { /* ROTL Rn */
  1225                                 uint32_t Rn = ((ir>>8)&0xF); 
  1226                                 sh4r.t = sh4r.r[Rn] >> 31;
  1227                                 sh4r.r[Rn] <<= 1;
  1228                                 sh4r.r[Rn] |= sh4r.t;
  1230                                 break;
  1231                             case 0x2:
  1232                                 { /* ROTCL Rn */
  1233                                 uint32_t Rn = ((ir>>8)&0xF); 
  1234                                 tmp = sh4r.r[Rn] >> 31;
  1235                                 sh4r.r[Rn] <<= 1;
  1236                                 sh4r.r[Rn] |= sh4r.t;
  1237                                 sh4r.t = tmp;
  1239                                 break;
  1240                             default:
  1241                                 UNDEF();
  1242                                 break;
  1244                         break;
  1245                     case 0x5:
  1246                         switch( (ir&0xF0) >> 4 ) {
  1247                             case 0x0:
  1248                                 { /* ROTR Rn */
  1249                                 uint32_t Rn = ((ir>>8)&0xF); 
  1250                                 sh4r.t = sh4r.r[Rn] & 0x00000001;
  1251                                 sh4r.r[Rn] >>= 1;
  1252                                 sh4r.r[Rn] |= (sh4r.t << 31);
  1254                                 break;
  1255                             case 0x1:
  1256                                 { /* CMP/PL Rn */
  1257                                 uint32_t Rn = ((ir>>8)&0xF); 
  1258                                 sh4r.t = ( ((int32_t)sh4r.r[Rn]) > 0 ? 1 : 0 );
  1260                                 break;
  1261                             case 0x2:
  1262                                 { /* ROTCR Rn */
  1263                                 uint32_t Rn = ((ir>>8)&0xF); 
  1264                                 tmp = sh4r.r[Rn] & 0x00000001;
  1265                                 sh4r.r[Rn] >>= 1;
  1266                                 sh4r.r[Rn] |= (sh4r.t << 31 );
  1267                                 sh4r.t = tmp;
  1269                                 break;
  1270                             default:
  1271                                 UNDEF();
  1272                                 break;
  1274                         break;
  1275                     case 0x6:
  1276                         switch( (ir&0xF0) >> 4 ) {
  1277                             case 0x0:
  1278                                 { /* LDS.L @Rm+, MACH */
  1279                                 uint32_t Rm = ((ir>>8)&0xF); 
  1280                                 CHECKRALIGN32( sh4r.r[Rm] );
  1281                                 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
  1282                                            (((uint64_t)MEM_READ_LONG(sh4r.r[Rm]))<<32);
  1283                                 sh4r.r[Rm] += 4;
  1285                                 break;
  1286                             case 0x1:
  1287                                 { /* LDS.L @Rm+, MACL */
  1288                                 uint32_t Rm = ((ir>>8)&0xF); 
  1289                                 CHECKRALIGN32( sh4r.r[Rm] );
  1290                                 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
  1291                                            (uint64_t)((uint32_t)MEM_READ_LONG(sh4r.r[Rm]));
  1292                                 sh4r.r[Rm] += 4;
  1294                                 break;
  1295                             case 0x2:
  1296                                 { /* LDS.L @Rm+, PR */
  1297                                 uint32_t Rm = ((ir>>8)&0xF); 
  1298                                 CHECKRALIGN32( sh4r.r[Rm] );
  1299                                 sh4r.pr = MEM_READ_LONG( sh4r.r[Rm] );
  1300                                 sh4r.r[Rm] += 4;
  1302                                 break;
  1303                             case 0x3:
  1304                                 { /* LDC.L @Rm+, SGR */
  1305                                 uint32_t Rm = ((ir>>8)&0xF); 
  1306                                 CHECKPRIV();
  1307                                 CHECKRALIGN32( sh4r.r[Rm] );
  1308                                 sh4r.sgr = MEM_READ_LONG(sh4r.r[Rm]);
  1309                                 sh4r.r[Rm] +=4;
  1311                                 break;
  1312                             case 0x5:
  1313                                 { /* LDS.L @Rm+, FPUL */
  1314                                 uint32_t Rm = ((ir>>8)&0xF); 
  1315                                 CHECKRALIGN32( sh4r.r[Rm] );
  1316                                 sh4r.fpul = MEM_READ_LONG(sh4r.r[Rm]);
  1317                                 sh4r.r[Rm] +=4;
  1319                                 break;
  1320                             case 0x6:
  1321                                 { /* LDS.L @Rm+, FPSCR */
  1322                                 uint32_t Rm = ((ir>>8)&0xF); 
  1323                                 CHECKRALIGN32( sh4r.r[Rm] );
  1324                                 sh4r.fpscr = MEM_READ_LONG(sh4r.r[Rm]);
  1325                                 sh4r.r[Rm] +=4;
  1327                                 break;
  1328                             case 0xF:
  1329                                 { /* LDC.L @Rm+, DBR */
  1330                                 uint32_t Rm = ((ir>>8)&0xF); 
  1331                                 CHECKPRIV();
  1332                                 CHECKRALIGN32( sh4r.r[Rm] );
  1333                                 sh4r.dbr = MEM_READ_LONG(sh4r.r[Rm]);
  1334                                 sh4r.r[Rm] +=4;
  1336                                 break;
  1337                             default:
  1338                                 UNDEF();
  1339                                 break;
  1341                         break;
  1342                     case 0x7:
  1343                         switch( (ir&0x80) >> 7 ) {
  1344                             case 0x0:
  1345                                 switch( (ir&0x70) >> 4 ) {
  1346                                     case 0x0:
  1347                                         { /* LDC.L @Rm+, SR */
  1348                                         uint32_t Rm = ((ir>>8)&0xF); 
  1349                                         CHECKSLOTILLEGAL();
  1350                                         CHECKPRIV();
  1351                                         CHECKWALIGN32( sh4r.r[Rm] );
  1352                                         sh4_load_sr( MEM_READ_LONG(sh4r.r[Rm]) );
  1353                                         sh4r.r[Rm] +=4;
  1355                                         break;
  1356                                     case 0x1:
  1357                                         { /* LDC.L @Rm+, GBR */
  1358                                         uint32_t Rm = ((ir>>8)&0xF); 
  1359                                         CHECKRALIGN32( sh4r.r[Rm] );
  1360                                         sh4r.gbr = MEM_READ_LONG(sh4r.r[Rm]);
  1361                                         sh4r.r[Rm] +=4;
  1363                                         break;
  1364                                     case 0x2:
  1365                                         { /* LDC.L @Rm+, VBR */
  1366                                         uint32_t Rm = ((ir>>8)&0xF); 
  1367                                         CHECKPRIV();
  1368                                         CHECKRALIGN32( sh4r.r[Rm] );
  1369                                         sh4r.vbr = MEM_READ_LONG(sh4r.r[Rm]);
  1370                                         sh4r.r[Rm] +=4;
  1372                                         break;
  1373                                     case 0x3:
  1374                                         { /* LDC.L @Rm+, SSR */
  1375                                         uint32_t Rm = ((ir>>8)&0xF); 
  1376                                         CHECKPRIV();
  1377                                         CHECKRALIGN32( sh4r.r[Rm] );
  1378                                         sh4r.ssr = MEM_READ_LONG(sh4r.r[Rm]);
  1379                                         sh4r.r[Rm] +=4;
  1381                                         break;
  1382                                     case 0x4:
  1383                                         { /* LDC.L @Rm+, SPC */
  1384                                         uint32_t Rm = ((ir>>8)&0xF); 
  1385                                         CHECKPRIV();
  1386                                         CHECKRALIGN32( sh4r.r[Rm] );
  1387                                         sh4r.spc = MEM_READ_LONG(sh4r.r[Rm]);
  1388                                         sh4r.r[Rm] +=4;
  1390                                         break;
  1391                                     default:
  1392                                         UNDEF();
  1393                                         break;
  1395                                 break;
  1396                             case 0x1:
  1397                                 { /* LDC.L @Rm+, Rn_BANK */
  1398                                 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
  1399                                 CHECKPRIV();
  1400                                 CHECKRALIGN32( sh4r.r[Rm] );
  1401                                 sh4r.r_bank[Rn_BANK] = MEM_READ_LONG( sh4r.r[Rm] );
  1402                                 sh4r.r[Rm] += 4;
  1404                                 break;
  1406                         break;
  1407                     case 0x8:
  1408                         switch( (ir&0xF0) >> 4 ) {
  1409                             case 0x0:
  1410                                 { /* SHLL2 Rn */
  1411                                 uint32_t Rn = ((ir>>8)&0xF); 
  1412                                 sh4r.r[Rn] <<= 2;
  1414                                 break;
  1415                             case 0x1:
  1416                                 { /* SHLL8 Rn */
  1417                                 uint32_t Rn = ((ir>>8)&0xF); 
  1418                                 sh4r.r[Rn] <<= 8;
  1420                                 break;
  1421                             case 0x2:
  1422                                 { /* SHLL16 Rn */
  1423                                 uint32_t Rn = ((ir>>8)&0xF); 
  1424                                 sh4r.r[Rn] <<= 16;
  1426                                 break;
  1427                             default:
  1428                                 UNDEF();
  1429                                 break;
  1431                         break;
  1432                     case 0x9:
  1433                         switch( (ir&0xF0) >> 4 ) {
  1434                             case 0x0:
  1435                                 { /* SHLR2 Rn */
  1436                                 uint32_t Rn = ((ir>>8)&0xF); 
  1437                                 sh4r.r[Rn] >>= 2;
  1439                                 break;
  1440                             case 0x1:
  1441                                 { /* SHLR8 Rn */
  1442                                 uint32_t Rn = ((ir>>8)&0xF); 
  1443                                 sh4r.r[Rn] >>= 8;
  1445                                 break;
  1446                             case 0x2:
  1447                                 { /* SHLR16 Rn */
  1448                                 uint32_t Rn = ((ir>>8)&0xF); 
  1449                                 sh4r.r[Rn] >>= 16;
  1451                                 break;
  1452                             default:
  1453                                 UNDEF();
  1454                                 break;
  1456                         break;
  1457                     case 0xA:
  1458                         switch( (ir&0xF0) >> 4 ) {
  1459                             case 0x0:
  1460                                 { /* LDS Rm, MACH */
  1461                                 uint32_t Rm = ((ir>>8)&0xF); 
  1462                                 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
  1463                                            (((uint64_t)sh4r.r[Rm])<<32);
  1465                                 break;
  1466                             case 0x1:
  1467                                 { /* LDS Rm, MACL */
  1468                                 uint32_t Rm = ((ir>>8)&0xF); 
  1469                                 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
  1470                                            (uint64_t)((uint32_t)(sh4r.r[Rm]));
  1472                                 break;
  1473                             case 0x2:
  1474                                 { /* LDS Rm, PR */
  1475                                 uint32_t Rm = ((ir>>8)&0xF); 
  1476                                 sh4r.pr = sh4r.r[Rm];
  1478                                 break;
  1479                             case 0x3:
  1480                                 { /* LDC Rm, SGR */
  1481                                 uint32_t Rm = ((ir>>8)&0xF); 
  1482                                 CHECKPRIV();
  1483                                 sh4r.sgr = sh4r.r[Rm];
  1485                                 break;
  1486                             case 0x5:
  1487                                 { /* LDS Rm, FPUL */
  1488                                 uint32_t Rm = ((ir>>8)&0xF); 
  1489                                 sh4r.fpul = sh4r.r[Rm];
  1491                                 break;
  1492                             case 0x6:
  1493                                 { /* LDS Rm, FPSCR */
  1494                                 uint32_t Rm = ((ir>>8)&0xF); 
  1495                                 sh4r.fpscr = sh4r.r[Rm];
  1497                                 break;
  1498                             case 0xF:
  1499                                 { /* LDC Rm, DBR */
  1500                                 uint32_t Rm = ((ir>>8)&0xF); 
  1501                                 CHECKPRIV();
  1502                                 sh4r.dbr = sh4r.r[Rm];
  1504                                 break;
  1505                             default:
  1506                                 UNDEF();
  1507                                 break;
  1509                         break;
  1510                     case 0xB:
  1511                         switch( (ir&0xF0) >> 4 ) {
  1512                             case 0x0:
  1513                                 { /* JSR @Rn */
  1514                                 uint32_t Rn = ((ir>>8)&0xF); 
  1515                                 CHECKDEST( sh4r.r[Rn] );
  1516                                 CHECKSLOTILLEGAL();
  1517                                 sh4r.in_delay_slot = 1;
  1518                                 sh4r.pc = sh4r.new_pc;
  1519                                 sh4r.new_pc = sh4r.r[Rn];
  1520                                 sh4r.pr = pc + 4;
  1521                                 TRACE_CALL( pc, sh4r.new_pc );
  1522                                 return TRUE;
  1524                                 break;
  1525                             case 0x1:
  1526                                 { /* TAS.B @Rn */
  1527                                 uint32_t Rn = ((ir>>8)&0xF); 
  1528                                 tmp = MEM_READ_BYTE( sh4r.r[Rn] );
  1529                                 sh4r.t = ( tmp == 0 ? 1 : 0 );
  1530                                 MEM_WRITE_BYTE( sh4r.r[Rn], tmp | 0x80 );
  1532                                 break;
  1533                             case 0x2:
  1534                                 { /* JMP @Rn */
  1535                                 uint32_t Rn = ((ir>>8)&0xF); 
  1536                                 CHECKDEST( sh4r.r[Rn] );
  1537                                 CHECKSLOTILLEGAL();
  1538                                 sh4r.in_delay_slot = 1;
  1539                                 sh4r.pc = sh4r.new_pc;
  1540                                 sh4r.new_pc = sh4r.r[Rn];
  1541                                 return TRUE;
  1543                                 break;
  1544                             default:
  1545                                 UNDEF();
  1546                                 break;
  1548                         break;
  1549                     case 0xC:
  1550                         { /* SHAD Rm, Rn */
  1551                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1552                         tmp = sh4r.r[Rm];
  1553                         if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
  1554                         else if( (tmp & 0x1F) == 0 )  
  1555                             sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 31;
  1556                         else 
  1557                     	sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> (((~sh4r.r[Rm]) & 0x1F)+1);
  1559                         break;
  1560                     case 0xD:
  1561                         { /* SHLD Rm, Rn */
  1562                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1563                         tmp = sh4r.r[Rm];
  1564                         if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
  1565                         else if( (tmp & 0x1F) == 0 ) sh4r.r[Rn] = 0;
  1566                         else sh4r.r[Rn] >>= (((~tmp) & 0x1F)+1);
  1568                         break;
  1569                     case 0xE:
  1570                         switch( (ir&0x80) >> 7 ) {
  1571                             case 0x0:
  1572                                 switch( (ir&0x70) >> 4 ) {
  1573                                     case 0x0:
  1574                                         { /* LDC Rm, SR */
  1575                                         uint32_t Rm = ((ir>>8)&0xF); 
  1576                                         CHECKSLOTILLEGAL();
  1577                                         CHECKPRIV();
  1578                                         sh4_load_sr( sh4r.r[Rm] );
  1580                                         break;
  1581                                     case 0x1:
  1582                                         { /* LDC Rm, GBR */
  1583                                         uint32_t Rm = ((ir>>8)&0xF); 
  1584                                         sh4r.gbr = sh4r.r[Rm];
  1586                                         break;
  1587                                     case 0x2:
  1588                                         { /* LDC Rm, VBR */
  1589                                         uint32_t Rm = ((ir>>8)&0xF); 
  1590                                         CHECKPRIV();
  1591                                         sh4r.vbr = sh4r.r[Rm];
  1593                                         break;
  1594                                     case 0x3:
  1595                                         { /* LDC Rm, SSR */
  1596                                         uint32_t Rm = ((ir>>8)&0xF); 
  1597                                         CHECKPRIV();
  1598                                         sh4r.ssr = sh4r.r[Rm];
  1600                                         break;
  1601                                     case 0x4:
  1602                                         { /* LDC Rm, SPC */
  1603                                         uint32_t Rm = ((ir>>8)&0xF); 
  1604                                         CHECKPRIV();
  1605                                         sh4r.spc = sh4r.r[Rm];
  1607                                         break;
  1608                                     default:
  1609                                         UNDEF();
  1610                                         break;
  1612                                 break;
  1613                             case 0x1:
  1614                                 { /* LDC Rm, Rn_BANK */
  1615                                 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
  1616                                 CHECKPRIV();
  1617                                 sh4r.r_bank[Rn_BANK] = sh4r.r[Rm];
  1619                                 break;
  1621                         break;
  1622                     case 0xF:
  1623                         { /* MAC.W @Rm+, @Rn+ */
  1624                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1625                         CHECKRALIGN16( sh4r.r[Rn] );
  1626                         CHECKRALIGN16( sh4r.r[Rm] );
  1627                         int32_t stmp = SIGNEXT16(MEM_READ_WORD(sh4r.r[Rn]));
  1628                         sh4r.r[Rn] += 2;
  1629                         stmp = stmp * SIGNEXT16(MEM_READ_WORD(sh4r.r[Rm]));
  1630                         sh4r.r[Rm] += 2;
  1631                         if( sh4r.s ) {
  1632                     	int64_t tmpl = (int64_t)((int32_t)sh4r.mac) + (int64_t)stmp;
  1633                     	if( tmpl > (int64_t)0x000000007FFFFFFFLL ) {
  1634                     	    sh4r.mac = 0x000000017FFFFFFFLL;
  1635                     	} else if( tmpl < (int64_t)0xFFFFFFFF80000000LL ) {
  1636                     	    sh4r.mac = 0x0000000180000000LL;
  1637                     	} else {
  1638                     	    sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
  1639                     		((uint32_t)(sh4r.mac + stmp));
  1641                         } else {
  1642                     	sh4r.mac += SIGNEXT32(stmp);
  1645                         break;
  1647                 break;
  1648             case 0x5:
  1649                 { /* MOV.L @(disp, Rm), Rn */
  1650                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
  1651                 tmp = sh4r.r[Rm] + disp;
  1652                 CHECKRALIGN32( tmp );
  1653                 sh4r.r[Rn] = MEM_READ_LONG( tmp );
  1655                 break;
  1656             case 0x6:
  1657                 switch( ir&0xF ) {
  1658                     case 0x0:
  1659                         { /* MOV.B @Rm, Rn */
  1660                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1661                         sh4r.r[Rn] = MEM_READ_BYTE( sh4r.r[Rm] );
  1663                         break;
  1664                     case 0x1:
  1665                         { /* MOV.W @Rm, Rn */
  1666                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1667                         CHECKRALIGN16( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_WORD( sh4r.r[Rm] );
  1669                         break;
  1670                     case 0x2:
  1671                         { /* MOV.L @Rm, Rn */
  1672                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1673                         CHECKRALIGN32( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_LONG( sh4r.r[Rm] );
  1675                         break;
  1676                     case 0x3:
  1677                         { /* MOV Rm, Rn */
  1678                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1679                         sh4r.r[Rn] = sh4r.r[Rm];
  1681                         break;
  1682                     case 0x4:
  1683                         { /* MOV.B @Rm+, Rn */
  1684                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1685                         sh4r.r[Rn] = MEM_READ_BYTE( sh4r.r[Rm] ); sh4r.r[Rm] ++;
  1687                         break;
  1688                     case 0x5:
  1689                         { /* MOV.W @Rm+, Rn */
  1690                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1691                         CHECKRALIGN16( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_WORD( sh4r.r[Rm] ); sh4r.r[Rm] += 2;
  1693                         break;
  1694                     case 0x6:
  1695                         { /* MOV.L @Rm+, Rn */
  1696                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1697                         CHECKRALIGN32( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_LONG( sh4r.r[Rm] ); sh4r.r[Rm] += 4;
  1699                         break;
  1700                     case 0x7:
  1701                         { /* NOT Rm, Rn */
  1702                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1703                         sh4r.r[Rn] = ~sh4r.r[Rm];
  1705                         break;
  1706                     case 0x8:
  1707                         { /* SWAP.B Rm, Rn */
  1708                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1709                         sh4r.r[Rn] = (sh4r.r[Rm]&0xFFFF0000) | ((sh4r.r[Rm]&0x0000FF00)>>8) | ((sh4r.r[Rm]&0x000000FF)<<8);
  1711                         break;
  1712                     case 0x9:
  1713                         { /* SWAP.W Rm, Rn */
  1714                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1715                         sh4r.r[Rn] = (sh4r.r[Rm]>>16) | (sh4r.r[Rm]<<16);
  1717                         break;
  1718                     case 0xA:
  1719                         { /* NEGC Rm, Rn */
  1720                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1721                         tmp = 0 - sh4r.r[Rm];
  1722                         sh4r.r[Rn] = tmp - sh4r.t;
  1723                         sh4r.t = ( 0<tmp || tmp<sh4r.r[Rn] ? 1 : 0 );
  1725                         break;
  1726                     case 0xB:
  1727                         { /* NEG Rm, Rn */
  1728                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1729                         sh4r.r[Rn] = 0 - sh4r.r[Rm];
  1731                         break;
  1732                     case 0xC:
  1733                         { /* EXTU.B Rm, Rn */
  1734                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1735                         sh4r.r[Rn] = sh4r.r[Rm]&0x000000FF;
  1737                         break;
  1738                     case 0xD:
  1739                         { /* EXTU.W Rm, Rn */
  1740                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1741                         sh4r.r[Rn] = sh4r.r[Rm]&0x0000FFFF;
  1743                         break;
  1744                     case 0xE:
  1745                         { /* EXTS.B Rm, Rn */
  1746                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1747                         sh4r.r[Rn] = SIGNEXT8( sh4r.r[Rm]&0x000000FF );
  1749                         break;
  1750                     case 0xF:
  1751                         { /* EXTS.W Rm, Rn */
  1752                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1753                         sh4r.r[Rn] = SIGNEXT16( sh4r.r[Rm]&0x0000FFFF );
  1755                         break;
  1757                 break;
  1758             case 0x7:
  1759                 { /* ADD #imm, Rn */
  1760                 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
  1761                 sh4r.r[Rn] += imm;
  1763                 break;
  1764             case 0x8:
  1765                 switch( (ir&0xF00) >> 8 ) {
  1766                     case 0x0:
  1767                         { /* MOV.B R0, @(disp, Rn) */
  1768                         uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
  1769                         MEM_WRITE_BYTE( sh4r.r[Rn] + disp, R0 );
  1771                         break;
  1772                     case 0x1:
  1773                         { /* MOV.W R0, @(disp, Rn) */
  1774                         uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
  1775                         tmp = sh4r.r[Rn] + disp;
  1776                         CHECKWALIGN16( tmp );
  1777                         MEM_WRITE_WORD( tmp, R0 );
  1779                         break;
  1780                     case 0x4:
  1781                         { /* MOV.B @(disp, Rm), R0 */
  1782                         uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
  1783                         R0 = MEM_READ_BYTE( sh4r.r[Rm] + disp );
  1785                         break;
  1786                     case 0x5:
  1787                         { /* MOV.W @(disp, Rm), R0 */
  1788                         uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
  1789                         tmp = sh4r.r[Rm] + disp;
  1790                         CHECKRALIGN16( tmp );
  1791                         R0 = MEM_READ_WORD( tmp );
  1793                         break;
  1794                     case 0x8:
  1795                         { /* CMP/EQ #imm, R0 */
  1796                         int32_t imm = SIGNEXT8(ir&0xFF); 
  1797                         sh4r.t = ( R0 == imm ? 1 : 0 );
  1799                         break;
  1800                     case 0x9:
  1801                         { /* BT disp */
  1802                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  1803                         CHECKSLOTILLEGAL();
  1804                         if( sh4r.t ) {
  1805                             CHECKDEST( sh4r.pc + disp + 4 )
  1806                             sh4r.pc += disp + 4;
  1807                             sh4r.new_pc = sh4r.pc + 2;
  1808                             return TRUE;
  1811                         break;
  1812                     case 0xB:
  1813                         { /* BF disp */
  1814                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  1815                         CHECKSLOTILLEGAL();
  1816                         if( !sh4r.t ) {
  1817                             CHECKDEST( sh4r.pc + disp + 4 )
  1818                             sh4r.pc += disp + 4;
  1819                             sh4r.new_pc = sh4r.pc + 2;
  1820                             return TRUE;
  1823                         break;
  1824                     case 0xD:
  1825                         { /* BT/S disp */
  1826                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  1827                         CHECKSLOTILLEGAL();
  1828                         if( sh4r.t ) {
  1829                             CHECKDEST( sh4r.pc + disp + 4 )
  1830                             sh4r.in_delay_slot = 1;
  1831                             sh4r.pc = sh4r.new_pc;
  1832                             sh4r.new_pc = pc + disp + 4;
  1833                             sh4r.in_delay_slot = 1;
  1834                             return TRUE;
  1837                         break;
  1838                     case 0xF:
  1839                         { /* BF/S disp */
  1840                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  1841                         CHECKSLOTILLEGAL();
  1842                         if( !sh4r.t ) {
  1843                             CHECKDEST( sh4r.pc + disp + 4 )
  1844                             sh4r.in_delay_slot = 1;
  1845                             sh4r.pc = sh4r.new_pc;
  1846                             sh4r.new_pc = pc + disp + 4;
  1847                             return TRUE;
  1850                         break;
  1851                     default:
  1852                         UNDEF();
  1853                         break;
  1855                 break;
  1856             case 0x9:
  1857                 { /* MOV.W @(disp, PC), Rn */
  1858                 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1; 
  1859                 CHECKSLOTILLEGAL();
  1860                 tmp = pc + 4 + disp;
  1861                 sh4r.r[Rn] = MEM_READ_WORD( tmp );
  1863                 break;
  1864             case 0xA:
  1865                 { /* BRA disp */
  1866                 int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
  1867                 CHECKSLOTILLEGAL();
  1868                 CHECKDEST( sh4r.pc + disp + 4 );
  1869                 sh4r.in_delay_slot = 1;
  1870                 sh4r.pc = sh4r.new_pc;
  1871                 sh4r.new_pc = pc + 4 + disp;
  1872                 return TRUE;
  1874                 break;
  1875             case 0xB:
  1876                 { /* BSR disp */
  1877                 int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
  1878                 CHECKDEST( sh4r.pc + disp + 4 );
  1879                 CHECKSLOTILLEGAL();
  1880                 sh4r.in_delay_slot = 1;
  1881                 sh4r.pr = pc + 4;
  1882                 sh4r.pc = sh4r.new_pc;
  1883                 sh4r.new_pc = pc + 4 + disp;
  1884                 TRACE_CALL( pc, sh4r.new_pc );
  1885                 return TRUE;
  1887                 break;
  1888             case 0xC:
  1889                 switch( (ir&0xF00) >> 8 ) {
  1890                     case 0x0:
  1891                         { /* MOV.B R0, @(disp, GBR) */
  1892                         uint32_t disp = (ir&0xFF); 
  1893                         MEM_WRITE_BYTE( sh4r.gbr + disp, R0 );
  1895                         break;
  1896                     case 0x1:
  1897                         { /* MOV.W R0, @(disp, GBR) */
  1898                         uint32_t disp = (ir&0xFF)<<1; 
  1899                         tmp = sh4r.gbr + disp;
  1900                         CHECKWALIGN16( tmp );
  1901                         MEM_WRITE_WORD( tmp, R0 );
  1903                         break;
  1904                     case 0x2:
  1905                         { /* MOV.L R0, @(disp, GBR) */
  1906                         uint32_t disp = (ir&0xFF)<<2; 
  1907                         tmp = sh4r.gbr + disp;
  1908                         CHECKWALIGN32( tmp );
  1909                         MEM_WRITE_LONG( tmp, R0 );
  1911                         break;
  1912                     case 0x3:
  1913                         { /* TRAPA #imm */
  1914                         uint32_t imm = (ir&0xFF); 
  1915                         CHECKSLOTILLEGAL();
  1916                         MMIO_WRITE( MMU, TRA, imm<<2 );
  1917                         sh4r.pc += 2;
  1918                         sh4_raise_exception( EXC_TRAP );
  1920                         break;
  1921                     case 0x4:
  1922                         { /* MOV.B @(disp, GBR), R0 */
  1923                         uint32_t disp = (ir&0xFF); 
  1924                         R0 = MEM_READ_BYTE( sh4r.gbr + disp );
  1926                         break;
  1927                     case 0x5:
  1928                         { /* MOV.W @(disp, GBR), R0 */
  1929                         uint32_t disp = (ir&0xFF)<<1; 
  1930                         tmp = sh4r.gbr + disp;
  1931                         CHECKRALIGN16( tmp );
  1932                         R0 = MEM_READ_WORD( tmp );
  1934                         break;
  1935                     case 0x6:
  1936                         { /* MOV.L @(disp, GBR), R0 */
  1937                         uint32_t disp = (ir&0xFF)<<2; 
  1938                         tmp = sh4r.gbr + disp;
  1939                         CHECKRALIGN32( tmp );
  1940                         R0 = MEM_READ_LONG( tmp );
  1942                         break;
  1943                     case 0x7:
  1944                         { /* MOVA @(disp, PC), R0 */
  1945                         uint32_t disp = (ir&0xFF)<<2; 
  1946                         CHECKSLOTILLEGAL();
  1947                         R0 = (pc&0xFFFFFFFC) + disp + 4;
  1949                         break;
  1950                     case 0x8:
  1951                         { /* TST #imm, R0 */
  1952                         uint32_t imm = (ir&0xFF); 
  1953                         sh4r.t = (R0 & imm ? 0 : 1);
  1955                         break;
  1956                     case 0x9:
  1957                         { /* AND #imm, R0 */
  1958                         uint32_t imm = (ir&0xFF); 
  1959                         R0 &= imm;
  1961                         break;
  1962                     case 0xA:
  1963                         { /* XOR #imm, R0 */
  1964                         uint32_t imm = (ir&0xFF); 
  1965                         R0 ^= imm;
  1967                         break;
  1968                     case 0xB:
  1969                         { /* OR #imm, R0 */
  1970                         uint32_t imm = (ir&0xFF); 
  1971                         R0 |= imm;
  1973                         break;
  1974                     case 0xC:
  1975                         { /* TST.B #imm, @(R0, GBR) */
  1976                         uint32_t imm = (ir&0xFF); 
  1977                         sh4r.t = ( MEM_READ_BYTE(R0 + sh4r.gbr) & imm ? 0 : 1 );
  1979                         break;
  1980                     case 0xD:
  1981                         { /* AND.B #imm, @(R0, GBR) */
  1982                         uint32_t imm = (ir&0xFF); 
  1983                         MEM_WRITE_BYTE( R0 + sh4r.gbr, imm & MEM_READ_BYTE(R0 + sh4r.gbr) );
  1985                         break;
  1986                     case 0xE:
  1987                         { /* XOR.B #imm, @(R0, GBR) */
  1988                         uint32_t imm = (ir&0xFF); 
  1989                         MEM_WRITE_BYTE( R0 + sh4r.gbr, imm ^ MEM_READ_BYTE(R0 + sh4r.gbr) );
  1991                         break;
  1992                     case 0xF:
  1993                         { /* OR.B #imm, @(R0, GBR) */
  1994                         uint32_t imm = (ir&0xFF); 
  1995                         MEM_WRITE_BYTE( R0 + sh4r.gbr, imm | MEM_READ_BYTE(R0 + sh4r.gbr) );
  1997                         break;
  1999                 break;
  2000             case 0xD:
  2001                 { /* MOV.L @(disp, PC), Rn */
  2002                 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<2; 
  2003                 CHECKSLOTILLEGAL();
  2004                 tmp = (pc&0xFFFFFFFC) + disp + 4;
  2005                 sh4r.r[Rn] = MEM_READ_LONG( tmp );
  2007                 break;
  2008             case 0xE:
  2009                 { /* MOV #imm, Rn */
  2010                 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
  2011                 sh4r.r[Rn] = imm;
  2013                 break;
  2014             case 0xF:
  2015                 switch( ir&0xF ) {
  2016                     case 0x0:
  2017                         { /* FADD FRm, FRn */
  2018                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2019                         CHECKFPUEN();
  2020                         if( IS_FPU_DOUBLEPREC() ) {
  2021                     	DR(FRn) += DR(FRm);
  2022                         } else {
  2023                     	FR(FRn) += FR(FRm);
  2026                         break;
  2027                     case 0x1:
  2028                         { /* FSUB FRm, FRn */
  2029                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2030                         CHECKFPUEN();
  2031                         if( IS_FPU_DOUBLEPREC() ) {
  2032                     	DR(FRn) -= DR(FRm);
  2033                         } else {
  2034                     	FR(FRn) -= FR(FRm);
  2037                         break;
  2038                     case 0x2:
  2039                         { /* FMUL FRm, FRn */
  2040                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2041                         CHECKFPUEN();
  2042                         if( IS_FPU_DOUBLEPREC() ) {
  2043                     	DR(FRn) *= DR(FRm);
  2044                         } else {
  2045                     	FR(FRn) *= FR(FRm);
  2048                         break;
  2049                     case 0x3:
  2050                         { /* FDIV FRm, FRn */
  2051                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2052                         CHECKFPUEN();
  2053                         if( IS_FPU_DOUBLEPREC() ) {
  2054                     	DR(FRn) /= DR(FRm);
  2055                         } else {
  2056                     	FR(FRn) /= FR(FRm);
  2059                         break;
  2060                     case 0x4:
  2061                         { /* FCMP/EQ FRm, FRn */
  2062                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2063                         CHECKFPUEN();
  2064                         if( IS_FPU_DOUBLEPREC() ) {
  2065                     	sh4r.t = ( DR(FRn) == DR(FRm) ? 1 : 0 );
  2066                         } else {
  2067                     	sh4r.t = ( FR(FRn) == FR(FRm) ? 1 : 0 );
  2070                         break;
  2071                     case 0x5:
  2072                         { /* FCMP/GT FRm, FRn */
  2073                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2074                         CHECKFPUEN();
  2075                         if( IS_FPU_DOUBLEPREC() ) {
  2076                     	sh4r.t = ( DR(FRn) > DR(FRm) ? 1 : 0 );
  2077                         } else {
  2078                     	sh4r.t = ( FR(FRn) > FR(FRm) ? 1 : 0 );
  2081                         break;
  2082                     case 0x6:
  2083                         { /* FMOV @(R0, Rm), FRn */
  2084                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2085                         MEM_FP_READ( sh4r.r[Rm] + R0, FRn );
  2087                         break;
  2088                     case 0x7:
  2089                         { /* FMOV FRm, @(R0, Rn) */
  2090                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2091                         MEM_FP_WRITE( sh4r.r[Rn] + R0, FRm );
  2093                         break;
  2094                     case 0x8:
  2095                         { /* FMOV @Rm, FRn */
  2096                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2097                         MEM_FP_READ( sh4r.r[Rm], FRn );
  2099                         break;
  2100                     case 0x9:
  2101                         { /* FMOV @Rm+, FRn */
  2102                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2103                         MEM_FP_READ( sh4r.r[Rm], FRn ); sh4r.r[Rm] += FP_WIDTH;
  2105                         break;
  2106                     case 0xA:
  2107                         { /* FMOV FRm, @Rn */
  2108                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2109                         MEM_FP_WRITE( sh4r.r[Rn], FRm );
  2111                         break;
  2112                     case 0xB:
  2113                         { /* FMOV FRm, @-Rn */
  2114                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2115                         sh4r.r[Rn] -= FP_WIDTH; MEM_FP_WRITE( sh4r.r[Rn], FRm );
  2117                         break;
  2118                     case 0xC:
  2119                         { /* FMOV FRm, FRn */
  2120                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2121                         if( IS_FPU_DOUBLESIZE() )
  2122                     	DR(FRn) = DR(FRm);
  2123                         else
  2124                     	FR(FRn) = FR(FRm);
  2126                         break;
  2127                     case 0xD:
  2128                         switch( (ir&0xF0) >> 4 ) {
  2129                             case 0x0:
  2130                                 { /* FSTS FPUL, FRn */
  2131                                 uint32_t FRn = ((ir>>8)&0xF); 
  2132                                 CHECKFPUEN(); FR(FRn) = FPULf;
  2134                                 break;
  2135                             case 0x1:
  2136                                 { /* FLDS FRm, FPUL */
  2137                                 uint32_t FRm = ((ir>>8)&0xF); 
  2138                                 CHECKFPUEN(); FPULf = FR(FRm);
  2140                                 break;
  2141                             case 0x2:
  2142                                 { /* FLOAT FPUL, FRn */
  2143                                 uint32_t FRn = ((ir>>8)&0xF); 
  2144                                 CHECKFPUEN();
  2145                                 if( IS_FPU_DOUBLEPREC() )
  2146                             	DR(FRn) = (float)FPULi;
  2147                                 else
  2148                             	FR(FRn) = (float)FPULi;
  2150                                 break;
  2151                             case 0x3:
  2152                                 { /* FTRC FRm, FPUL */
  2153                                 uint32_t FRm = ((ir>>8)&0xF); 
  2154                                 CHECKFPUEN();
  2155                                 if( IS_FPU_DOUBLEPREC() ) {
  2156                                     dtmp = DR(FRm);
  2157                                     if( dtmp >= MAX_INTF )
  2158                                         FPULi = MAX_INT;
  2159                                     else if( dtmp <= MIN_INTF )
  2160                                         FPULi = MIN_INT;
  2161                                     else 
  2162                                         FPULi = (int32_t)dtmp;
  2163                                 } else {
  2164                             	ftmp = FR(FRm);
  2165                             	if( ftmp >= MAX_INTF )
  2166                             	    FPULi = MAX_INT;
  2167                             	else if( ftmp <= MIN_INTF )
  2168                             	    FPULi = MIN_INT;
  2169                             	else
  2170                             	    FPULi = (int32_t)ftmp;
  2173                                 break;
  2174                             case 0x4:
  2175                                 { /* FNEG FRn */
  2176                                 uint32_t FRn = ((ir>>8)&0xF); 
  2177                                 CHECKFPUEN();
  2178                                 if( IS_FPU_DOUBLEPREC() ) {
  2179                             	DR(FRn) = -DR(FRn);
  2180                                 } else {
  2181                                     FR(FRn) = -FR(FRn);
  2184                                 break;
  2185                             case 0x5:
  2186                                 { /* FABS FRn */
  2187                                 uint32_t FRn = ((ir>>8)&0xF); 
  2188                                 CHECKFPUEN();
  2189                                 if( IS_FPU_DOUBLEPREC() ) {
  2190                             	DR(FRn) = fabs(DR(FRn));
  2191                                 } else {
  2192                                     FR(FRn) = fabsf(FR(FRn));
  2195                                 break;
  2196                             case 0x6:
  2197                                 { /* FSQRT FRn */
  2198                                 uint32_t FRn = ((ir>>8)&0xF); 
  2199                                 CHECKFPUEN();
  2200                                 if( IS_FPU_DOUBLEPREC() ) {
  2201                             	DR(FRn) = sqrt(DR(FRn));
  2202                                 } else {
  2203                                     FR(FRn) = sqrtf(FR(FRn));
  2206                                 break;
  2207                             case 0x7:
  2208                                 { /* FSRRA FRn */
  2209                                 uint32_t FRn = ((ir>>8)&0xF); 
  2210                                 CHECKFPUEN();
  2211                                 if( !IS_FPU_DOUBLEPREC() ) {
  2212                             	FR(FRn) = 1.0/sqrtf(FR(FRn));
  2215                                 break;
  2216                             case 0x8:
  2217                                 { /* FLDI0 FRn */
  2218                                 uint32_t FRn = ((ir>>8)&0xF); 
  2219                                 CHECKFPUEN();
  2220                                 if( IS_FPU_DOUBLEPREC() ) {
  2221                             	DR(FRn) = 0.0;
  2222                                 } else {
  2223                                     FR(FRn) = 0.0;
  2226                                 break;
  2227                             case 0x9:
  2228                                 { /* FLDI1 FRn */
  2229                                 uint32_t FRn = ((ir>>8)&0xF); 
  2230                                 CHECKFPUEN();
  2231                                 if( IS_FPU_DOUBLEPREC() ) {
  2232                             	DR(FRn) = 1.0;
  2233                                 } else {
  2234                                     FR(FRn) = 1.0;
  2237                                 break;
  2238                             case 0xA:
  2239                                 { /* FCNVSD FPUL, FRn */
  2240                                 uint32_t FRn = ((ir>>8)&0xF); 
  2241                                 CHECKFPUEN();
  2242                                 if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
  2243                             	DR(FRn) = (double)FPULf;
  2246                                 break;
  2247                             case 0xB:
  2248                                 { /* FCNVDS FRm, FPUL */
  2249                                 uint32_t FRm = ((ir>>8)&0xF); 
  2250                                 CHECKFPUEN();
  2251                                 if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
  2252                             	FPULf = (float)DR(FRm);
  2255                                 break;
  2256                             case 0xE:
  2257                                 { /* FIPR FVm, FVn */
  2258                                 uint32_t FVn = ((ir>>10)&0x3); uint32_t FVm = ((ir>>8)&0x3); 
  2259                                 CHECKFPUEN();
  2260                                 if( !IS_FPU_DOUBLEPREC() ) {
  2261                                     int tmp2 = FVn<<2;
  2262                                     tmp = FVm<<2;
  2263                                     FR(tmp2+3) = FR(tmp)*FR(tmp2) +
  2264                                         FR(tmp+1)*FR(tmp2+1) +
  2265                                         FR(tmp+2)*FR(tmp2+2) +
  2266                                         FR(tmp+3)*FR(tmp2+3);
  2269                                 break;
  2270                             case 0xF:
  2271                                 switch( (ir&0x100) >> 8 ) {
  2272                                     case 0x0:
  2273                                         { /* FSCA FPUL, FRn */
  2274                                         uint32_t FRn = ((ir>>9)&0x7)<<1; 
  2275                                         CHECKFPUEN();
  2276                                         if( !IS_FPU_DOUBLEPREC() ) {
  2277                                             float angle = (((float)(FPULi&0xFFFF))/65536.0) * 2 * M_PI;
  2278                                             FR(FRn) = sinf(angle);
  2279                                             FR((FRn)+1) = cosf(angle);
  2282                                         break;
  2283                                     case 0x1:
  2284                                         switch( (ir&0x200) >> 9 ) {
  2285                                             case 0x0:
  2286                                                 { /* FTRV XMTRX, FVn */
  2287                                                 uint32_t FVn = ((ir>>10)&0x3); 
  2288                                                 CHECKFPUEN();
  2289                                                 if( !IS_FPU_DOUBLEPREC() ) {
  2290                                                     tmp = FVn<<2;
  2291                                                     float fv[4] = { FR(tmp), FR(tmp+1), FR(tmp+2), FR(tmp+3) };
  2292                                                     FR(tmp) = XF(0) * fv[0] + XF(4)*fv[1] +
  2293                                             	    XF(8)*fv[2] + XF(12)*fv[3];
  2294                                                     FR(tmp+1) = XF(1) * fv[0] + XF(5)*fv[1] +
  2295                                             	    XF(9)*fv[2] + XF(13)*fv[3];
  2296                                                     FR(tmp+2) = XF(2) * fv[0] + XF(6)*fv[1] +
  2297                                             	    XF(10)*fv[2] + XF(14)*fv[3];
  2298                                                     FR(tmp+3) = XF(3) * fv[0] + XF(7)*fv[1] +
  2299                                             	    XF(11)*fv[2] + XF(15)*fv[3];
  2302                                                 break;
  2303                                             case 0x1:
  2304                                                 switch( (ir&0xC00) >> 10 ) {
  2305                                                     case 0x0:
  2306                                                         { /* FSCHG */
  2307                                                         CHECKFPUEN(); sh4r.fpscr ^= FPSCR_SZ;
  2309                                                         break;
  2310                                                     case 0x2:
  2311                                                         { /* FRCHG */
  2312                                                         CHECKFPUEN(); sh4r.fpscr ^= FPSCR_FR;
  2314                                                         break;
  2315                                                     case 0x3:
  2316                                                         { /* UNDEF */
  2317                                                         UNDEF(ir);
  2319                                                         break;
  2320                                                     default:
  2321                                                         UNDEF();
  2322                                                         break;
  2324                                                 break;
  2326                                         break;
  2328                                 break;
  2329                             default:
  2330                                 UNDEF();
  2331                                 break;
  2333                         break;
  2334                     case 0xE:
  2335                         { /* FMAC FR0, FRm, FRn */
  2336                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2337                         CHECKFPUEN();
  2338                         if( IS_FPU_DOUBLEPREC() ) {
  2339                             DR(FRn) += DR(FRm)*DR(0);
  2340                         } else {
  2341                     	FR(FRn) += FR(FRm)*FR(0);
  2344                         break;
  2345                     default:
  2346                         UNDEF();
  2347                         break;
  2349                 break;
  2352     sh4r.pc = sh4r.new_pc;
  2353     sh4r.new_pc += 2;
  2354     sh4r.in_delay_slot = 0;
  2355     return TRUE;
.