filename | src/sh4/sh4core.in |
changeset | 359:c588dce7ebde |
next | 367:9c52dcbad3fb |
author | nkeynes |
date | Thu Aug 23 12:33:27 2007 +0000 (16 years ago) |
permissions | -rw-r--r-- |
last change | Commit decoder generator Translator work in progress Fix mac.l, mac.w in emu core |
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1 /**
2 * $Id: sh4core.in,v 1.1 2007-08-23 12:33:27 nkeynes Exp $
3 *
4 * SH4 emulation core, and parent module for all the SH4 peripheral
5 * modules.
6 *
7 * Copyright (c) 2005 Nathan Keynes.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
20 #define MODULE sh4_module
21 #include <math.h>
22 #include "dream.h"
23 #include "sh4/sh4core.h"
24 #include "sh4/sh4mmio.h"
25 #include "sh4/intc.h"
26 #include "mem.h"
27 #include "clock.h"
28 #include "syscall.h"
30 #define SH4_CALLTRACE 1
32 #define MAX_INT 0x7FFFFFFF
33 #define MIN_INT 0x80000000
34 #define MAX_INTF 2147483647.0
35 #define MIN_INTF -2147483648.0
37 /* CPU-generated exception code/vector pairs */
38 #define EXC_POWER_RESET 0x000 /* vector special */
39 #define EXC_MANUAL_RESET 0x020
40 #define EXC_READ_ADDR_ERR 0x0E0
41 #define EXC_WRITE_ADDR_ERR 0x100
42 #define EXC_SLOT_ILLEGAL 0x1A0
43 #define EXC_ILLEGAL 0x180
44 #define EXC_TRAP 0x160
45 #define EXC_FPDISABLE 0x800
46 #define EXC_SLOT_FPDISABLE 0x820
48 #define EXV_EXCEPTION 0x100 /* General exception vector */
49 #define EXV_TLBMISS 0x400 /* TLB-miss exception vector */
50 #define EXV_INTERRUPT 0x600 /* External interrupt vector */
52 /********************** SH4 Module Definition ****************************/
54 void sh4_init( void );
55 void sh4_reset( void );
56 uint32_t sh4_run_slice( uint32_t );
57 void sh4_start( void );
58 void sh4_stop( void );
59 void sh4_save_state( FILE *f );
60 int sh4_load_state( FILE *f );
61 void sh4_accept_interrupt( void );
63 struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset,
64 NULL, sh4_run_slice, sh4_stop,
65 sh4_save_state, sh4_load_state };
67 struct sh4_registers sh4r;
69 void sh4_init(void)
70 {
71 register_io_regions( mmio_list_sh4mmio );
72 MMU_init();
73 sh4_reset();
74 }
76 void sh4_reset(void)
77 {
78 /* zero everything out, for the sake of having a consistent state. */
79 memset( &sh4r, 0, sizeof(sh4r) );
81 /* Resume running if we were halted */
82 sh4r.sh4_state = SH4_STATE_RUNNING;
84 sh4r.pc = 0xA0000000;
85 sh4r.new_pc= 0xA0000002;
86 sh4r.vbr = 0x00000000;
87 sh4r.fpscr = 0x00040001;
88 sh4r.sr = 0x700000F0;
90 /* Mem reset will do this, but if we want to reset _just_ the SH4... */
91 MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
93 /* Peripheral modules */
94 CPG_reset();
95 INTC_reset();
96 MMU_reset();
97 TMU_reset();
98 SCIF_reset();
99 }
101 static struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
102 static int sh4_breakpoint_count = 0;
103 static uint16_t *sh4_icache = NULL;
104 static uint32_t sh4_icache_addr = 0;
106 void sh4_set_breakpoint( uint32_t pc, int type )
107 {
108 sh4_breakpoints[sh4_breakpoint_count].address = pc;
109 sh4_breakpoints[sh4_breakpoint_count].type = type;
110 sh4_breakpoint_count++;
111 }
113 gboolean sh4_clear_breakpoint( uint32_t pc, int type )
114 {
115 int i;
117 for( i=0; i<sh4_breakpoint_count; i++ ) {
118 if( sh4_breakpoints[i].address == pc &&
119 sh4_breakpoints[i].type == type ) {
120 while( ++i < sh4_breakpoint_count ) {
121 sh4_breakpoints[i-1].address = sh4_breakpoints[i].address;
122 sh4_breakpoints[i-1].type = sh4_breakpoints[i].type;
123 }
124 sh4_breakpoint_count--;
125 return TRUE;
126 }
127 }
128 return FALSE;
129 }
131 int sh4_get_breakpoint( uint32_t pc )
132 {
133 int i;
134 for( i=0; i<sh4_breakpoint_count; i++ ) {
135 if( sh4_breakpoints[i].address == pc )
136 return sh4_breakpoints[i].type;
137 }
138 return 0;
139 }
141 uint32_t sh4_run_slice( uint32_t nanosecs )
142 {
143 int i;
144 sh4r.slice_cycle = 0;
146 if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
147 if( sh4r.event_pending < nanosecs ) {
148 sh4r.sh4_state = SH4_STATE_RUNNING;
149 sh4r.slice_cycle = sh4r.event_pending;
150 }
151 }
153 if( sh4_breakpoint_count == 0 ) {
154 for( ; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
155 if( SH4_EVENT_PENDING() ) {
156 if( sh4r.event_types & PENDING_EVENT ) {
157 event_execute();
158 }
159 /* Eventq execute may (quite likely) deliver an immediate IRQ */
160 if( sh4r.event_types & PENDING_IRQ ) {
161 sh4_accept_interrupt();
162 }
163 }
164 if( !sh4_execute_instruction() ) {
165 break;
166 }
167 }
168 } else {
169 for( ;sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
170 if( SH4_EVENT_PENDING() ) {
171 if( sh4r.event_types & PENDING_EVENT ) {
172 event_execute();
173 }
174 /* Eventq execute may (quite likely) deliver an immediate IRQ */
175 if( sh4r.event_types & PENDING_IRQ ) {
176 sh4_accept_interrupt();
177 }
178 }
180 if( !sh4_execute_instruction() )
181 break;
182 #ifdef ENABLE_DEBUG_MODE
183 for( i=0; i<sh4_breakpoint_count; i++ ) {
184 if( sh4_breakpoints[i].address == sh4r.pc ) {
185 break;
186 }
187 }
188 if( i != sh4_breakpoint_count ) {
189 dreamcast_stop();
190 if( sh4_breakpoints[i].type == BREAK_ONESHOT )
191 sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );
192 break;
193 }
194 #endif
195 }
196 }
198 /* If we aborted early, but the cpu is still technically running,
199 * we're doing a hard abort - cut the timeslice back to what we
200 * actually executed
201 */
202 if( sh4r.slice_cycle != nanosecs && sh4r.sh4_state == SH4_STATE_RUNNING ) {
203 nanosecs = sh4r.slice_cycle;
204 }
205 if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
206 TMU_run_slice( nanosecs );
207 SCIF_run_slice( nanosecs );
208 }
209 return nanosecs;
210 }
212 void sh4_stop(void)
213 {
215 }
217 void sh4_save_state( FILE *f )
218 {
219 fwrite( &sh4r, sizeof(sh4r), 1, f );
220 MMU_save_state( f );
221 INTC_save_state( f );
222 TMU_save_state( f );
223 SCIF_save_state( f );
224 }
226 int sh4_load_state( FILE * f )
227 {
228 fread( &sh4r, sizeof(sh4r), 1, f );
229 MMU_load_state( f );
230 INTC_load_state( f );
231 TMU_load_state( f );
232 return SCIF_load_state( f );
233 }
235 /********************** SH4 emulation core ****************************/
237 void sh4_set_pc( int pc )
238 {
239 sh4r.pc = pc;
240 sh4r.new_pc = pc+2;
241 }
243 #define UNDEF(ir) return sh4_raise_slot_exception(EXC_ILLEGAL, EXC_SLOT_ILLEGAL)
244 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)
246 #if(SH4_CALLTRACE == 1)
247 #define MAX_CALLSTACK 32
248 static struct call_stack {
249 sh4addr_t call_addr;
250 sh4addr_t target_addr;
251 sh4addr_t stack_pointer;
252 } call_stack[MAX_CALLSTACK];
254 static int call_stack_depth = 0;
255 int sh4_call_trace_on = 0;
257 static inline trace_call( sh4addr_t source, sh4addr_t dest )
258 {
259 if( call_stack_depth < MAX_CALLSTACK ) {
260 call_stack[call_stack_depth].call_addr = source;
261 call_stack[call_stack_depth].target_addr = dest;
262 call_stack[call_stack_depth].stack_pointer = sh4r.r[15];
263 }
264 call_stack_depth++;
265 }
267 static inline trace_return( sh4addr_t source, sh4addr_t dest )
268 {
269 if( call_stack_depth > 0 ) {
270 call_stack_depth--;
271 }
272 }
274 void fprint_stack_trace( FILE *f )
275 {
276 int i = call_stack_depth -1;
277 if( i >= MAX_CALLSTACK )
278 i = MAX_CALLSTACK - 1;
279 for( ; i >= 0; i-- ) {
280 fprintf( f, "%d. Call from %08X => %08X, SP=%08X\n",
281 (call_stack_depth - i), call_stack[i].call_addr,
282 call_stack[i].target_addr, call_stack[i].stack_pointer );
283 }
284 }
286 #define TRACE_CALL( source, dest ) trace_call(source, dest)
287 #define TRACE_RETURN( source, dest ) trace_return(source, dest)
288 #else
289 #define TRACE_CALL( dest, rts )
290 #define TRACE_RETURN( source, dest )
291 #endif
293 #define RAISE( x, v ) do{ \
294 if( sh4r.vbr == 0 ) { \
295 ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
296 dreamcast_stop(); return FALSE; \
297 } else { \
298 sh4r.spc = sh4r.pc; \
299 sh4r.ssr = sh4_read_sr(); \
300 sh4r.sgr = sh4r.r[15]; \
301 MMIO_WRITE(MMU,EXPEVT,x); \
302 sh4r.pc = sh4r.vbr + v; \
303 sh4r.new_pc = sh4r.pc + 2; \
304 sh4_load_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
305 if( sh4r.in_delay_slot ) { \
306 sh4r.in_delay_slot = 0; \
307 sh4r.spc -= 2; \
308 } \
309 } \
310 return TRUE; } while(0)
312 #define MEM_READ_BYTE( addr ) sh4_read_byte(addr)
313 #define MEM_READ_WORD( addr ) sh4_read_word(addr)
314 #define MEM_READ_LONG( addr ) sh4_read_long(addr)
315 #define MEM_WRITE_BYTE( addr, val ) sh4_write_byte(addr, val)
316 #define MEM_WRITE_WORD( addr, val ) sh4_write_word(addr, val)
317 #define MEM_WRITE_LONG( addr, val ) sh4_write_long(addr, val)
319 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
321 #define MEM_FP_READ( addr, reg ) sh4_read_float( addr, reg );
322 #define MEM_FP_WRITE( addr, reg ) sh4_write_float( addr, reg );
324 #define CHECKPRIV() if( !IS_SH4_PRIVMODE() ) return sh4_raise_slot_exception( EXC_ILLEGAL, EXC_SLOT_ILLEGAL )
325 #define CHECKRALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_READ_ADDR_ERR )
326 #define CHECKRALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_READ_ADDR_ERR )
327 #define CHECKWALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_WRITE_ADDR_ERR )
328 #define CHECKWALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_WRITE_ADDR_ERR )
330 #define CHECKFPUEN() if( !IS_FPU_ENABLED() ) { if( ir == 0xFFFD ) { UNDEF(ir); } else { return sh4_raise_slot_exception( EXC_FPDISABLE, EXC_SLOT_FPDISABLE ); } }
331 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); dreamcast_stop(); return FALSE; }
332 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) return sh4_raise_exception(EXC_SLOT_ILLEGAL)
334 static void sh4_switch_banks( )
335 {
336 uint32_t tmp[8];
338 memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
339 memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
340 memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
341 }
343 static void sh4_load_sr( uint32_t newval )
344 {
345 if( (newval ^ sh4r.sr) & SR_RB )
346 sh4_switch_banks();
347 sh4r.sr = newval;
348 sh4r.t = (newval&SR_T) ? 1 : 0;
349 sh4r.s = (newval&SR_S) ? 1 : 0;
350 sh4r.m = (newval&SR_M) ? 1 : 0;
351 sh4r.q = (newval&SR_Q) ? 1 : 0;
352 intc_mask_changed();
353 }
355 static void sh4_write_float( uint32_t addr, int reg )
356 {
357 if( IS_FPU_DOUBLESIZE() ) {
358 if( reg & 1 ) {
359 sh4_write_long( addr, *((uint32_t *)&XF((reg)&0x0E)) );
360 sh4_write_long( addr+4, *((uint32_t *)&XF(reg)) );
361 } else {
362 sh4_write_long( addr, *((uint32_t *)&FR(reg)) );
363 sh4_write_long( addr+4, *((uint32_t *)&FR((reg)|0x01)) );
364 }
365 } else {
366 sh4_write_long( addr, *((uint32_t *)&FR((reg))) );
367 }
368 }
370 static void sh4_read_float( uint32_t addr, int reg )
371 {
372 if( IS_FPU_DOUBLESIZE() ) {
373 if( reg & 1 ) {
374 *((uint32_t *)&XF((reg) & 0x0E)) = sh4_read_long(addr);
375 *((uint32_t *)&XF(reg)) = sh4_read_long(addr+4);
376 } else {
377 *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
378 *((uint32_t *)&FR((reg) | 0x01)) = sh4_read_long(addr+4);
379 }
380 } else {
381 *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
382 }
383 }
385 static uint32_t sh4_read_sr( void )
386 {
387 /* synchronize sh4r.sr with the various bitflags */
388 sh4r.sr &= SR_MQSTMASK;
389 if( sh4r.t ) sh4r.sr |= SR_T;
390 if( sh4r.s ) sh4r.sr |= SR_S;
391 if( sh4r.m ) sh4r.sr |= SR_M;
392 if( sh4r.q ) sh4r.sr |= SR_Q;
393 return sh4r.sr;
394 }
396 /**
397 * Raise a general CPU exception for the specified exception code.
398 * (NOT for TRAPA or TLB exceptions)
399 */
400 gboolean sh4_raise_exception( int code )
401 {
402 RAISE( code, EXV_EXCEPTION );
403 }
405 gboolean sh4_raise_slot_exception( int normal_code, int slot_code ) {
406 if( sh4r.in_delay_slot ) {
407 return sh4_raise_exception(slot_code);
408 } else {
409 return sh4_raise_exception(normal_code);
410 }
411 }
413 gboolean sh4_raise_tlb_exception( int code )
414 {
415 RAISE( code, EXV_TLBMISS );
416 }
418 void sh4_accept_interrupt( void )
419 {
420 uint32_t code = intc_accept_interrupt();
421 sh4r.ssr = sh4_read_sr();
422 sh4r.spc = sh4r.pc;
423 sh4r.sgr = sh4r.r[15];
424 sh4_load_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
425 MMIO_WRITE( MMU, INTEVT, code );
426 sh4r.pc = sh4r.vbr + 0x600;
427 sh4r.new_pc = sh4r.pc + 2;
428 // WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
429 }
431 gboolean sh4_execute_instruction( void )
432 {
433 uint32_t pc;
434 unsigned short ir;
435 uint32_t tmp;
436 float ftmp;
437 double dtmp;
439 #define R0 sh4r.r[0]
440 pc = sh4r.pc;
441 if( pc > 0xFFFFFF00 ) {
442 /* SYSCALL Magic */
443 syscall_invoke( pc );
444 sh4r.in_delay_slot = 0;
445 pc = sh4r.pc = sh4r.pr;
446 sh4r.new_pc = sh4r.pc + 2;
447 }
448 CHECKRALIGN16(pc);
450 /* Read instruction */
451 uint32_t pageaddr = pc >> 12;
452 if( sh4_icache != NULL && pageaddr == sh4_icache_addr ) {
453 ir = sh4_icache[(pc&0xFFF)>>1];
454 } else {
455 sh4_icache = (uint16_t *)mem_get_page(pc);
456 if( ((uint32_t)sh4_icache) < MAX_IO_REGIONS ) {
457 /* If someone's actually been so daft as to try to execute out of an IO
458 * region, fallback on the full-blown memory read
459 */
460 sh4_icache = NULL;
461 ir = MEM_READ_WORD(pc);
462 } else {
463 sh4_icache_addr = pageaddr;
464 ir = sh4_icache[(pc&0xFFF)>>1];
465 }
466 }
467 %%
468 AND Rm, Rn {: sh4r.r[Rn] &= sh4r.r[Rm]; :}
469 AND #imm, R0 {: R0 &= imm; :}
470 AND.B #imm, @(R0, GBR) {: MEM_WRITE_BYTE( R0 + sh4r.gbr, imm & MEM_READ_BYTE(R0 + sh4r.gbr) ); :}
471 NOT Rm, Rn {: sh4r.r[Rn] = ~sh4r.r[Rm]; :}
472 OR Rm, Rn {: sh4r.r[Rn] |= sh4r.r[Rm]; :}
473 OR #imm, R0 {: R0 |= imm; :}
474 OR.B #imm, @(R0, GBR) {: MEM_WRITE_BYTE( R0 + sh4r.gbr, imm | MEM_READ_BYTE(R0 + sh4r.gbr) ); :}
475 TAS.B @Rn {:
476 tmp = MEM_READ_BYTE( sh4r.r[Rn] );
477 sh4r.t = ( tmp == 0 ? 1 : 0 );
478 MEM_WRITE_BYTE( sh4r.r[Rn], tmp | 0x80 );
479 :}
480 TST Rm, Rn {: sh4r.t = (sh4r.r[Rn]&sh4r.r[Rm] ? 0 : 1); :}
481 TST #imm, R0 {: sh4r.t = (R0 & imm ? 0 : 1); :}
482 TST.B #imm, @(R0, GBR) {: sh4r.t = ( MEM_READ_BYTE(R0 + sh4r.gbr) & imm ? 0 : 1 ); :}
483 XOR Rm, Rn {: sh4r.r[Rn] ^= sh4r.r[Rm]; :}
484 XOR #imm, R0 {: R0 ^= imm; :}
485 XOR.B #imm, @(R0, GBR) {: MEM_WRITE_BYTE( R0 + sh4r.gbr, imm ^ MEM_READ_BYTE(R0 + sh4r.gbr) ); :}
486 XTRCT Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rn]>>16) | (sh4r.r[Rm]<<16); :}
488 ROTL Rn {:
489 sh4r.t = sh4r.r[Rn] >> 31;
490 sh4r.r[Rn] <<= 1;
491 sh4r.r[Rn] |= sh4r.t;
492 :}
493 ROTR Rn {:
494 sh4r.t = sh4r.r[Rn] & 0x00000001;
495 sh4r.r[Rn] >>= 1;
496 sh4r.r[Rn] |= (sh4r.t << 31);
497 :}
498 ROTCL Rn {:
499 tmp = sh4r.r[Rn] >> 31;
500 sh4r.r[Rn] <<= 1;
501 sh4r.r[Rn] |= sh4r.t;
502 sh4r.t = tmp;
503 :}
504 ROTCR Rn {:
505 tmp = sh4r.r[Rn] & 0x00000001;
506 sh4r.r[Rn] >>= 1;
507 sh4r.r[Rn] |= (sh4r.t << 31 );
508 sh4r.t = tmp;
509 :}
510 SHAD Rm, Rn {:
511 tmp = sh4r.r[Rm];
512 if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
513 else if( (tmp & 0x1F) == 0 )
514 sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 31;
515 else
516 sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> (((~sh4r.r[Rm]) & 0x1F)+1);
517 :}
518 SHLD Rm, Rn {:
519 tmp = sh4r.r[Rm];
520 if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
521 else if( (tmp & 0x1F) == 0 ) sh4r.r[Rn] = 0;
522 else sh4r.r[Rn] >>= (((~tmp) & 0x1F)+1);
523 :}
524 SHAL Rn {:
525 sh4r.t = sh4r.r[Rn] >> 31;
526 sh4r.r[Rn] <<= 1;
527 :}
528 SHAR Rn {:
529 sh4r.t = sh4r.r[Rn] & 0x00000001;
530 sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 1;
531 :}
532 SHLL Rn {: sh4r.t = sh4r.r[Rn] >> 31; sh4r.r[Rn] <<= 1; :}
533 SHLR Rn {: sh4r.t = sh4r.r[Rn] & 0x00000001; sh4r.r[Rn] >>= 1; :}
534 SHLL2 Rn {: sh4r.r[Rn] <<= 2; :}
535 SHLR2 Rn {: sh4r.r[Rn] >>= 2; :}
536 SHLL8 Rn {: sh4r.r[Rn] <<= 8; :}
537 SHLR8 Rn {: sh4r.r[Rn] >>= 8; :}
538 SHLL16 Rn {: sh4r.r[Rn] <<= 16; :}
539 SHLR16 Rn {: sh4r.r[Rn] >>= 16; :}
541 EXTU.B Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]&0x000000FF; :}
542 EXTU.W Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]&0x0000FFFF; :}
543 EXTS.B Rm, Rn {: sh4r.r[Rn] = SIGNEXT8( sh4r.r[Rm]&0x000000FF ); :}
544 EXTS.W Rm, Rn {: sh4r.r[Rn] = SIGNEXT16( sh4r.r[Rm]&0x0000FFFF ); :}
545 SWAP.B Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rm]&0xFFFF0000) | ((sh4r.r[Rm]&0x0000FF00)>>8) | ((sh4r.r[Rm]&0x000000FF)<<8); :}
546 SWAP.W Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rm]>>16) | (sh4r.r[Rm]<<16); :}
548 CLRT {: sh4r.t = 0; :}
549 SETT {: sh4r.t = 1; :}
550 CLRMAC {: sh4r.mac = 0; :}
551 LDTLB {: /* TODO */ :}
552 CLRS {: sh4r.s = 0; :}
553 SETS {: sh4r.s = 1; :}
554 MOVT Rn {: sh4r.r[Rn] = sh4r.t; :}
555 NOP {: /* NOP */ :}
557 PREF @Rn {:
558 tmp = sh4r.r[Rn];
559 if( (tmp & 0xFC000000) == 0xE0000000 ) {
560 /* Store queue operation */
561 int queue = (tmp&0x20)>>2;
562 int32_t *src = &sh4r.store_queue[queue];
563 uint32_t hi = (MMIO_READ( MMU, (queue == 0 ? QACR0 : QACR1) ) & 0x1C) << 24;
564 uint32_t target = tmp&0x03FFFFE0 | hi;
565 mem_copy_to_sh4( target, src, 32 );
566 }
567 :}
568 OCBI @Rn {: :}
569 OCBP @Rn {: :}
570 OCBWB @Rn {: :}
571 MOVCA.L R0, @Rn {:
572 tmp = sh4r.r[Rn];
573 CHECKWALIGN32(tmp);
574 MEM_WRITE_LONG( tmp, R0 );
575 :}
576 MOV.B Rm, @(R0, Rn) {: MEM_WRITE_BYTE( R0 + sh4r.r[Rn], sh4r.r[Rm] ); :}
577 MOV.W Rm, @(R0, Rn) {:
578 CHECKWALIGN16( R0 + sh4r.r[Rn] );
579 MEM_WRITE_WORD( R0 + sh4r.r[Rn], sh4r.r[Rm] );
580 :}
581 MOV.L Rm, @(R0, Rn) {:
582 CHECKWALIGN32( R0 + sh4r.r[Rn] );
583 MEM_WRITE_LONG( R0 + sh4r.r[Rn], sh4r.r[Rm] );
584 :}
585 MOV.B @(R0, Rm), Rn {: sh4r.r[Rn] = MEM_READ_BYTE( R0 + sh4r.r[Rm] ); :}
586 MOV.W @(R0, Rm), Rn {: CHECKRALIGN16( R0 + sh4r.r[Rm] );
587 sh4r.r[Rn] = MEM_READ_WORD( R0 + sh4r.r[Rm] );
588 :}
589 MOV.L @(R0, Rm), Rn {: CHECKRALIGN32( R0 + sh4r.r[Rm] );
590 sh4r.r[Rn] = MEM_READ_LONG( R0 + sh4r.r[Rm] );
591 :}
592 MOV.L Rm, @(disp, Rn) {:
593 tmp = sh4r.r[Rn] + disp;
594 CHECKWALIGN32( tmp );
595 MEM_WRITE_LONG( tmp, sh4r.r[Rm] );
596 :}
597 MOV.B Rm, @Rn {: MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] ); :}
598 MOV.W Rm, @Rn {: CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] ); :}
599 MOV.L Rm, @Rn {: CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] ); :}
600 MOV.B Rm, @-Rn {: sh4r.r[Rn] --; MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] ); :}
601 MOV.W Rm, @-Rn {: sh4r.r[Rn] -= 2; CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] ); :}
602 MOV.L Rm, @-Rn {: sh4r.r[Rn] -= 4; CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] ); :}
603 MOV.L @(disp, Rm), Rn {:
604 tmp = sh4r.r[Rm] + disp;
605 CHECKRALIGN32( tmp );
606 sh4r.r[Rn] = MEM_READ_LONG( tmp );
607 :}
608 MOV.B @Rm, Rn {: sh4r.r[Rn] = MEM_READ_BYTE( sh4r.r[Rm] ); :}
609 MOV.W @Rm, Rn {: CHECKRALIGN16( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_WORD( sh4r.r[Rm] ); :}
610 MOV.L @Rm, Rn {: CHECKRALIGN32( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_LONG( sh4r.r[Rm] ); :}
611 MOV Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]; :}
612 MOV.B @Rm+, Rn {: sh4r.r[Rn] = MEM_READ_BYTE( sh4r.r[Rm] ); sh4r.r[Rm] ++; :}
613 MOV.W @Rm+, Rn {: CHECKRALIGN16( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_WORD( sh4r.r[Rm] ); sh4r.r[Rm] += 2; :}
614 MOV.L @Rm+, Rn {: CHECKRALIGN32( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_LONG( sh4r.r[Rm] ); sh4r.r[Rm] += 4; :}
615 MOV.L @(disp, PC), Rn {:
616 CHECKSLOTILLEGAL();
617 tmp = (pc&0xFFFFFFFC) + disp + 4;
618 sh4r.r[Rn] = MEM_READ_LONG( tmp );
619 :}
620 MOV.B R0, @(disp, GBR) {: MEM_WRITE_BYTE( sh4r.gbr + disp, R0 ); :}
621 MOV.W R0, @(disp, GBR) {:
622 tmp = sh4r.gbr + disp;
623 CHECKWALIGN16( tmp );
624 MEM_WRITE_WORD( tmp, R0 );
625 :}
626 MOV.L R0, @(disp, GBR) {:
627 tmp = sh4r.gbr + disp;
628 CHECKWALIGN32( tmp );
629 MEM_WRITE_LONG( tmp, R0 );
630 :}
631 MOV.B @(disp, GBR), R0 {: R0 = MEM_READ_BYTE( sh4r.gbr + disp ); :}
632 MOV.W @(disp, GBR), R0 {:
633 tmp = sh4r.gbr + disp;
634 CHECKRALIGN16( tmp );
635 R0 = MEM_READ_WORD( tmp );
636 :}
637 MOV.L @(disp, GBR), R0 {:
638 tmp = sh4r.gbr + disp;
639 CHECKRALIGN32( tmp );
640 R0 = MEM_READ_LONG( tmp );
641 :}
642 MOV.B R0, @(disp, Rn) {: MEM_WRITE_BYTE( sh4r.r[Rn] + disp, R0 ); :}
643 MOV.W R0, @(disp, Rn) {:
644 tmp = sh4r.r[Rn] + disp;
645 CHECKWALIGN16( tmp );
646 MEM_WRITE_WORD( tmp, R0 );
647 :}
648 MOV.B @(disp, Rm), R0 {: R0 = MEM_READ_BYTE( sh4r.r[Rm] + disp ); :}
649 MOV.W @(disp, Rm), R0 {:
650 tmp = sh4r.r[Rm] + disp;
651 CHECKRALIGN16( tmp );
652 R0 = MEM_READ_WORD( tmp );
653 :}
654 MOV.W @(disp, PC), Rn {:
655 CHECKSLOTILLEGAL();
656 tmp = pc + 4 + disp;
657 sh4r.r[Rn] = MEM_READ_WORD( tmp );
658 :}
659 MOVA @(disp, PC), R0 {:
660 CHECKSLOTILLEGAL();
661 R0 = (pc&0xFFFFFFFC) + disp + 4;
662 :}
663 MOV #imm, Rn {: sh4r.r[Rn] = imm; :}
665 CMP/EQ #imm, R0 {: sh4r.t = ( R0 == imm ? 1 : 0 ); :}
666 CMP/EQ Rm, Rn {: sh4r.t = ( sh4r.r[Rm] == sh4r.r[Rn] ? 1 : 0 ); :}
667 CMP/GE Rm, Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= ((int32_t)sh4r.r[Rm]) ? 1 : 0 ); :}
668 CMP/GT Rm, Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) > ((int32_t)sh4r.r[Rm]) ? 1 : 0 ); :}
669 CMP/HI Rm, Rn {: sh4r.t = ( sh4r.r[Rn] > sh4r.r[Rm] ? 1 : 0 ); :}
670 CMP/HS Rm, Rn {: sh4r.t = ( sh4r.r[Rn] >= sh4r.r[Rm] ? 1 : 0 ); :}
671 CMP/PL Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) > 0 ? 1 : 0 ); :}
672 CMP/PZ Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= 0 ? 1 : 0 ); :}
673 CMP/STR Rm, Rn {:
674 /* set T = 1 if any byte in RM & RN is the same */
675 tmp = sh4r.r[Rm] ^ sh4r.r[Rn];
676 sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
677 (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
678 :}
680 ADD Rm, Rn {: sh4r.r[Rn] += sh4r.r[Rm]; :}
681 ADD #imm, Rn {: sh4r.r[Rn] += imm; :}
682 ADDC Rm, Rn {:
683 tmp = sh4r.r[Rn];
684 sh4r.r[Rn] += sh4r.r[Rm] + sh4r.t;
685 sh4r.t = ( sh4r.r[Rn] < tmp || (sh4r.r[Rn] == tmp && sh4r.t != 0) ? 1 : 0 );
686 :}
687 ADDV Rm, Rn {:
688 tmp = sh4r.r[Rn] + sh4r.r[Rm];
689 sh4r.t = ( (sh4r.r[Rn]>>31) == (sh4r.r[Rm]>>31) && ((sh4r.r[Rn]>>31) != (tmp>>31)) );
690 sh4r.r[Rn] = tmp;
691 :}
692 DIV0U {: sh4r.m = sh4r.q = sh4r.t = 0; :}
693 DIV0S Rm, Rn {:
694 sh4r.q = sh4r.r[Rn]>>31;
695 sh4r.m = sh4r.r[Rm]>>31;
696 sh4r.t = sh4r.q ^ sh4r.m;
697 :}
698 DIV1 Rm, Rn {:
699 /* This is just from the sh4p manual with some
700 * simplifications (someone want to check it's correct? :)
701 * Why they couldn't just provide a real DIV instruction...
702 */
703 uint32_t tmp0, tmp1, tmp2, dir;
705 dir = sh4r.q ^ sh4r.m;
706 sh4r.q = (sh4r.r[Rn] >> 31);
707 tmp2 = sh4r.r[Rm];
708 sh4r.r[Rn] = (sh4r.r[Rn] << 1) | sh4r.t;
709 tmp0 = sh4r.r[Rn];
710 if( dir ) {
711 sh4r.r[Rn] += tmp2;
712 tmp1 = (sh4r.r[Rn]<tmp0 ? 1 : 0 );
713 } else {
714 sh4r.r[Rn] -= tmp2;
715 tmp1 = (sh4r.r[Rn]>tmp0 ? 1 : 0 );
716 }
717 sh4r.q ^= sh4r.m ^ tmp1;
718 sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
719 :}
720 DMULS.L Rm, Rn {: sh4r.mac = SIGNEXT32(sh4r.r[Rm]) * SIGNEXT32(sh4r.r[Rn]); :}
721 DMULU.L Rm, Rn {: sh4r.mac = ((uint64_t)sh4r.r[Rm]) * ((uint64_t)sh4r.r[Rn]); :}
722 DT Rn {:
723 sh4r.r[Rn] --;
724 sh4r.t = ( sh4r.r[Rn] == 0 ? 1 : 0 );
725 :}
726 MAC.W @Rm+, @Rn+ {:
727 CHECKRALIGN16( sh4r.r[Rn] );
728 CHECKRALIGN16( sh4r.r[Rm] );
729 int32_t stmp = SIGNEXT16(MEM_READ_WORD(sh4r.r[Rn]));
730 sh4r.r[Rn] += 2;
731 stmp = stmp * SIGNEXT16(MEM_READ_WORD(sh4r.r[Rm]));
732 sh4r.r[Rm] += 2;
733 if( sh4r.s ) {
734 int64_t tmpl = (int64_t)((int32_t)sh4r.mac) + (int64_t)stmp;
735 if( tmpl > (int64_t)0x000000007FFFFFFFLL ) {
736 sh4r.mac = 0x000000017FFFFFFFLL;
737 } else if( tmpl < (int64_t)0xFFFFFFFF80000000LL ) {
738 sh4r.mac = 0x0000000180000000LL;
739 } else {
740 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
741 ((uint32_t)(sh4r.mac + stmp));
742 }
743 } else {
744 sh4r.mac += SIGNEXT32(stmp);
745 }
746 :}
747 MAC.L @Rm+, @Rn+ {:
748 CHECKRALIGN32( sh4r.r[Rm] );
749 CHECKRALIGN32( sh4r.r[Rn] );
750 int64_t tmpl = SIGNEXT32(MEM_READ_LONG(sh4r.r[Rn]));
751 sh4r.r[Rn] += 4;
752 tmpl = tmpl * SIGNEXT32(MEM_READ_LONG(sh4r.r[Rm])) + sh4r.mac;
753 sh4r.r[Rm] += 4;
754 if( sh4r.s ) {
755 /* 48-bit Saturation. Yuch */
756 if( tmpl < (int64_t)0xFFFF800000000000LL )
757 tmpl = 0xFFFF800000000000LL;
758 else if( tmpl > (int64_t)0x00007FFFFFFFFFFFLL )
759 tmpl = 0x00007FFFFFFFFFFFLL;
760 }
761 sh4r.mac = tmpl;
762 :}
763 MUL.L Rm, Rn {: sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
764 (sh4r.r[Rm] * sh4r.r[Rn]); :}
765 MULU.W Rm, Rn {:
766 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
767 (uint32_t)((sh4r.r[Rm]&0xFFFF) * (sh4r.r[Rn]&0xFFFF));
768 :}
769 MULS.W Rm, Rn {:
770 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
771 (uint32_t)(SIGNEXT32(sh4r.r[Rm]&0xFFFF) * SIGNEXT32(sh4r.r[Rn]&0xFFFF));
772 :}
773 NEGC Rm, Rn {:
774 tmp = 0 - sh4r.r[Rm];
775 sh4r.r[Rn] = tmp - sh4r.t;
776 sh4r.t = ( 0<tmp || tmp<sh4r.r[Rn] ? 1 : 0 );
777 :}
778 NEG Rm, Rn {: sh4r.r[Rn] = 0 - sh4r.r[Rm]; :}
779 SUB Rm, Rn {: sh4r.r[Rn] -= sh4r.r[Rm]; :}
780 SUBC Rm, Rn {:
781 tmp = sh4r.r[Rn];
782 sh4r.r[Rn] = sh4r.r[Rn] - sh4r.r[Rm] - sh4r.t;
783 sh4r.t = (sh4r.r[Rn] > tmp || (sh4r.r[Rn] == tmp && sh4r.t == 1));
784 :}
786 BRAF Rn {:
787 CHECKSLOTILLEGAL();
788 CHECKDEST( pc + 4 + sh4r.r[Rn] );
789 sh4r.in_delay_slot = 1;
790 sh4r.pc = sh4r.new_pc;
791 sh4r.new_pc = pc + 4 + sh4r.r[Rn];
792 return TRUE;
793 :}
794 BSRF Rn {:
795 CHECKSLOTILLEGAL();
796 CHECKDEST( pc + 4 + sh4r.r[Rn] );
797 sh4r.in_delay_slot = 1;
798 sh4r.pr = sh4r.pc + 4;
799 sh4r.pc = sh4r.new_pc;
800 sh4r.new_pc = pc + 4 + sh4r.r[Rn];
801 TRACE_CALL( pc, sh4r.new_pc );
802 return TRUE;
803 :}
804 BT disp {:
805 CHECKSLOTILLEGAL();
806 if( sh4r.t ) {
807 CHECKDEST( sh4r.pc + disp + 4 )
808 sh4r.pc += disp + 4;
809 sh4r.new_pc = sh4r.pc + 2;
810 return TRUE;
811 }
812 :}
813 BF disp {:
814 CHECKSLOTILLEGAL();
815 if( !sh4r.t ) {
816 CHECKDEST( sh4r.pc + disp + 4 )
817 sh4r.pc += disp + 4;
818 sh4r.new_pc = sh4r.pc + 2;
819 return TRUE;
820 }
821 :}
822 BT/S disp {:
823 CHECKSLOTILLEGAL();
824 if( sh4r.t ) {
825 CHECKDEST( sh4r.pc + disp + 4 )
826 sh4r.in_delay_slot = 1;
827 sh4r.pc = sh4r.new_pc;
828 sh4r.new_pc = pc + disp + 4;
829 sh4r.in_delay_slot = 1;
830 return TRUE;
831 }
832 :}
833 BF/S disp {:
834 CHECKSLOTILLEGAL();
835 if( !sh4r.t ) {
836 CHECKDEST( sh4r.pc + disp + 4 )
837 sh4r.in_delay_slot = 1;
838 sh4r.pc = sh4r.new_pc;
839 sh4r.new_pc = pc + disp + 4;
840 return TRUE;
841 }
842 :}
843 BRA disp {:
844 CHECKSLOTILLEGAL();
845 CHECKDEST( sh4r.pc + disp + 4 );
846 sh4r.in_delay_slot = 1;
847 sh4r.pc = sh4r.new_pc;
848 sh4r.new_pc = pc + 4 + disp;
849 return TRUE;
850 :}
851 BSR disp {:
852 CHECKDEST( sh4r.pc + disp + 4 );
853 CHECKSLOTILLEGAL();
854 sh4r.in_delay_slot = 1;
855 sh4r.pr = pc + 4;
856 sh4r.pc = sh4r.new_pc;
857 sh4r.new_pc = pc + 4 + disp;
858 TRACE_CALL( pc, sh4r.new_pc );
859 return TRUE;
860 :}
861 TRAPA #imm {:
862 CHECKSLOTILLEGAL();
863 MMIO_WRITE( MMU, TRA, imm<<2 );
864 sh4r.pc += 2;
865 sh4_raise_exception( EXC_TRAP );
866 :}
867 RTS {:
868 CHECKSLOTILLEGAL();
869 CHECKDEST( sh4r.pr );
870 sh4r.in_delay_slot = 1;
871 sh4r.pc = sh4r.new_pc;
872 sh4r.new_pc = sh4r.pr;
873 TRACE_RETURN( pc, sh4r.new_pc );
874 return TRUE;
875 :}
876 SLEEP {:
877 if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
878 sh4r.sh4_state = SH4_STATE_STANDBY;
879 } else {
880 sh4r.sh4_state = SH4_STATE_SLEEP;
881 }
882 return FALSE; /* Halt CPU */
883 :}
884 RTE {:
885 CHECKPRIV();
886 CHECKDEST( sh4r.spc );
887 CHECKSLOTILLEGAL();
888 sh4r.in_delay_slot = 1;
889 sh4r.pc = sh4r.new_pc;
890 sh4r.new_pc = sh4r.spc;
891 sh4_load_sr( sh4r.ssr );
892 return TRUE;
893 :}
894 JMP @Rn {:
895 CHECKDEST( sh4r.r[Rn] );
896 CHECKSLOTILLEGAL();
897 sh4r.in_delay_slot = 1;
898 sh4r.pc = sh4r.new_pc;
899 sh4r.new_pc = sh4r.r[Rn];
900 return TRUE;
901 :}
902 JSR @Rn {:
903 CHECKDEST( sh4r.r[Rn] );
904 CHECKSLOTILLEGAL();
905 sh4r.in_delay_slot = 1;
906 sh4r.pc = sh4r.new_pc;
907 sh4r.new_pc = sh4r.r[Rn];
908 sh4r.pr = pc + 4;
909 TRACE_CALL( pc, sh4r.new_pc );
910 return TRUE;
911 :}
912 STS MACH, Rn {: sh4r.r[Rn] = (sh4r.mac>>32); :}
913 STS.L MACH, @-Rn {:
914 sh4r.r[Rn] -= 4;
915 CHECKWALIGN32( sh4r.r[Rn] );
916 MEM_WRITE_LONG( sh4r.r[Rn], (sh4r.mac>>32) );
917 :}
918 STC.L SR, @-Rn {:
919 CHECKPRIV();
920 sh4r.r[Rn] -= 4;
921 CHECKWALIGN32( sh4r.r[Rn] );
922 MEM_WRITE_LONG( sh4r.r[Rn], sh4_read_sr() );
923 :}
924 LDS.L @Rm+, MACH {:
925 CHECKRALIGN32( sh4r.r[Rm] );
926 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
927 (((uint64_t)MEM_READ_LONG(sh4r.r[Rm]))<<32);
928 sh4r.r[Rm] += 4;
929 :}
930 LDC.L @Rm+, SR {:
931 CHECKSLOTILLEGAL();
932 CHECKPRIV();
933 CHECKWALIGN32( sh4r.r[Rm] );
934 sh4_load_sr( MEM_READ_LONG(sh4r.r[Rm]) );
935 sh4r.r[Rm] +=4;
936 :}
937 LDS Rm, MACH {:
938 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
939 (((uint64_t)sh4r.r[Rm])<<32);
940 :}
941 LDC Rm, SR {:
942 CHECKSLOTILLEGAL();
943 CHECKPRIV();
944 sh4_load_sr( sh4r.r[Rm] );
945 :}
946 LDC Rm, SGR {:
947 CHECKPRIV();
948 sh4r.sgr = sh4r.r[Rm];
949 :}
950 LDC.L @Rm+, SGR {:
951 CHECKPRIV();
952 CHECKRALIGN32( sh4r.r[Rm] );
953 sh4r.sgr = MEM_READ_LONG(sh4r.r[Rm]);
954 sh4r.r[Rm] +=4;
955 :}
956 STS MACL, Rn {: sh4r.r[Rn] = (uint32_t)sh4r.mac; :}
957 STS.L MACL, @-Rn {:
958 sh4r.r[Rn] -= 4;
959 CHECKWALIGN32( sh4r.r[Rn] );
960 MEM_WRITE_LONG( sh4r.r[Rn], (uint32_t)sh4r.mac );
961 :}
962 STC.L GBR, @-Rn {:
963 sh4r.r[Rn] -= 4;
964 CHECKWALIGN32( sh4r.r[Rn] );
965 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.gbr );
966 :}
967 LDS.L @Rm+, MACL {:
968 CHECKRALIGN32( sh4r.r[Rm] );
969 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
970 (uint64_t)((uint32_t)MEM_READ_LONG(sh4r.r[Rm]));
971 sh4r.r[Rm] += 4;
972 :}
973 LDC.L @Rm+, GBR {:
974 CHECKRALIGN32( sh4r.r[Rm] );
975 sh4r.gbr = MEM_READ_LONG(sh4r.r[Rm]);
976 sh4r.r[Rm] +=4;
977 :}
978 LDS Rm, MACL {:
979 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
980 (uint64_t)((uint32_t)(sh4r.r[Rm]));
981 :}
982 LDC Rm, GBR {: sh4r.gbr = sh4r.r[Rm]; :}
983 STS PR, Rn {: sh4r.r[Rn] = sh4r.pr; :}
984 STS.L PR, @-Rn {:
985 sh4r.r[Rn] -= 4;
986 CHECKWALIGN32( sh4r.r[Rn] );
987 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.pr );
988 :}
989 STC.L VBR, @-Rn {:
990 CHECKPRIV();
991 sh4r.r[Rn] -= 4;
992 CHECKWALIGN32( sh4r.r[Rn] );
993 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.vbr );
994 :}
995 LDS.L @Rm+, PR {:
996 CHECKRALIGN32( sh4r.r[Rm] );
997 sh4r.pr = MEM_READ_LONG( sh4r.r[Rm] );
998 sh4r.r[Rm] += 4;
999 :}
1000 LDC.L @Rm+, VBR {:
1001 CHECKPRIV();
1002 CHECKRALIGN32( sh4r.r[Rm] );
1003 sh4r.vbr = MEM_READ_LONG(sh4r.r[Rm]);
1004 sh4r.r[Rm] +=4;
1005 :}
1006 LDS Rm, PR {: sh4r.pr = sh4r.r[Rm]; :}
1007 LDC Rm, VBR {:
1008 CHECKPRIV();
1009 sh4r.vbr = sh4r.r[Rm];
1010 :}
1011 STC SGR, Rn {:
1012 CHECKPRIV();
1013 sh4r.r[Rn] = sh4r.sgr;
1014 :}
1015 STC.L SGR, @-Rn {:
1016 CHECKPRIV();
1017 sh4r.r[Rn] -= 4;
1018 CHECKWALIGN32( sh4r.r[Rn] );
1019 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.sgr );
1020 :}
1021 STC.L SSR, @-Rn {:
1022 CHECKPRIV();
1023 sh4r.r[Rn] -= 4;
1024 CHECKWALIGN32( sh4r.r[Rn] );
1025 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.ssr );
1026 :}
1027 LDC.L @Rm+, SSR {:
1028 CHECKPRIV();
1029 CHECKRALIGN32( sh4r.r[Rm] );
1030 sh4r.ssr = MEM_READ_LONG(sh4r.r[Rm]);
1031 sh4r.r[Rm] +=4;
1032 :}
1033 LDC Rm, SSR {:
1034 CHECKPRIV();
1035 sh4r.ssr = sh4r.r[Rm];
1036 :}
1037 STC.L SPC, @-Rn {:
1038 CHECKPRIV();
1039 sh4r.r[Rn] -= 4;
1040 CHECKWALIGN32( sh4r.r[Rn] );
1041 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.spc );
1042 :}
1043 LDC.L @Rm+, SPC {:
1044 CHECKPRIV();
1045 CHECKRALIGN32( sh4r.r[Rm] );
1046 sh4r.spc = MEM_READ_LONG(sh4r.r[Rm]);
1047 sh4r.r[Rm] +=4;
1048 :}
1049 LDC Rm, SPC {:
1050 CHECKPRIV();
1051 sh4r.spc = sh4r.r[Rm];
1052 :}
1053 STS FPUL, Rn {: sh4r.r[Rn] = sh4r.fpul; :}
1054 STS.L FPUL, @-Rn {:
1055 sh4r.r[Rn] -= 4;
1056 CHECKWALIGN32( sh4r.r[Rn] );
1057 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.fpul );
1058 :}
1059 LDS.L @Rm+, FPUL {:
1060 CHECKRALIGN32( sh4r.r[Rm] );
1061 sh4r.fpul = MEM_READ_LONG(sh4r.r[Rm]);
1062 sh4r.r[Rm] +=4;
1063 :}
1064 LDS Rm, FPUL {: sh4r.fpul = sh4r.r[Rm]; :}
1065 STS FPSCR, Rn {: sh4r.r[Rn] = sh4r.fpscr; :}
1066 STS.L FPSCR, @-Rn {:
1067 sh4r.r[Rn] -= 4;
1068 CHECKWALIGN32( sh4r.r[Rn] );
1069 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.fpscr );
1070 :}
1071 LDS.L @Rm+, FPSCR {:
1072 CHECKRALIGN32( sh4r.r[Rm] );
1073 sh4r.fpscr = MEM_READ_LONG(sh4r.r[Rm]);
1074 sh4r.r[Rm] +=4;
1075 :}
1076 LDS Rm, FPSCR {: sh4r.fpscr = sh4r.r[Rm]; :}
1077 STC DBR, Rn {: CHECKPRIV(); sh4r.r[Rn] = sh4r.dbr; :}
1078 STC.L DBR, @-Rn {:
1079 CHECKPRIV();
1080 sh4r.r[Rn] -= 4;
1081 CHECKWALIGN32( sh4r.r[Rn] );
1082 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.dbr );
1083 :}
1084 LDC.L @Rm+, DBR {:
1085 CHECKPRIV();
1086 CHECKRALIGN32( sh4r.r[Rm] );
1087 sh4r.dbr = MEM_READ_LONG(sh4r.r[Rm]);
1088 sh4r.r[Rm] +=4;
1089 :}
1090 LDC Rm, DBR {:
1091 CHECKPRIV();
1092 sh4r.dbr = sh4r.r[Rm];
1093 :}
1094 STC.L Rm_BANK, @-Rn {:
1095 CHECKPRIV();
1096 sh4r.r[Rn] -= 4;
1097 CHECKWALIGN32( sh4r.r[Rn] );
1098 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r_bank[Rm_BANK] );
1099 :}
1100 LDC.L @Rm+, Rn_BANK {:
1101 CHECKPRIV();
1102 CHECKRALIGN32( sh4r.r[Rm] );
1103 sh4r.r_bank[Rn_BANK] = MEM_READ_LONG( sh4r.r[Rm] );
1104 sh4r.r[Rm] += 4;
1105 :}
1106 LDC Rm, Rn_BANK {:
1107 CHECKPRIV();
1108 sh4r.r_bank[Rn_BANK] = sh4r.r[Rm];
1109 :}
1110 STC SR, Rn {:
1111 CHECKPRIV();
1112 sh4r.r[Rn] = sh4_read_sr();
1113 :}
1114 STC GBR, Rn {:
1115 CHECKPRIV();
1116 sh4r.r[Rn] = sh4r.gbr;
1117 :}
1118 STC VBR, Rn {:
1119 CHECKPRIV();
1120 sh4r.r[Rn] = sh4r.vbr;
1121 :}
1122 STC SSR, Rn {:
1123 CHECKPRIV();
1124 sh4r.r[Rn] = sh4r.ssr;
1125 :}
1126 STC SPC, Rn {:
1127 CHECKPRIV();
1128 sh4r.r[Rn] = sh4r.spc;
1129 :}
1130 STC Rm_BANK, Rn {:
1131 CHECKPRIV();
1132 sh4r.r[Rn] = sh4r.r_bank[Rm_BANK];
1133 :}
1135 FADD FRm, FRn {:
1136 CHECKFPUEN();
1137 if( IS_FPU_DOUBLEPREC() ) {
1138 DR(FRn) += DR(FRm);
1139 } else {
1140 FR(FRn) += FR(FRm);
1141 }
1142 :}
1143 FSUB FRm, FRn {:
1144 CHECKFPUEN();
1145 if( IS_FPU_DOUBLEPREC() ) {
1146 DR(FRn) -= DR(FRm);
1147 } else {
1148 FR(FRn) -= FR(FRm);
1149 }
1150 :}
1152 FMUL FRm, FRn {:
1153 CHECKFPUEN();
1154 if( IS_FPU_DOUBLEPREC() ) {
1155 DR(FRn) *= DR(FRm);
1156 } else {
1157 FR(FRn) *= FR(FRm);
1158 }
1159 :}
1161 FDIV FRm, FRn {:
1162 CHECKFPUEN();
1163 if( IS_FPU_DOUBLEPREC() ) {
1164 DR(FRn) /= DR(FRm);
1165 } else {
1166 FR(FRn) /= FR(FRm);
1167 }
1168 :}
1170 FCMP/EQ FRm, FRn {:
1171 CHECKFPUEN();
1172 if( IS_FPU_DOUBLEPREC() ) {
1173 sh4r.t = ( DR(FRn) == DR(FRm) ? 1 : 0 );
1174 } else {
1175 sh4r.t = ( FR(FRn) == FR(FRm) ? 1 : 0 );
1176 }
1177 :}
1179 FCMP/GT FRm, FRn {:
1180 CHECKFPUEN();
1181 if( IS_FPU_DOUBLEPREC() ) {
1182 sh4r.t = ( DR(FRn) > DR(FRm) ? 1 : 0 );
1183 } else {
1184 sh4r.t = ( FR(FRn) > FR(FRm) ? 1 : 0 );
1185 }
1186 :}
1188 FMOV @(R0, Rm), FRn {: MEM_FP_READ( sh4r.r[Rm] + R0, FRn ); :}
1189 FMOV FRm, @(R0, Rn) {: MEM_FP_WRITE( sh4r.r[Rn] + R0, FRm ); :}
1190 FMOV @Rm, FRn {: MEM_FP_READ( sh4r.r[Rm], FRn ); :}
1191 FMOV @Rm+, FRn {: MEM_FP_READ( sh4r.r[Rm], FRn ); sh4r.r[Rm] += FP_WIDTH; :}
1192 FMOV FRm, @Rn {: MEM_FP_WRITE( sh4r.r[Rn], FRm ); :}
1193 FMOV FRm, @-Rn {: sh4r.r[Rn] -= FP_WIDTH; MEM_FP_WRITE( sh4r.r[Rn], FRm ); :}
1194 FMOV FRm, FRn {:
1195 if( IS_FPU_DOUBLESIZE() )
1196 DR(FRn) = DR(FRm);
1197 else
1198 FR(FRn) = FR(FRm);
1199 :}
1200 FSTS FPUL, FRn {: CHECKFPUEN(); FR(FRn) = FPULf; :}
1201 FLDS FRm, FPUL {: CHECKFPUEN(); FPULf = FR(FRm); :}
1202 FLOAT FPUL, FRn {:
1203 CHECKFPUEN();
1204 if( IS_FPU_DOUBLEPREC() )
1205 DR(FRn) = (float)FPULi;
1206 else
1207 FR(FRn) = (float)FPULi;
1208 :}
1209 FTRC FRm, FPUL {:
1210 CHECKFPUEN();
1211 if( IS_FPU_DOUBLEPREC() ) {
1212 dtmp = DR(FRm);
1213 if( dtmp >= MAX_INTF )
1214 FPULi = MAX_INT;
1215 else if( dtmp <= MIN_INTF )
1216 FPULi = MIN_INT;
1217 else
1218 FPULi = (int32_t)dtmp;
1219 } else {
1220 ftmp = FR(FRm);
1221 if( ftmp >= MAX_INTF )
1222 FPULi = MAX_INT;
1223 else if( ftmp <= MIN_INTF )
1224 FPULi = MIN_INT;
1225 else
1226 FPULi = (int32_t)ftmp;
1227 }
1228 :}
1229 FNEG FRn {:
1230 CHECKFPUEN();
1231 if( IS_FPU_DOUBLEPREC() ) {
1232 DR(FRn) = -DR(FRn);
1233 } else {
1234 FR(FRn) = -FR(FRn);
1235 }
1236 :}
1237 FABS FRn {:
1238 CHECKFPUEN();
1239 if( IS_FPU_DOUBLEPREC() ) {
1240 DR(FRn) = fabs(DR(FRn));
1241 } else {
1242 FR(FRn) = fabsf(FR(FRn));
1243 }
1244 :}
1245 FSQRT FRn {:
1246 CHECKFPUEN();
1247 if( IS_FPU_DOUBLEPREC() ) {
1248 DR(FRn) = sqrt(DR(FRn));
1249 } else {
1250 FR(FRn) = sqrtf(FR(FRn));
1251 }
1252 :}
1253 FLDI0 FRn {:
1254 CHECKFPUEN();
1255 if( IS_FPU_DOUBLEPREC() ) {
1256 DR(FRn) = 0.0;
1257 } else {
1258 FR(FRn) = 0.0;
1259 }
1260 :}
1261 FLDI1 FRn {:
1262 CHECKFPUEN();
1263 if( IS_FPU_DOUBLEPREC() ) {
1264 DR(FRn) = 1.0;
1265 } else {
1266 FR(FRn) = 1.0;
1267 }
1268 :}
1269 FMAC FR0, FRm, FRn {:
1270 CHECKFPUEN();
1271 if( IS_FPU_DOUBLEPREC() ) {
1272 DR(FRn) += DR(FRm)*DR(0);
1273 } else {
1274 FR(FRn) += FR(FRm)*FR(0);
1275 }
1276 :}
1277 FRCHG {: CHECKFPUEN(); sh4r.fpscr ^= FPSCR_FR; :}
1278 FSCHG {: CHECKFPUEN(); sh4r.fpscr ^= FPSCR_SZ; :}
1279 FCNVSD FPUL, FRn {:
1280 CHECKFPUEN();
1281 if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
1282 DR(FRn) = (double)FPULf;
1283 }
1284 :}
1285 FCNVDS FRm, FPUL {:
1286 CHECKFPUEN();
1287 if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
1288 FPULf = (float)DR(FRm);
1289 }
1290 :}
1292 FSRRA FRn {:
1293 CHECKFPUEN();
1294 if( !IS_FPU_DOUBLEPREC() ) {
1295 FR(FRn) = 1.0/sqrtf(FR(FRn));
1296 }
1297 :}
1298 FIPR FVm, FVn {:
1299 CHECKFPUEN();
1300 if( !IS_FPU_DOUBLEPREC() ) {
1301 int tmp2 = FVn<<2;
1302 tmp = FVm<<2;
1303 FR(tmp2+3) = FR(tmp)*FR(tmp2) +
1304 FR(tmp+1)*FR(tmp2+1) +
1305 FR(tmp+2)*FR(tmp2+2) +
1306 FR(tmp+3)*FR(tmp2+3);
1307 }
1308 :}
1309 FSCA FPUL, FRn {:
1310 CHECKFPUEN();
1311 if( !IS_FPU_DOUBLEPREC() ) {
1312 float angle = (((float)(FPULi&0xFFFF))/65536.0) * 2 * M_PI;
1313 FR(FRn) = sinf(angle);
1314 FR((FRn)+1) = cosf(angle);
1315 }
1316 :}
1317 FTRV XMTRX, FVn {:
1318 CHECKFPUEN();
1319 if( !IS_FPU_DOUBLEPREC() ) {
1320 tmp = FVn<<2;
1321 float fv[4] = { FR(tmp), FR(tmp+1), FR(tmp+2), FR(tmp+3) };
1322 FR(tmp) = XF(0) * fv[0] + XF(4)*fv[1] +
1323 XF(8)*fv[2] + XF(12)*fv[3];
1324 FR(tmp+1) = XF(1) * fv[0] + XF(5)*fv[1] +
1325 XF(9)*fv[2] + XF(13)*fv[3];
1326 FR(tmp+2) = XF(2) * fv[0] + XF(6)*fv[1] +
1327 XF(10)*fv[2] + XF(14)*fv[3];
1328 FR(tmp+3) = XF(3) * fv[0] + XF(7)*fv[1] +
1329 XF(11)*fv[2] + XF(15)*fv[3];
1330 }
1331 :}
1332 UNDEF {:
1333 UNDEF(ir);
1334 :}
1335 %%
1336 sh4r.pc = sh4r.new_pc;
1337 sh4r.new_pc += 2;
1338 sh4r.in_delay_slot = 0;
1339 return TRUE;
1340 }
.