filename | src/asic.c |
changeset | 137:41907543d890 |
prev | 125:49bf45f8210a |
next | 155:be61d1a20937 |
author | nkeynes |
date | Tue May 23 13:10:28 2006 +0000 (17 years ago) |
permissions | -rw-r--r-- |
last change | Add texcache invalidates on direct writes to 64-bit vram. Technically we should do it on direct writes to 32-bit vram as well, but noone (sane) is going to try to write a texture there... |
view | annotate | diff | log | raw |
1 /**
2 * $Id: asic.c,v 1.14 2006-04-30 01:50:13 nkeynes Exp $
3 *
4 * Support for the miscellaneous ASIC functions (Primarily event multiplexing,
5 * and DMA).
6 *
7 * Copyright (c) 2005 Nathan Keynes.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
20 #define MODULE asic_module
22 #include <assert.h>
23 #include <stdlib.h>
24 #include "dream.h"
25 #include "mem.h"
26 #include "sh4/intc.h"
27 #include "sh4/dmac.h"
28 #include "dreamcast.h"
29 #include "maple/maple.h"
30 #include "gdrom/ide.h"
31 #include "asic.h"
32 #define MMIO_IMPL
33 #include "asic.h"
34 /*
35 * Open questions:
36 * 1) Does changing the mask after event occurance result in the
37 * interrupt being delivered immediately?
38 * TODO: Logic diagram of ASIC event/interrupt logic.
39 *
40 * ... don't even get me started on the "EXTDMA" page, about which, apparently,
41 * practically nothing is publicly known...
42 */
44 struct dreamcast_module asic_module = { "ASIC", asic_init, NULL, NULL, NULL,
45 NULL, NULL, NULL };
47 #define G2_BIT5_TICKS 8
48 #define G2_BIT4_TICKS 16
49 #define G2_BIT0_ON_TICKS 24
50 #define G2_BIT0_OFF_TICKS 24
52 struct asic_g2_state {
53 unsigned int bit5_off_timer;
54 unsigned int bit4_on_timer;
55 unsigned int bit4_off_timer;
56 unsigned int bit0_on_timer;
57 unsigned int bit0_off_timer;
58 } g2_state;
60 /* FIXME: Handle rollover */
61 void asic_g2_write_word()
62 {
63 g2_state.bit5_off_timer = sh4r.icount + G2_BIT5_TICKS;
64 if( g2_state.bit4_off_timer < sh4r.icount )
65 g2_state.bit4_on_timer = sh4r.icount + G2_BIT5_TICKS;
66 g2_state.bit4_off_timer = max(sh4r.icount,g2_state.bit4_off_timer) + G2_BIT4_TICKS;
67 if( g2_state.bit0_off_timer < sh4r.icount ) {
68 g2_state.bit0_on_timer = sh4r.icount + G2_BIT0_ON_TICKS;
69 g2_state.bit0_off_timer = g2_state.bit0_on_timer + G2_BIT0_OFF_TICKS;
70 } else {
71 g2_state.bit0_off_timer += G2_BIT0_OFF_TICKS;
72 }
73 MMIO_WRITE( ASIC, G2STATUS, MMIO_READ(ASIC, G2STATUS) | 0x20 );
74 }
76 static uint32_t g2_read_status()
77 {
78 uint32_t val = MMIO_READ( ASIC, G2STATUS );
79 if( g2_state.bit5_off_timer <= sh4r.icount )
80 val = val & (~0x20);
81 if( g2_state.bit4_off_timer <= sh4r.icount )
82 val = val & (~0x10);
83 else if( g2_state.bit4_on_timer <= sh4r.icount )
84 val = val | 0x10;
85 if( g2_state.bit0_off_timer <= sh4r.icount )
86 val = val & (~0x01);
87 else if( g2_state.bit0_on_timer <= sh4r.icount )
88 val = val | 0x01;
89 return val | 0x0E;
90 }
92 void asic_check_cleared_events( void );
94 void asic_init( void )
95 {
96 register_io_region( &mmio_region_ASIC );
97 register_io_region( &mmio_region_EXTDMA );
98 mmio_region_ASIC.trace_flag = 0; /* Because this is called so often */
99 }
101 void mmio_region_ASIC_write( uint32_t reg, uint32_t val )
102 {
103 switch( reg ) {
104 case PIRQ1:
105 val = val & 0xFFFFFFFE; /* Prevent the IDE event from clearing */
106 /* fallthrough */
107 case PIRQ0:
108 case PIRQ2:
109 /* Clear any interrupts */
110 MMIO_WRITE( ASIC, reg, MMIO_READ(ASIC, reg)&~val );
111 asic_check_cleared_events();
112 break;
113 case MAPLE_STATE:
114 MMIO_WRITE( ASIC, reg, val );
115 if( val & 1 ) {
116 uint32_t maple_addr = MMIO_READ( ASIC, MAPLE_DMA) &0x1FFFFFE0;
117 WARN( "Maple request initiated at %08X, halting", maple_addr );
118 maple_handle_buffer( maple_addr );
119 MMIO_WRITE( ASIC, reg, 0 );
120 }
121 break;
122 case PVRDMACTL: /* Initiate PVR DMA transfer */
123 MMIO_WRITE( ASIC, reg, val );
124 WARN( "Write to ASIC (%03X <= %08X) [%s: %s]",
125 reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );
126 if( val & 1 ) {
127 uint32_t dest_addr = MMIO_READ( ASIC, PVRDMADEST) &0x1FFFFFE0;
128 uint32_t count = MMIO_READ( ASIC, PVRDMACNT );
129 char *data = alloca( count );
130 uint32_t rcount = DMAC_get_buffer( 2, data, count );
131 if( rcount != count )
132 WARN( "PVR received %08X bytes from DMA, expected %08X", rcount, count );
133 mem_copy_to_sh4( dest_addr, data, rcount );
134 asic_event( EVENT_PVR_DMA );
135 }
136 break;
137 default:
138 MMIO_WRITE( ASIC, reg, val );
139 WARN( "Write to ASIC (%03X <= %08X) [%s: %s]",
140 reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );
141 }
142 }
144 int32_t mmio_region_ASIC_read( uint32_t reg )
145 {
146 int32_t val;
147 switch( reg ) {
148 /*
149 case 0x89C:
150 sh4_stop();
151 return 0x000000B;
152 */
153 case PIRQ0:
154 case PIRQ1:
155 case PIRQ2:
156 case IRQA0:
157 case IRQA1:
158 case IRQA2:
159 case IRQB0:
160 case IRQB1:
161 case IRQB2:
162 case IRQC0:
163 case IRQC1:
164 case IRQC2:
165 val = MMIO_READ(ASIC, reg);
166 // WARN( "Read from ASIC (%03X => %08X) [%s: %s]",
167 // reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );
168 return val;
169 case G2STATUS:
170 return g2_read_status();
171 default:
172 val = MMIO_READ(ASIC, reg);
173 WARN( "Read from ASIC (%03X => %08X) [%s: %s]",
174 reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );
175 return val;
176 }
178 }
180 void asic_event( int event )
181 {
182 int offset = ((event&0x60)>>3);
183 int result = (MMIO_READ(ASIC, PIRQ0 + offset)) |= (1<<(event&0x1F));
185 if( result & MMIO_READ(ASIC, IRQA0 + offset) )
186 intc_raise_interrupt( INT_IRQ13 );
187 if( result & MMIO_READ(ASIC, IRQB0 + offset) )
188 intc_raise_interrupt( INT_IRQ11 );
189 if( result & MMIO_READ(ASIC, IRQC0 + offset) )
190 intc_raise_interrupt( INT_IRQ9 );
191 }
193 void asic_clear_event( int event ) {
194 int offset = ((event&0x60)>>3);
195 uint32_t result = MMIO_READ(ASIC, PIRQ0 + offset) & (~(1<<(event&0x1F)));
196 MMIO_WRITE( ASIC, PIRQ0 + offset, result );
198 asic_check_cleared_events();
199 }
201 void asic_check_cleared_events( )
202 {
203 int i, setA = 0, setB = 0, setC = 0;
204 uint32_t bits;
205 for( i=0; i<3; i++ ) {
206 bits = MMIO_READ( ASIC, PIRQ0 + i );
207 setA |= (bits & MMIO_READ(ASIC, IRQA0 + i ));
208 setB |= (bits & MMIO_READ(ASIC, IRQB0 + i ));
209 setC |= (bits & MMIO_READ(ASIC, IRQC0 + i ));
210 }
211 if( setA == 0 )
212 intc_clear_interrupt( INT_IRQ13 );
213 if( setB == 0 )
214 intc_clear_interrupt( INT_IRQ11 );
215 if( setC == 0 )
216 intc_clear_interrupt( INT_IRQ9 );
217 }
220 MMIO_REGION_WRITE_FN( EXTDMA, reg, val )
221 {
222 WARN( "EXTDMA write %08X <= %08X", reg, val );
224 switch( reg ) {
225 case IDEALTSTATUS: /* Device control */
226 ide_write_control( val );
227 break;
228 case IDEDATA:
229 ide_write_data_pio( val );
230 break;
231 case IDEFEAT:
232 if( ide_can_write_regs() )
233 idereg.feature = (uint8_t)val;
234 break;
235 case IDECOUNT:
236 if( ide_can_write_regs() )
237 idereg.count = (uint8_t)val;
238 break;
239 case IDELBA0:
240 if( ide_can_write_regs() )
241 idereg.lba0 = (uint8_t)val;
242 break;
243 case IDELBA1:
244 if( ide_can_write_regs() )
245 idereg.lba1 = (uint8_t)val;
246 break;
247 case IDELBA2:
248 if( ide_can_write_regs() )
249 idereg.lba2 = (uint8_t)val;
250 break;
251 case IDEDEV:
252 if( ide_can_write_regs() )
253 idereg.device = (uint8_t)val;
254 break;
255 case IDECMD:
256 if( ide_can_write_regs() ) {
257 ide_write_command( (uint8_t)val );
258 }
259 break;
260 case IDEDMACTL1:
261 case IDEDMACTL2:
262 MMIO_WRITE( EXTDMA, reg, val );
263 if( MMIO_READ( EXTDMA, IDEDMACTL1 ) == 1 &&
264 MMIO_READ( EXTDMA, IDEDMACTL2 ) == 1 ) {
265 uint32_t target_addr = MMIO_READ( EXTDMA, IDEDMASH4 );
266 uint32_t length = MMIO_READ( EXTDMA, IDEDMASIZ );
267 int dir = MMIO_READ( EXTDMA, IDEDMADIR );
268 }
269 break;
270 default:
271 MMIO_WRITE( EXTDMA, reg, val );
272 }
273 }
275 MMIO_REGION_READ_FN( EXTDMA, reg )
276 {
277 uint32_t val;
278 switch( reg ) {
279 case IDEALTSTATUS: return idereg.status;
280 case IDEDATA: return ide_read_data_pio( );
281 case IDEFEAT: return idereg.error;
282 case IDECOUNT:return idereg.count;
283 case IDELBA0: return idereg.disc;
284 case IDELBA1: return idereg.lba1;
285 case IDELBA2: return idereg.lba2;
286 case IDEDEV: return idereg.device;
287 case IDECMD:
288 return ide_read_status();
289 default:
290 val = MMIO_READ( EXTDMA, reg );
291 //DEBUG( "EXTDMA read %08X => %08X", reg, val );
292 return val;
293 }
294 }
.