filename | src/sh4/intc.h |
changeset | 1:eea311cfd33e |
next | 31:495e480360d7 |
author | nkeynes |
date | Sun Dec 11 05:15:36 2005 +0000 (18 years ago) |
permissions | -rw-r--r-- |
last change | Add CPU disasembly options to mode dropdown Split sh4/mem.c into core mem.c and sh4/mem.c Start adding copyright comments to file headers |
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1 #ifndef sh4intc_H
2 #define sh4intc_H 1
4 #include "sh4core.h"
6 #ifdef __cplusplus
7 extern "C" {
8 #if 0
9 }
10 #endif
11 #endif
13 #define INT_IRQ0 0 /* External Interrupt request 0 */
14 #define INT_IRQ1 1
15 #define INT_IRQ2 2
16 #define INT_IRQ3 3
17 #define INT_IRQ4 4
18 #define INT_IRQ5 5
19 #define INT_IRQ6 6
20 #define INT_IRQ7 7
21 #define INT_IRQ8 8
22 #define INT_IRQ9 9
23 #define INT_IRQ10 10
24 #define INT_IRQ11 11
25 #define INT_IRQ12 12
26 #define INT_IRQ13 13
27 #define INT_IRQ14 14
28 #define INT_NMI 15 /* Non-Maskable Interrupt */
29 #define INT_HUDI 16 /* Hitachi use debug interface */
30 #define INT_GPIO 17 /* I/O port interrupt */
31 #define INT_DMA_DMTE0 18 /* DMA transfer end 0 */
32 #define INT_DMA_DMTE1 19 /* DMA transfer end 1 */
33 #define INT_DMA_DMTE2 20 /* DMA transfer end 2 */
34 #define INT_DMA_DMTE3 21 /* DMA transfer end 3 */
35 #define INT_DMA_DMAE 22 /* DMA address error */
36 #define INT_TMU_TUNI0 23 /* Timer underflow interrupt 0 */
37 #define INT_TMU_TUNI1 24 /* Timer underflow interrupt 1 */
38 #define INT_TMU_TUNI2 25 /* Timer underflow interrupt 2 */
39 #define INT_TMU_TICPI2 26 /* Timer input capture interrupt */
40 #define INT_RTC_ATI 27 /* RTC Alarm interrupt */
41 #define INT_RTC_PRI 28 /* RTC periodic interrupt */
42 #define INT_RTC_CUI 29 /* RTC Carry-up interrupt */
43 #define INT_SCI_ERI 30 /* SCI receive-error interrupt */
44 #define INT_SCI_RXI 31 /* SCI receive-data-full interrupt */
45 #define INT_SCI_TXI 32 /* SCI transmit-data-empty interrupt */
46 #define INT_SCI_TEI 33 /* SCI transmit-end interrupt */
47 #define INT_SCIF_ERI 34 /* SCIF receive-error interrupt */
48 #define INT_SCIF_RXI 35 /* SCIF receive-data-full interrupt */
49 #define INT_SCIF_BRI 36 /* SCIF break interrupt request */
50 #define INT_SCIF_TXI 37 /* SCIF Transmit-data-empty interrupt */
51 #define INT_WDT_ITI 38 /* WDT Interval timer interval (CPG) */
52 #define INT_REF_RCMI 39 /* Compare-match interrupt */
53 #define INT_REF_ROVI 40 /* Refresh counter overflow interrupt */
55 #define INT_NUM_SOURCES 41
57 char *intc_get_interrupt_name( int which );
58 void intc_raise_interrupt( int which );
59 void intc_clear_interrupt( int which );
60 uint32_t intc_accept_interrupt( void );
61 void intc_reset( void );
62 void intc_mask_changed( void );
64 #ifdef __cplusplus
65 }
66 #endif
68 #endif /* !sh4intc_H */
.