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lxdream.org :: lxdream/src/sh4/sh4core.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4core.c
changeset 10:c898b37506e0
prev9:2784c7660165
next15:5194dd0fdb60
author nkeynes
date Sun Dec 11 05:15:36 2005 +0000 (14 years ago)
permissions -rw-r--r--
last change Add CPU disasembly options to mode dropdown
Split sh4/mem.c into core mem.c and sh4/mem.c
Start adding copyright comments to file headers
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     1 #include <math.h>
     2 #include "dream.h"
     3 #include "sh4core.h"
     4 #include "sh4mmio.h"
     5 #include "mem.h"
     6 #include "intc.h"
     8 struct sh4_registers sh4r;
    10 static int running = 0;
    12 void sh4_init(void)
    13 {
    14     register_io_regions( mmio_list_sh4mmio );
    15     mmu_init();
    16 }
    18 void sh4_reset(void)
    19 {
    20     sh4r.pc    = 0xA0000000;
    21     sh4r.new_pc= 0xA0000002;
    22     sh4r.vbr   = 0x00000000;
    23     sh4r.fpscr = 0x00040001;
    24     sh4r.sr    = 0x700000F0;
    25     sh4r.icount= 0;
    26     /* Everything else is undefined anyway, so don't bother setting it */
    27     intc_reset();
    28 }
    30 void sh4_set_pc( int pc )
    31 {
    32     sh4r.pc = pc;
    33     sh4r.new_pc = pc+2;
    34 }
    36 void sh4_stop(void)
    37 {
    38     running = 0;
    39 }
    41 void sh4_run(void)
    42 {
    43     running = 1;
    44     while( running ) {
    45         sh4_execute_instruction();
    46     }
    47 }
    49 void sh4_runfor(uint32_t count)
    50 {
    51     running = 1;
    52     while( running && count--) {
    53         int pc = sh4r.pc;
    54         sh4_execute_instruction();
    55         /*
    56         if( sh4r.pc == 0x8C0C1636 ||
    57             sh4r.pc == 0x8C0C1634 ) {
    58             WARN( "Branching to %08X from %08X", sh4r.pc, pc );
    59             sh4_stop();
    60             }*/
    61     }
    62 }
    64 int sh4_isrunning(void)
    65 {
    66     return running;
    67 }
    69 void sh4_runto( uint32_t target_pc, uint32_t count )
    70 {
    71     running = 1;
    72     while( running && count--) {
    73         sh4_execute_instruction();
    74         if( sh4r.pc == target_pc ) {
    75             running = 0;
    76             break;
    77         }
    78     }
    79 }
    81 #define UNDEF(ir) do{ ERROR( "Raising exception on undefined instruction at %08x, opcode = %04x", sh4r.pc, ir ); sh4_stop(); RAISE( EXC_ILLEGAL, EXV_ILLEGAL ); }while(0)
    82 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); sh4_stop(); return; }while(0)
    84 #define RAISE( x, v ) do{ \
    85     if( sh4r.vbr == 0 ) { \
    86         ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
    87         sh4_stop(); \
    88     } else { \
    89         sh4r.spc = sh4r.pc + 2; \
    90         sh4r.ssr = sh4_read_sr(); \
    91         sh4r.sgr = sh4r.r[15]; \
    92         MMIO_WRITE(MMU,EXPEVT,x); \
    93         sh4r.pc = sh4r.vbr + v; \
    94         sh4r.new_pc = sh4r.pc + 2; \
    95         sh4_load_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
    96     } \
    97     return; } while(0)
    99 #define MEM_READ_BYTE( addr ) sh4_read_byte(addr)
   100 #define MEM_READ_WORD( addr ) sh4_read_word(addr)
   101 #define MEM_READ_LONG( addr ) sh4_read_long(addr)
   102 #define MEM_WRITE_BYTE( addr, val ) sh4_write_byte(addr, val)
   103 #define MEM_WRITE_WORD( addr, val ) sh4_write_word(addr, val)
   104 #define MEM_WRITE_LONG( addr, val ) sh4_write_long(addr, val)
   106 #define MEM_FP_READ( addr, reg ) if( IS_FPU_DOUBLESIZE() ) { \
   107     ((uint32_t *)FR)[(reg)&0xE0] = sh4_read_long(addr); \
   108     ((uint32_t *)FR)[(reg)|1] = sh4_read_long(addr+4); \
   109 } else ((uint32_t *)FR)[reg] = sh4_read_long(addr)
   111 #define MEM_FP_WRITE( addr, reg ) if( IS_FPU_DOUBLESIZE() ) { \
   112     sh4_write_long( addr, ((uint32_t *)FR)[(reg)&0xE0] ); \
   113     sh4_write_long( addr+4, ((uint32_t *)FR)[(reg)|1] ); \
   114 } else sh4_write_long( addr, ((uint32_t *)FR)[reg] )
   116 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
   118 #define EXC_POWER_RESET  0x000 /* vector special */
   119 #define EXC_MANUAL_RESET 0x020
   120 #define EXC_SLOT_ILLEGAL 0x1A0
   121 #define EXC_ILLEGAL      0x180
   122 #define EXV_ILLEGAL      0x100
   123 #define EXC_TRAP         0x160
   124 #define EXV_TRAP         0x100
   125 #define EXC_FPDISABLE    0x800
   126 #define EXV_FPDISABLE    0x100
   128 #define CHECK( x, c, v ) if( !x ) RAISE( c, v )
   129 #define CHECKPRIV() CHECK( IS_SH4_PRIVMODE(), EXC_ILLEGAL, EXV_ILLEGAL )
   130 #define CHECKFPUEN() CHECK( IS_FPU_ENABLED(), EXC_FPDISABLE, EXV_FPDISABLE )
   131 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); sh4_stop(); return; }
   132 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) { RAISE(EXC_SLOT_ILLEGAL,EXV_ILLEGAL); }
   134 static void sh4_switch_banks( )
   135 {
   136     uint32_t tmp[8];
   138     memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
   139     memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
   140     memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
   141 }
   143 static void sh4_load_sr( uint32_t newval )
   144 {
   145     if( (newval ^ sh4r.sr) & SR_RB )
   146         sh4_switch_banks();
   147     sh4r.sr = newval;
   148     sh4r.t = (newval&SR_T) ? 1 : 0;
   149     sh4r.s = (newval&SR_S) ? 1 : 0;
   150     sh4r.m = (newval&SR_M) ? 1 : 0;
   151     sh4r.q = (newval&SR_Q) ? 1 : 0;
   152     intc_mask_changed();
   153 }
   155 static uint32_t sh4_read_sr( void )
   156 {
   157     /* synchronize sh4r.sr with the various bitflags */
   158     sh4r.sr &= SR_MQSTMASK;
   159     if( sh4r.t ) sh4r.sr |= SR_T;
   160     if( sh4r.s ) sh4r.sr |= SR_S;
   161     if( sh4r.m ) sh4r.sr |= SR_M;
   162     if( sh4r.q ) sh4r.sr |= SR_Q;
   163     return sh4r.sr;
   164 }
   165 /* function for external use */
   166 void sh4_raise_exception( int code, int vector )
   167 {
   168     RAISE(code, vector);
   169 }
   171 static void sh4_accept_interrupt( void )
   172 {
   173     uint32_t code = intc_accept_interrupt();
   174     sh4r.ssr = sh4_read_sr();
   175     sh4r.spc = sh4r.pc;
   176     sh4r.sgr = sh4r.r[15];
   177     sh4_load_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
   178     MMIO_WRITE( MMU, INTEVT, code );
   179     sh4r.pc = sh4r.vbr + 0x600;
   180     sh4r.new_pc = sh4r.pc + 2;
   181     WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
   182 }
   184 void sh4_execute_instruction( void )
   185 {
   186     int pc;
   187     unsigned short ir;
   188     uint32_t tmp;
   189     uint64_t tmpl;
   191 #define R0 sh4r.r[0]
   192 #define FR0 (FR[0])
   193 #define RN(ir) sh4r.r[(ir&0x0F00)>>8]
   194 #define RN_BANK(ir) sh4r.r_bank[(ir&0x0070)>>4]
   195 #define RM(ir) sh4r.r[(ir&0x00F0)>>4]
   196 #define DISP4(ir) (ir&0x000F) /* 4-bit displacements are *NOT* sign-extended */
   197 #define DISP8(ir) (ir&0x00FF)
   198 #define PCDISP8(ir) SIGNEXT8(ir&0x00FF)
   199 #define IMM8(ir) SIGNEXT8(ir&0x00FF)
   200 #define UIMM8(ir) (ir&0x00FF) /* Unsigned immmediate */
   201 #define DISP12(ir) SIGNEXT12(ir&0x0FFF)
   202 #define FVN(ir) ((ir&0x0C00)>>8)
   203 #define FVM(ir) ((ir&0x0300)>>6)
   204 #define FRN(ir) (FR[(ir&0x0F00)>>8])
   205 #define FRM(ir) (FR[(ir&0x00F0)>>4])
   206 #define FRNi(ir) (((uint32_t *)FR)[(ir&0x0F00)>>8])
   207 #define FRMi(ir) (((uint32_t *)FR)[(ir&0x00F0)>>4])
   208 #define DRN(ir) (((double *)FR)[(ir&0x0E00)>>9])
   209 #define DRM(ir) (((double *)FR)[(ir&0x00E0)>>5])
   210 #define DRNi(ir) (((uint64_t *)FR)[(ir&0x0E00)>>9])
   211 #define DRMi(ir) (((uint64_t *)FR)[(ir&0x00E0)>>5])
   212 #define FRNn(ir) ((ir&0x0F00)>>8)
   213 #define FRMn(ir) ((ir&0x00F0)>>4)
   214 #define FPULf   *((float *)&sh4r.fpul)
   215 #define FPULi    (sh4r.fpul)
   217     if( SH4_INT_PENDING() ) 
   218         sh4_accept_interrupt();
   220     pc = sh4r.pc;
   221     ir = MEM_READ_WORD(pc);
   222     sh4r.icount++;
   224     switch( (ir&0xF000)>>12 ) {
   225         case 0: /* 0000nnnnmmmmxxxx */
   226             switch( ir&0x000F ) {
   227                 case 2:
   228                     switch( (ir&0x00F0)>>4 ) {
   229                         case 0: /* STC     SR, Rn */
   230                             CHECKPRIV();
   231                             RN(ir) = sh4_read_sr();
   232                             break;
   233                         case 1: /* STC     GBR, Rn */
   234                             RN(ir) = sh4r.gbr;
   235                             break;
   236                         case 2: /* STC     VBR, Rn */
   237                             CHECKPRIV();
   238                             RN(ir) = sh4r.vbr;
   239                             break;
   240                         case 3: /* STC     SSR, Rn */
   241                             CHECKPRIV();
   242                             RN(ir) = sh4r.ssr;
   243                             break;
   244                         case 4: /* STC     SPC, Rn */
   245                             CHECKPRIV();
   246                             RN(ir) = sh4r.spc;
   247                             break;
   248                         case 8: case 9: case 10: case 11: case 12: case 13:
   249                         case 14: case 15:/* STC     Rm_bank, Rn */
   250                             CHECKPRIV();
   251                             RN(ir) = RN_BANK(ir);
   252                             break;
   253                         default: UNDEF(ir);
   254                     }
   255                     break;
   256                 case 3:
   257                     switch( (ir&0x00F0)>>4 ) {
   258                         case 0: /* BSRF    Rn */
   259                             CHECKDEST( pc + 4 + RN(ir) );
   260                             CHECKSLOTILLEGAL();
   261                             sh4r.in_delay_slot = 1;
   262                             sh4r.pr = sh4r.pc + 4;
   263                             sh4r.pc = sh4r.new_pc;
   264                             sh4r.new_pc = pc + 4 + RN(ir);
   265                             return;
   266                         case 2: /* BRAF    Rn */
   267                             CHECKDEST( pc + 4 + RN(ir) );
   268                             CHECKSLOTILLEGAL();
   269                             sh4r.in_delay_slot = 1;
   270                             sh4r.pc = sh4r.new_pc;
   271                             sh4r.new_pc = pc + 4 + RN(ir);
   272                             return;
   273                         case 8: /* PREF    [Rn] */
   274                             tmp = RN(ir);
   275                             if( (tmp & 0xFC000000) == 0xE0000000 ) {
   276                                 /* Store queue operation */
   277                                 int queue = (tmp&0x20)>>2;
   278                                 int32_t *src = &sh4r.store_queue[queue];
   279                                 uint32_t hi = (MMIO_READ( MMU, (queue == 0 ? QACR0 : QACR1) ) & 0x1C) << 24;
   280                                 uint32_t target = tmp&0x03FFFFE0 | hi;
   281                                 mem_copy_to_sh4( target, src, 32 );
   282                                 WARN( "Executed SQ%c => %08X",
   283                                       (queue == 0 ? '0' : '1'), target );
   284                             }
   285                             break;
   286                         case 9: /* OCBI    [Rn] */
   287                         case 10:/* OCBP    [Rn] */
   288                         case 11:/* OCBWB   [Rn] */
   289                             /* anything? */
   290                             break;
   291                         case 12:/* MOVCA.L R0, [Rn] */
   292                             UNIMP(ir);
   293                         default: UNDEF(ir);
   294                     }
   295                     break;
   296                 case 4: /* MOV.B   Rm, [R0 + Rn] */
   297                     MEM_WRITE_BYTE( R0 + RN(ir), RM(ir) );
   298                     break;
   299                 case 5: /* MOV.W   Rm, [R0 + Rn] */
   300                     MEM_WRITE_WORD( R0 + RN(ir), RM(ir) );
   301                     break;
   302                 case 6: /* MOV.L   Rm, [R0 + Rn] */
   303                     MEM_WRITE_LONG( R0 + RN(ir), RM(ir) );
   304                     break;
   305                 case 7: /* MUL.L   Rm, Rn */
   306                     sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   307                         (RM(ir) * RN(ir));
   308                     break;
   309                 case 8: 
   310                     switch( (ir&0x0FF0)>>4 ) {
   311                         case 0: /* CLRT    */
   312                             sh4r.t = 0;
   313                             break;
   314                         case 1: /* SETT    */
   315                             sh4r.t = 1;
   316                             break;
   317                         case 2: /* CLRMAC  */
   318                             sh4r.mac = 0;
   319                             break;
   320                         case 3: /* LDTLB   */
   321                             break;
   322                         case 4: /* CLRS    */
   323                             sh4r.s = 0;
   324                             break;
   325                         case 5: /* SETS    */
   326                             sh4r.s = 1;
   327                             break;
   328                         default: UNDEF(ir);
   329                     }
   330                     break;
   331                 case 9: 
   332                     if( (ir&0x00F0) == 0x20 ) /* MOVT    Rn */
   333                         RN(ir) = sh4r.t;
   334                     else if( ir == 0x0019 ) /* DIV0U   */
   335                         sh4r.m = sh4r.q = sh4r.t = 0;
   336                     else if( ir == 0x0009 )
   337                         /* NOP     */;
   338                     else UNDEF(ir);
   339                     break;
   340                 case 10:
   341                     switch( (ir&0x00F0) >> 4 ) {
   342                         case 0: /* STS     MACH, Rn */
   343                             RN(ir) = sh4r.mac >> 32;
   344                             break;
   345                         case 1: /* STS     MACL, Rn */
   346                             RN(ir) = (uint32_t)sh4r.mac;
   347                             break;
   348                         case 2: /* STS     PR, Rn */
   349                             RN(ir) = sh4r.pr;
   350                             break;
   351                         case 3: /* STC     SGR, Rn */
   352                             CHECKPRIV();
   353                             RN(ir) = sh4r.sgr;
   354                             break;
   355                         case 5:/* STS      FPUL, Rn */
   356                             RN(ir) = sh4r.fpul;
   357                             break;
   358                         case 6: /* STS     FPSCR, Rn */
   359                             RN(ir) = sh4r.fpscr;
   360                             break;
   361                         case 15:/* STC     DBR, Rn */
   362                             CHECKPRIV();
   363                             RN(ir) = sh4r.dbr;
   364                             break;
   365                         default: UNDEF(ir);
   366                     }
   367                     break;
   368                 case 11:
   369                     switch( (ir&0x0FF0)>>4 ) {
   370                         case 0: /* RTS     */
   371                             CHECKDEST( sh4r.pr );
   372                             CHECKSLOTILLEGAL();
   373                             sh4r.in_delay_slot = 1;
   374                             sh4r.pc = sh4r.new_pc;
   375                             sh4r.new_pc = sh4r.pr;
   376                             return;
   377                         case 1: /* SLEEP   */
   378                             running = 0;
   379                             break;
   380                         case 2: /* RTE     */
   381                             CHECKPRIV();
   382                             CHECKDEST( sh4r.spc );
   383                             CHECKSLOTILLEGAL();
   384                             sh4r.in_delay_slot = 1;
   385                             sh4r.pc = sh4r.new_pc;
   386                             sh4r.new_pc = sh4r.spc;
   387                             sh4_load_sr( sh4r.ssr );
   388                             WARN( "RTE => %08X", sh4r.new_pc );
   389                             return;
   390                         default:UNDEF(ir);
   391                     }
   392                     break;
   393                 case 12:/* MOV.B   [R0+R%d], R%d */
   394                     RN(ir) = MEM_READ_BYTE( R0 + RM(ir) );
   395                     break;
   396                 case 13:/* MOV.W   [R0+R%d], R%d */
   397                     RN(ir) = MEM_READ_WORD( R0 + RM(ir) );
   398                     break;
   399                 case 14:/* MOV.L   [R0+R%d], R%d */
   400                     RN(ir) = MEM_READ_LONG( R0 + RM(ir) );
   401                     break;
   402                 case 15:/* MAC.L   [Rm++], [Rn++] */
   403                     tmpl = ( SIGNEXT32(MEM_READ_LONG(RM(ir))) *
   404                                   SIGNEXT32(MEM_READ_LONG(RN(ir))) );
   405                     if( sh4r.s ) {
   406                         /* 48-bit Saturation. Yuch */
   407                         tmpl += SIGNEXT48(sh4r.mac);
   408                         if( tmpl < 0xFFFF800000000000LL )
   409                             tmpl = 0xFFFF800000000000LL;
   410                         else if( tmpl > 0x00007FFFFFFFFFFFLL )
   411                             tmpl = 0x00007FFFFFFFFFFFLL;
   412                         sh4r.mac = (sh4r.mac&0xFFFF000000000000LL) |
   413                             (tmpl&0x0000FFFFFFFFFFFFLL);
   414                     } else sh4r.mac = tmpl;
   416                     RM(ir) += 4;
   417                     RN(ir) += 4;
   419                     break;
   420                 default: UNDEF(ir);
   421             }
   422             break;
   423         case 1: /* 0001nnnnmmmmdddd */
   424             /* MOV.L   Rm, [Rn + disp4*4] */
   425             MEM_WRITE_LONG( RN(ir) + (DISP4(ir)<<2), RM(ir) );
   426             break;
   427         case 2: /* 0010nnnnmmmmxxxx */
   428             switch( ir&0x000F ) {
   429                 case 0: /* MOV.B   Rm, [Rn] */
   430                     MEM_WRITE_BYTE( RN(ir), RM(ir) );
   431                     break;
   432                 case 1: /* MOV.W   Rm, [Rn] */
   433                     MEM_WRITE_WORD( RN(ir), RM(ir) );
   434                     break;
   435                 case 2: /* MOV.L   Rm, [Rn] */
   436                     MEM_WRITE_LONG( RN(ir), RM(ir) );
   437                     break;
   438                 case 3: UNDEF(ir);
   439                     break;
   440                 case 4: /* MOV.B   Rm, [--Rn] */
   441                     RN(ir) --;
   442                     MEM_WRITE_BYTE( RN(ir), RM(ir) );
   443                     break;
   444                 case 5: /* MOV.W   Rm, [--Rn] */
   445                     RN(ir) -= 2;
   446                     MEM_WRITE_WORD( RN(ir), RM(ir) );
   447                     break;
   448                 case 6: /* MOV.L   Rm, [--Rn] */
   449                     RN(ir) -= 4;
   450                     MEM_WRITE_LONG( RN(ir), RM(ir) );
   451                     break;
   452                 case 7: /* DIV0S   Rm, Rn */
   453                     sh4r.q = RN(ir)>>31;
   454                     sh4r.m = RM(ir)>>31;
   455                     sh4r.t = sh4r.q ^ sh4r.m;
   456                     break;
   457                 case 8: /* TST     Rm, Rn */
   458                     sh4r.t = (RN(ir)&RM(ir) ? 0 : 1);
   459                     break;
   460                 case 9: /* AND     Rm, Rn */
   461                     RN(ir) &= RM(ir);
   462                     break;
   463                 case 10:/* XOR     Rm, Rn */
   464                     RN(ir) ^= RM(ir);
   465                     break;
   466                 case 11:/* OR      Rm, Rn */
   467                     RN(ir) |= RM(ir);
   468                     break;
   469                 case 12:/* CMP/STR Rm, Rn */
   470                     /* set T = 1 if any byte in RM & RN is the same */
   471                     tmp = RM(ir) ^ RN(ir);
   472                     sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
   473                               (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
   474                     break;
   475                 case 13:/* XTRCT   Rm, Rn */
   476                     RN(ir) = (RN(ir)>>16) | (RM(ir)<<16);
   477                     break;
   478                 case 14:/* MULU.W  Rm, Rn */
   479                     sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   480                         (uint32_t)((RM(ir)&0xFFFF) * (RN(ir)&0xFFFF));
   481                     break;
   482                 case 15:/* MULS.W  Rm, Rn */
   483                     sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   484                         (uint32_t)(SIGNEXT32(RM(ir)&0xFFFF) * SIGNEXT32(RN(ir)&0xFFFF));
   485                     break;
   486             }
   487             break;
   488         case 3: /* 0011nnnnmmmmxxxx */
   489             switch( ir&0x000F ) {
   490                 case 0: /* CMP/EQ  Rm, Rn */
   491                     sh4r.t = ( RM(ir) == RN(ir) ? 1 : 0 );
   492                     break;
   493                 case 2: /* CMP/HS  Rm, Rn */
   494                     sh4r.t = ( RN(ir) >= RM(ir) ? 1 : 0 );
   495                     break;
   496                 case 3: /* CMP/GE  Rm, Rn */
   497                     sh4r.t = ( ((int32_t)RN(ir)) >= ((int32_t)RM(ir)) ? 1 : 0 );
   498                     break;
   499                 case 4: { /* DIV1    Rm, Rn */
   500                     /* This is just from the sh4p manual with some
   501                      * simplifications (someone want to check it's correct? :)
   502                      * Why they couldn't just provide a real DIV instruction...
   503                      * Please oh please let the translator batch these things
   504                      * up into a single DIV... */
   505                     uint32_t tmp0, tmp1, tmp2, dir;
   507                     dir = sh4r.q ^ sh4r.m;
   508                     sh4r.q = (RN(ir) >> 31);
   509                     tmp2 = RM(ir);
   510                     RN(ir) = (RN(ir) << 1) | sh4r.t;
   511                     tmp0 = RN(ir);
   512                     if( dir ) {
   513                         RN(ir) += tmp2;
   514                         tmp1 = (RN(ir)<tmp0 ? 1 : 0 );
   515                     } else {
   516                         RN(ir) -= tmp2;
   517                         tmp1 = (RN(ir)>tmp0 ? 1 : 0 );
   518                     }
   519                     sh4r.q ^= sh4r.m ^ tmp1;
   520                     sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
   521                     break; }
   522                 case 5: /* DMULU.L Rm, Rn */
   523                     sh4r.mac = ((uint64_t)RM(ir)) * ((uint64_t)RN(ir));
   524                     break;
   525                 case 6: /* CMP/HI  Rm, Rn */
   526                     sh4r.t = ( RN(ir) > RM(ir) ? 1 : 0 );
   527                     break;
   528                 case 7: /* CMP/GT  Rm, Rn */
   529                     sh4r.t = ( ((int32_t)RN(ir)) > ((int32_t)RM(ir)) ? 1 : 0 );
   530                     break;
   531                 case 8: /* SUB     Rm, Rn */
   532                     RN(ir) -= RM(ir);
   533                     break;
   534                 case 10:/* SUBC    Rm, Rn */
   535                     tmp = RN(ir);
   536                     RN(ir) = RN(ir) - RM(ir) - sh4r.t;
   537                     sh4r.t = (RN(ir) > tmp || (RN(ir) == tmp && sh4r.t == 1));
   538                     break;
   539                 case 11:/* SUBV    Rm, Rn */
   540                     UNIMP(ir);
   541                     break;
   542                 case 12:/* ADD     Rm, Rn */
   543                     RN(ir) += RM(ir);
   544                     break;
   545                 case 13:/* DMULS.L Rm, Rn */
   546                     sh4r.mac = SIGNEXT32(RM(ir)) * SIGNEXT32(RN(ir));
   547                     break;
   548                 case 14:/* ADDC    Rm, Rn */
   549                     tmp = RN(ir);
   550                     RN(ir) += RM(ir) + sh4r.t;
   551                     sh4r.t = ( RN(ir) < tmp || (RN(ir) == tmp && sh4r.t != 0) ? 1 : 0 );
   552                     break;
   553                 case 15:/* ADDV    Rm, Rn */
   554                     UNIMP(ir);
   555                     break;
   556                 default: UNDEF(ir);
   557             }
   558             break;
   559         case 4: /* 0100nnnnxxxxxxxx */
   560             switch( ir&0x00FF ) {
   561                 case 0x00: /* SHLL    Rn */
   562                     sh4r.t = RN(ir) >> 31;
   563                     RN(ir) <<= 1;
   564                     break;
   565                 case 0x01: /* SHLR    Rn */
   566                     sh4r.t = RN(ir) & 0x00000001;
   567                     RN(ir) >>= 1;
   568                     break;
   569                 case 0x02: /* STS.L   MACH, [--Rn] */
   570                     RN(ir) -= 4;
   571                     MEM_WRITE_LONG( RN(ir), (sh4r.mac>>32) );
   572                     break;
   573                 case 0x03: /* STC.L   SR, [--Rn] */
   574                     CHECKPRIV();
   575                     RN(ir) -= 4;
   576                     MEM_WRITE_LONG( RN(ir), sh4_read_sr() );
   577                     break;
   578                 case 0x04: /* ROTL    Rn */
   579                     sh4r.t = RN(ir) >> 31;
   580                     RN(ir) <<= 1;
   581                     RN(ir) |= sh4r.t;
   582                     break;
   583                 case 0x05: /* ROTR    Rn */
   584                     sh4r.t = RN(ir) & 0x00000001;
   585                     RN(ir) >>= 1;
   586                     RN(ir) |= (sh4r.t << 31);
   587                     break;
   588                 case 0x06: /* LDS.L   [Rn++], MACH */
   589                     sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
   590                         (((uint64_t)MEM_READ_LONG(RN(ir)))<<32);
   591                     RN(ir) += 4;
   592                     break;
   593                 case 0x07: /* LDC.L   [Rn++], SR */
   594                     CHECKPRIV();
   595                     sh4_load_sr( MEM_READ_LONG(RN(ir)) );
   596                     RN(ir) +=4;
   597                     break;
   598                 case 0x08: /* SHLL2   Rn */
   599                     RN(ir) <<= 2;
   600                     break;
   601                 case 0x09: /* SHLR2   Rn */
   602                     RN(ir) >>= 2;
   603                     break;
   604                 case 0x0A: /* LDS     Rn, MACH */
   605                     sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
   606                         (((uint64_t)RN(ir))<<32);
   607                     break;
   608                 case 0x0B: /* JSR     [Rn] */
   609                     CHECKDEST( RN(ir) );
   610                     CHECKSLOTILLEGAL();
   611                     sh4r.in_delay_slot = 1;
   612                     sh4r.pc = sh4r.new_pc;
   613                     sh4r.new_pc = RN(ir);
   614                     sh4r.pr = pc + 4;
   615                     return;
   616                 case 0x0E: /* LDC     Rn, SR */
   617                     CHECKPRIV();
   618                     sh4_load_sr( RN(ir) );
   619                     break;
   620                 case 0x10: /* DT      Rn */
   621                     RN(ir) --;
   622                     sh4r.t = ( RN(ir) == 0 ? 1 : 0 );
   623                     break;
   624                 case 0x11: /* CMP/PZ  Rn */
   625                     sh4r.t = ( ((int32_t)RN(ir)) >= 0 ? 1 : 0 );
   626                     break;
   627                 case 0x12: /* STS.L   MACL, [--Rn] */
   628                     RN(ir) -= 4;
   629                     MEM_WRITE_LONG( RN(ir), (uint32_t)sh4r.mac );
   630                     break;
   631                 case 0x13: /* STC.L   GBR, [--Rn] */
   632                     RN(ir) -= 4;
   633                     MEM_WRITE_LONG( RN(ir), sh4r.gbr );
   634                     break;
   635                 case 0x15: /* CMP/PL  Rn */
   636                     sh4r.t = ( ((int32_t)RN(ir)) > 0 ? 1 : 0 );
   637                     break;
   638                 case 0x16: /* LDS.L   [Rn++], MACL */
   639                     sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
   640                         (uint64_t)((uint32_t)MEM_READ_LONG(RN(ir)));
   641                     RN(ir) += 4;
   642                     break;
   643                 case 0x17: /* LDC.L   [Rn++], GBR */
   644                     sh4r.gbr = MEM_READ_LONG(RN(ir));
   645                     RN(ir) +=4;
   646                     break;
   647                 case 0x18: /* SHLL8   Rn */
   648                     RN(ir) <<= 8;
   649                     break;
   650                 case 0x19: /* SHLR8   Rn */
   651                     RN(ir) >>= 8;
   652                     break;
   653                 case 0x1A: /* LDS     Rn, MACL */
   654                     sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
   655                         (uint64_t)((uint32_t)(RN(ir)));
   656                     break;
   657                 case 0x1B: /* TAS.B   [Rn] */
   658                     tmp = MEM_READ_BYTE( RN(ir) );
   659                     sh4r.t = ( tmp == 0 ? 1 : 0 );
   660                     MEM_WRITE_BYTE( RN(ir), tmp | 0x80 );
   661                     break;
   662                 case 0x1E: /* LDC     Rn, GBR */
   663                     sh4r.gbr = RN(ir);
   664                     break;
   665                 case 0x20: /* SHAL    Rn */
   666                     sh4r.t = RN(ir) >> 31;
   667                     RN(ir) <<= 1;
   668                     break;
   669                 case 0x21: /* SHAR    Rn */
   670                     sh4r.t = RN(ir) & 0x00000001;
   671                     RN(ir) = ((int32_t)RN(ir)) >> 1;
   672                     break;
   673                 case 0x22: /* STS.L   PR, [--Rn] */
   674                     RN(ir) -= 4;
   675                     MEM_WRITE_LONG( RN(ir), sh4r.pr );
   676                     break;
   677                 case 0x23: /* STC.L   VBR, [--Rn] */
   678                     CHECKPRIV();
   679                     RN(ir) -= 4;
   680                     MEM_WRITE_LONG( RN(ir), sh4r.vbr );
   681                     break;
   682                 case 0x24: /* ROTCL   Rn */
   683                     tmp = RN(ir) >> 31;
   684                     RN(ir) <<= 1;
   685                     RN(ir) |= sh4r.t;
   686                     sh4r.t = tmp;
   687                     break;
   688                 case 0x25: /* ROTCR   Rn */
   689                     tmp = RN(ir) & 0x00000001;
   690                     RN(ir) >>= 1;
   691                     RN(ir) |= (sh4r.t << 31 );
   692                     sh4r.t = tmp;
   693                     break;
   694                 case 0x26: /* LDS.L   [Rn++], PR */
   695                     sh4r.pr = MEM_READ_LONG( RN(ir) );
   696                     RN(ir) += 4;
   697                     break;
   698                 case 0x27: /* LDC.L   [Rn++], VBR */
   699                     CHECKPRIV();
   700                     sh4r.vbr = MEM_READ_LONG(RN(ir));
   701                     RN(ir) +=4;
   702                     break;
   703                 case 0x28: /* SHLL16  Rn */
   704                     RN(ir) <<= 16;
   705                     break;
   706                 case 0x29: /* SHLR16  Rn */
   707                     RN(ir) >>= 16;
   708                     break;
   709                 case 0x2A: /* LDS     Rn, PR */
   710                     sh4r.pr = RN(ir);
   711                     break;
   712                 case 0x2B: /* JMP     [Rn] */
   713                     CHECKDEST( RN(ir) );
   714                     CHECKSLOTILLEGAL();
   715                     sh4r.in_delay_slot = 1;
   716                     sh4r.pc = sh4r.new_pc;
   717                     sh4r.new_pc = RN(ir);
   718                     return;
   719                 case 0x2E: /* LDC     Rn, VBR */
   720                     CHECKPRIV();
   721                     sh4r.vbr = RN(ir);
   722                     break;
   723                 case 0x32: /* STC.L   SGR, [--Rn] */
   724                     CHECKPRIV();
   725                     RN(ir) -= 4;
   726                     MEM_WRITE_LONG( RN(ir), sh4r.sgr );
   727                     break;
   728                 case 0x33: /* STC.L   SSR, [--Rn] */
   729                     CHECKPRIV();
   730                     RN(ir) -= 4;
   731                     MEM_WRITE_LONG( RN(ir), sh4r.ssr );
   732                     break;
   733                 case 0x37: /* LDC.L   [Rn++], SSR */
   734                     CHECKPRIV();
   735                     sh4r.ssr = MEM_READ_LONG(RN(ir));
   736                     RN(ir) +=4;
   737                     break;
   738                 case 0x3E: /* LDC     Rn, SSR */
   739                     CHECKPRIV();
   740                     sh4r.ssr = RN(ir);
   741                     break;
   742                 case 0x43: /* STC.L   SPC, [--Rn] */
   743                     CHECKPRIV();
   744                     RN(ir) -= 4;
   745                     MEM_WRITE_LONG( RN(ir), sh4r.spc );
   746                     break;
   747                 case 0x47: /* LDC.L   [Rn++], SPC */
   748                     CHECKPRIV();
   749                     sh4r.spc = MEM_READ_LONG(RN(ir));
   750                     RN(ir) +=4;
   751                     break;
   752                 case 0x4E: /* LDC     Rn, SPC */
   753                     CHECKPRIV();
   754                     sh4r.spc = RN(ir);
   755                     break;
   756                 case 0x52: /* STS.L   FPUL, [--Rn] */
   757                     RN(ir) -= 4;
   758                     MEM_WRITE_LONG( RN(ir), sh4r.fpul );
   759                     break;
   760                 case 0x56: /* LDS.L   [Rn++], FPUL */
   761                     sh4r.fpul = MEM_READ_LONG(RN(ir));
   762                     RN(ir) +=4;
   763                     break;
   764                 case 0x5A: /* LDS     Rn, FPUL */
   765                     sh4r.fpul = RN(ir);
   766                     break;
   767                 case 0x62: /* STS.L   FPSCR, [--Rn] */
   768                     RN(ir) -= 4;
   769                     MEM_WRITE_LONG( RN(ir), sh4r.fpscr );
   770                     break;
   771                 case 0x66: /* LDS.L   [Rn++], FPSCR */
   772                     sh4r.fpscr = MEM_READ_LONG(RN(ir));
   773                     RN(ir) +=4;
   774                     break;
   775                 case 0x6A: /* LDS     Rn, FPSCR */
   776                     sh4r.fpscr = RN(ir);
   777                     break;
   778                 case 0xF2: /* STC.L   DBR, [--Rn] */
   779                     CHECKPRIV();
   780                     RN(ir) -= 4;
   781                     MEM_WRITE_LONG( RN(ir), sh4r.dbr );
   782                     break;
   783                 case 0xF6: /* LDC.L   [Rn++], DBR */
   784                     CHECKPRIV();
   785                     sh4r.dbr = MEM_READ_LONG(RN(ir));
   786                     RN(ir) +=4;
   787                     break;
   788                 case 0xFA: /* LDC     Rn, DBR */
   789                     CHECKPRIV();
   790                     sh4r.dbr = RN(ir);
   791                     break;
   792                 case 0x83: case 0x93: case 0xA3: case 0xB3: case 0xC3:
   793                 case 0xD3: case 0xE3: case 0xF3: /* STC.L   Rn_BANK, [--Rn] */
   794                     CHECKPRIV();
   795                     RN(ir) -= 4;
   796                     MEM_WRITE_LONG( RN(ir), RN_BANK(ir) );
   797                     break;
   798                 case 0x87: case 0x97: case 0xA7: case 0xB7: case 0xC7:
   799                 case 0xD7: case 0xE7: case 0xF7: /* LDC.L   [Rn++], Rn_BANK */
   800                     CHECKPRIV();
   801                     RN_BANK(ir) = MEM_READ_LONG( RN(ir) );
   802                     RN(ir) += 4;
   803                     break;
   804                 case 0x8E: case 0x9E: case 0xAE: case 0xBE: case 0xCE:
   805                 case 0xDE: case 0xEE: case 0xFE: /* LDC     Rm, Rn_BANK */
   806                     CHECKPRIV();
   807                     RN_BANK(ir) = RM(ir);
   808                     break;
   809                 default:
   810                     if( (ir&0x000F) == 0x0F ) {
   811                         /* MAC.W   [Rm++], [Rn++] */
   812                         tmp = SIGNEXT16(MEM_READ_WORD(RM(ir))) *
   813                             SIGNEXT16(MEM_READ_WORD(RN(ir)));
   814                         if( sh4r.s ) {
   815                             /* FIXME */
   816                             UNIMP(ir);
   817                         } else sh4r.mac += SIGNEXT32(tmp);
   818                         RM(ir) += 2;
   819                         RN(ir) += 2;
   820                     } else if( (ir&0x000F) == 0x0C ) {
   821                         /* SHAD    Rm, Rn */
   822                         tmp = RM(ir);
   823                         if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);
   824                         else if( (tmp & 0x1F) == 0 )  
   825 			  RN(ir) = ((int32_t)RN(ir)) >> 31;
   826                         else 
   827 			  RN(ir) = ((int32_t)RN(ir)) >> (((~RM(ir)) & 0x1F)+1);
   828                     } else if( (ir&0x000F) == 0x0D ) {
   829                         /* SHLD    Rm, Rn */
   830                         tmp = RM(ir);
   831                         if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);
   832                         else if( (tmp & 0x1F) == 0 ) RN(ir) = 0;
   833                         else RN(ir) >>= (((~tmp) & 0x1F)+1);
   834                     } else UNDEF(ir);
   835             }
   836             break;
   837         case 5: /* 0101nnnnmmmmdddd */
   838             /* MOV.L   [Rm + disp4*4], Rn */
   839             RN(ir) = MEM_READ_LONG( RM(ir) + (DISP4(ir)<<2) );
   840             break;
   841         case 6: /* 0110xxxxxxxxxxxx */
   842             switch( ir&0x000f ) {
   843                 case 0: /* MOV.B   [Rm], Rn */
   844                     RN(ir) = MEM_READ_BYTE( RM(ir) );
   845                     break;
   846                 case 1: /* MOV.W   [Rm], Rn */
   847                     RN(ir) = MEM_READ_WORD( RM(ir) );
   848                     break;
   849                 case 2: /* MOV.L   [Rm], Rn */
   850                     RN(ir) = MEM_READ_LONG( RM(ir) );
   851                     break;
   852                 case 3: /* MOV     Rm, Rn */
   853                     RN(ir) = RM(ir);
   854                     break;
   855                 case 4: /* MOV.B   [Rm++], Rn */
   856                     RN(ir) = MEM_READ_BYTE( RM(ir) );
   857                     RM(ir) ++;
   858                     break;
   859                 case 5: /* MOV.W   [Rm++], Rn */
   860                     RN(ir) = MEM_READ_WORD( RM(ir) );
   861                     RM(ir) += 2;
   862                     break;
   863                 case 6: /* MOV.L   [Rm++], Rn */
   864                     RN(ir) = MEM_READ_LONG( RM(ir) );
   865                     RM(ir) += 4;
   866                     break;
   867                 case 7: /* NOT     Rm, Rn */
   868                     RN(ir) = ~RM(ir);
   869                     break;
   870                 case 8: /* SWAP.B  Rm, Rn */
   871                     RN(ir) = (RM(ir)&0xFFFF0000) | ((RM(ir)&0x0000FF00)>>8) |
   872                         ((RM(ir)&0x000000FF)<<8);
   873                     break;
   874                 case 9: /* SWAP.W  Rm, Rn */
   875                     RN(ir) = (RM(ir)>>16) | (RM(ir)<<16);
   876                     break;
   877                 case 10:/* NEGC    Rm, Rn */
   878                     tmp = 0 - RM(ir);
   879                     RN(ir) = tmp - sh4r.t;
   880                     sh4r.t = ( 0<tmp || tmp<RN(ir) ? 1 : 0 );
   881                     break;
   882                 case 11:/* NEG     Rm, Rn */
   883                     RN(ir) = 0 - RM(ir);
   884                     break;
   885                 case 12:/* EXTU.B  Rm, Rn */
   886                     RN(ir) = RM(ir)&0x000000FF;
   887                     break;
   888                 case 13:/* EXTU.W  Rm, Rn */
   889                     RN(ir) = RM(ir)&0x0000FFFF;
   890                     break;
   891                 case 14:/* EXTS.B  Rm, Rn */
   892                     RN(ir) = SIGNEXT8( RM(ir)&0x000000FF );
   893                     break;
   894                 case 15:/* EXTS.W  Rm, Rn */
   895                     RN(ir) = SIGNEXT16( RM(ir)&0x0000FFFF );
   896                     break;
   897             }
   898             break;
   899         case 7: /* 0111nnnniiiiiiii */
   900             /* ADD    imm8, Rn */
   901             RN(ir) += IMM8(ir);
   902             break;
   903         case 8: /* 1000xxxxxxxxxxxx */
   904             switch( (ir&0x0F00) >> 8 ) {
   905                 case 0: /* MOV.B   R0, [Rm + disp4] */
   906                     MEM_WRITE_BYTE( RM(ir) + DISP4(ir), R0 );
   907                     break;
   908                 case 1: /* MOV.W   R0, [Rm + disp4*2] */
   909                     MEM_WRITE_WORD( RM(ir) + (DISP4(ir)<<1), R0 );
   910                     break;
   911                 case 4: /* MOV.B   [Rm + disp4], R0 */
   912                     R0 = MEM_READ_BYTE( RM(ir) + DISP4(ir) );
   913                     break;
   914                 case 5: /* MOV.W   [Rm + disp4*2], R0 */
   915                     R0 = MEM_READ_WORD( RM(ir) + (DISP4(ir)<<1) );
   916                     break;
   917                 case 8: /* CMP/EQ  imm, R0 */
   918                     sh4r.t = ( R0 == IMM8(ir) ? 1 : 0 );
   919                     break;
   920                 case 9: /* BT      disp8 */
   921                     CHECKSLOTILLEGAL()
   922                     if( sh4r.t ) {
   923                         CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
   924                         sh4r.pc += (PCDISP8(ir)<<1) + 4;
   925                         sh4r.new_pc = sh4r.pc + 2;
   926                         return;
   927                     }
   928                     break;
   929                 case 11:/* BF      disp8 */
   930                     CHECKSLOTILLEGAL()
   931                     if( !sh4r.t ) {
   932                         CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
   933                         sh4r.pc += (PCDISP8(ir)<<1) + 4;
   934                         sh4r.new_pc = sh4r.pc + 2;
   935                         return;
   936                     }
   937                     break;
   938                 case 13:/* BT/S    disp8 */
   939                     CHECKSLOTILLEGAL()
   940                     if( sh4r.t ) {
   941                         CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
   942                         sh4r.in_delay_slot = 1;
   943                         sh4r.pc = sh4r.new_pc;
   944                         sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;
   945                         sh4r.in_delay_slot = 1;
   946                         return;
   947                     }
   948                     break;
   949                 case 15:/* BF/S    disp8 */
   950                     CHECKSLOTILLEGAL()
   951                     if( !sh4r.t ) {
   952                         CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
   953                         sh4r.in_delay_slot = 1;
   954                         sh4r.pc = sh4r.new_pc;
   955                         sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;
   956                         return;
   957                     }
   958                     break;
   959                 default: UNDEF(ir);
   960             }
   961             break;
   962         case 9: /* 1001xxxxxxxxxxxx */
   963             /* MOV.W   [disp8*2 + pc + 4], Rn */
   964             RN(ir) = MEM_READ_WORD( pc + 4 + (DISP8(ir)<<1) );
   965             break;
   966         case 10:/* 1010dddddddddddd */
   967             /* BRA     disp12 */
   968             CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 )
   969             CHECKSLOTILLEGAL()
   970             sh4r.in_delay_slot = 1;
   971             sh4r.pc = sh4r.new_pc;
   972             sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);
   973             return;
   974         case 11:/* 1011dddddddddddd */
   975             /* BSR     disp12 */
   976             CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 )
   977             CHECKSLOTILLEGAL()
   978             sh4r.in_delay_slot = 1;
   979             sh4r.pr = pc + 4;
   980             sh4r.pc = sh4r.new_pc;
   981             sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);
   982             return;
   983         case 12:/* 1100xxxxdddddddd */
   984         switch( (ir&0x0F00)>>8 ) {
   985                 case 0: /* MOV.B  R0, [GBR + disp8] */
   986                     MEM_WRITE_BYTE( sh4r.gbr + DISP8(ir), R0 );
   987                     break;
   988                 case 1: /* MOV.W  R0, [GBR + disp8*2] */
   989                     MEM_WRITE_WORD( sh4r.gbr + (DISP8(ir)<<1), R0 );
   990                     break;
   991                 case  2: /*MOV.L   R0, [GBR + disp8*4] */
   992                     MEM_WRITE_LONG( sh4r.gbr + (DISP8(ir)<<2), R0 );
   993                     break;
   994                 case 3: /* TRAPA   imm8 */
   995                     CHECKSLOTILLEGAL()
   996                     sh4r.in_delay_slot = 1;
   997                     MMIO_WRITE( MMU, TRA, UIMM8(ir) );
   998                     sh4r.pc = sh4r.new_pc;  /* RAISE ends the instruction */
   999                     sh4r.new_pc += 2;
  1000                     RAISE( EXC_TRAP, EXV_TRAP );
  1001                     break;
  1002                 case 4: /* MOV.B   [GBR + disp8], R0 */
  1003                     R0 = MEM_READ_BYTE( sh4r.gbr + DISP8(ir) );
  1004                     break;
  1005                 case 5: /* MOV.W   [GBR + disp8*2], R0 */
  1006                     R0 = MEM_READ_WORD( sh4r.gbr + (DISP8(ir)<<1) );
  1007                     break;
  1008                 case 6: /* MOV.L   [GBR + disp8*4], R0 */
  1009                     R0 = MEM_READ_LONG( sh4r.gbr + (DISP8(ir)<<2) );
  1010                     break;
  1011                 case 7: /* MOVA    disp8 + pc&~3 + 4, R0 */
  1012                     R0 = (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4;
  1013                     break;
  1014                 case 8: /* TST     imm8, R0 */
  1015                     sh4r.t = (R0 & UIMM8(ir) ? 0 : 1);
  1016                     break;
  1017                 case 9: /* AND     imm8, R0 */
  1018                     R0 &= UIMM8(ir);
  1019                     break;
  1020                 case 10:/* XOR     imm8, R0 */
  1021                     R0 ^= UIMM8(ir);
  1022                     break;
  1023                 case 11:/* OR      imm8, R0 */
  1024                     R0 |= UIMM8(ir);
  1025                     break;
  1026                 case 12:/* TST.B   imm8, [R0+GBR] */
  1027                     sh4r.t = ( MEM_READ_BYTE(R0 + sh4r.gbr) & UIMM8(ir) ? 0 : 1 );
  1028                     break;
  1029                 case 13:/* AND.B   imm8, [R0+GBR] */
  1030                     MEM_WRITE_BYTE( R0 + sh4r.gbr,
  1031                                     UIMM8(ir) & MEM_READ_BYTE(R0 + sh4r.gbr) );
  1032                     break;
  1033                 case 14:/* XOR.B   imm8, [R0+GBR] */
  1034                     MEM_WRITE_BYTE( R0 + sh4r.gbr,
  1035                                     UIMM8(ir) ^ MEM_READ_BYTE(R0 + sh4r.gbr) );
  1036                     break;
  1037                 case 15:/* OR.B    imm8, [R0+GBR] */
  1038                     MEM_WRITE_BYTE( R0 + sh4r.gbr,
  1039                                     UIMM8(ir) | MEM_READ_BYTE(R0 + sh4r.gbr) );
  1040                     break;
  1042             break;
  1043         case 13:/* 1101nnnndddddddd */
  1044             /* MOV.L   [disp8*4 + pc&~3 + 4], Rn */
  1045             RN(ir) = MEM_READ_LONG( (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4 );
  1046             break;
  1047         case 14:/* 1110nnnniiiiiiii */
  1048             /* MOV     imm8, Rn */
  1049             RN(ir) = IMM8(ir);
  1050             break;
  1051         case 15:/* 1111xxxxxxxxxxxx */
  1052             CHECKFPUEN();
  1053             switch( ir&0x000F ) {
  1054                 case 0: /* FADD    FRm, FRn */
  1055                     FRN(ir) += FRM(ir);
  1056                     break;
  1057                 case 1: /* FSUB    FRm, FRn */
  1058                     FRN(ir) -= FRM(ir);
  1059                     break;
  1060                 case 2: /* FMUL    FRm, FRn */
  1061                     FRN(ir) = FRN(ir) * FRM(ir);
  1062                     break;
  1063                 case 3: /* FDIV    FRm, FRn */
  1064                     FRN(ir) = FRN(ir) / FRM(ir);
  1065                     break;
  1066                 case 4: /* FCMP/EQ FRm, FRn */
  1067                     sh4r.t = ( FRN(ir) == FRM(ir) ? 1 : 0 );
  1068                     break;
  1069                 case 5: /* FCMP/GT FRm, FRn */
  1070                     sh4r.t = ( FRN(ir) > FRM(ir) ? 1 : 0 );
  1071                     break;
  1072                 case 6: /* FMOV.S  [Rm+R0], FRn */
  1073                     MEM_FP_READ( RM(ir) + R0, FRNn(ir) );
  1074                     break;
  1075                 case 7: /* FMOV.S  FRm, [Rn+R0] */
  1076                     MEM_FP_WRITE( RN(ir) + R0, FRMn(ir) );
  1077                     break;
  1078                 case 8: /* FMOV.S  [Rm], FRn */
  1079                     MEM_FP_READ( RM(ir), FRNn(ir) );
  1080                     break;
  1081                 case 9: /* FMOV.S  [Rm++], FRn */
  1082                     MEM_FP_READ( RM(ir), FRNn(ir) );
  1083                     RM(ir) += FP_WIDTH;
  1084                     break;
  1085                 case 10:/* FMOV.S  FRm, [Rn] */
  1086                     MEM_FP_WRITE( RN(ir), FRMn(ir) );
  1087                     break;
  1088                 case 11:/* FMOV.S  FRm, [--Rn] */
  1089                     RN(ir) -= FP_WIDTH;
  1090                     MEM_FP_WRITE( RN(ir), FRMn(ir) );
  1091                     break;
  1092                 case 12:/* FMOV    FRm, FRn */
  1093                     if( IS_FPU_DOUBLESIZE() ) {
  1094                         DRN(ir) = DRM(ir);
  1095                     } else {
  1096                         FRN(ir) = FRM(ir);
  1098                     break;
  1099                 case 13:
  1100                     switch( (ir&0x00F0) >> 4 ) {
  1101                         case 0: /* FSTS    FPUL, FRn */
  1102                             FRN(ir) = FPULf;
  1103                             break;
  1104                         case 1: /* FLDS    FRn, FPUL */
  1105                             FPULf = FRN(ir);
  1106                             break;
  1107                         case 2: /* FLOAT   FPUL, FRn */
  1108                             FRN(ir) = (float)FPULi;
  1109                             break;
  1110                         case 3: /* FTRC    FRn, FPUL */
  1111                             FPULi = (uint32_t)FRN(ir);
  1112                             /* FIXME: is this sufficient? */
  1113                             break;
  1114                         case 4: /* FNEG    FRn */
  1115                             FRN(ir) = -FRN(ir);
  1116                             break;
  1117                         case 5: /* FABS    FRn */
  1118                             FRN(ir) = fabsf(FRN(ir));
  1119                             break;
  1120                         case 6: /* FSQRT   FRn */
  1121                             FRN(ir) = sqrtf(FRN(ir));
  1122                             break;
  1123                         case 7: /* FSRRA FRn */
  1124                             FRN(ir) = 1.0/sqrtf(FRN(ir));
  1125                             break;
  1126                         case 8: /* FLDI0   FRn */
  1127                             FRN(ir) = 0.0;
  1128                             break;
  1129                         case 9: /* FLDI1   FRn */
  1130                             FRN(ir) = 1.0;
  1131                             break;
  1132                         case 10: /* FCNVSD FPUL, DRn */
  1133                             if( IS_FPU_DOUBLEPREC() )
  1134                                 DRN(ir) = (double)FPULf;
  1135                             else UNDEF(ir);
  1136                             break;
  1137                         case 11: /* FCNVDS DRn, FPUL */
  1138                             if( IS_FPU_DOUBLEPREC() ) 
  1139                                 FPULf = (float)DRN(ir);
  1140                             else UNDEF(ir);
  1141                             break;
  1142                         case 14:/* FIPR    FVm, FVn */
  1143                             /* FIXME: This is not going to be entirely accurate
  1144                              * as the SH4 instruction is less precise. Also
  1145                              * need to check for 0s and infinities.
  1146                              */
  1148                             float *fr_bank = FR;
  1149                             int tmp2 = FVN(ir);
  1150                             tmp = FVM(ir);
  1151                             fr_bank[tmp2+3] = fr_bank[tmp]*fr_bank[tmp2] +
  1152                                 fr_bank[tmp+1]*fr_bank[tmp2+1] +
  1153                                 fr_bank[tmp+2]*fr_bank[tmp2+2] +
  1154                                 fr_bank[tmp+3]*fr_bank[tmp2+3];
  1155                             break;
  1157                         case 15:
  1158                             if( (ir&0x0300) == 0x0100 ) { /* FTRV    XMTRX,FVn */
  1159                                 float *fvout = FR+FVN(ir);
  1160                                 float *xm = XF;
  1161                                 float fv[4] = { fvout[0], fvout[1], fvout[2], fvout[3] };
  1162                                 fvout[0] = xm[0] * fv[0] + xm[4]*fv[1] +
  1163                                     xm[8]*fv[2] + xm[12]*fv[3];
  1164                                 fvout[1] = xm[1] * fv[0] + xm[5]*fv[1] +
  1165                                     xm[9]*fv[2] + xm[13]*fv[3];
  1166                                 fvout[2] = xm[2] * fv[0] + xm[6]*fv[1] +
  1167                                     xm[10]*fv[2] + xm[14]*fv[3];
  1168                                 fvout[3] = xm[3] * fv[0] + xm[7]*fv[1] +
  1169                                     xm[11]*fv[2] + xm[15]*fv[3];
  1170                                 break;
  1172                             else if( (ir&0x0100) == 0 ) { /* FSCA    FPUL, DRn */
  1173                                 float angle = (((float)(short)(FPULi>>16)) +
  1174                                                ((float)(FPULi&16)/65536.0)) *
  1175                                     2 * M_PI;
  1176                                 int reg = FRNn(ir);
  1177                                 FR[reg] = sinf(angle);
  1178                                 FR[reg+1] = cosf(angle);
  1179                                 break;
  1181                             else if( ir == 0xFBFD ) {
  1182                                 /* FRCHG   */
  1183                                 sh4r.fpscr ^= FPSCR_FR;
  1184                                 break;
  1186                             else if( ir == 0xF3FD ) {
  1187                                 /* FSCHG   */
  1188                                 sh4r.fpscr ^= FPSCR_SZ;
  1189                                 break;
  1191                         default: UNDEF(ir);
  1193                     break;
  1194                 case 14:/* FMAC    FR0, FRm, FRn */
  1195                     FRN(ir) += FRM(ir)*FR0;
  1196                     break;
  1197                 default: UNDEF(ir);
  1199             break;
  1201     sh4r.pc = sh4r.new_pc;
  1202     sh4r.new_pc += 2;
  1203     sh4r.in_delay_slot = 0;
.