lxdream 0.9.1| filename | src/sh4/sh4mmio.c |
| changeset | 10:c898b37506e0 |
| prev | 1:eea311cfd33e |
| next | 19:9da7a8e38f9d |
| author | nkeynes |
| date | Sun Dec 11 05:15:36 2005 +0000 (18 years ago) |
| permissions | -rw-r--r-- |
| last change | Add CPU disasembly options to mode dropdown Split sh4/mem.c into core mem.c and sh4/mem.c Start adding copyright comments to file headers |
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1 #include "dream.h"
2 #include "mem.h"
3 #include "sh4core.h"
4 #include "sh4mmio.h"
5 #define MMIO_IMPL
6 #include "sh4mmio.h"
8 /********************************* MMU *************************************/
10 MMIO_REGION_READ_STUBFN( MMU )
12 #define OCRAM_START (0x1C000000>>PAGE_BITS)
13 #define OCRAM_END (0x20000000>>PAGE_BITS)
15 static char *cache = NULL;
17 void mmio_region_MMU_write( uint32_t reg, uint32_t val )
18 {
19 switch(reg) {
20 case CCR:
21 mmu_set_cache_mode( val & (CCR_OIX|CCR_ORA) );
22 INFO( "Cache mode set to %08X", val );
23 break;
24 default:
25 break;
26 }
27 MMIO_WRITE( MMU, reg, val );
28 }
31 void mmu_init()
32 {
33 cache = mem_alloc_pages(2);
34 }
36 void mmu_set_cache_mode( int mode )
37 {
38 uint32_t i;
39 switch( mode ) {
40 case MEM_OC_INDEX0: /* OIX=0 */
41 for( i=OCRAM_START; i<OCRAM_END; i++ )
42 page_map[i] = cache + ((i&0x02)<<(PAGE_BITS-1));
43 break;
44 case MEM_OC_INDEX1: /* OIX=1 */
45 for( i=OCRAM_START; i<OCRAM_END; i++ )
46 page_map[i] = cache + ((i&0x02000000)>>(25-PAGE_BITS));
47 break;
48 default: /* disabled */
49 for( i=OCRAM_START; i<OCRAM_END; i++ )
50 page_map[i] = NULL;
51 break;
52 }
53 }
56 /********************************* BSC *************************************/
58 uint16_t bsc_output_mask_lo = 0, bsc_output_mask_hi = 0;
59 uint16_t bsc_input_mask_lo = 0, bsc_input_mask_hi = 0;
60 uint32_t bsc_output = 0, bsc_input = 0x0300;
62 void bsc_out( int output, int mask )
63 {
64 /* Go figure... The BIOS won't start without this mess though */
65 if( ((output | (~mask)) & 0x03) == 3 ) {
66 bsc_output |= 0x03;
67 } else {
68 bsc_output &= ~0x03;
69 }
70 }
72 void mmio_region_BSC_write( uint32_t reg, uint32_t val )
73 {
74 int i;
75 switch( reg ) {
76 case PCTRA:
77 bsc_input_mask_lo = bsc_output_mask_lo = 0;
78 for( i=0; i<16; i++ ) {
79 int bits = (val >> (i<<1)) & 0x03;
80 if( bits == 2 ) bsc_input_mask_lo |= (1<<i);
81 else if( bits != 0 ) bsc_output_mask_lo |= (1<<i);
82 }
83 bsc_output = (bsc_output&0x000F0000) |
84 (MMIO_READ( BSC, PDTRA ) & bsc_output_mask_lo);
85 bsc_out( MMIO_READ( BSC, PDTRA ) | ((MMIO_READ(BSC,PDTRB)<<16)),
86 bsc_output_mask_lo | (bsc_output_mask_hi<<16) );
87 break;
88 case PCTRB:
89 bsc_input_mask_hi = bsc_output_mask_hi = 0;
90 for( i=0; i<4; i++ ) {
91 int bits = (val >> (i>>1)) & 0x03;
92 if( bits == 2 ) bsc_input_mask_hi |= (1<<i);
93 else if( bits != 0 ) bsc_output_mask_hi |= (1<<i);
94 }
95 bsc_output = (bsc_output&0xFFFF) |
96 ((MMIO_READ( BSC, PDTRA ) & bsc_output_mask_hi)<<16);
97 break;
98 case PDTRA:
99 bsc_output = (bsc_output&0x000F0000) |
100 (val & bsc_output_mask_lo );
101 bsc_out( val | ((MMIO_READ(BSC,PDTRB)<<16)),
102 bsc_output_mask_lo | (bsc_output_mask_hi<<16) );
103 break;
104 case PDTRB:
105 bsc_output = (bsc_output&0xFFFF) |
106 ( (val & bsc_output_mask_hi)<<16 );
107 break;
108 }
109 WARN( "Write to (mostly) unimplemented BSC (%03X <= %08X) [%s: %s]",
110 reg, val, MMIO_REGID(BSC,reg), MMIO_REGDESC(BSC,reg) );
111 MMIO_WRITE( BSC, reg, val );
112 }
114 int32_t mmio_region_BSC_read( uint32_t reg )
115 {
116 int32_t val;
117 switch( reg ) {
118 case PDTRA:
119 val = (bsc_input & bsc_input_mask_lo) | (bsc_output&0xFFFF);
120 break;
121 case PDTRB:
122 val = ((bsc_input>>16) & bsc_input_mask_hi) | (bsc_output>>16);
123 break;
124 default:
125 val = MMIO_READ( BSC, reg );
126 }
127 WARN( "Read from (mostly) unimplemented BSC (%03X => %08X) [%s: %s]",
128 reg, val, MMIO_REGID(BSC,reg), MMIO_REGDESC(BSC,reg) );
129 return val;
130 }
132 /********************************* UBC *************************************/
134 MMIO_REGION_STUBFNS( UBC )
136 /********************************* CPG *************************************/
138 MMIO_REGION_STUBFNS( CPG )
140 /********************************* DMAC *************************************/
142 MMIO_REGION_STUBFNS( DMAC )
144 /********************************** RTC *************************************/
146 MMIO_REGION_STUBFNS( RTC )
148 /********************************** TMU *************************************/
150 int timer_divider[3] = {16,16,16};
151 MMIO_REGION_READ_DEFFN( TMU )
153 int get_timer_div( int val )
154 {
155 switch( val & 0x07 ) {
156 case 0: return 16; /* assume peripheral clock is IC/4 */
157 case 1: return 64;
158 case 2: return 256;
159 case 3: return 1024;
160 case 4: return 4096;
161 }
162 return 1;
163 }
165 void mmio_region_TMU_write( uint32_t reg, uint32_t val )
166 {
167 switch( reg ) {
168 case TCR0:
169 timer_divider[0] = get_timer_div(val);
170 break;
171 case TCR1:
172 timer_divider[1] = get_timer_div(val);
173 break;
174 case TCR2:
175 timer_divider[2] = get_timer_div(val);
176 break;
177 }
178 MMIO_WRITE( TMU, reg, val );
179 }
181 void run_timers( int cycles )
182 {
183 int tcr = MMIO_READ( TMU, TSTR );
184 cycles *= 16;
185 if( tcr & 1 ) {
186 int count = cycles / timer_divider[0];
187 int *val = MMIO_REG( TMU, TCNT0 );
188 if( *val < count ) {
189 MMIO_READ( TMU, TCR0 ) |= 0x100;
190 /* interrupt goes here */
191 count -= *val;
192 *val = MMIO_READ( TMU, TCOR0 ) - count;
193 } else {
194 *val -= count;
195 }
196 }
197 }
199 /********************************** SCI *************************************/
201 MMIO_REGION_STUBFNS( SCI )
203 /********************************* SCIF *************************************/
205 MMIO_REGION_STUBFNS( SCIF )
.