filename | src/gdrom/ide.h |
changeset | 858:368fc0dcd57c |
prev | 736:a02d1475ccfd |
next | 1097:d4807997e450 |
author | nkeynes |
date | Fri Nov 07 06:39:12 2008 +0000 (15 years ago) |
permissions | -rw-r--r-- |
last change | Implement a sorted TLB lookup table (big improvement over the linear table scan) Optimize out the 1C000000 -> FC000000 check at the end of the lookup functions |
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1 /**
2 * $Id$
3 *
4 * This file defines the interface and structures of the dreamcast's IDE
5 * port. Note that the register definitions are in asic.h, as the registers
6 * fall into the general ASIC ranges (and I don't want to use smaller pages
7 * at this stage). The registers here are exactly as per the ATA
8 * specifications, which makes things a little easier.
9 *
10 * Copyright (c) 2005 Nathan Keynes.
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 */
23 #ifndef lxdream_ide_H
24 #define lxdream_ide_H 1
26 #include "lxdream.h"
28 #ifdef __cplusplus
29 extern "C" {
30 #endif
32 #define GDROM_DRIVE_STATUS_LENGTH 10
33 #define GDROM_SENSE_LENGTH 10
34 #define GDROM_MODE_LENGTH 32
36 struct ide_registers {
37 /* IDE interface registers */
38 uint8_t status; /* A05F709C + A05F7018 Read-only */
39 uint8_t control; /* A05F7018 Write-only 01110 */
40 uint8_t error; /* A05F7084 Read-only 10001 */
41 uint8_t feature; /* A05F7084 Write-only 10001 */
42 uint8_t count; /* A05F7088 Read/Write 10010 */
43 uint8_t disc; /* A05F708C Read-only 10011 */
44 uint8_t lba0; /* A05F708C Write-only 10011 (NB: Presumed, TBV */
45 uint8_t lba1; /* A05F7090 Read/Write 10100 */
46 uint8_t lba2; /* A05F7094 Read/Write 10101 */
47 uint8_t device; /* A05F7098 Read/Write 10110 */
48 uint8_t command; /* A05F709C Write-only 10111 */
50 /* Internal IDE state */
51 uint8_t intrq_pending; /* Flag to indicate if the INTRQ line is active */
52 gboolean interface_enabled;
53 gboolean was_reset; /* Flag indicating that the device has just been reset */
54 uint32_t state;
55 uint32_t last_packet_command; /* Identifies the command executing during a r/w cycle */
57 /* Sense response for the last executed packet command */
58 unsigned char gdrom_sense[GDROM_SENSE_LENGTH];
59 unsigned char gdrom_mode[GDROM_MODE_LENGTH];
61 /* offset in the buffer of the next word to read/write, or -1
62 * if inactive.
63 */
64 int32_t data_offset;
65 int32_t data_length;
67 /* Status reporting information */
68 uint8_t last_read_track;
69 uint32_t current_lba;
70 uint32_t current_mode;
71 uint32_t sectors_left; /* sectors left after current read */
72 };
74 #define IDE_STATE_IDLE 0
75 #define IDE_STATE_CMD_WRITE 1
76 #define IDE_STATE_PIO_READ 2
77 #define IDE_STATE_PIO_WRITE 3
78 #define IDE_STATE_DMA_READ 4
79 #define IDE_STATE_DMA_WRITE 5
80 #define IDE_STATE_BUSY 6
82 /* Flag bits */
83 #define IDE_STATUS_BSY 0x80 /* Busy */
84 #define IDE_STATUS_DRDY 0x40 /* Device ready */
85 #define IDE_STATUS_DMRD 0x20 /* DMA Request */
86 #define IDE_STATUS_SERV 0x10
87 #define IDE_STATUS_DRQ 0x08
88 #define IDE_STATUS_CHK 0x01 /* Check condition (ie error) */
90 #define IDE_FEAT_DMA 0x01
91 #define IDE_FEAT_OVL 0x02
93 #define IDE_COUNT_CD 0x01 /* Command (1)/Data (0) */
94 #define IDE_COUNT_IO 0x02 /* Input (1)/Output (0) */
95 #define IDE_COUNT_REL 0x04 /* Release device */
98 #define IDE_CTL_RESET 0x04
99 #define IDE_CTL_IRQEN 0x02 /* IRQ enabled when == 0 */
101 #define IDE_CMD_NOP 0x00
102 #define IDE_CMD_RESET_DEVICE 0x08
103 #define IDE_CMD_PACKET 0xA0
104 #define IDE_CMD_IDENTIFY_PACKET_DEVICE 0xA1
105 #define IDE_CMD_SERVICE 0xA2
106 #define IDE_CMD_SET_FEATURE 0xEF
108 #define IDE_FEAT_SET_TRANSFER_MODE 0x03
109 #define IDE_XFER_PIO 0x00
110 #define IDE_XFER_PIO_FLOW 0x08
111 #define IDE_XFER_MULTI_DMA 0x20
112 #define IDE_XFER_ULTRA_DMA 0x40
114 extern struct ide_registers idereg;
116 /* Note: control can be written at any time - all other registers are writable
117 * only when ide_can_write_regs() is true
118 */
119 #define ide_can_write_regs() ((idereg.status&0x80)==0)
120 #define IS_IDE_IRQ_ENABLED() ((idereg.control&0x02)==0)
123 uint16_t ide_read_data_pio(void);
124 void ide_write_data_pio( uint16_t value );
125 uint32_t ide_read_data_dma( uint32_t addr, uint32_t length );
126 uint8_t ide_read_status(void);
127 uint8_t ide_get_drive_status(void);
128 void ide_write_buffer( unsigned char *data, uint32_t length );
130 void ide_write_command( uint8_t command );
131 void ide_write_control( uint8_t value );
133 void ide_dma_read_req( uint32_t addr, uint32_t length );
135 #ifdef __cplusplus
136 }
137 #endif
139 #endif /* !lxdream_ide_H */
.