2 * $Id: sh4core.c,v 1.15 2005-12-26 10:47:10 nkeynes Exp $
4 * SH4 emulation core, and parent module for all the SH4 peripheral
7 * Copyright (c) 2005 Nathan Keynes.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
20 #define MODULE sh4_module
29 /* CPU-generated exception code/vector pairs */
30 #define EXC_POWER_RESET 0x000 /* vector special */
31 #define EXC_MANUAL_RESET 0x020
32 #define EXC_SLOT_ILLEGAL 0x1A0
33 #define EXC_ILLEGAL 0x180
34 #define EXV_ILLEGAL 0x100
35 #define EXC_TRAP 0x160
36 #define EXV_TRAP 0x100
37 #define EXC_FPDISABLE 0x800
38 #define EXV_FPDISABLE 0x100
40 uint32_t sh4_freq = SH4_BASE_RATE;
41 uint32_t sh4_bus_freq = SH4_BASE_RATE;
42 uint32_t sh4_peripheral_freq = SH4_BASE_RATE / 2;
44 uint32_t sh4_cpu_period = 1000 / SH4_BASE_RATE; /* in nanoseconds */
45 uint32_t sh4_bus_period = 1000 / SH4_BASE_RATE;
46 uint32_t sh4_peripheral_period = 2000 / SH4_BASE_RATE;
48 /********************** SH4 Module Definition ****************************/
50 void sh4_init( void );
51 void sh4_reset( void );
52 uint32_t sh4_run_slice( uint32_t );
53 void sh4_start( void );
54 void sh4_stop( void );
55 void sh4_save_state( FILE *f );
56 int sh4_load_state( FILE *f );
58 struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset,
59 NULL, sh4_run_slice, sh4_stop,
60 sh4_save_state, sh4_load_state };
62 struct sh4_registers sh4r;
66 register_io_regions( mmio_list_sh4mmio );
73 /* zero everything out, for the sake of having a consistent state. */
74 memset( &sh4r, 0, sizeof(sh4r) );
76 /* Resume running if we were halted */
77 sh4r.sh4_state = SH4_STATE_RUNNING;
80 sh4r.new_pc= 0xA0000002;
81 sh4r.vbr = 0x00000000;
82 sh4r.fpscr = 0x00040001;
85 /* Mem reset will do this, but if we want to reset _just_ the SH4... */
86 MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
88 /* Peripheral modules */
93 uint32_t sh4_run_slice( uint32_t nanosecs )
95 int target = sh4r.icount + nanosecs / sh4_cpu_period;
96 int start = sh4r.icount;
99 if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
100 if( sh4r.int_pending != 0 )
101 sh4r.sh4_state = SH4_STATE_RUNNING;;
104 while( sh4r.icount < target && sh4r.sh4_state == SH4_STATE_RUNNING ) {
106 if( !sh4_execute_instruction() )
110 /* If we aborted early, but the cpu is still technically running,
111 * we're doing a hard abort - cut the timeslice back to what we
114 if( target != sh4r.icount && sh4r.sh4_state == SH4_STATE_RUNNING ) {
115 /* Halted - compute time actually executed */
116 nanosecs = (sh4r.icount - start) * sh4_cpu_period;
118 if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
119 TMU_run_slice( nanosecs );
120 SCIF_run_slice( nanosecs );
130 void sh4_save_state( FILE *f )
132 fwrite( &sh4r, sizeof(sh4r), 1, f );
133 SCIF_save_state( f );
136 int sh4_load_state( FILE * f )
138 fread( &sh4r, sizeof(sh4r), 1, f );
139 return SCIF_load_state( f );
142 /********************** SH4 emulation core ****************************/
144 void sh4_set_pc( int pc )
150 void sh4_set_breakpoint( uint32_t pc, int type )
155 #define UNDEF(ir) do{ ERROR( "Raising exception on undefined instruction at %08x, opcode = %04x", sh4r.pc, ir ); RAISE( EXC_ILLEGAL, EXV_ILLEGAL ); }while(0)
156 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)
158 #define RAISE( x, v ) do{ \
159 if( sh4r.vbr == 0 ) { \
160 ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
163 sh4r.spc = sh4r.pc + 2; \
164 sh4r.ssr = sh4_read_sr(); \
165 sh4r.sgr = sh4r.r[15]; \
166 MMIO_WRITE(MMU,EXPEVT,x); \
167 sh4r.pc = sh4r.vbr + v; \
168 sh4r.new_pc = sh4r.pc + 2; \
169 sh4_load_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
171 return TRUE; } while(0)
173 #define MEM_READ_BYTE( addr ) sh4_read_byte(addr)
174 #define MEM_READ_WORD( addr ) sh4_read_word(addr)
175 #define MEM_READ_LONG( addr ) sh4_read_long(addr)
176 #define MEM_WRITE_BYTE( addr, val ) sh4_write_byte(addr, val)
177 #define MEM_WRITE_WORD( addr, val ) sh4_write_word(addr, val)
178 #define MEM_WRITE_LONG( addr, val ) sh4_write_long(addr, val)
180 #define MEM_FP_READ( addr, reg ) if( IS_FPU_DOUBLESIZE() ) { \
181 ((uint32_t *)FR)[(reg)&0xE0] = sh4_read_long(addr); \
182 ((uint32_t *)FR)[(reg)|1] = sh4_read_long(addr+4); \
183 } else ((uint32_t *)FR)[reg] = sh4_read_long(addr)
185 #define MEM_FP_WRITE( addr, reg ) if( IS_FPU_DOUBLESIZE() ) { \
186 sh4_write_long( addr, ((uint32_t *)FR)[(reg)&0xE0] ); \
187 sh4_write_long( addr+4, ((uint32_t *)FR)[(reg)|1] ); \
188 } else sh4_write_long( addr, ((uint32_t *)FR)[reg] )
190 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
192 #define CHECK( x, c, v ) if( !x ) RAISE( c, v )
193 #define CHECKPRIV() CHECK( IS_SH4_PRIVMODE(), EXC_ILLEGAL, EXV_ILLEGAL )
194 #define CHECKFPUEN() CHECK( IS_FPU_ENABLED(), EXC_FPDISABLE, EXV_FPDISABLE )
195 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); sh4_stop(); return; }
196 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) { RAISE(EXC_SLOT_ILLEGAL,EXV_ILLEGAL); }
198 static void sh4_switch_banks( )
202 memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
203 memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
204 memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
207 static void sh4_load_sr( uint32_t newval )
209 if( (newval ^ sh4r.sr) & SR_RB )
212 sh4r.t = (newval&SR_T) ? 1 : 0;
213 sh4r.s = (newval&SR_S) ? 1 : 0;
214 sh4r.m = (newval&SR_M) ? 1 : 0;
215 sh4r.q = (newval&SR_Q) ? 1 : 0;
219 static uint32_t sh4_read_sr( void )
221 /* synchronize sh4r.sr with the various bitflags */
222 sh4r.sr &= SR_MQSTMASK;
223 if( sh4r.t ) sh4r.sr |= SR_T;
224 if( sh4r.s ) sh4r.sr |= SR_S;
225 if( sh4r.m ) sh4r.sr |= SR_M;
226 if( sh4r.q ) sh4r.sr |= SR_Q;
229 /* function for external use */
230 void sh4_raise_exception( int code, int vector )
235 static void sh4_accept_interrupt( void )
237 uint32_t code = intc_accept_interrupt();
238 sh4r.ssr = sh4_read_sr();
240 sh4r.sgr = sh4r.r[15];
241 sh4_load_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
242 MMIO_WRITE( MMU, INTEVT, code );
243 sh4r.pc = sh4r.vbr + 0x600;
244 sh4r.new_pc = sh4r.pc + 2;
245 WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
248 gboolean sh4_execute_instruction( void )
257 #define RN(ir) sh4r.r[(ir&0x0F00)>>8]
258 #define RN_BANK(ir) sh4r.r_bank[(ir&0x0070)>>4]
259 #define RM(ir) sh4r.r[(ir&0x00F0)>>4]
260 #define DISP4(ir) (ir&0x000F) /* 4-bit displacements are *NOT* sign-extended */
261 #define DISP8(ir) (ir&0x00FF)
262 #define PCDISP8(ir) SIGNEXT8(ir&0x00FF)
263 #define IMM8(ir) SIGNEXT8(ir&0x00FF)
264 #define UIMM8(ir) (ir&0x00FF) /* Unsigned immmediate */
265 #define DISP12(ir) SIGNEXT12(ir&0x0FFF)
266 #define FVN(ir) ((ir&0x0C00)>>8)
267 #define FVM(ir) ((ir&0x0300)>>6)
268 #define FRN(ir) (FR[(ir&0x0F00)>>8])
269 #define FRM(ir) (FR[(ir&0x00F0)>>4])
270 #define FRNi(ir) (((uint32_t *)FR)[(ir&0x0F00)>>8])
271 #define FRMi(ir) (((uint32_t *)FR)[(ir&0x00F0)>>4])
272 #define DRN(ir) (((double *)FR)[(ir&0x0E00)>>9])
273 #define DRM(ir) (((double *)FR)[(ir&0x00E0)>>5])
274 #define DRNi(ir) (((uint64_t *)FR)[(ir&0x0E00)>>9])
275 #define DRMi(ir) (((uint64_t *)FR)[(ir&0x00E0)>>5])
276 #define FRNn(ir) ((ir&0x0F00)>>8)
277 #define FRMn(ir) ((ir&0x00F0)>>4)
278 #define FPULf *((float *)&sh4r.fpul)
279 #define FPULi (sh4r.fpul)
281 if( SH4_INT_PENDING() )
282 sh4_accept_interrupt();
285 ir = MEM_READ_WORD(pc);
288 switch( (ir&0xF000)>>12 ) {
289 case 0: /* 0000nnnnmmmmxxxx */
290 switch( ir&0x000F ) {
292 switch( (ir&0x00F0)>>4 ) {
293 case 0: /* STC SR, Rn */
295 RN(ir) = sh4_read_sr();
297 case 1: /* STC GBR, Rn */
300 case 2: /* STC VBR, Rn */
304 case 3: /* STC SSR, Rn */
308 case 4: /* STC SPC, Rn */
312 case 8: case 9: case 10: case 11: case 12: case 13:
313 case 14: case 15:/* STC Rm_bank, Rn */
315 RN(ir) = RN_BANK(ir);
321 switch( (ir&0x00F0)>>4 ) {
322 case 0: /* BSRF Rn */
323 CHECKDEST( pc + 4 + RN(ir) );
325 sh4r.in_delay_slot = 1;
326 sh4r.pr = sh4r.pc + 4;
327 sh4r.pc = sh4r.new_pc;
328 sh4r.new_pc = pc + 4 + RN(ir);
330 case 2: /* BRAF Rn */
331 CHECKDEST( pc + 4 + RN(ir) );
333 sh4r.in_delay_slot = 1;
334 sh4r.pc = sh4r.new_pc;
335 sh4r.new_pc = pc + 4 + RN(ir);
337 case 8: /* PREF [Rn] */
339 if( (tmp & 0xFC000000) == 0xE0000000 ) {
340 /* Store queue operation */
341 int queue = (tmp&0x20)>>2;
342 int32_t *src = &sh4r.store_queue[queue];
343 uint32_t hi = (MMIO_READ( MMU, (queue == 0 ? QACR0 : QACR1) ) & 0x1C) << 24;
344 uint32_t target = tmp&0x03FFFFE0 | hi;
345 mem_copy_to_sh4( target, src, 32 );
346 // WARN( "Executed SQ%c => %08X",
347 // (queue == 0 ? '0' : '1'), target );
350 case 9: /* OCBI [Rn] */
351 case 10:/* OCBP [Rn] */
352 case 11:/* OCBWB [Rn] */
355 case 12:/* MOVCA.L R0, [Rn] */
360 case 4: /* MOV.B Rm, [R0 + Rn] */
361 MEM_WRITE_BYTE( R0 + RN(ir), RM(ir) );
363 case 5: /* MOV.W Rm, [R0 + Rn] */
364 MEM_WRITE_WORD( R0 + RN(ir), RM(ir) );
366 case 6: /* MOV.L Rm, [R0 + Rn] */
367 MEM_WRITE_LONG( R0 + RN(ir), RM(ir) );
369 case 7: /* MUL.L Rm, Rn */
370 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
374 switch( (ir&0x0FF0)>>4 ) {
396 if( (ir&0x00F0) == 0x20 ) /* MOVT Rn */
398 else if( ir == 0x0019 ) /* DIV0U */
399 sh4r.m = sh4r.q = sh4r.t = 0;
400 else if( ir == 0x0009 )
405 switch( (ir&0x00F0) >> 4 ) {
406 case 0: /* STS MACH, Rn */
407 RN(ir) = sh4r.mac >> 32;
409 case 1: /* STS MACL, Rn */
410 RN(ir) = (uint32_t)sh4r.mac;
412 case 2: /* STS PR, Rn */
415 case 3: /* STC SGR, Rn */
419 case 5:/* STS FPUL, Rn */
422 case 6: /* STS FPSCR, Rn */
425 case 15:/* STC DBR, Rn */
433 switch( (ir&0x0FF0)>>4 ) {
435 CHECKDEST( sh4r.pr );
437 sh4r.in_delay_slot = 1;
438 sh4r.pc = sh4r.new_pc;
439 sh4r.new_pc = sh4r.pr;
442 if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
443 sh4r.sh4_state = SH4_STATE_STANDBY;
445 sh4r.sh4_state = SH4_STATE_SLEEP;
447 return FALSE; /* Halt CPU */
450 CHECKDEST( sh4r.spc );
452 sh4r.in_delay_slot = 1;
453 sh4r.pc = sh4r.new_pc;
454 sh4r.new_pc = sh4r.spc;
455 sh4_load_sr( sh4r.ssr );
460 case 12:/* MOV.B [R0+R%d], R%d */
461 RN(ir) = MEM_READ_BYTE( R0 + RM(ir) );
463 case 13:/* MOV.W [R0+R%d], R%d */
464 RN(ir) = MEM_READ_WORD( R0 + RM(ir) );
466 case 14:/* MOV.L [R0+R%d], R%d */
467 RN(ir) = MEM_READ_LONG( R0 + RM(ir) );
469 case 15:/* MAC.L [Rm++], [Rn++] */
470 tmpl = ( SIGNEXT32(MEM_READ_LONG(RM(ir))) *
471 SIGNEXT32(MEM_READ_LONG(RN(ir))) );
473 /* 48-bit Saturation. Yuch */
474 tmpl += SIGNEXT48(sh4r.mac);
475 if( tmpl < 0xFFFF800000000000LL )
476 tmpl = 0xFFFF800000000000LL;
477 else if( tmpl > 0x00007FFFFFFFFFFFLL )
478 tmpl = 0x00007FFFFFFFFFFFLL;
479 sh4r.mac = (sh4r.mac&0xFFFF000000000000LL) |
480 (tmpl&0x0000FFFFFFFFFFFFLL);
481 } else sh4r.mac = tmpl;
490 case 1: /* 0001nnnnmmmmdddd */
491 /* MOV.L Rm, [Rn + disp4*4] */
492 MEM_WRITE_LONG( RN(ir) + (DISP4(ir)<<2), RM(ir) );
494 case 2: /* 0010nnnnmmmmxxxx */
495 switch( ir&0x000F ) {
496 case 0: /* MOV.B Rm, [Rn] */
497 MEM_WRITE_BYTE( RN(ir), RM(ir) );
499 case 1: /* MOV.W Rm, [Rn] */
500 MEM_WRITE_WORD( RN(ir), RM(ir) );
502 case 2: /* MOV.L Rm, [Rn] */
503 MEM_WRITE_LONG( RN(ir), RM(ir) );
507 case 4: /* MOV.B Rm, [--Rn] */
509 MEM_WRITE_BYTE( RN(ir), RM(ir) );
511 case 5: /* MOV.W Rm, [--Rn] */
513 MEM_WRITE_WORD( RN(ir), RM(ir) );
515 case 6: /* MOV.L Rm, [--Rn] */
517 MEM_WRITE_LONG( RN(ir), RM(ir) );
519 case 7: /* DIV0S Rm, Rn */
522 sh4r.t = sh4r.q ^ sh4r.m;
524 case 8: /* TST Rm, Rn */
525 sh4r.t = (RN(ir)&RM(ir) ? 0 : 1);
527 case 9: /* AND Rm, Rn */
530 case 10:/* XOR Rm, Rn */
533 case 11:/* OR Rm, Rn */
536 case 12:/* CMP/STR Rm, Rn */
537 /* set T = 1 if any byte in RM & RN is the same */
538 tmp = RM(ir) ^ RN(ir);
539 sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
540 (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
542 case 13:/* XTRCT Rm, Rn */
543 RN(ir) = (RN(ir)>>16) | (RM(ir)<<16);
545 case 14:/* MULU.W Rm, Rn */
546 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
547 (uint32_t)((RM(ir)&0xFFFF) * (RN(ir)&0xFFFF));
549 case 15:/* MULS.W Rm, Rn */
550 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
551 (uint32_t)(SIGNEXT32(RM(ir)&0xFFFF) * SIGNEXT32(RN(ir)&0xFFFF));
555 case 3: /* 0011nnnnmmmmxxxx */
556 switch( ir&0x000F ) {
557 case 0: /* CMP/EQ Rm, Rn */
558 sh4r.t = ( RM(ir) == RN(ir) ? 1 : 0 );
560 case 2: /* CMP/HS Rm, Rn */
561 sh4r.t = ( RN(ir) >= RM(ir) ? 1 : 0 );
563 case 3: /* CMP/GE Rm, Rn */
564 sh4r.t = ( ((int32_t)RN(ir)) >= ((int32_t)RM(ir)) ? 1 : 0 );
566 case 4: { /* DIV1 Rm, Rn */
567 /* This is just from the sh4p manual with some
568 * simplifications (someone want to check it's correct? :)
569 * Why they couldn't just provide a real DIV instruction...
570 * Please oh please let the translator batch these things
571 * up into a single DIV... */
572 uint32_t tmp0, tmp1, tmp2, dir;
574 dir = sh4r.q ^ sh4r.m;
575 sh4r.q = (RN(ir) >> 31);
577 RN(ir) = (RN(ir) << 1) | sh4r.t;
581 tmp1 = (RN(ir)<tmp0 ? 1 : 0 );
584 tmp1 = (RN(ir)>tmp0 ? 1 : 0 );
586 sh4r.q ^= sh4r.m ^ tmp1;
587 sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
589 case 5: /* DMULU.L Rm, Rn */
590 sh4r.mac = ((uint64_t)RM(ir)) * ((uint64_t)RN(ir));
592 case 6: /* CMP/HI Rm, Rn */
593 sh4r.t = ( RN(ir) > RM(ir) ? 1 : 0 );
595 case 7: /* CMP/GT Rm, Rn */
596 sh4r.t = ( ((int32_t)RN(ir)) > ((int32_t)RM(ir)) ? 1 : 0 );
598 case 8: /* SUB Rm, Rn */
601 case 10:/* SUBC Rm, Rn */
603 RN(ir) = RN(ir) - RM(ir) - sh4r.t;
604 sh4r.t = (RN(ir) > tmp || (RN(ir) == tmp && sh4r.t == 1));
606 case 11:/* SUBV Rm, Rn */
609 case 12:/* ADD Rm, Rn */
612 case 13:/* DMULS.L Rm, Rn */
613 sh4r.mac = SIGNEXT32(RM(ir)) * SIGNEXT32(RN(ir));
615 case 14:/* ADDC Rm, Rn */
617 RN(ir) += RM(ir) + sh4r.t;
618 sh4r.t = ( RN(ir) < tmp || (RN(ir) == tmp && sh4r.t != 0) ? 1 : 0 );
620 case 15:/* ADDV Rm, Rn */
626 case 4: /* 0100nnnnxxxxxxxx */
627 switch( ir&0x00FF ) {
628 case 0x00: /* SHLL Rn */
629 sh4r.t = RN(ir) >> 31;
632 case 0x01: /* SHLR Rn */
633 sh4r.t = RN(ir) & 0x00000001;
636 case 0x02: /* STS.L MACH, [--Rn] */
638 MEM_WRITE_LONG( RN(ir), (sh4r.mac>>32) );
640 case 0x03: /* STC.L SR, [--Rn] */
643 MEM_WRITE_LONG( RN(ir), sh4_read_sr() );
645 case 0x04: /* ROTL Rn */
646 sh4r.t = RN(ir) >> 31;
650 case 0x05: /* ROTR Rn */
651 sh4r.t = RN(ir) & 0x00000001;
653 RN(ir) |= (sh4r.t << 31);
655 case 0x06: /* LDS.L [Rn++], MACH */
656 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
657 (((uint64_t)MEM_READ_LONG(RN(ir)))<<32);
660 case 0x07: /* LDC.L [Rn++], SR */
662 sh4_load_sr( MEM_READ_LONG(RN(ir)) );
665 case 0x08: /* SHLL2 Rn */
668 case 0x09: /* SHLR2 Rn */
671 case 0x0A: /* LDS Rn, MACH */
672 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
673 (((uint64_t)RN(ir))<<32);
675 case 0x0B: /* JSR [Rn] */
678 sh4r.in_delay_slot = 1;
679 sh4r.pc = sh4r.new_pc;
680 sh4r.new_pc = RN(ir);
683 case 0x0E: /* LDC Rn, SR */
685 sh4_load_sr( RN(ir) );
687 case 0x10: /* DT Rn */
689 sh4r.t = ( RN(ir) == 0 ? 1 : 0 );
691 case 0x11: /* CMP/PZ Rn */
692 sh4r.t = ( ((int32_t)RN(ir)) >= 0 ? 1 : 0 );
694 case 0x12: /* STS.L MACL, [--Rn] */
696 MEM_WRITE_LONG( RN(ir), (uint32_t)sh4r.mac );
698 case 0x13: /* STC.L GBR, [--Rn] */
700 MEM_WRITE_LONG( RN(ir), sh4r.gbr );
702 case 0x15: /* CMP/PL Rn */
703 sh4r.t = ( ((int32_t)RN(ir)) > 0 ? 1 : 0 );
705 case 0x16: /* LDS.L [Rn++], MACL */
706 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
707 (uint64_t)((uint32_t)MEM_READ_LONG(RN(ir)));
710 case 0x17: /* LDC.L [Rn++], GBR */
711 sh4r.gbr = MEM_READ_LONG(RN(ir));
714 case 0x18: /* SHLL8 Rn */
717 case 0x19: /* SHLR8 Rn */
720 case 0x1A: /* LDS Rn, MACL */
721 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
722 (uint64_t)((uint32_t)(RN(ir)));
724 case 0x1B: /* TAS.B [Rn] */
725 tmp = MEM_READ_BYTE( RN(ir) );
726 sh4r.t = ( tmp == 0 ? 1 : 0 );
727 MEM_WRITE_BYTE( RN(ir), tmp | 0x80 );
729 case 0x1E: /* LDC Rn, GBR */
732 case 0x20: /* SHAL Rn */
733 sh4r.t = RN(ir) >> 31;
736 case 0x21: /* SHAR Rn */
737 sh4r.t = RN(ir) & 0x00000001;
738 RN(ir) = ((int32_t)RN(ir)) >> 1;
740 case 0x22: /* STS.L PR, [--Rn] */
742 MEM_WRITE_LONG( RN(ir), sh4r.pr );
744 case 0x23: /* STC.L VBR, [--Rn] */
747 MEM_WRITE_LONG( RN(ir), sh4r.vbr );
749 case 0x24: /* ROTCL Rn */
755 case 0x25: /* ROTCR Rn */
756 tmp = RN(ir) & 0x00000001;
758 RN(ir) |= (sh4r.t << 31 );
761 case 0x26: /* LDS.L [Rn++], PR */
762 sh4r.pr = MEM_READ_LONG( RN(ir) );
765 case 0x27: /* LDC.L [Rn++], VBR */
767 sh4r.vbr = MEM_READ_LONG(RN(ir));
770 case 0x28: /* SHLL16 Rn */
773 case 0x29: /* SHLR16 Rn */
776 case 0x2A: /* LDS Rn, PR */
779 case 0x2B: /* JMP [Rn] */
782 sh4r.in_delay_slot = 1;
783 sh4r.pc = sh4r.new_pc;
784 sh4r.new_pc = RN(ir);
786 case 0x2E: /* LDC Rn, VBR */
790 case 0x32: /* STC.L SGR, [--Rn] */
793 MEM_WRITE_LONG( RN(ir), sh4r.sgr );
795 case 0x33: /* STC.L SSR, [--Rn] */
798 MEM_WRITE_LONG( RN(ir), sh4r.ssr );
800 case 0x37: /* LDC.L [Rn++], SSR */
802 sh4r.ssr = MEM_READ_LONG(RN(ir));
805 case 0x3E: /* LDC Rn, SSR */
809 case 0x43: /* STC.L SPC, [--Rn] */
812 MEM_WRITE_LONG( RN(ir), sh4r.spc );
814 case 0x47: /* LDC.L [Rn++], SPC */
816 sh4r.spc = MEM_READ_LONG(RN(ir));
819 case 0x4E: /* LDC Rn, SPC */
823 case 0x52: /* STS.L FPUL, [--Rn] */
825 MEM_WRITE_LONG( RN(ir), sh4r.fpul );
827 case 0x56: /* LDS.L [Rn++], FPUL */
828 sh4r.fpul = MEM_READ_LONG(RN(ir));
831 case 0x5A: /* LDS Rn, FPUL */
834 case 0x62: /* STS.L FPSCR, [--Rn] */
836 MEM_WRITE_LONG( RN(ir), sh4r.fpscr );
838 case 0x66: /* LDS.L [Rn++], FPSCR */
839 sh4r.fpscr = MEM_READ_LONG(RN(ir));
842 case 0x6A: /* LDS Rn, FPSCR */
845 case 0xF2: /* STC.L DBR, [--Rn] */
848 MEM_WRITE_LONG( RN(ir), sh4r.dbr );
850 case 0xF6: /* LDC.L [Rn++], DBR */
852 sh4r.dbr = MEM_READ_LONG(RN(ir));
855 case 0xFA: /* LDC Rn, DBR */
859 case 0x83: case 0x93: case 0xA3: case 0xB3: case 0xC3:
860 case 0xD3: case 0xE3: case 0xF3: /* STC.L Rn_BANK, [--Rn] */
863 MEM_WRITE_LONG( RN(ir), RN_BANK(ir) );
865 case 0x87: case 0x97: case 0xA7: case 0xB7: case 0xC7:
866 case 0xD7: case 0xE7: case 0xF7: /* LDC.L [Rn++], Rn_BANK */
868 RN_BANK(ir) = MEM_READ_LONG( RN(ir) );
871 case 0x8E: case 0x9E: case 0xAE: case 0xBE: case 0xCE:
872 case 0xDE: case 0xEE: case 0xFE: /* LDC Rm, Rn_BANK */
874 RN_BANK(ir) = RM(ir);
877 if( (ir&0x000F) == 0x0F ) {
878 /* MAC.W [Rm++], [Rn++] */
879 tmp = SIGNEXT16(MEM_READ_WORD(RM(ir))) *
880 SIGNEXT16(MEM_READ_WORD(RN(ir)));
884 } else sh4r.mac += SIGNEXT32(tmp);
887 } else if( (ir&0x000F) == 0x0C ) {
890 if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);
891 else if( (tmp & 0x1F) == 0 )
892 RN(ir) = ((int32_t)RN(ir)) >> 31;
894 RN(ir) = ((int32_t)RN(ir)) >> (((~RM(ir)) & 0x1F)+1);
895 } else if( (ir&0x000F) == 0x0D ) {
898 if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);
899 else if( (tmp & 0x1F) == 0 ) RN(ir) = 0;
900 else RN(ir) >>= (((~tmp) & 0x1F)+1);
904 case 5: /* 0101nnnnmmmmdddd */
905 /* MOV.L [Rm + disp4*4], Rn */
906 RN(ir) = MEM_READ_LONG( RM(ir) + (DISP4(ir)<<2) );
908 case 6: /* 0110xxxxxxxxxxxx */
909 switch( ir&0x000f ) {
910 case 0: /* MOV.B [Rm], Rn */
911 RN(ir) = MEM_READ_BYTE( RM(ir) );
913 case 1: /* MOV.W [Rm], Rn */
914 RN(ir) = MEM_READ_WORD( RM(ir) );
916 case 2: /* MOV.L [Rm], Rn */
917 RN(ir) = MEM_READ_LONG( RM(ir) );
919 case 3: /* MOV Rm, Rn */
922 case 4: /* MOV.B [Rm++], Rn */
923 RN(ir) = MEM_READ_BYTE( RM(ir) );
926 case 5: /* MOV.W [Rm++], Rn */
927 RN(ir) = MEM_READ_WORD( RM(ir) );
930 case 6: /* MOV.L [Rm++], Rn */
931 RN(ir) = MEM_READ_LONG( RM(ir) );
934 case 7: /* NOT Rm, Rn */
937 case 8: /* SWAP.B Rm, Rn */
938 RN(ir) = (RM(ir)&0xFFFF0000) | ((RM(ir)&0x0000FF00)>>8) |
939 ((RM(ir)&0x000000FF)<<8);
941 case 9: /* SWAP.W Rm, Rn */
942 RN(ir) = (RM(ir)>>16) | (RM(ir)<<16);
944 case 10:/* NEGC Rm, Rn */
946 RN(ir) = tmp - sh4r.t;
947 sh4r.t = ( 0<tmp || tmp<RN(ir) ? 1 : 0 );
949 case 11:/* NEG Rm, Rn */
952 case 12:/* EXTU.B Rm, Rn */
953 RN(ir) = RM(ir)&0x000000FF;
955 case 13:/* EXTU.W Rm, Rn */
956 RN(ir) = RM(ir)&0x0000FFFF;
958 case 14:/* EXTS.B Rm, Rn */
959 RN(ir) = SIGNEXT8( RM(ir)&0x000000FF );
961 case 15:/* EXTS.W Rm, Rn */
962 RN(ir) = SIGNEXT16( RM(ir)&0x0000FFFF );
966 case 7: /* 0111nnnniiiiiiii */
970 case 8: /* 1000xxxxxxxxxxxx */
971 switch( (ir&0x0F00) >> 8 ) {
972 case 0: /* MOV.B R0, [Rm + disp4] */
973 MEM_WRITE_BYTE( RM(ir) + DISP4(ir), R0 );
975 case 1: /* MOV.W R0, [Rm + disp4*2] */
976 MEM_WRITE_WORD( RM(ir) + (DISP4(ir)<<1), R0 );
978 case 4: /* MOV.B [Rm + disp4], R0 */
979 R0 = MEM_READ_BYTE( RM(ir) + DISP4(ir) );
981 case 5: /* MOV.W [Rm + disp4*2], R0 */
982 R0 = MEM_READ_WORD( RM(ir) + (DISP4(ir)<<1) );
984 case 8: /* CMP/EQ imm, R0 */
985 sh4r.t = ( R0 == IMM8(ir) ? 1 : 0 );
987 case 9: /* BT disp8 */
990 CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
991 sh4r.pc += (PCDISP8(ir)<<1) + 4;
992 sh4r.new_pc = sh4r.pc + 2;
996 case 11:/* BF disp8 */
999 CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
1000 sh4r.pc += (PCDISP8(ir)<<1) + 4;
1001 sh4r.new_pc = sh4r.pc + 2;
1005 case 13:/* BT/S disp8 */
1008 CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
1009 sh4r.in_delay_slot = 1;
1010 sh4r.pc = sh4r.new_pc;
1011 sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;
1012 sh4r.in_delay_slot = 1;
1016 case 15:/* BF/S disp8 */
1019 CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
1020 sh4r.in_delay_slot = 1;
1021 sh4r.pc = sh4r.new_pc;
1022 sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;
1029 case 9: /* 1001xxxxxxxxxxxx */
1030 /* MOV.W [disp8*2 + pc + 4], Rn */
1031 RN(ir) = MEM_READ_WORD( pc + 4 + (DISP8(ir)<<1) );
1033 case 10:/* 1010dddddddddddd */
1035 CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 )
1037 sh4r.in_delay_slot = 1;
1038 sh4r.pc = sh4r.new_pc;
1039 sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);
1041 case 11:/* 1011dddddddddddd */
1043 CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 )
1045 sh4r.in_delay_slot = 1;
1047 sh4r.pc = sh4r.new_pc;
1048 sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);
1050 case 12:/* 1100xxxxdddddddd */
1051 switch( (ir&0x0F00)>>8 ) {
1052 case 0: /* MOV.B R0, [GBR + disp8] */
1053 MEM_WRITE_BYTE( sh4r.gbr + DISP8(ir), R0 );
1055 case 1: /* MOV.W R0, [GBR + disp8*2] */
1056 MEM_WRITE_WORD( sh4r.gbr + (DISP8(ir)<<1), R0 );
1058 case 2: /*MOV.L R0, [GBR + disp8*4] */
1059 MEM_WRITE_LONG( sh4r.gbr + (DISP8(ir)<<2), R0 );
1061 case 3: /* TRAPA imm8 */
1063 sh4r.in_delay_slot = 1;
1064 MMIO_WRITE( MMU, TRA, UIMM8(ir) );
1065 sh4r.pc = sh4r.new_pc; /* RAISE ends the instruction */
1067 RAISE( EXC_TRAP, EXV_TRAP );
1069 case 4: /* MOV.B [GBR + disp8], R0 */
1070 R0 = MEM_READ_BYTE( sh4r.gbr + DISP8(ir) );
1072 case 5: /* MOV.W [GBR + disp8*2], R0 */
1073 R0 = MEM_READ_WORD( sh4r.gbr + (DISP8(ir)<<1) );
1075 case 6: /* MOV.L [GBR + disp8*4], R0 */
1076 R0 = MEM_READ_LONG( sh4r.gbr + (DISP8(ir)<<2) );
1078 case 7: /* MOVA disp8 + pc&~3 + 4, R0 */
1079 R0 = (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4;
1081 case 8: /* TST imm8, R0 */
1082 sh4r.t = (R0 & UIMM8(ir) ? 0 : 1);
1084 case 9: /* AND imm8, R0 */
1087 case 10:/* XOR imm8, R0 */
1090 case 11:/* OR imm8, R0 */
1093 case 12:/* TST.B imm8, [R0+GBR] */
1094 sh4r.t = ( MEM_READ_BYTE(R0 + sh4r.gbr) & UIMM8(ir) ? 0 : 1 );
1096 case 13:/* AND.B imm8, [R0+GBR] */
1097 MEM_WRITE_BYTE( R0 + sh4r.gbr,
1098 UIMM8(ir) & MEM_READ_BYTE(R0 + sh4r.gbr) );
1100 case 14:/* XOR.B imm8, [R0+GBR] */
1101 MEM_WRITE_BYTE( R0 + sh4r.gbr,
1102 UIMM8(ir) ^ MEM_READ_BYTE(R0 + sh4r.gbr) );
1104 case 15:/* OR.B imm8, [R0+GBR] */
1105 MEM_WRITE_BYTE( R0 + sh4r.gbr,
1106 UIMM8(ir) | MEM_READ_BYTE(R0 + sh4r.gbr) );
1110 case 13:/* 1101nnnndddddddd */
1111 /* MOV.L [disp8*4 + pc&~3 + 4], Rn */
1112 RN(ir) = MEM_READ_LONG( (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4 );
1114 case 14:/* 1110nnnniiiiiiii */
1118 case 15:/* 1111xxxxxxxxxxxx */
1120 switch( ir&0x000F ) {
1121 case 0: /* FADD FRm, FRn */
1124 case 1: /* FSUB FRm, FRn */
1127 case 2: /* FMUL FRm, FRn */
1128 FRN(ir) = FRN(ir) * FRM(ir);
1130 case 3: /* FDIV FRm, FRn */
1131 FRN(ir) = FRN(ir) / FRM(ir);
1133 case 4: /* FCMP/EQ FRm, FRn */
1134 sh4r.t = ( FRN(ir) == FRM(ir) ? 1 : 0 );
1136 case 5: /* FCMP/GT FRm, FRn */
1137 sh4r.t = ( FRN(ir) > FRM(ir) ? 1 : 0 );
1139 case 6: /* FMOV.S [Rm+R0], FRn */
1140 MEM_FP_READ( RM(ir) + R0, FRNn(ir) );
1142 case 7: /* FMOV.S FRm, [Rn+R0] */
1143 MEM_FP_WRITE( RN(ir) + R0, FRMn(ir) );
1145 case 8: /* FMOV.S [Rm], FRn */
1146 MEM_FP_READ( RM(ir), FRNn(ir) );
1148 case 9: /* FMOV.S [Rm++], FRn */
1149 MEM_FP_READ( RM(ir), FRNn(ir) );
1152 case 10:/* FMOV.S FRm, [Rn] */
1153 MEM_FP_WRITE( RN(ir), FRMn(ir) );
1155 case 11:/* FMOV.S FRm, [--Rn] */
1157 MEM_FP_WRITE( RN(ir), FRMn(ir) );
1159 case 12:/* FMOV FRm, FRn */
1160 if( IS_FPU_DOUBLESIZE() ) {
1167 switch( (ir&0x00F0) >> 4 ) {
1168 case 0: /* FSTS FPUL, FRn */
1171 case 1: /* FLDS FRn, FPUL */
1174 case 2: /* FLOAT FPUL, FRn */
1175 FRN(ir) = (float)FPULi;
1177 case 3: /* FTRC FRn, FPUL */
1178 FPULi = (uint32_t)FRN(ir);
1179 /* FIXME: is this sufficient? */
1181 case 4: /* FNEG FRn */
1184 case 5: /* FABS FRn */
1185 FRN(ir) = fabsf(FRN(ir));
1187 case 6: /* FSQRT FRn */
1188 FRN(ir) = sqrtf(FRN(ir));
1190 case 7: /* FSRRA FRn */
1191 FRN(ir) = 1.0/sqrtf(FRN(ir));
1193 case 8: /* FLDI0 FRn */
1196 case 9: /* FLDI1 FRn */
1199 case 10: /* FCNVSD FPUL, DRn */
1200 if( IS_FPU_DOUBLEPREC() )
1201 DRN(ir) = (double)FPULf;
1204 case 11: /* FCNVDS DRn, FPUL */
1205 if( IS_FPU_DOUBLEPREC() )
1206 FPULf = (float)DRN(ir);
1209 case 14:/* FIPR FVm, FVn */
1210 /* FIXME: This is not going to be entirely accurate
1211 * as the SH4 instruction is less precise. Also
1212 * need to check for 0s and infinities.
1215 float *fr_bank = FR;
1218 fr_bank[tmp2+3] = fr_bank[tmp]*fr_bank[tmp2] +
1219 fr_bank[tmp+1]*fr_bank[tmp2+1] +
1220 fr_bank[tmp+2]*fr_bank[tmp2+2] +
1221 fr_bank[tmp+3]*fr_bank[tmp2+3];
1225 if( (ir&0x0300) == 0x0100 ) { /* FTRV XMTRX,FVn */
1226 float *fvout = FR+FVN(ir);
1228 float fv[4] = { fvout[0], fvout[1], fvout[2], fvout[3] };
1229 fvout[0] = xm[0] * fv[0] + xm[4]*fv[1] +
1230 xm[8]*fv[2] + xm[12]*fv[3];
1231 fvout[1] = xm[1] * fv[0] + xm[5]*fv[1] +
1232 xm[9]*fv[2] + xm[13]*fv[3];
1233 fvout[2] = xm[2] * fv[0] + xm[6]*fv[1] +
1234 xm[10]*fv[2] + xm[14]*fv[3];
1235 fvout[3] = xm[3] * fv[0] + xm[7]*fv[1] +
1236 xm[11]*fv[2] + xm[15]*fv[3];
1239 else if( (ir&0x0100) == 0 ) { /* FSCA FPUL, DRn */
1240 float angle = (((float)(short)(FPULi>>16)) +
1241 ((float)(FPULi&16)/65536.0)) *
1244 FR[reg] = sinf(angle);
1245 FR[reg+1] = cosf(angle);
1248 else if( ir == 0xFBFD ) {
1250 sh4r.fpscr ^= FPSCR_FR;
1253 else if( ir == 0xF3FD ) {
1255 sh4r.fpscr ^= FPSCR_SZ;
1261 case 14:/* FMAC FR0, FRm, FRn */
1262 FRN(ir) += FRM(ir)*FR0;
1268 sh4r.pc = sh4r.new_pc;
1270 sh4r.in_delay_slot = 0;
.