2 * $Id: sh4core.c,v 1.30 2006-08-06 09:43:03 nkeynes Exp $
4 * SH4 emulation core, and parent module for all the SH4 peripheral
7 * Copyright (c) 2005 Nathan Keynes.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
20 #define MODULE sh4_module
23 #include "sh4/sh4core.h"
24 #include "sh4/sh4mmio.h"
30 #define SH4_CALLTRACE 1
32 #define MAX_INT 0x7FFFFFFF
33 #define MIN_INT 0x80000000
34 #define MAX_INTF 2147483647.0
35 #define MIN_INTF -2147483648.0
37 /* CPU-generated exception code/vector pairs */
38 #define EXC_POWER_RESET 0x000 /* vector special */
39 #define EXC_MANUAL_RESET 0x020
40 #define EXC_READ_ADDR_ERR 0x0E0
41 #define EXC_WRITE_ADDR_ERR 0x100
42 #define EXC_SLOT_ILLEGAL 0x1A0
43 #define EXC_ILLEGAL 0x180
44 #define EXV_ILLEGAL 0x100
45 #define EXC_TRAP 0x160
46 #define EXV_TRAP 0x100
47 #define EXC_FPDISABLE 0x800
48 #define EXV_FPDISABLE 0x100
50 /********************** SH4 Module Definition ****************************/
52 void sh4_init( void );
53 void sh4_reset( void );
54 uint32_t sh4_run_slice( uint32_t );
55 void sh4_start( void );
56 void sh4_stop( void );
57 void sh4_save_state( FILE *f );
58 int sh4_load_state( FILE *f );
60 struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset,
61 NULL, sh4_run_slice, sh4_stop,
62 sh4_save_state, sh4_load_state };
64 struct sh4_registers sh4r;
68 register_io_regions( mmio_list_sh4mmio );
75 /* zero everything out, for the sake of having a consistent state. */
76 memset( &sh4r, 0, sizeof(sh4r) );
78 /* Resume running if we were halted */
79 sh4r.sh4_state = SH4_STATE_RUNNING;
82 sh4r.new_pc= 0xA0000002;
83 sh4r.vbr = 0x00000000;
84 sh4r.fpscr = 0x00040001;
87 /* Mem reset will do this, but if we want to reset _just_ the SH4... */
88 MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
90 /* Peripheral modules */
96 static struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
97 static int sh4_breakpoint_count = 0;
99 void sh4_set_breakpoint( uint32_t pc, int type )
101 sh4_breakpoints[sh4_breakpoint_count].address = pc;
102 sh4_breakpoints[sh4_breakpoint_count].type = type;
103 sh4_breakpoint_count++;
106 gboolean sh4_clear_breakpoint( uint32_t pc, int type )
110 for( i=0; i<sh4_breakpoint_count; i++ ) {
111 if( sh4_breakpoints[i].address == pc &&
112 sh4_breakpoints[i].type == type ) {
113 while( ++i < sh4_breakpoint_count ) {
114 sh4_breakpoints[i-1].address = sh4_breakpoints[i].address;
115 sh4_breakpoints[i-1].type = sh4_breakpoints[i].type;
117 sh4_breakpoint_count--;
124 int sh4_get_breakpoint( uint32_t pc )
127 for( i=0; i<sh4_breakpoint_count; i++ ) {
128 if( sh4_breakpoints[i].address == pc )
129 return sh4_breakpoints[i].type;
134 uint32_t sh4_run_slice( uint32_t nanosecs )
136 int target = sh4r.icount + nanosecs / sh4_cpu_period;
137 int start = sh4r.icount;
140 if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
141 if( sh4r.int_pending != 0 )
142 sh4r.sh4_state = SH4_STATE_RUNNING;;
145 for( sh4r.slice_cycle = 0; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
146 if( !sh4_execute_instruction() )
148 #ifdef ENABLE_DEBUG_MODE
149 for( i=0; i<sh4_breakpoint_count; i++ ) {
150 if( sh4_breakpoints[i].address == sh4r.pc ) {
154 if( i != sh4_breakpoint_count ) {
156 if( sh4_breakpoints[i].type == BREAK_ONESHOT )
157 sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );
163 /* If we aborted early, but the cpu is still technically running,
164 * we're doing a hard abort - cut the timeslice back to what we
167 if( sh4r.slice_cycle != nanosecs && sh4r.sh4_state == SH4_STATE_RUNNING ) {
168 nanosecs = sh4r.slice_cycle;
170 if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
171 TMU_run_slice( nanosecs );
172 SCIF_run_slice( nanosecs );
174 sh4r.icount += sh4r.slice_cycle / sh4_cpu_period;
183 void sh4_save_state( FILE *f )
185 fwrite( &sh4r, sizeof(sh4r), 1, f );
186 INTC_save_state( f );
188 SCIF_save_state( f );
191 int sh4_load_state( FILE * f )
193 fread( &sh4r, sizeof(sh4r), 1, f );
194 INTC_load_state( f );
196 return SCIF_load_state( f );
199 /********************** SH4 emulation core ****************************/
201 void sh4_set_pc( int pc )
207 #define UNDEF(ir) do{ ERROR( "Raising exception on undefined instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)
208 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)
210 #if(SH4_CALLTRACE == 1)
211 #define MAX_CALLSTACK 32
212 static struct call_stack {
214 sh4addr_t target_addr;
215 sh4addr_t stack_pointer;
216 } call_stack[MAX_CALLSTACK];
218 static int call_stack_depth = 0;
219 int sh4_call_trace_on = 0;
221 static inline trace_call( sh4addr_t source, sh4addr_t dest )
223 if( call_stack_depth < MAX_CALLSTACK ) {
224 call_stack[call_stack_depth].call_addr = source;
225 call_stack[call_stack_depth].target_addr = dest;
226 call_stack[call_stack_depth].stack_pointer = sh4r.r[15];
231 static inline trace_return( sh4addr_t source, sh4addr_t dest )
233 if( call_stack_depth > 0 ) {
238 void fprint_stack_trace( FILE *f )
240 int i = call_stack_depth -1;
241 if( i >= MAX_CALLSTACK )
242 i = MAX_CALLSTACK - 1;
243 for( ; i >= 0; i-- ) {
244 fprintf( f, "%d. Call from %08X => %08X, SP=%08X\n",
245 (call_stack_depth - i), call_stack[i].call_addr,
246 call_stack[i].target_addr, call_stack[i].stack_pointer );
250 #define TRACE_CALL( source, dest ) trace_call(source, dest)
251 #define TRACE_RETURN( source, dest ) trace_return(source, dest)
253 #define TRACE_CALL( dest, rts )
254 #define TRACE_RETURN( source, dest )
257 #define RAISE( x, v ) do{ \
258 if( sh4r.vbr == 0 ) { \
259 ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
260 dreamcast_stop(); return FALSE; \
262 sh4r.spc = sh4r.pc + 2; \
263 sh4r.ssr = sh4_read_sr(); \
264 sh4r.sgr = sh4r.r[15]; \
265 MMIO_WRITE(MMU,EXPEVT,x); \
266 sh4r.pc = sh4r.vbr + v; \
267 sh4r.new_pc = sh4r.pc + 2; \
268 sh4_load_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
270 return TRUE; } while(0)
272 #define MEM_READ_BYTE( addr ) sh4_read_byte(addr)
273 #define MEM_READ_WORD( addr ) sh4_read_word(addr)
274 #define MEM_READ_LONG( addr ) sh4_read_long(addr)
275 #define MEM_WRITE_BYTE( addr, val ) sh4_write_byte(addr, val)
276 #define MEM_WRITE_WORD( addr, val ) sh4_write_word(addr, val)
277 #define MEM_WRITE_LONG( addr, val ) sh4_write_long(addr, val)
279 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
281 #define MEM_FP_READ( addr, reg ) sh4_read_float( addr, reg );
283 #define MEM_FP_WRITE( addr, reg ) sh4_write_float( addr, reg );
285 #define CHECK( x, c, v ) if( !x ) RAISE( c, v )
286 #define CHECKPRIV() CHECK( IS_SH4_PRIVMODE(), EXC_ILLEGAL, EXV_ILLEGAL )
287 #define CHECKRALIGN16(addr) if( (addr)&0x01 ) RAISE( EXC_READ_ADDR_ERR, EXV_TRAP )
288 #define CHECKRALIGN32(addr) if( (addr)&0x03 ) RAISE( EXC_READ_ADDR_ERR, EXV_TRAP )
289 #define CHECKWALIGN16(addr) if( (addr)&0x01 ) RAISE( EXC_WRITE_ADDR_ERR, EXV_TRAP )
290 #define CHECKWALIGN32(addr) if( (addr)&0x03 ) RAISE( EXC_WRITE_ADDR_ERR, EXV_TRAP )
292 #define CHECKFPUEN() CHECK( IS_FPU_ENABLED(), EXC_FPDISABLE, EXV_FPDISABLE )
293 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); dreamcast_stop(); return FALSE; }
294 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) { RAISE(EXC_SLOT_ILLEGAL,EXV_ILLEGAL); }
296 static void sh4_switch_banks( )
300 memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
301 memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
302 memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
305 static void sh4_load_sr( uint32_t newval )
307 if( (newval ^ sh4r.sr) & SR_RB )
310 sh4r.t = (newval&SR_T) ? 1 : 0;
311 sh4r.s = (newval&SR_S) ? 1 : 0;
312 sh4r.m = (newval&SR_M) ? 1 : 0;
313 sh4r.q = (newval&SR_Q) ? 1 : 0;
317 static void sh4_write_float( uint32_t addr, int reg )
319 if( IS_FPU_DOUBLESIZE() ) {
321 sh4_write_long( addr, *((uint32_t *)&XF((reg)&0x0E)) );
322 sh4_write_long( addr+4, *((uint32_t *)&XF(reg)) );
324 sh4_write_long( addr, *((uint32_t *)&FR(reg)) );
325 sh4_write_long( addr+4, *((uint32_t *)&FR((reg)|0x01)) );
328 sh4_write_long( addr, *((uint32_t *)&FR((reg))) );
332 static void sh4_read_float( uint32_t addr, int reg )
334 if( IS_FPU_DOUBLESIZE() ) {
336 *((uint32_t *)&XF((reg) & 0x0E)) = sh4_read_long(addr);
337 *((uint32_t *)&XF(reg)) = sh4_read_long(addr+4);
339 *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
340 *((uint32_t *)&FR((reg) | 0x01)) = sh4_read_long(addr+4);
343 *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
347 static uint32_t sh4_read_sr( void )
349 /* synchronize sh4r.sr with the various bitflags */
350 sh4r.sr &= SR_MQSTMASK;
351 if( sh4r.t ) sh4r.sr |= SR_T;
352 if( sh4r.s ) sh4r.sr |= SR_S;
353 if( sh4r.m ) sh4r.sr |= SR_M;
354 if( sh4r.q ) sh4r.sr |= SR_Q;
357 /* function for external use */
358 void sh4_raise_exception( int code, int vector )
363 static void sh4_accept_interrupt( void )
365 uint32_t code = intc_accept_interrupt();
366 sh4r.ssr = sh4_read_sr();
368 sh4r.sgr = sh4r.r[15];
369 sh4_load_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
370 MMIO_WRITE( MMU, INTEVT, code );
371 sh4r.pc = sh4r.vbr + 0x600;
372 sh4r.new_pc = sh4r.pc + 2;
373 // WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
376 gboolean sh4_execute_instruction( void )
388 #define RN(ir) sh4r.r[(ir&0x0F00)>>8]
389 #define RN_BANK(ir) sh4r.r_bank[(ir&0x0070)>>4]
390 #define RM(ir) sh4r.r[(ir&0x00F0)>>4]
391 #define DISP4(ir) (ir&0x000F) /* 4-bit displacements are *NOT* sign-extended */
392 #define DISP8(ir) (ir&0x00FF)
393 #define PCDISP8(ir) SIGNEXT8(ir&0x00FF)
394 #define IMM8(ir) SIGNEXT8(ir&0x00FF)
395 #define UIMM8(ir) (ir&0x00FF) /* Unsigned immmediate */
396 #define DISP12(ir) SIGNEXT12(ir&0x0FFF)
397 #define FRNn(ir) ((ir&0x0F00)>>8)
398 #define FRMn(ir) ((ir&0x00F0)>>4)
399 #define DRNn(ir) ((ir&0x0E00)>>9)
400 #define DRMn(ir) ((ir&0x00E0)>>5)
401 #define FVN(ir) ((ir&0x0C00)>>8)
402 #define FVM(ir) ((ir&0x0300)>>6)
403 #define FRN(ir) FR(FRNn(ir))
404 #define FRM(ir) FR(FRMn(ir))
405 #define FRNi(ir) (*((uint32_t *)&FR(FRNn(ir))))
406 #define FRMi(ir) (*((uint32_t *)&FR(FRMn(ir))))
407 #define DRN(ir) DRb(DRNn(ir), ir&0x0100)
408 #define DRM(ir) DRb(DRMn(ir),ir&0x0010)
409 #define DRNi(ir) (*((uint64_t *)&DR(FRNn(ir))))
410 #define DRMi(ir) (*((uint64_t *)&DR(FRMn(ir))))
411 #define FPULf *((float *)&sh4r.fpul)
412 #define FPULi (sh4r.fpul)
414 if( SH4_INT_PENDING() )
415 sh4_accept_interrupt();
418 if( pc > 0xFFFFFF00 ) {
420 syscall_invoke( pc );
421 sh4r.in_delay_slot = 0;
422 pc = sh4r.pc = sh4r.pr;
423 sh4r.new_pc = sh4r.pc + 2;
426 ir = MEM_READ_WORD(pc);
429 switch( (ir&0xF000)>>12 ) {
430 case 0: /* 0000nnnnmmmmxxxx */
431 switch( ir&0x000F ) {
433 switch( (ir&0x00F0)>>4 ) {
434 case 0: /* STC SR, Rn */
436 RN(ir) = sh4_read_sr();
438 case 1: /* STC GBR, Rn */
441 case 2: /* STC VBR, Rn */
445 case 3: /* STC SSR, Rn */
449 case 4: /* STC SPC, Rn */
453 case 8: case 9: case 10: case 11: case 12: case 13:
454 case 14: case 15:/* STC Rm_bank, Rn */
456 RN(ir) = RN_BANK(ir);
462 switch( (ir&0x00F0)>>4 ) {
463 case 0: /* BSRF Rn */
464 CHECKDEST( pc + 4 + RN(ir) );
466 sh4r.in_delay_slot = 1;
467 sh4r.pr = sh4r.pc + 4;
468 sh4r.pc = sh4r.new_pc;
469 sh4r.new_pc = pc + 4 + RN(ir);
470 TRACE_CALL( pc, sh4r.new_pc );
472 case 2: /* BRAF Rn */
473 CHECKDEST( pc + 4 + RN(ir) );
475 sh4r.in_delay_slot = 1;
476 sh4r.pc = sh4r.new_pc;
477 sh4r.new_pc = pc + 4 + RN(ir);
479 case 8: /* PREF [Rn] */
481 if( (tmp & 0xFC000000) == 0xE0000000 ) {
482 /* Store queue operation */
483 int queue = (tmp&0x20)>>2;
484 int32_t *src = &sh4r.store_queue[queue];
485 uint32_t hi = (MMIO_READ( MMU, (queue == 0 ? QACR0 : QACR1) ) & 0x1C) << 24;
486 uint32_t target = tmp&0x03FFFFE0 | hi;
487 mem_copy_to_sh4( target, src, 32 );
490 case 9: /* OCBI [Rn] */
491 case 10:/* OCBP [Rn] */
492 case 11:/* OCBWB [Rn] */
495 case 12:/* MOVCA.L R0, [Rn] */
498 MEM_WRITE_LONG( tmp, R0 );
503 case 4: /* MOV.B Rm, [R0 + Rn] */
504 MEM_WRITE_BYTE( R0 + RN(ir), RM(ir) );
506 case 5: /* MOV.W Rm, [R0 + Rn] */
507 CHECKWALIGN16( R0 + RN(ir) );
508 MEM_WRITE_WORD( R0 + RN(ir), RM(ir) );
510 case 6: /* MOV.L Rm, [R0 + Rn] */
511 CHECKWALIGN32( R0 + RN(ir) );
512 MEM_WRITE_LONG( R0 + RN(ir), RM(ir) );
514 case 7: /* MUL.L Rm, Rn */
515 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
519 switch( (ir&0x0FF0)>>4 ) {
541 if( (ir&0x00F0) == 0x20 ) /* MOVT Rn */
543 else if( ir == 0x0019 ) /* DIV0U */
544 sh4r.m = sh4r.q = sh4r.t = 0;
545 else if( ir == 0x0009 )
550 switch( (ir&0x00F0) >> 4 ) {
551 case 0: /* STS MACH, Rn */
552 RN(ir) = sh4r.mac >> 32;
554 case 1: /* STS MACL, Rn */
555 RN(ir) = (uint32_t)sh4r.mac;
557 case 2: /* STS PR, Rn */
560 case 3: /* STC SGR, Rn */
564 case 5:/* STS FPUL, Rn */
567 case 6: /* STS FPSCR, Rn */
570 case 15:/* STC DBR, Rn */
578 switch( (ir&0x0FF0)>>4 ) {
580 CHECKDEST( sh4r.pr );
582 sh4r.in_delay_slot = 1;
583 sh4r.pc = sh4r.new_pc;
584 sh4r.new_pc = sh4r.pr;
585 TRACE_RETURN( pc, sh4r.new_pc );
588 if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
589 sh4r.sh4_state = SH4_STATE_STANDBY;
591 sh4r.sh4_state = SH4_STATE_SLEEP;
593 return FALSE; /* Halt CPU */
596 CHECKDEST( sh4r.spc );
598 sh4r.in_delay_slot = 1;
599 sh4r.pc = sh4r.new_pc;
600 sh4r.new_pc = sh4r.spc;
601 sh4_load_sr( sh4r.ssr );
606 case 12:/* MOV.B [R0+R%d], R%d */
607 RN(ir) = MEM_READ_BYTE( R0 + RM(ir) );
609 case 13:/* MOV.W [R0+R%d], R%d */
610 CHECKRALIGN16( R0 + RM(ir) );
611 RN(ir) = MEM_READ_WORD( R0 + RM(ir) );
613 case 14:/* MOV.L [R0+R%d], R%d */
614 CHECKRALIGN32( R0 + RM(ir) );
615 RN(ir) = MEM_READ_LONG( R0 + RM(ir) );
617 case 15:/* MAC.L [Rm++], [Rn++] */
618 CHECKRALIGN32( RM(ir) );
619 CHECKRALIGN32( RN(ir) );
620 tmpl = ( SIGNEXT32(MEM_READ_LONG(RM(ir))) *
621 SIGNEXT32(MEM_READ_LONG(RN(ir))) );
623 /* 48-bit Saturation. Yuch */
624 tmpl += SIGNEXT48(sh4r.mac);
625 if( tmpl < 0xFFFF800000000000LL )
626 tmpl = 0xFFFF800000000000LL;
627 else if( tmpl > 0x00007FFFFFFFFFFFLL )
628 tmpl = 0x00007FFFFFFFFFFFLL;
629 sh4r.mac = (sh4r.mac&0xFFFF000000000000LL) |
630 (tmpl&0x0000FFFFFFFFFFFFLL);
631 } else sh4r.mac = tmpl;
640 case 1: /* 0001nnnnmmmmdddd */
641 /* MOV.L Rm, [Rn + disp4*4] */
642 tmp = RN(ir) + (DISP4(ir)<<2);
643 CHECKWALIGN32( tmp );
644 MEM_WRITE_LONG( tmp, RM(ir) );
646 case 2: /* 0010nnnnmmmmxxxx */
647 switch( ir&0x000F ) {
648 case 0: /* MOV.B Rm, [Rn] */
649 MEM_WRITE_BYTE( RN(ir), RM(ir) );
651 case 1: /* MOV.W Rm, [Rn] */
652 CHECKWALIGN16( RN(ir) );
653 MEM_WRITE_WORD( RN(ir), RM(ir) );
655 case 2: /* MOV.L Rm, [Rn] */
656 CHECKWALIGN32( RN(ir) );
657 MEM_WRITE_LONG( RN(ir), RM(ir) );
661 case 4: /* MOV.B Rm, [--Rn] */
663 MEM_WRITE_BYTE( RN(ir), RM(ir) );
665 case 5: /* MOV.W Rm, [--Rn] */
667 CHECKWALIGN16( RN(ir) );
668 MEM_WRITE_WORD( RN(ir), RM(ir) );
670 case 6: /* MOV.L Rm, [--Rn] */
672 CHECKWALIGN32( RN(ir) );
673 MEM_WRITE_LONG( RN(ir), RM(ir) );
675 case 7: /* DIV0S Rm, Rn */
678 sh4r.t = sh4r.q ^ sh4r.m;
680 case 8: /* TST Rm, Rn */
681 sh4r.t = (RN(ir)&RM(ir) ? 0 : 1);
683 case 9: /* AND Rm, Rn */
686 case 10:/* XOR Rm, Rn */
689 case 11:/* OR Rm, Rn */
692 case 12:/* CMP/STR Rm, Rn */
693 /* set T = 1 if any byte in RM & RN is the same */
694 tmp = RM(ir) ^ RN(ir);
695 sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
696 (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
698 case 13:/* XTRCT Rm, Rn */
699 RN(ir) = (RN(ir)>>16) | (RM(ir)<<16);
701 case 14:/* MULU.W Rm, Rn */
702 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
703 (uint32_t)((RM(ir)&0xFFFF) * (RN(ir)&0xFFFF));
705 case 15:/* MULS.W Rm, Rn */
706 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
707 (uint32_t)(SIGNEXT32(RM(ir)&0xFFFF) * SIGNEXT32(RN(ir)&0xFFFF));
711 case 3: /* 0011nnnnmmmmxxxx */
712 switch( ir&0x000F ) {
713 case 0: /* CMP/EQ Rm, Rn */
714 sh4r.t = ( RM(ir) == RN(ir) ? 1 : 0 );
716 case 2: /* CMP/HS Rm, Rn */
717 sh4r.t = ( RN(ir) >= RM(ir) ? 1 : 0 );
719 case 3: /* CMP/GE Rm, Rn */
720 sh4r.t = ( ((int32_t)RN(ir)) >= ((int32_t)RM(ir)) ? 1 : 0 );
722 case 4: { /* DIV1 Rm, Rn */
723 /* This is just from the sh4p manual with some
724 * simplifications (someone want to check it's correct? :)
725 * Why they couldn't just provide a real DIV instruction...
726 * Please oh please let the translator batch these things
727 * up into a single DIV... */
728 uint32_t tmp0, tmp1, tmp2, dir;
730 dir = sh4r.q ^ sh4r.m;
731 sh4r.q = (RN(ir) >> 31);
733 RN(ir) = (RN(ir) << 1) | sh4r.t;
737 tmp1 = (RN(ir)<tmp0 ? 1 : 0 );
740 tmp1 = (RN(ir)>tmp0 ? 1 : 0 );
742 sh4r.q ^= sh4r.m ^ tmp1;
743 sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
745 case 5: /* DMULU.L Rm, Rn */
746 sh4r.mac = ((uint64_t)RM(ir)) * ((uint64_t)RN(ir));
748 case 6: /* CMP/HI Rm, Rn */
749 sh4r.t = ( RN(ir) > RM(ir) ? 1 : 0 );
751 case 7: /* CMP/GT Rm, Rn */
752 sh4r.t = ( ((int32_t)RN(ir)) > ((int32_t)RM(ir)) ? 1 : 0 );
754 case 8: /* SUB Rm, Rn */
757 case 10:/* SUBC Rm, Rn */
759 RN(ir) = RN(ir) - RM(ir) - sh4r.t;
760 sh4r.t = (RN(ir) > tmp || (RN(ir) == tmp && sh4r.t == 1));
762 case 11:/* SUBV Rm, Rn */
765 case 12:/* ADD Rm, Rn */
768 case 13:/* DMULS.L Rm, Rn */
769 sh4r.mac = SIGNEXT32(RM(ir)) * SIGNEXT32(RN(ir));
771 case 14:/* ADDC Rm, Rn */
773 RN(ir) += RM(ir) + sh4r.t;
774 sh4r.t = ( RN(ir) < tmp || (RN(ir) == tmp && sh4r.t != 0) ? 1 : 0 );
776 case 15:/* ADDV Rm, Rn */
782 case 4: /* 0100nnnnxxxxxxxx */
783 switch( ir&0x00FF ) {
784 case 0x00: /* SHLL Rn */
785 sh4r.t = RN(ir) >> 31;
788 case 0x01: /* SHLR Rn */
789 sh4r.t = RN(ir) & 0x00000001;
792 case 0x02: /* STS.L MACH, [--Rn] */
794 CHECKWALIGN32( RN(ir) );
795 MEM_WRITE_LONG( RN(ir), (sh4r.mac>>32) );
797 case 0x03: /* STC.L SR, [--Rn] */
800 CHECKWALIGN32( RN(ir) );
801 MEM_WRITE_LONG( RN(ir), sh4_read_sr() );
803 case 0x04: /* ROTL Rn */
804 sh4r.t = RN(ir) >> 31;
808 case 0x05: /* ROTR Rn */
809 sh4r.t = RN(ir) & 0x00000001;
811 RN(ir) |= (sh4r.t << 31);
813 case 0x06: /* LDS.L [Rn++], MACH */
814 CHECKRALIGN32( RN(ir) );
815 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
816 (((uint64_t)MEM_READ_LONG(RN(ir)))<<32);
819 case 0x07: /* LDC.L [Rn++], SR */
821 CHECKWALIGN32( RN(ir) );
822 sh4_load_sr( MEM_READ_LONG(RN(ir)) );
825 case 0x08: /* SHLL2 Rn */
828 case 0x09: /* SHLR2 Rn */
831 case 0x0A: /* LDS Rn, MACH */
832 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
833 (((uint64_t)RN(ir))<<32);
835 case 0x0B: /* JSR [Rn] */
838 sh4r.in_delay_slot = 1;
839 sh4r.pc = sh4r.new_pc;
840 sh4r.new_pc = RN(ir);
842 TRACE_CALL( pc, sh4r.new_pc );
844 case 0x0E: /* LDC Rn, SR */
846 sh4_load_sr( RN(ir) );
848 case 0x10: /* DT Rn */
850 sh4r.t = ( RN(ir) == 0 ? 1 : 0 );
852 case 0x11: /* CMP/PZ Rn */
853 sh4r.t = ( ((int32_t)RN(ir)) >= 0 ? 1 : 0 );
855 case 0x12: /* STS.L MACL, [--Rn] */
857 CHECKWALIGN32( RN(ir) );
858 MEM_WRITE_LONG( RN(ir), (uint32_t)sh4r.mac );
860 case 0x13: /* STC.L GBR, [--Rn] */
862 CHECKWALIGN32( RN(ir) );
863 MEM_WRITE_LONG( RN(ir), sh4r.gbr );
865 case 0x15: /* CMP/PL Rn */
866 sh4r.t = ( ((int32_t)RN(ir)) > 0 ? 1 : 0 );
868 case 0x16: /* LDS.L [Rn++], MACL */
869 CHECKRALIGN32( RN(ir) );
870 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
871 (uint64_t)((uint32_t)MEM_READ_LONG(RN(ir)));
874 case 0x17: /* LDC.L [Rn++], GBR */
875 CHECKRALIGN32( RN(ir) );
876 sh4r.gbr = MEM_READ_LONG(RN(ir));
879 case 0x18: /* SHLL8 Rn */
882 case 0x19: /* SHLR8 Rn */
885 case 0x1A: /* LDS Rn, MACL */
886 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
887 (uint64_t)((uint32_t)(RN(ir)));
889 case 0x1B: /* TAS.B [Rn] */
890 tmp = MEM_READ_BYTE( RN(ir) );
891 sh4r.t = ( tmp == 0 ? 1 : 0 );
892 MEM_WRITE_BYTE( RN(ir), tmp | 0x80 );
894 case 0x1E: /* LDC Rn, GBR */
897 case 0x20: /* SHAL Rn */
898 sh4r.t = RN(ir) >> 31;
901 case 0x21: /* SHAR Rn */
902 sh4r.t = RN(ir) & 0x00000001;
903 RN(ir) = ((int32_t)RN(ir)) >> 1;
905 case 0x22: /* STS.L PR, [--Rn] */
907 CHECKWALIGN32( RN(ir) );
908 MEM_WRITE_LONG( RN(ir), sh4r.pr );
910 case 0x23: /* STC.L VBR, [--Rn] */
913 CHECKWALIGN32( RN(ir) );
914 MEM_WRITE_LONG( RN(ir), sh4r.vbr );
916 case 0x24: /* ROTCL Rn */
922 case 0x25: /* ROTCR Rn */
923 tmp = RN(ir) & 0x00000001;
925 RN(ir) |= (sh4r.t << 31 );
928 case 0x26: /* LDS.L [Rn++], PR */
929 CHECKRALIGN32( RN(ir) );
930 sh4r.pr = MEM_READ_LONG( RN(ir) );
933 case 0x27: /* LDC.L [Rn++], VBR */
935 CHECKRALIGN32( RN(ir) );
936 sh4r.vbr = MEM_READ_LONG(RN(ir));
939 case 0x28: /* SHLL16 Rn */
942 case 0x29: /* SHLR16 Rn */
945 case 0x2A: /* LDS Rn, PR */
948 case 0x2B: /* JMP [Rn] */
951 sh4r.in_delay_slot = 1;
952 sh4r.pc = sh4r.new_pc;
953 sh4r.new_pc = RN(ir);
955 case 0x2E: /* LDC Rn, VBR */
959 case 0x32: /* STC.L SGR, [--Rn] */
962 CHECKWALIGN32( RN(ir) );
963 MEM_WRITE_LONG( RN(ir), sh4r.sgr );
965 case 0x33: /* STC.L SSR, [--Rn] */
968 CHECKWALIGN32( RN(ir) );
969 MEM_WRITE_LONG( RN(ir), sh4r.ssr );
971 case 0x37: /* LDC.L [Rn++], SSR */
973 CHECKRALIGN32( RN(ir) );
974 sh4r.ssr = MEM_READ_LONG(RN(ir));
977 case 0x3E: /* LDC Rn, SSR */
981 case 0x43: /* STC.L SPC, [--Rn] */
984 CHECKWALIGN32( RN(ir) );
985 MEM_WRITE_LONG( RN(ir), sh4r.spc );
987 case 0x47: /* LDC.L [Rn++], SPC */
989 CHECKRALIGN32( RN(ir) );
990 sh4r.spc = MEM_READ_LONG(RN(ir));
993 case 0x4E: /* LDC Rn, SPC */
997 case 0x52: /* STS.L FPUL, [--Rn] */
999 CHECKWALIGN32( RN(ir) );
1000 MEM_WRITE_LONG( RN(ir), sh4r.fpul );
1002 case 0x56: /* LDS.L [Rn++], FPUL */
1003 CHECKRALIGN32( RN(ir) );
1004 sh4r.fpul = MEM_READ_LONG(RN(ir));
1007 case 0x5A: /* LDS Rn, FPUL */
1010 case 0x62: /* STS.L FPSCR, [--Rn] */
1012 CHECKWALIGN32( RN(ir) );
1013 MEM_WRITE_LONG( RN(ir), sh4r.fpscr );
1015 case 0x66: /* LDS.L [Rn++], FPSCR */
1016 CHECKRALIGN32( RN(ir) );
1017 sh4r.fpscr = MEM_READ_LONG(RN(ir));
1020 case 0x6A: /* LDS Rn, FPSCR */
1021 sh4r.fpscr = RN(ir);
1023 case 0xF2: /* STC.L DBR, [--Rn] */
1026 CHECKWALIGN32( RN(ir) );
1027 MEM_WRITE_LONG( RN(ir), sh4r.dbr );
1029 case 0xF6: /* LDC.L [Rn++], DBR */
1031 CHECKRALIGN32( RN(ir) );
1032 sh4r.dbr = MEM_READ_LONG(RN(ir));
1035 case 0xFA: /* LDC Rn, DBR */
1039 case 0x83: case 0x93: case 0xA3: case 0xB3: case 0xC3:
1040 case 0xD3: case 0xE3: case 0xF3: /* STC.L Rn_BANK, [--Rn] */
1043 CHECKWALIGN32( RN(ir) );
1044 MEM_WRITE_LONG( RN(ir), RN_BANK(ir) );
1046 case 0x87: case 0x97: case 0xA7: case 0xB7: case 0xC7:
1047 case 0xD7: case 0xE7: case 0xF7: /* LDC.L [Rn++], Rn_BANK */
1049 CHECKRALIGN32( RN(ir) );
1050 RN_BANK(ir) = MEM_READ_LONG( RN(ir) );
1053 case 0x8E: case 0x9E: case 0xAE: case 0xBE: case 0xCE:
1054 case 0xDE: case 0xEE: case 0xFE: /* LDC Rm, Rn_BANK */
1056 RN_BANK(ir) = RM(ir);
1059 if( (ir&0x000F) == 0x0F ) {
1060 /* MAC.W [Rm++], [Rn++] */
1061 CHECKRALIGN16( RN(ir) );
1062 CHECKRALIGN16( RM(ir) );
1063 tmp = SIGNEXT16(MEM_READ_WORD(RM(ir))) *
1064 SIGNEXT16(MEM_READ_WORD(RN(ir)));
1068 } else sh4r.mac += SIGNEXT32(tmp);
1071 } else if( (ir&0x000F) == 0x0C ) {
1074 if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);
1075 else if( (tmp & 0x1F) == 0 )
1076 RN(ir) = ((int32_t)RN(ir)) >> 31;
1078 RN(ir) = ((int32_t)RN(ir)) >> (((~RM(ir)) & 0x1F)+1);
1079 } else if( (ir&0x000F) == 0x0D ) {
1082 if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);
1083 else if( (tmp & 0x1F) == 0 ) RN(ir) = 0;
1084 else RN(ir) >>= (((~tmp) & 0x1F)+1);
1088 case 5: /* 0101nnnnmmmmdddd */
1089 /* MOV.L [Rm + disp4*4], Rn */
1090 tmp = RM(ir) + (DISP4(ir)<<2);
1091 CHECKRALIGN32( tmp );
1092 RN(ir) = MEM_READ_LONG( tmp );
1094 case 6: /* 0110xxxxxxxxxxxx */
1095 switch( ir&0x000f ) {
1096 case 0: /* MOV.B [Rm], Rn */
1097 RN(ir) = MEM_READ_BYTE( RM(ir) );
1099 case 1: /* MOV.W [Rm], Rn */
1100 CHECKRALIGN16( RM(ir) );
1101 RN(ir) = MEM_READ_WORD( RM(ir) );
1103 case 2: /* MOV.L [Rm], Rn */
1104 CHECKRALIGN32( RM(ir) );
1105 RN(ir) = MEM_READ_LONG( RM(ir) );
1107 case 3: /* MOV Rm, Rn */
1110 case 4: /* MOV.B [Rm++], Rn */
1111 RN(ir) = MEM_READ_BYTE( RM(ir) );
1114 case 5: /* MOV.W [Rm++], Rn */
1115 CHECKRALIGN16( RM(ir) );
1116 RN(ir) = MEM_READ_WORD( RM(ir) );
1119 case 6: /* MOV.L [Rm++], Rn */
1120 CHECKRALIGN32( RM(ir) );
1121 RN(ir) = MEM_READ_LONG( RM(ir) );
1124 case 7: /* NOT Rm, Rn */
1127 case 8: /* SWAP.B Rm, Rn */
1128 RN(ir) = (RM(ir)&0xFFFF0000) | ((RM(ir)&0x0000FF00)>>8) |
1129 ((RM(ir)&0x000000FF)<<8);
1131 case 9: /* SWAP.W Rm, Rn */
1132 RN(ir) = (RM(ir)>>16) | (RM(ir)<<16);
1134 case 10:/* NEGC Rm, Rn */
1136 RN(ir) = tmp - sh4r.t;
1137 sh4r.t = ( 0<tmp || tmp<RN(ir) ? 1 : 0 );
1139 case 11:/* NEG Rm, Rn */
1140 RN(ir) = 0 - RM(ir);
1142 case 12:/* EXTU.B Rm, Rn */
1143 RN(ir) = RM(ir)&0x000000FF;
1145 case 13:/* EXTU.W Rm, Rn */
1146 RN(ir) = RM(ir)&0x0000FFFF;
1148 case 14:/* EXTS.B Rm, Rn */
1149 RN(ir) = SIGNEXT8( RM(ir)&0x000000FF );
1151 case 15:/* EXTS.W Rm, Rn */
1152 RN(ir) = SIGNEXT16( RM(ir)&0x0000FFFF );
1156 case 7: /* 0111nnnniiiiiiii */
1160 case 8: /* 1000xxxxxxxxxxxx */
1161 switch( (ir&0x0F00) >> 8 ) {
1162 case 0: /* MOV.B R0, [Rm + disp4] */
1163 MEM_WRITE_BYTE( RM(ir) + DISP4(ir), R0 );
1165 case 1: /* MOV.W R0, [Rm + disp4*2] */
1166 tmp = RM(ir) + (DISP4(ir)<<1);
1167 CHECKWALIGN16( tmp );
1168 MEM_WRITE_WORD( tmp, R0 );
1170 case 4: /* MOV.B [Rm + disp4], R0 */
1171 R0 = MEM_READ_BYTE( RM(ir) + DISP4(ir) );
1173 case 5: /* MOV.W [Rm + disp4*2], R0 */
1174 tmp = RM(ir) + (DISP4(ir)<<1);
1175 CHECKRALIGN16( tmp );
1176 R0 = MEM_READ_WORD( tmp );
1178 case 8: /* CMP/EQ imm, R0 */
1179 sh4r.t = ( R0 == IMM8(ir) ? 1 : 0 );
1181 case 9: /* BT disp8 */
1184 CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
1185 sh4r.pc += (PCDISP8(ir)<<1) + 4;
1186 sh4r.new_pc = sh4r.pc + 2;
1190 case 11:/* BF disp8 */
1193 CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
1194 sh4r.pc += (PCDISP8(ir)<<1) + 4;
1195 sh4r.new_pc = sh4r.pc + 2;
1199 case 13:/* BT/S disp8 */
1202 CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
1203 sh4r.in_delay_slot = 1;
1204 sh4r.pc = sh4r.new_pc;
1205 sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;
1206 sh4r.in_delay_slot = 1;
1210 case 15:/* BF/S disp8 */
1213 CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
1214 sh4r.in_delay_slot = 1;
1215 sh4r.pc = sh4r.new_pc;
1216 sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;
1223 case 9: /* 1001xxxxxxxxxxxx */
1224 /* MOV.W [disp8*2 + pc + 4], Rn */
1225 tmp = pc + 4 + (DISP8(ir)<<1);
1226 CHECKRALIGN16( tmp );
1227 RN(ir) = MEM_READ_WORD( tmp );
1229 case 10:/* 1010dddddddddddd */
1231 CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 )
1233 sh4r.in_delay_slot = 1;
1234 sh4r.pc = sh4r.new_pc;
1235 sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);
1237 case 11:/* 1011dddddddddddd */
1239 CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 )
1241 sh4r.in_delay_slot = 1;
1243 sh4r.pc = sh4r.new_pc;
1244 sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);
1245 TRACE_CALL( pc, sh4r.new_pc );
1247 case 12:/* 1100xxxxdddddddd */
1248 switch( (ir&0x0F00)>>8 ) {
1249 case 0: /* MOV.B R0, [GBR + disp8] */
1250 MEM_WRITE_BYTE( sh4r.gbr + DISP8(ir), R0 );
1252 case 1: /* MOV.W R0, [GBR + disp8*2] */
1253 tmp = sh4r.gbr + (DISP8(ir)<<1);
1254 CHECKWALIGN16( tmp );
1255 MEM_WRITE_WORD( tmp, R0 );
1257 case 2: /*MOV.L R0, [GBR + disp8*4] */
1258 tmp = sh4r.gbr + (DISP8(ir)<<2);
1259 CHECKWALIGN32( tmp );
1260 MEM_WRITE_LONG( tmp, R0 );
1262 case 3: /* TRAPA imm8 */
1264 sh4r.in_delay_slot = 1;
1265 MMIO_WRITE( MMU, TRA, UIMM8(ir)<<2 );
1266 RAISE( EXC_TRAP, EXV_TRAP );
1268 case 4: /* MOV.B [GBR + disp8], R0 */
1269 R0 = MEM_READ_BYTE( sh4r.gbr + DISP8(ir) );
1271 case 5: /* MOV.W [GBR + disp8*2], R0 */
1272 tmp = sh4r.gbr + (DISP8(ir)<<1);
1273 CHECKRALIGN16( tmp );
1274 R0 = MEM_READ_WORD( tmp );
1276 case 6: /* MOV.L [GBR + disp8*4], R0 */
1277 tmp = sh4r.gbr + (DISP8(ir)<<2);
1278 CHECKRALIGN32( tmp );
1279 R0 = MEM_READ_LONG( tmp );
1281 case 7: /* MOVA disp8 + pc&~3 + 4, R0 */
1282 R0 = (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4;
1284 case 8: /* TST imm8, R0 */
1285 sh4r.t = (R0 & UIMM8(ir) ? 0 : 1);
1287 case 9: /* AND imm8, R0 */
1290 case 10:/* XOR imm8, R0 */
1293 case 11:/* OR imm8, R0 */
1296 case 12:/* TST.B imm8, [R0+GBR] */
1297 sh4r.t = ( MEM_READ_BYTE(R0 + sh4r.gbr) & UIMM8(ir) ? 0 : 1 );
1299 case 13:/* AND.B imm8, [R0+GBR] */
1300 MEM_WRITE_BYTE( R0 + sh4r.gbr,
1301 UIMM8(ir) & MEM_READ_BYTE(R0 + sh4r.gbr) );
1303 case 14:/* XOR.B imm8, [R0+GBR] */
1304 MEM_WRITE_BYTE( R0 + sh4r.gbr,
1305 UIMM8(ir) ^ MEM_READ_BYTE(R0 + sh4r.gbr) );
1307 case 15:/* OR.B imm8, [R0+GBR] */
1308 MEM_WRITE_BYTE( R0 + sh4r.gbr,
1309 UIMM8(ir) | MEM_READ_BYTE(R0 + sh4r.gbr) );
1313 case 13:/* 1101nnnndddddddd */
1314 /* MOV.L [disp8*4 + pc&~3 + 4], Rn */
1315 tmp = (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4;
1316 CHECKRALIGN32( tmp );
1317 RN(ir) = MEM_READ_LONG( tmp );
1319 case 14:/* 1110nnnniiiiiiii */
1323 case 15:/* 1111xxxxxxxxxxxx */
1325 if( IS_FPU_DOUBLEPREC() ) {
1326 switch( ir&0x000F ) {
1327 case 0: /* FADD FRm, FRn */
1330 case 1: /* FSUB FRm, FRn */
1333 case 2: /* FMUL FRm, FRn */
1334 DRN(ir) = DRN(ir) * DRM(ir);
1336 case 3: /* FDIV FRm, FRn */
1337 DRN(ir) = DRN(ir) / DRM(ir);
1339 case 4: /* FCMP/EQ FRm, FRn */
1340 sh4r.t = ( DRN(ir) == DRM(ir) ? 1 : 0 );
1342 case 5: /* FCMP/GT FRm, FRn */
1343 sh4r.t = ( DRN(ir) > DRM(ir) ? 1 : 0 );
1345 case 6: /* FMOV.S [Rm+R0], FRn */
1346 MEM_FP_READ( RM(ir) + R0, FRNn(ir) );
1348 case 7: /* FMOV.S FRm, [Rn+R0] */
1349 MEM_FP_WRITE( RN(ir) + R0, FRMn(ir) );
1351 case 8: /* FMOV.S [Rm], FRn */
1352 MEM_FP_READ( RM(ir), FRNn(ir) );
1354 case 9: /* FMOV.S [Rm++], FRn */
1355 MEM_FP_READ( RM(ir), FRNn(ir) );
1358 case 10:/* FMOV.S FRm, [Rn] */
1359 MEM_FP_WRITE( RN(ir), FRMn(ir) );
1361 case 11:/* FMOV.S FRm, [--Rn] */
1363 MEM_FP_WRITE( RN(ir), FRMn(ir) );
1365 case 12:/* FMOV FRm, FRn */
1366 if( IS_FPU_DOUBLESIZE() )
1372 switch( (ir&0x00F0) >> 4 ) {
1373 case 0: /* FSTS FPUL, FRn */
1376 case 1: /* FLDS FRn,FPUL */
1379 case 2: /* FLOAT FPUL, FRn */
1380 DRN(ir) = (float)FPULi;
1382 case 3: /* FTRC FRn, FPUL */
1384 if( dtmp >= MAX_INTF )
1386 else if( dtmp <= MIN_INTF )
1389 FPULi = (int32_t)dtmp;
1391 case 4: /* FNEG FRn */
1394 case 5: /* FABS FRn */
1395 DRN(ir) = fabs(DRN(ir));
1397 case 6: /* FSQRT FRn */
1398 DRN(ir) = sqrt(DRN(ir));
1400 case 7: /* FSRRA FRn */
1401 /* NO-OP when PR=1 */
1403 case 8: /* FLDI0 FRn */
1406 case 9: /* FLDI1 FRn */
1409 case 10: /* FCNVSD FPUL, DRn */
1410 if( ! IS_FPU_DOUBLESIZE() )
1411 DRN(ir) = (double)FPULf;
1413 case 11: /* FCNVDS DRn, FPUL */
1414 if( ! IS_FPU_DOUBLESIZE() )
1415 FPULf = (float)DRN(ir);
1417 case 14:/* FIPR FVm, FVn */
1418 /* NO-OP when PR=1 */
1421 if( (ir&0x0300) == 0x0100 ) { /* FTRV XMTRX,FVn */
1422 /* NO-OP when PR=1 */
1425 else if( (ir&0x0100) == 0 ) { /* FSCA FPUL, DRn */
1426 /* NO-OP when PR=1 */
1429 else if( ir == 0xFBFD ) {
1431 sh4r.fpscr ^= FPSCR_FR;
1434 else if( ir == 0xF3FD ) {
1436 sh4r.fpscr ^= FPSCR_SZ;
1442 case 14:/* FMAC FR0, FRm, FRn */
1443 DRN(ir) += DRM(ir)*DR0;
1447 } else { /* Single precision */
1448 switch( ir&0x000F ) {
1449 case 0: /* FADD FRm, FRn */
1452 case 1: /* FSUB FRm, FRn */
1455 case 2: /* FMUL FRm, FRn */
1456 FRN(ir) = FRN(ir) * FRM(ir);
1458 case 3: /* FDIV FRm, FRn */
1459 FRN(ir) = FRN(ir) / FRM(ir);
1461 case 4: /* FCMP/EQ FRm, FRn */
1462 sh4r.t = ( FRN(ir) == FRM(ir) ? 1 : 0 );
1464 case 5: /* FCMP/GT FRm, FRn */
1465 sh4r.t = ( FRN(ir) > FRM(ir) ? 1 : 0 );
1467 case 6: /* FMOV.S [Rm+R0], FRn */
1468 MEM_FP_READ( RM(ir) + R0, FRNn(ir) );
1470 case 7: /* FMOV.S FRm, [Rn+R0] */
1471 MEM_FP_WRITE( RN(ir) + R0, FRMn(ir) );
1473 case 8: /* FMOV.S [Rm], FRn */
1474 MEM_FP_READ( RM(ir), FRNn(ir) );
1476 case 9: /* FMOV.S [Rm++], FRn */
1477 MEM_FP_READ( RM(ir), FRNn(ir) );
1480 case 10:/* FMOV.S FRm, [Rn] */
1481 MEM_FP_WRITE( RN(ir), FRMn(ir) );
1483 case 11:/* FMOV.S FRm, [--Rn] */
1485 MEM_FP_WRITE( RN(ir), FRMn(ir) );
1487 case 12:/* FMOV FRm, FRn */
1488 if( IS_FPU_DOUBLESIZE() )
1494 switch( (ir&0x00F0) >> 4 ) {
1495 case 0: /* FSTS FPUL, FRn */
1498 case 1: /* FLDS FRn,FPUL */
1501 case 2: /* FLOAT FPUL, FRn */
1502 FRN(ir) = (float)FPULi;
1504 case 3: /* FTRC FRn, FPUL */
1506 if( ftmp >= MAX_INTF )
1508 else if( ftmp <= MIN_INTF )
1511 FPULi = (int32_t)ftmp;
1513 case 4: /* FNEG FRn */
1516 case 5: /* FABS FRn */
1517 FRN(ir) = fabsf(FRN(ir));
1519 case 6: /* FSQRT FRn */
1520 FRN(ir) = sqrtf(FRN(ir));
1522 case 7: /* FSRRA FRn */
1523 FRN(ir) = 1.0/sqrtf(FRN(ir));
1525 case 8: /* FLDI0 FRn */
1528 case 9: /* FLDI1 FRn */
1531 case 10: /* FCNVSD FPUL, DRn */
1533 case 11: /* FCNVDS DRn, FPUL */
1535 case 14:/* FIPR FVm, FVn */
1536 /* FIXME: This is not going to be entirely accurate
1537 * as the SH4 instruction is less precise. Also
1538 * need to check for 0s and infinities.
1543 FR(tmp2+3) = FR(tmp)*FR(tmp2) +
1544 FR(tmp+1)*FR(tmp2+1) +
1545 FR(tmp+2)*FR(tmp2+2) +
1546 FR(tmp+3)*FR(tmp2+3);
1550 if( (ir&0x0300) == 0x0100 ) { /* FTRV XMTRX,FVn */
1552 float fv[4] = { FR(tmp), FR(tmp+1), FR(tmp+2), FR(tmp+3) };
1553 FR(tmp) = XF(0) * fv[0] + XF(4)*fv[1] +
1554 XF(8)*fv[2] + XF(12)*fv[3];
1555 FR(tmp+1) = XF(1) * fv[0] + XF(5)*fv[1] +
1556 XF(9)*fv[2] + XF(13)*fv[3];
1557 FR(tmp+2) = XF(2) * fv[0] + XF(6)*fv[1] +
1558 XF(10)*fv[2] + XF(14)*fv[3];
1559 FR(tmp+3) = XF(3) * fv[0] + XF(7)*fv[1] +
1560 XF(11)*fv[2] + XF(15)*fv[3];
1563 else if( (ir&0x0100) == 0 ) { /* FSCA FPUL, DRn */
1564 float angle = (((float)(short)(FPULi>>16)) +
1565 (((float)(FPULi&0xFFFF))/65536.0)) *
1568 FR(reg) = sinf(angle);
1569 FR(reg+1) = cosf(angle);
1572 else if( ir == 0xFBFD ) {
1574 sh4r.fpscr ^= FPSCR_FR;
1577 else if( ir == 0xF3FD ) {
1579 sh4r.fpscr ^= FPSCR_SZ;
1585 case 14:/* FMAC FR0, FRm, FRn */
1586 FRN(ir) += FRM(ir)*FR0;
1593 sh4r.pc = sh4r.new_pc;
1595 sh4r.in_delay_slot = 0;
.