lxdream 0.9.1| filename | src/sh4/timer.c |
| changeset | 975:007bf7eb944f |
| prev | 929:fd8cb0c82f5f |
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| author | nkeynes |
| date | Mon Dec 21 08:23:54 2009 +1000 (14 years ago) |
| permissions | -rw-r--r-- |
| last change | Fix symbol output in 64-bit disassembly Add sh4_translate_dump_block(pc) function |
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1 /**
2 * $Id$
3 *
4 * SH4 Timer/Clock peripheral modules (CPG, TMU, RTC), combined together to
5 * keep things simple (they intertwine a bit).
6 *
7 * Copyright (c) 2005 Nathan Keynes.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
20 #include <assert.h>
21 #include "lxdream.h"
22 #include "mem.h"
23 #include "clock.h"
24 #include "eventq.h"
25 #include "sh4/sh4core.h"
26 #include "sh4/sh4mmio.h"
27 #include "sh4/intc.h"
29 /********************************* CPG *************************************/
30 /* This is the base clock from which all other clocks are derived.
31 * Note: The real clock runs at 33Mhz, which is multiplied by the PLL to
32 * run the instruction clock at 200Mhz. For sake of simplicity/precision,
33 * we instead use 200Mhz as the base rate and divide everything down instead.
34 **/
35 uint32_t sh4_input_freq = SH4_BASE_RATE;
37 uint32_t sh4_cpu_multiplier = 2000; /* = 0.5 * frequency */
39 uint32_t sh4_cpu_freq = SH4_BASE_RATE;
40 uint32_t sh4_bus_freq = SH4_BASE_RATE / 2;
41 uint32_t sh4_peripheral_freq = SH4_BASE_RATE / 4;
43 uint32_t sh4_cpu_period = 1000 / SH4_BASE_RATE; /* in nanoseconds */
44 uint32_t sh4_bus_period = 2* 1000 / SH4_BASE_RATE;
45 uint32_t sh4_peripheral_period = 4 * 2000 / SH4_BASE_RATE;
47 MMIO_REGION_READ_FN( CPG, reg )
48 {
49 return MMIO_READ( CPG, reg&0xFFF );
50 }
51 MMIO_REGION_READ_DEFSUBFNS(CPG)
53 /* CPU + bus dividers (note officially only the first 6 values are valid) */
54 int ifc_divider[8] = { 1, 2, 3, 4, 5, 8, 8, 8 };
55 /* Peripheral clock dividers (only first 5 are officially valid) */
56 int pfc_divider[8] = { 2, 3, 4, 6, 8, 8, 8, 8 };
58 MMIO_REGION_WRITE_FN( CPG, reg, val )
59 {
60 uint32_t div;
61 uint32_t primary_clock = sh4_input_freq;
62 reg &= 0xFFF;
63 switch( reg ) {
64 case FRQCR: /* Frequency control */
65 if( (val & FRQCR_PLL1EN) == 0 )
66 primary_clock /= 6;
67 div = ifc_divider[(val >> 6) & 0x07];
68 sh4_cpu_freq = primary_clock / div;
69 sh4_cpu_period = sh4_cpu_multiplier * div / sh4_input_freq;
70 div = ifc_divider[(val >> 3) & 0x07];
71 sh4_bus_freq = primary_clock / div;
72 sh4_bus_period = 1000 * div / sh4_input_freq;
73 div = pfc_divider[val & 0x07];
74 sh4_peripheral_freq = primary_clock / div;
75 sh4_peripheral_period = 1000 * div / sh4_input_freq;
77 /* Update everything that depends on the peripheral frequency */
78 SCIF_update_line_speed();
79 break;
80 case WTCSR: /* Watchdog timer */
81 break;
82 }
84 MMIO_WRITE( CPG, reg, val );
85 }
87 /**
88 * We don't really know what the default reset value is as it's determined
89 * by the mode select pins. This is the standard value that the BIOS sets,
90 * however, so it works for now.
91 */
92 void CPG_reset( )
93 {
94 mmio_region_CPG_write( FRQCR, 0x0E0A );
95 }
98 /********************************** RTC *************************************/
100 uint32_t rtc_output_period;
102 MMIO_REGION_READ_FN( RTC, reg )
103 {
104 return MMIO_READ( RTC, reg &0xFFF );
105 }
106 MMIO_REGION_READ_DEFSUBFNS(RTC)
108 MMIO_REGION_WRITE_FN( RTC, reg, val )
109 {
110 MMIO_WRITE( RTC, reg &0xFFF, val );
111 }
113 /********************************** TMU *************************************/
115 #define TMU_IS_RUNNING(timer) (MMIO_READ(TMU,TSTR) & (1<<timer))
117 uint32_t TMU_count( int timer, uint32_t nanosecs );
119 void TMU_event_callback( int eventid )
120 {
121 TMU_count( eventid - EVENT_TMU0, sh4r.slice_cycle );
122 }
124 void TMU_init(void)
125 {
126 register_event_callback( EVENT_TMU0, TMU_event_callback );
127 register_event_callback( EVENT_TMU1, TMU_event_callback );
128 register_event_callback( EVENT_TMU2, TMU_event_callback );
129 }
131 #define TCR_ICPF 0x0200
132 #define TCR_UNF 0x0100
133 #define TCR_UNIE 0x0020
135 #define TCR_IRQ_ACTIVE (TCR_UNF|TCR_UNIE)
137 struct TMU_timer {
138 uint32_t timer_period;
139 uint32_t timer_remainder; /* left-over cycles from last count */
140 uint32_t timer_run; /* cycles already run from this slice */
141 };
143 static struct TMU_timer TMU_timers[3];
145 void TMU_set_timer_control( int timer, int tcr )
146 {
147 uint32_t period = 1;
148 uint32_t oldtcr = MMIO_READ( TMU, TCR0 + (12*timer) );
150 if( (oldtcr & TCR_UNF) == 0 ) {
151 tcr = tcr & (~TCR_UNF);
152 } else {
153 if( ((oldtcr & TCR_UNIE) == 0) &&
154 (tcr & TCR_IRQ_ACTIVE) == TCR_IRQ_ACTIVE ) {
155 intc_raise_interrupt( INT_TMU_TUNI0 + timer );
156 } else if( (oldtcr & TCR_UNIE) != 0 &&
157 (tcr & TCR_IRQ_ACTIVE) != TCR_IRQ_ACTIVE ) {
158 intc_clear_interrupt( INT_TMU_TUNI0 + timer );
159 }
160 }
162 switch( tcr & 0x07 ) {
163 case 0:
164 period = sh4_peripheral_period << 2 ;
165 break;
166 case 1:
167 period = sh4_peripheral_period << 4;
168 break;
169 case 2:
170 period = sh4_peripheral_period << 6;
171 break;
172 case 3:
173 period = sh4_peripheral_period << 8;
174 break;
175 case 4:
176 period = sh4_peripheral_period << 10;
177 break;
178 case 5:
179 /* Illegal value. */
180 ERROR( "TMU %d period set to illegal value (5)", timer );
181 period = sh4_peripheral_period << 12; /* for something to do */
182 break;
183 case 6:
184 period = rtc_output_period;
185 break;
186 case 7:
187 /* External clock... Hrm? */
188 period = sh4_peripheral_period; /* I dunno... */
189 break;
190 }
191 TMU_timers[timer].timer_period = period;
193 MMIO_WRITE( TMU, TCR0 + (12*timer), tcr );
194 }
196 void TMU_schedule_timer( int timer )
197 {
198 uint64_t duration = (uint64_t)((uint32_t)(MMIO_READ( TMU, TCNT0 + 12*timer )+1)) *
199 (uint64_t)TMU_timers[timer].timer_period - TMU_timers[timer].timer_remainder;
200 event_schedule_long( EVENT_TMU0+timer, (uint32_t)(duration / 1000000000),
201 (uint32_t)(duration % 1000000000) );
202 }
204 void TMU_start( int timer )
205 {
206 TMU_timers[timer].timer_run = sh4r.slice_cycle;
207 TMU_timers[timer].timer_remainder = 0;
208 TMU_schedule_timer( timer );
209 }
211 /**
212 * Stop the given timer. Run it up to the current time and leave it there.
213 */
214 void TMU_stop( int timer )
215 {
216 TMU_count( timer, sh4r.slice_cycle );
217 event_cancel( EVENT_TMU0+timer );
218 }
220 /**
221 * Count the specified timer for a given number of nanoseconds.
222 */
223 uint32_t TMU_count( int timer, uint32_t nanosecs )
224 {
225 uint32_t run_ns = nanosecs + TMU_timers[timer].timer_remainder -
226 TMU_timers[timer].timer_run;
227 TMU_timers[timer].timer_remainder =
228 run_ns % TMU_timers[timer].timer_period;
229 TMU_timers[timer].timer_run = nanosecs;
230 uint32_t count = run_ns / TMU_timers[timer].timer_period;
231 uint32_t value = MMIO_READ( TMU, TCNT0 + 12*timer );
232 uint32_t reset = MMIO_READ( TMU, TCOR0 + 12*timer );
233 if( count > value ) {
234 uint32_t tcr = MMIO_READ( TMU, TCR0 + 12*timer );
235 tcr |= TCR_UNF;
236 count -= value;
237 value = reset - (count % reset) + 1;
238 MMIO_WRITE( TMU, TCR0 + 12*timer, tcr );
239 if( tcr & TCR_UNIE )
240 intc_raise_interrupt( INT_TMU_TUNI0 + timer );
241 MMIO_WRITE( TMU, TCNT0 + 12*timer, value );
242 TMU_schedule_timer(timer);
243 } else {
244 value -= count;
245 MMIO_WRITE( TMU, TCNT0 + 12*timer, value );
246 }
247 return value;
248 }
250 MMIO_REGION_READ_FN( TMU, reg )
251 {
252 reg &= 0xFFF;
253 switch( reg ) {
254 case TCNT0:
255 TMU_count( 0, sh4r.slice_cycle );
256 break;
257 case TCNT1:
258 TMU_count( 1, sh4r.slice_cycle );
259 break;
260 case TCNT2:
261 TMU_count( 2, sh4r.slice_cycle );
262 break;
263 }
264 return MMIO_READ( TMU, reg );
265 }
266 MMIO_REGION_READ_DEFSUBFNS(TMU)
269 MMIO_REGION_WRITE_FN( TMU, reg, val )
270 {
271 uint32_t oldval;
272 int i;
273 reg &= 0xFFF;
274 switch( reg ) {
275 case TSTR:
276 oldval = MMIO_READ( TMU, TSTR );
277 for( i=0; i<3; i++ ) {
278 uint32_t tmp = 1<<i;
279 if( (oldval & tmp) != 0 && (val&tmp) == 0 )
280 TMU_stop(i);
281 else if( (oldval&tmp) == 0 && (val&tmp) != 0 )
282 TMU_start(i);
283 }
284 break;
285 case TCR0:
286 TMU_set_timer_control( 0, val );
287 return;
288 case TCR1:
289 TMU_set_timer_control( 1, val );
290 return;
291 case TCR2:
292 TMU_set_timer_control( 2, val );
293 return;
294 case TCNT0:
295 MMIO_WRITE( TMU, reg, val );
296 if( TMU_IS_RUNNING(0) ) { // reschedule
297 TMU_timers[0].timer_run = sh4r.slice_cycle;
298 TMU_schedule_timer( 0 );
299 }
300 return;
301 case TCNT1:
302 MMIO_WRITE( TMU, reg, val );
303 if( TMU_IS_RUNNING(1) ) { // reschedule
304 TMU_timers[1].timer_run = sh4r.slice_cycle;
305 TMU_schedule_timer( 1 );
306 }
307 return;
308 case TCNT2:
309 MMIO_WRITE( TMU, reg, val );
310 if( TMU_IS_RUNNING(2) ) { // reschedule
311 TMU_timers[2].timer_run = sh4r.slice_cycle;
312 TMU_schedule_timer( 2 );
313 }
314 return;
315 }
316 MMIO_WRITE( TMU, reg, val );
317 }
319 void TMU_count_all( uint32_t nanosecs )
320 {
321 int tcr = MMIO_READ( TMU, TSTR );
322 if( tcr & 0x01 ) {
323 TMU_count( 0, nanosecs );
324 }
325 if( tcr & 0x02 ) {
326 TMU_count( 1, nanosecs );
327 }
328 if( tcr & 0x04 ) {
329 TMU_count( 2, nanosecs );
330 }
331 }
333 void TMU_run_slice( uint32_t nanosecs )
334 {
335 TMU_count_all( nanosecs );
336 TMU_timers[0].timer_run = 0;
337 TMU_timers[1].timer_run = 0;
338 TMU_timers[2].timer_run = 0;
339 }
341 void TMU_update_clocks()
342 {
343 TMU_set_timer_control( 0, MMIO_READ( TMU, TCR0 ) );
344 TMU_set_timer_control( 1, MMIO_READ( TMU, TCR1 ) );
345 TMU_set_timer_control( 2, MMIO_READ( TMU, TCR2 ) );
346 }
348 void TMU_reset( )
349 {
350 TMU_timers[0].timer_remainder = 0;
351 TMU_timers[0].timer_run = 0;
352 TMU_timers[1].timer_remainder = 0;
353 TMU_timers[1].timer_run = 0;
354 TMU_timers[2].timer_remainder = 0;
355 TMU_timers[2].timer_run = 0;
356 TMU_update_clocks();
357 }
359 void TMU_save_state( FILE *f ) {
360 fwrite( &TMU_timers, sizeof(TMU_timers), 1, f );
361 }
363 int TMU_load_state( FILE *f )
364 {
365 fread( &TMU_timers, sizeof(TMU_timers), 1, f );
366 return 0;
367 }
.