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lxdream.org :: lxdream/src/sh4/ia32mac.h
lxdream 0.9.1
released Jun 29
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filename src/sh4/ia32mac.h
changeset 570:d2893980fbf5
prev569:a1c49e1e8776
next571:9bc09948d0f2
author nkeynes
date Sun Jan 06 12:24:18 2008 +0000 (14 years ago)
branchlxdream-mmu
permissions -rw-r--r--
last change Change to generate different code for mmu on/off cases
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     1 /**
     2  * $Id$
     3  * 
     4  * Provides the implementation for the ia32 ABI (eg prologue, epilogue, and
     5  * calling conventions)
     6  *
     7  * Copyright (c) 2007 Nathan Keynes.
     8  *
     9  * This program is free software; you can redistribute it and/or modify
    10  * it under the terms of the GNU General Public License as published by
    11  * the Free Software Foundation; either version 2 of the License, or
    12  * (at your option) any later version.
    13  *
    14  * This program is distributed in the hope that it will be useful,
    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17  * GNU General Public License for more details.
    18  */
    20 #ifndef __lxdream_ia32abi_H
    21 #define __lxdream_ia32abi_H 1
    23 #define load_ptr( reg, ptr ) load_imm32( reg, (uint32_t)ptr );
    25 /**
    26  * Note: clobbers EAX to make the indirect call - this isn't usually
    27  * a problem since the callee will usually clobber it anyway.
    28  */
    29 #define CALL_FUNC0_SIZE 13
    30 static inline void call_func0( void *ptr )
    31 {
    32     int adj = (-sh4_x86.stack_posn)&0x0F;
    33     SUB_imm8s_r32( adj, R_ESP );
    34     load_imm32(R_EAX, (uint32_t)ptr);
    35     CALL_r32(R_EAX);
    36     ADD_imm8s_r32( adj, R_ESP );
    37 }
    39 #define CALL_FUNC1_SIZE 14
    40 static inline void call_func1( void *ptr, int arg1 )
    41 {
    42     int adj = (-4-sh4_x86.stack_posn)&0x0F;
    43     SUB_imm8s_r32( adj, R_ESP );
    44     PUSH_r32(arg1);
    45     load_imm32(R_EAX, (uint32_t)ptr);
    46     CALL_r32(R_EAX);
    47     ADD_imm8s_r32( adj+4, R_ESP );
    48     sh4_x86.stack_posn -= 4;
    49 }
    51 #define CALL_FUNC2_SIZE 15
    52 static inline void call_func2( void *ptr, int arg1, int arg2 )
    53 {
    54     int adj = (-8-sh4_x86.stack_posn)&0x0F;
    55     SUB_imm8s_r32( adj, R_ESP );
    56     PUSH_r32(arg2);
    57     PUSH_r32(arg1);
    58     load_imm32(R_EAX, (uint32_t)ptr);
    59     CALL_r32(R_EAX);
    60     ADD_imm8s_r32( adj+8, R_ESP );
    61     sh4_x86.stack_posn -= 8;
    62 }
    64 /**
    65  * Write a double (64-bit) value into memory, with the first word in arg2a, and
    66  * the second in arg2b
    67  * NB: 30 bytes
    68  */
    69 #define MEM_WRITE_DOUBLE_SIZE 36
    70 static inline void MEM_WRITE_DOUBLE( int addr, int arg2a, int arg2b )
    71 {
    72     int adj = (-8-sh4_x86.stack_posn)&0x0F;
    73     SUB_imm8s_r32( adj, R_ESP );
    74     ADD_imm8s_r32( 4, addr );
    75     PUSH_r32(arg2b);
    76     PUSH_r32(addr);
    77     ADD_imm8s_r32( -4, addr );
    78     SUB_imm8s_r32( 8, R_ESP );
    79     PUSH_r32(arg2a);
    80     PUSH_r32(addr);
    81     load_imm32(R_EAX, (uint32_t)sh4_write_long);
    82     CALL_r32(R_EAX);
    83     ADD_imm8s_r32( 16, R_ESP );
    84     load_imm32(R_EAX, (uint32_t)sh4_write_long);
    85     CALL_r32(R_EAX);
    86     ADD_imm8s_r32( adj+8, R_ESP );
    87     sh4_x86.stack_posn -= 16;
    88 }
    90 /**
    91  * Read a double (64-bit) value from memory, writing the first word into arg2a
    92  * and the second into arg2b. The addr must not be in EAX
    93  * NB: 27 bytes
    94  */
    95 #define MEM_READ_DOUBLE_SIZE 36
    96 static inline void MEM_READ_DOUBLE( int addr, int arg2a, int arg2b )
    97 {
    98     int adj = (-4-sh4_x86.stack_posn)&0x0F;
    99     int adj2 = (-8-sh4_x86.stack_posn)&0x0F;
   100     SUB_imm8s_r32( adj, R_ESP );
   101     PUSH_r32(addr);
   102     load_imm32(R_EAX, (uint32_t)sh4_read_long);
   103     CALL_r32(R_EAX);
   104     POP_r32(addr);
   105     SUB_imm8s_r32( adj2-adj, R_ESP );
   106     PUSH_r32(R_EAX);
   107     ADD_imm8s_r32( 4, addr );
   108     PUSH_r32(addr);
   109     load_imm32(R_EAX, (uint32_t)sh4_read_long);
   110     CALL_r32(R_EAX);
   111     ADD_imm8s_r32( 4, R_ESP );
   112     MOV_r32_r32( R_EAX, arg2b );
   113     POP_r32(arg2a);
   114     ADD_imm8s_r32( adj2, R_ESP );
   115     sh4_x86.stack_posn -= 4;
   116 }
   118 #define EXIT_BLOCK_SIZE 29
   121 /**
   122  * Emit the 'start of block' assembly. Sets up the stack frame and save
   123  * SI/DI as required
   124  */
   125 void sh4_translate_begin_block( sh4addr_t pc ) 
   126 {
   127     PUSH_r32(R_EBP);
   128     /* mov &sh4r, ebp */
   129     load_ptr( R_EBP, &sh4r );
   131     sh4_x86.in_delay_slot = FALSE;
   132     sh4_x86.priv_checked = FALSE;
   133     sh4_x86.fpuen_checked = FALSE;
   134     sh4_x86.branch_taken = FALSE;
   135     sh4_x86.backpatch_posn = 0;
   136     sh4_x86.block_start_pc = pc;
   137     sh4_x86.tstate = TSTATE_NONE;
   138     sh4_x86.tlb_on = MMIO_READ(MMU,MMUCR)&MMUCR_AT;
   139     sh4_x86.stack_posn = 8;
   140 }
   142 /**
   143  * Exit the block with sh4r.pc already written
   144  * Bytes: 15
   145  */
   146 void exit_block_pcset( sh4addr_t pc )
   147 {
   148     load_imm32( R_ECX, ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
   149     ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );    // 6
   150     load_spreg( R_EAX, REG_OFFSET(pc) );
   151     if( sh4_x86.tlb_on ) {
   152 	call_func1(xlat_get_code_by_vma,R_EAX);
   153     } else {
   154 	call_func1(xlat_get_code,R_EAX);
   155     }
   156     POP_r32(R_EBP);
   157     RET();
   158 }
   160 /**
   161  * Exit the block to an absolute PC
   162  */
   163 void exit_block( sh4addr_t pc, sh4addr_t endpc )
   164 {
   165     load_imm32( R_ECX, pc );                            // 5
   166     store_spreg( R_ECX, REG_OFFSET(pc) );               // 3
   167     MOV_moff32_EAX( xlat_get_lut_entry(pc) ); // 5
   168     AND_imm8s_r32( 0xFC, R_EAX ); // 3
   169     load_imm32( R_ECX, ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
   170     ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );     // 6
   171     POP_r32(R_EBP);
   172     RET();
   173 }
   175 /**
   176  * Write the block trailer (exception handling block)
   177  */
   178 void sh4_translate_end_block( sh4addr_t pc ) {
   179     if( sh4_x86.branch_taken == FALSE ) {
   180 	// Didn't exit unconditionally already, so write the termination here
   181 	exit_block( pc, pc );
   182     }
   183     if( sh4_x86.backpatch_posn != 0 ) {
   184 	unsigned int i;
   185 	// Raise exception
   186 	uint8_t *end_ptr = xlat_output;
   187 	load_spreg( R_ECX, REG_OFFSET(pc) );
   188 	ADD_r32_r32( R_EDX, R_ECX );
   189 	ADD_r32_r32( R_EDX, R_ECX );
   190 	store_spreg( R_ECX, REG_OFFSET(pc) );
   191 	MOV_moff32_EAX( &sh4_cpu_period );
   192 	MUL_r32( R_EDX );
   193 	ADD_r32_sh4r( R_EAX, REG_OFFSET(slice_cycle) );
   195         POP_r32(R_EDX);
   196         call_func1( sh4_raise_exception, R_EDX );
   197 	load_spreg( R_EAX, REG_OFFSET(pc) );
   198 	if( sh4_x86.tlb_on ) {
   199 	    call_func1(xlat_get_code_by_vma,R_EAX);
   200 	} else {
   201 	    call_func1(xlat_get_code,R_EAX);
   202 	}
   203 	POP_r32(R_EBP);
   204 	RET();
   206 	// Exception already raised - just cleanup
   207 	uint8_t *preexc_ptr = xlat_output;
   208 	load_imm32( R_ECX, sh4_x86.block_start_pc );
   209 	ADD_r32_r32( R_EDX, R_ECX );
   210 	ADD_r32_r32( R_EDX, R_ECX );
   211 	store_spreg( R_ECX, REG_OFFSET(spc) );
   212 	MOV_moff32_EAX( &sh4_cpu_period );
   213 	MUL_r32( R_EDX );
   214 	ADD_r32_sh4r( R_EAX, REG_OFFSET(slice_cycle) );
   215 	load_spreg( R_EAX, REG_OFFSET(pc) );
   216 	if( sh4_x86.tlb_on ) {
   217 	    call_func1(xlat_get_code_by_vma,R_EAX);
   218 	} else {
   219 	    call_func1(xlat_get_code,R_EAX);
   220 	}
   221 	POP_r32(R_EBP);
   222 	RET();
   224 	for( i=0; i< sh4_x86.backpatch_posn; i++ ) {
   225 	    *sh4_x86.backpatch_list[i].fixup_addr =
   226 		xlat_output - ((uint8_t *)sh4_x86.backpatch_list[i].fixup_addr) - 4;
   227 	    if( sh4_x86.backpatch_list[i].exc_code == -1 ) {
   228 		load_imm32( R_EDX, sh4_x86.backpatch_list[i].fixup_icount );
   229 		int rel = preexc_ptr - xlat_output;
   230 		JMP_rel(rel);
   231 	    } else {
   232 		PUSH_imm32( sh4_x86.backpatch_list[i].exc_code );
   233 		load_imm32( R_EDX, sh4_x86.backpatch_list[i].fixup_icount );
   234 		int rel = end_ptr - xlat_output;
   235 		JMP_rel(rel);
   236 	    }
   237 	}
   238     }
   239 }
   241 #endif
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