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lxdream.org :: lxdream/src/sh4/mmu.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/mmu.c
changeset 570:d2893980fbf5
prev569:a1c49e1e8776
next571:9bc09948d0f2
author nkeynes
date Sun Jan 06 12:24:18 2008 +0000 (13 years ago)
branchlxdream-mmu
permissions -rw-r--r--
last change Change to generate different code for mmu on/off cases
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     1 /**
     2  * $Id$
     3  * 
     4  * MMU implementation
     5  *
     6  * Copyright (c) 2005 Nathan Keynes.
     7  *
     8  * This program is free software; you can redistribute it and/or modify
     9  * it under the terms of the GNU General Public License as published by
    10  * the Free Software Foundation; either version 2 of the License, or
    11  * (at your option) any later version.
    12  *
    13  * This program is distributed in the hope that it will be useful,
    14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    16  * GNU General Public License for more details.
    17  */
    18 #define MODULE sh4_module
    20 #include <stdio.h>
    21 #include "sh4/sh4mmio.h"
    22 #include "sh4/sh4core.h"
    23 #include "mem.h"
    25 #define VMA_TO_EXT_ADDR(vma) ((vma)&0x1FFFFFFF)
    27 /* The MMU (practically unique in the system) is allowed to raise exceptions
    28  * directly, with a return code indicating that one was raised and the caller
    29  * had better behave appropriately.
    30  */
    31 #define RAISE_TLB_ERROR(code, vpn) \
    32     MMIO_WRITE(MMU, TEA, vpn); \
    33     MMIO_WRITE(MMU, PTEH, ((MMIO_READ(MMU, PTEH) & 0x000003FF) | (vpn&0xFFFFFC00))); \
    34     sh4_raise_tlb_exception(code);
    36 #define RAISE_MEM_ERROR(code, vpn) \
    37     MMIO_WRITE(MMU, TEA, vpn); \
    38     MMIO_WRITE(MMU, PTEH, ((MMIO_READ(MMU, PTEH) & 0x000003FF) | (vpn&0xFFFFFC00))); \
    39     sh4_raise_exception(code);
    41 #define RAISE_OTHER_ERROR(code) \
    42     sh4_raise_exception(code);
    43 /**
    44  * Abort with a non-MMU address error. Caused by user-mode code attempting
    45  * to access privileged regions, or alignment faults.
    46  */
    47 #define MMU_READ_ADDR_ERROR() RAISE_OTHER_ERROR(EXC_DATA_ADDR_READ)
    48 #define MMU_WRITE_ADDR_ERROR() RAISE_OTHER_ERROR(EXC_DATA_ADDR_WRITE)
    50 #define MMU_TLB_READ_MISS_ERROR(vpn) RAISE_TLB_ERROR(EXC_TLB_MISS_READ, vpn)
    51 #define MMU_TLB_WRITE_MISS_ERROR(vpn) RAISE_TLB_ERROR(EXC_TLB_MISS_WRITE, vpn)
    52 #define MMU_TLB_INITIAL_WRITE_ERROR(vpn) RAISE_MEM_ERROR(EXC_INIT_PAGE_WRITE, vpn)
    53 #define MMU_TLB_READ_PROT_ERROR(vpn) RAISE_MEM_ERROR(EXC_TLB_PROT_READ, vpn)
    54 #define MMU_TLB_WRITE_PROT_ERROR(vpn) RAISE_MEM_ERROR(EXC_TLB_PROT_WRITE, vpn)
    55 #define MMU_TLB_MULTI_HIT_ERROR(vpn) sh4_raise_reset(EXC_TLB_MULTI_HIT); \
    56     MMIO_WRITE(MMU, TEA, vpn); \
    57     MMIO_WRITE(MMU, PTEH, ((MMIO_READ(MMU, PTEH) & 0x000003FF) | (vpn&0xFFFFFC00)));
    60 #define OCRAM_START (0x1C000000>>PAGE_BITS)
    61 #define OCRAM_END   (0x20000000>>PAGE_BITS)
    63 #define ITLB_ENTRY_COUNT 4
    64 #define UTLB_ENTRY_COUNT 64
    66 /* Entry address */
    67 #define TLB_VALID     0x00000100
    68 #define TLB_USERMODE  0x00000040
    69 #define TLB_WRITABLE  0x00000020
    70 #define TLB_USERWRITABLE (TLB_WRITABLE|TLB_USERMODE)
    71 #define TLB_SIZE_MASK 0x00000090
    72 #define TLB_SIZE_1K   0x00000000
    73 #define TLB_SIZE_4K   0x00000010
    74 #define TLB_SIZE_64K  0x00000080
    75 #define TLB_SIZE_1M   0x00000090
    76 #define TLB_CACHEABLE 0x00000008
    77 #define TLB_DIRTY     0x00000004
    78 #define TLB_SHARE     0x00000002
    79 #define TLB_WRITETHRU 0x00000001
    81 #define MASK_1K  0xFFFFFC00
    82 #define MASK_4K  0xFFFFF000
    83 #define MASK_64K 0xFFFF0000
    84 #define MASK_1M  0xFFF00000
    86 struct itlb_entry {
    87     sh4addr_t vpn; // Virtual Page Number
    88     uint32_t asid; // Process ID
    89     uint32_t mask;
    90     sh4addr_t ppn; // Physical Page Number
    91     uint32_t flags;
    92 };
    94 struct utlb_entry {
    95     sh4addr_t vpn; // Virtual Page Number
    96     uint32_t mask; // Page size mask
    97     uint32_t asid; // Process ID
    98     sh4addr_t ppn; // Physical Page Number
    99     uint32_t flags;
   100     uint32_t pcmcia; // extra pcmcia data - not used
   101 };
   103 static struct itlb_entry mmu_itlb[ITLB_ENTRY_COUNT];
   104 static struct utlb_entry mmu_utlb[UTLB_ENTRY_COUNT];
   105 static uint32_t mmu_urc;
   106 static uint32_t mmu_urb;
   107 static uint32_t mmu_lrui;
   108 static uint32_t mmu_asid; // current asid
   110 static sh4ptr_t cache = NULL;
   112 static void mmu_invalidate_tlb();
   115 static uint32_t get_mask_for_flags( uint32_t flags )
   116 {
   117     switch( flags & TLB_SIZE_MASK ) {
   118     case TLB_SIZE_1K: return MASK_1K;
   119     case TLB_SIZE_4K: return MASK_4K;
   120     case TLB_SIZE_64K: return MASK_64K;
   121     case TLB_SIZE_1M: return MASK_1M;
   122     }
   123 }
   125 int32_t mmio_region_MMU_read( uint32_t reg )
   126 {
   127     switch( reg ) {
   128     case MMUCR:
   129 	return MMIO_READ( MMU, MMUCR) | (mmu_urc<<10) | (mmu_urb<<18) | (mmu_lrui<<26);
   130     default:
   131 	return MMIO_READ( MMU, reg );
   132     }
   133 }
   135 void mmio_region_MMU_write( uint32_t reg, uint32_t val )
   136 {
   137     uint32_t tmp;
   138     switch(reg) {
   139     case PTEH:
   140 	val &= 0xFFFFFCFF;
   141 	if( (val & 0xFF) != mmu_asid ) {
   142 	    mmu_asid = val&0xFF;
   143 	    sh4_icache.page_vma = -1; // invalidate icache as asid has changed
   144 	}
   145 	break;
   146     case PTEL:
   147 	val &= 0x1FFFFDFF;
   148 	break;
   149     case PTEA:
   150 	val &= 0x0000000F;
   151 	break;
   152     case MMUCR:
   153 	if( val & MMUCR_TI ) {
   154 	    mmu_invalidate_tlb();
   155 	}
   156 	mmu_urc = (val >> 10) & 0x3F;
   157 	mmu_urb = (val >> 18) & 0x3F;
   158 	mmu_lrui = (val >> 26) & 0x3F;
   159 	val &= 0x00000301;
   160 	tmp = MMIO_READ( MMU, MMUCR );
   161 	if( ((val ^ tmp) & MMUCR_AT) ) {
   162 	    // AT flag has changed state - flush the xlt cache as all bets
   163 	    // are off now. We also need to force an immediate exit from the
   164 	    // current block
   165 	    xlat_flush_cache();
   166 	}
   167 	break;
   168     case CCR:
   169 	mmu_set_cache_mode( val & (CCR_OIX|CCR_ORA) );
   170 	break;
   171     default:
   172 	break;
   173     }
   174     MMIO_WRITE( MMU, reg, val );
   175 }
   178 void MMU_init() 
   179 {
   180     cache = mem_alloc_pages(2);
   181 }
   183 void MMU_reset()
   184 {
   185     mmio_region_MMU_write( CCR, 0 );
   186 }
   188 void MMU_save_state( FILE *f )
   189 {
   190     fwrite( cache, 4096, 2, f );
   191     fwrite( &mmu_itlb, sizeof(mmu_itlb), 1, f );
   192     fwrite( &mmu_utlb, sizeof(mmu_utlb), 1, f );
   193     fwrite( &mmu_urc, sizeof(mmu_urc), 1, f );
   194     fwrite( &mmu_urb, sizeof(mmu_urb), 1, f );
   195     fwrite( &mmu_lrui, sizeof(mmu_lrui), 1, f );
   196     fwrite( &mmu_asid, sizeof(mmu_asid), 1, f );
   197 }
   199 int MMU_load_state( FILE *f )
   200 {
   201     /* Setup the cache mode according to the saved register value
   202      * (mem_load runs before this point to load all MMIO data)
   203      */
   204     mmio_region_MMU_write( CCR, MMIO_READ(MMU, CCR) );
   205     if( fread( cache, 4096, 2, f ) != 2 ) {
   206 	return 1;
   207     }
   208     if( fread( &mmu_itlb, sizeof(mmu_itlb), 1, f ) != 1 ) {
   209 	return 1;
   210     }
   211     if( fread( &mmu_utlb, sizeof(mmu_utlb), 1, f ) != 1 ) {
   212 	return 1;
   213     }
   214     if( fread( &mmu_urc, sizeof(mmu_urc), 1, f ) != 1 ) {
   215 	return 1;
   216     }
   217     if( fread( &mmu_urc, sizeof(mmu_urb), 1, f ) != 1 ) {
   218 	return 1;
   219     }
   220     if( fread( &mmu_lrui, sizeof(mmu_lrui), 1, f ) != 1 ) {
   221 	return 1;
   222     }
   223     if( fread( &mmu_asid, sizeof(mmu_asid), 1, f ) != 1 ) {
   224 	return 1;
   225     }
   226     return 0;
   227 }
   229 void mmu_set_cache_mode( int mode )
   230 {
   231     uint32_t i;
   232     switch( mode ) {
   233         case MEM_OC_INDEX0: /* OIX=0 */
   234             for( i=OCRAM_START; i<OCRAM_END; i++ )
   235                 page_map[i] = cache + ((i&0x02)<<(PAGE_BITS-1));
   236             break;
   237         case MEM_OC_INDEX1: /* OIX=1 */
   238             for( i=OCRAM_START; i<OCRAM_END; i++ )
   239                 page_map[i] = cache + ((i&0x02000000)>>(25-PAGE_BITS));
   240             break;
   241         default: /* disabled */
   242             for( i=OCRAM_START; i<OCRAM_END; i++ )
   243                 page_map[i] = NULL;
   244             break;
   245     }
   246 }
   248 /* TLB maintanence */
   250 /**
   251  * LDTLB instruction implementation. Copies PTEH, PTEL and PTEA into the UTLB
   252  * entry identified by MMUCR.URC. Does not modify MMUCR or the ITLB.
   253  */
   254 void MMU_ldtlb()
   255 {
   256     mmu_utlb[mmu_urc].vpn = MMIO_READ(MMU, PTEH) & 0xFFFFFC00;
   257     mmu_utlb[mmu_urc].asid = MMIO_READ(MMU, PTEH) & 0x000000FF;
   258     mmu_utlb[mmu_urc].ppn = MMIO_READ(MMU, PTEL) & 0x1FFFFC00;
   259     mmu_utlb[mmu_urc].flags = MMIO_READ(MMU, PTEL) & 0x00001FF;
   260     mmu_utlb[mmu_urc].pcmcia = MMIO_READ(MMU, PTEA);
   261     mmu_utlb[mmu_urc].mask = get_mask_for_flags(mmu_utlb[mmu_urc].flags);
   262 }
   264 static void mmu_invalidate_tlb()
   265 {
   266     int i;
   267     for( i=0; i<ITLB_ENTRY_COUNT; i++ ) {
   268 	mmu_itlb[i].flags &= (~TLB_VALID);
   269     }
   270     for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
   271 	mmu_utlb[i].flags &= (~TLB_VALID);
   272     }
   273 }
   275 #define ITLB_ENTRY(addr) ((addr>>7)&0x03)
   277 int32_t mmu_itlb_addr_read( sh4addr_t addr )
   278 {
   279     struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
   280     return ent->vpn | ent->asid | (ent->flags & TLB_VALID);
   281 }
   282 int32_t mmu_itlb_data_read( sh4addr_t addr )
   283 {
   284     struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
   285     return ent->ppn | ent->flags;
   286 }
   288 void mmu_itlb_addr_write( sh4addr_t addr, uint32_t val )
   289 {
   290     struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
   291     ent->vpn = val & 0xFFFFFC00;
   292     ent->asid = val & 0x000000FF;
   293     ent->flags = (ent->flags & ~(TLB_VALID)) | (val&TLB_VALID);
   294 }
   296 void mmu_itlb_data_write( sh4addr_t addr, uint32_t val )
   297 {
   298     struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
   299     ent->ppn = val & 0x1FFFFC00;
   300     ent->flags = val & 0x00001DA;
   301     ent->mask = get_mask_for_flags(val);
   302 }
   304 #define UTLB_ENTRY(addr) ((addr>>8)&0x3F)
   305 #define UTLB_ASSOC(addr) (addr&0x80)
   306 #define UTLB_DATA2(addr) (addr&0x00800000)
   308 int32_t mmu_utlb_addr_read( sh4addr_t addr )
   309 {
   310     struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
   311     return ent->vpn | ent->asid | (ent->flags & TLB_VALID) |
   312 	((ent->flags & TLB_DIRTY)<<7);
   313 }
   314 int32_t mmu_utlb_data_read( sh4addr_t addr )
   315 {
   316     struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
   317     if( UTLB_DATA2(addr) ) {
   318 	return ent->pcmcia;
   319     } else {
   320 	return ent->ppn | ent->flags;
   321     }
   322 }
   324 /**
   325  * Find a UTLB entry for the associative TLB write - same as the normal
   326  * lookup but ignores the valid bit.
   327  */
   328 static inline mmu_utlb_lookup_assoc( uint32_t vpn, uint32_t asid )
   329 {
   330     int result = -1;
   331     unsigned int i;
   332     for( i = 0; i < UTLB_ENTRY_COUNT; i++ ) {
   333 	if( ((mmu_utlb[i].flags & TLB_SHARE) || asid == mmu_utlb[i].asid) && 
   334 	    ((mmu_utlb[i].vpn ^ vpn) & mmu_utlb[i].mask) == 0 ) {
   335 	    if( result != -1 ) {
   336 		return -2;
   337 	    }
   338 	    result = i;
   339 	}
   340     }
   341     return result;
   342 }
   344 /**
   345  * Find a ITLB entry for the associative TLB write - same as the normal
   346  * lookup but ignores the valid bit.
   347  */
   348 static inline mmu_itlb_lookup_assoc( uint32_t vpn, uint32_t asid )
   349 {
   350     int result = -1;
   351     unsigned int i;
   352     for( i = 0; i < ITLB_ENTRY_COUNT; i++ ) {
   353 	if( ((mmu_itlb[i].flags & TLB_SHARE) || asid == mmu_itlb[i].asid) && 
   354 	    ((mmu_itlb[i].vpn ^ vpn) & mmu_itlb[i].mask) == 0 ) {
   355 	    if( result != -1 ) {
   356 		return -2;
   357 	    }
   358 	    result = i;
   359 	}
   360     }
   361     return result;
   362 }
   364 void mmu_utlb_addr_write( sh4addr_t addr, uint32_t val )
   365 {
   366     if( UTLB_ASSOC(addr) ) {
   367 	uint32_t asid = MMIO_READ( MMU, PTEH ) & 0xFF;
   368 	int utlb = mmu_utlb_lookup_assoc( val, asid );
   369 	if( utlb >= 0 ) {
   370 	    struct utlb_entry *ent = &mmu_utlb[utlb];
   371 	    ent->flags = ent->flags & ~(TLB_DIRTY|TLB_VALID);
   372 	    ent->flags |= (val & TLB_VALID);
   373 	    ent->flags |= ((val & 0x200)>>7);
   374 	}
   376 	int itlb = mmu_itlb_lookup_assoc( val, asid );
   377 	if( itlb >= 0 ) {
   378 	    struct itlb_entry *ent = &mmu_itlb[itlb];
   379 	    ent->flags = (ent->flags & (~TLB_VALID)) | (val & TLB_VALID);
   380 	}
   382 	if( itlb == -2 || utlb == -2 ) {
   383 	    MMU_TLB_MULTI_HIT_ERROR(addr);
   384 	    return;
   385 	}
   386     } else {
   387 	struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
   388 	ent->vpn = (val & 0xFFFFFC00);
   389 	ent->asid = (val & 0xFF);
   390 	ent->flags = (ent->flags & ~(TLB_DIRTY|TLB_VALID));
   391 	ent->flags |= (val & TLB_VALID);
   392 	ent->flags |= ((val & 0x200)>>7);
   393     }
   394 }
   396 void mmu_utlb_data_write( sh4addr_t addr, uint32_t val )
   397 {
   398     struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
   399     if( UTLB_DATA2(addr) ) {
   400 	ent->pcmcia = val & 0x0000000F;
   401     } else {
   402 	ent->ppn = (val & 0x1FFFFC00);
   403 	ent->flags = (val & 0x000001FF);
   404 	ent->mask = get_mask_for_flags(val);
   405     }
   406 }
   408 /* Cache access - not implemented */
   410 int32_t mmu_icache_addr_read( sh4addr_t addr )
   411 {
   412     return 0; // not implemented
   413 }
   414 int32_t mmu_icache_data_read( sh4addr_t addr )
   415 {
   416     return 0; // not implemented
   417 }
   418 int32_t mmu_ocache_addr_read( sh4addr_t addr )
   419 {
   420     return 0; // not implemented
   421 }
   422 int32_t mmu_ocache_data_read( sh4addr_t addr )
   423 {
   424     return 0; // not implemented
   425 }
   427 void mmu_icache_addr_write( sh4addr_t addr, uint32_t val )
   428 {
   429 }
   431 void mmu_icache_data_write( sh4addr_t addr, uint32_t val )
   432 {
   433 }
   435 void mmu_ocache_addr_write( sh4addr_t addr, uint32_t val )
   436 {
   437 }
   439 void mmu_ocache_data_write( sh4addr_t addr, uint32_t val )
   440 {
   441 }
   443 /******************************************************************************/
   444 /*                        MMU TLB address translation                         */
   445 /******************************************************************************/
   447 /**
   448  * The translations are excessively complicated, but unfortunately it's a 
   449  * complicated system. TODO: make this not be painfully slow.
   450  */
   452 /**
   453  * Perform the actual utlb lookup w/ asid matching.
   454  * Possible utcomes are:
   455  *   0..63 Single match - good, return entry found
   456  *   -1 No match - raise a tlb data miss exception
   457  *   -2 Multiple matches - raise a multi-hit exception (reset)
   458  * @param vpn virtual address to resolve
   459  * @return the resultant UTLB entry, or an error.
   460  */
   461 static inline int mmu_utlb_lookup_vpn_asid( uint32_t vpn )
   462 {
   463     int result = -1;
   464     unsigned int i;
   466     mmu_urc++;
   467     if( mmu_urc == mmu_urb || mmu_urc == 0x40 ) {
   468 	mmu_urc = 0;
   469     }
   471     for( i = 0; i < UTLB_ENTRY_COUNT; i++ ) {
   472 	if( (mmu_utlb[i].flags & TLB_VALID) &&
   473 	    ((mmu_utlb[i].flags & TLB_SHARE) || mmu_asid == mmu_utlb[i].asid) && 
   474 	    ((mmu_utlb[i].vpn ^ vpn) & mmu_utlb[i].mask) == 0 ) {
   475 	    if( result != -1 ) {
   476 		return -2;
   477 	    }
   478 	    result = i;
   479 	}
   480     }
   481     return result;
   482 }
   484 /**
   485  * Perform the actual utlb lookup matching on vpn only
   486  * Possible utcomes are:
   487  *   0..63 Single match - good, return entry found
   488  *   -1 No match - raise a tlb data miss exception
   489  *   -2 Multiple matches - raise a multi-hit exception (reset)
   490  * @param vpn virtual address to resolve
   491  * @return the resultant UTLB entry, or an error.
   492  */
   493 static inline int mmu_utlb_lookup_vpn( uint32_t vpn )
   494 {
   495     int result = -1;
   496     unsigned int i;
   498     mmu_urc++;
   499     if( mmu_urc == mmu_urb || mmu_urc == 0x40 ) {
   500 	mmu_urc = 0;
   501     }
   503     for( i = 0; i < UTLB_ENTRY_COUNT; i++ ) {
   504 	if( (mmu_utlb[i].flags & TLB_VALID) &&
   505 	    ((mmu_utlb[i].vpn ^ vpn) & mmu_utlb[i].mask) == 0 ) {
   506 	    if( result != -1 ) {
   507 		return -2;
   508 	    }
   509 	    result = i;
   510 	}
   511     }
   513     return result;
   514 }
   516 /**
   517  * Update the ITLB by replacing the LRU entry with the specified UTLB entry.
   518  * @return the number (0-3) of the replaced entry.
   519  */
   520 static int inline mmu_itlb_update_from_utlb( int entryNo )
   521 {
   522     int replace;
   523     /* Determine entry to replace based on lrui */
   524     if( mmu_lrui & 0x38 == 0x38 ) {
   525 	replace = 0;
   526 	mmu_lrui = mmu_lrui & 0x07;
   527     } else if( (mmu_lrui & 0x26) == 0x06 ) {
   528 	replace = 1;
   529 	mmu_lrui = (mmu_lrui & 0x19) | 0x20;
   530     } else if( (mmu_lrui & 0x15) == 0x01 ) {
   531 	replace = 2;
   532 	mmu_lrui = (mmu_lrui & 0x3E) | 0x14;
   533     } else { // Note - gets invalid entries too
   534 	replace = 3;
   535 	mmu_lrui = (mmu_lrui | 0x0B);
   536     } 
   538     mmu_itlb[replace].vpn = mmu_utlb[entryNo].vpn;
   539     mmu_itlb[replace].mask = mmu_utlb[entryNo].mask;
   540     mmu_itlb[replace].ppn = mmu_utlb[entryNo].ppn;
   541     mmu_itlb[replace].asid = mmu_utlb[entryNo].asid;
   542     mmu_itlb[replace].flags = mmu_utlb[entryNo].flags & 0x01DA;
   543     return replace;
   544 }
   546 /**
   547  * Perform the actual itlb lookup w/ asid protection
   548  * Possible utcomes are:
   549  *   0..63 Single match - good, return entry found
   550  *   -1 No match - raise a tlb data miss exception
   551  *   -2 Multiple matches - raise a multi-hit exception (reset)
   552  * @param vpn virtual address to resolve
   553  * @return the resultant ITLB entry, or an error.
   554  */
   555 static inline int mmu_itlb_lookup_vpn_asid( uint32_t vpn )
   556 {
   557     int result = -1;
   558     unsigned int i;
   560     for( i = 0; i < ITLB_ENTRY_COUNT; i++ ) {
   561 	if( (mmu_itlb[i].flags & TLB_VALID) &&
   562 	    ((mmu_itlb[i].flags & TLB_SHARE) || mmu_asid == mmu_itlb[i].asid) && 
   563 	    ((mmu_itlb[i].vpn ^ vpn) & mmu_itlb[i].mask) == 0 ) {
   564 	    if( result != -1 ) {
   565 		return -2;
   566 	    }
   567 	    result = i;
   568 	}
   569     }
   571     if( result == -1 ) {
   572 	int utlbEntry = mmu_utlb_lookup_vpn( vpn );
   573 	if( utlbEntry == -1 ) {
   574 	    return -1;
   575 	} else {
   576 	    return mmu_itlb_update_from_utlb( utlbEntry );
   577 	}
   578     }
   580     switch( result ) {
   581     case 0: mmu_lrui = (mmu_lrui & 0x07); break;
   582     case 1: mmu_lrui = (mmu_lrui & 0x19) | 0x20; break;
   583     case 2: mmu_lrui = (mmu_lrui & 0x3E) | 0x14; break;
   584     case 3: mmu_lrui = (mmu_lrui | 0x0B); break;
   585     }
   587     return result;
   588 }
   590 /**
   591  * Perform the actual itlb lookup on vpn only
   592  * Possible utcomes are:
   593  *   0..63 Single match - good, return entry found
   594  *   -1 No match - raise a tlb data miss exception
   595  *   -2 Multiple matches - raise a multi-hit exception (reset)
   596  * @param vpn virtual address to resolve
   597  * @return the resultant ITLB entry, or an error.
   598  */
   599 static inline int mmu_itlb_lookup_vpn( uint32_t vpn )
   600 {
   601     int result = -1;
   602     unsigned int i;
   604     for( i = 0; i < ITLB_ENTRY_COUNT; i++ ) {
   605 	if( (mmu_itlb[i].flags & TLB_VALID) &&
   606 	    ((mmu_itlb[i].vpn ^ vpn) & mmu_itlb[i].mask) == 0 ) {
   607 	    if( result != -1 ) {
   608 		return -2;
   609 	    }
   610 	    result = i;
   611 	}
   612     }
   614     if( result == -1 ) {
   615 	int utlbEntry = mmu_utlb_lookup_vpn( vpn );
   616 	if( utlbEntry == -1 ) {
   617 	    return -1;
   618 	} else {
   619 	    return mmu_itlb_update_from_utlb( utlbEntry );
   620 	}
   621     }
   623     switch( result ) {
   624     case 0: mmu_lrui = (mmu_lrui & 0x07); break;
   625     case 1: mmu_lrui = (mmu_lrui & 0x19) | 0x20; break;
   626     case 2: mmu_lrui = (mmu_lrui & 0x3E) | 0x14; break;
   627     case 3: mmu_lrui = (mmu_lrui | 0x0B); break;
   628     }
   630     return result;
   631 }
   633 sh4addr_t mmu_vma_to_phys_read( sh4vma_t addr )
   634 {
   635     uint32_t mmucr = MMIO_READ(MMU,MMUCR);
   636     if( addr & 0x80000000 ) {
   637 	if( IS_SH4_PRIVMODE() ) {
   638 	    if( addr >= 0xE0000000 ) {
   639 		return addr; /* P4 - passthrough */
   640 	    } else if( addr < 0xC0000000 ) {
   641 		/* P1, P2 regions are pass-through (no translation) */
   642 		return VMA_TO_EXT_ADDR(addr);
   643 	    }
   644 	} else {
   645 	    if( addr >= 0xE0000000 && addr < 0xE4000000 &&
   646 		((mmucr&MMUCR_SQMD) == 0) ) {
   647 		/* Conditional user-mode access to the store-queue (no translation) */
   648 		return addr;
   649 	    }
   650 	    MMU_READ_ADDR_ERROR();
   651 	    return MMU_VMA_ERROR;
   652 	}
   653     }
   655     if( (mmucr & MMUCR_AT) == 0 ) {
   656 	return VMA_TO_EXT_ADDR(addr);
   657     }
   659     /* If we get this far, translation is required */
   660     int entryNo;
   661     if( ((mmucr & MMUCR_SV) == 0) || !IS_SH4_PRIVMODE() ) {
   662 	entryNo = mmu_utlb_lookup_vpn_asid( addr );
   663     } else {
   664 	entryNo = mmu_utlb_lookup_vpn( addr );
   665     }
   667     switch(entryNo) {
   668     case -1:
   669 	MMU_TLB_READ_MISS_ERROR(addr);
   670 	return MMU_VMA_ERROR;
   671     case -2:
   672 	MMU_TLB_MULTI_HIT_ERROR(addr);
   673 	return MMU_VMA_ERROR;
   674     default:
   675 	if( (mmu_utlb[entryNo].flags & TLB_USERMODE) == 0 &&
   676 	    !IS_SH4_PRIVMODE() ) {
   677 	    /* protection violation */
   678 	    MMU_TLB_READ_PROT_ERROR(addr);
   679 	    return MMU_VMA_ERROR;
   680 	}
   682 	/* finally generate the target address */
   683 	return (mmu_utlb[entryNo].ppn & mmu_utlb[entryNo].mask) | 
   684 	    (addr & (~mmu_utlb[entryNo].mask));
   685     }
   686 }
   688 sh4addr_t mmu_vma_to_phys_write( sh4vma_t addr )
   689 {
   690     uint32_t mmucr = MMIO_READ(MMU,MMUCR);
   691     if( addr & 0x80000000 ) {
   692 	if( IS_SH4_PRIVMODE() ) {
   693 	    if( addr >= 0xE0000000 ) {
   694 		return addr; /* P4 - passthrough */
   695 	    } else if( addr < 0xC0000000 ) {
   696 		/* P1, P2 regions are pass-through (no translation) */
   697 		return VMA_TO_EXT_ADDR(addr);
   698 	    }
   699 	} else {
   700 	    if( addr >= 0xE0000000 && addr < 0xE4000000 &&
   701 		((mmucr&MMUCR_SQMD) == 0) ) {
   702 		/* Conditional user-mode access to the store-queue (no translation) */
   703 		return addr;
   704 	    }
   705 	    MMU_WRITE_ADDR_ERROR();
   706 	    return MMU_VMA_ERROR;
   707 	}
   708     }
   710     if( (mmucr & MMUCR_AT) == 0 ) {
   711 	return VMA_TO_EXT_ADDR(addr);
   712     }
   714     /* If we get this far, translation is required */
   715     int entryNo;
   716     if( ((mmucr & MMUCR_SV) == 0) || !IS_SH4_PRIVMODE() ) {
   717 	entryNo = mmu_utlb_lookup_vpn_asid( addr );
   718     } else {
   719 	entryNo = mmu_utlb_lookup_vpn( addr );
   720     }
   722     switch(entryNo) {
   723     case -1:
   724 	MMU_TLB_WRITE_MISS_ERROR(addr);
   725 	return MMU_VMA_ERROR;
   726     case -2:
   727 	MMU_TLB_MULTI_HIT_ERROR(addr);
   728 	return MMU_VMA_ERROR;
   729     default:
   730 	if( IS_SH4_PRIVMODE() ? ((mmu_utlb[entryNo].flags & TLB_WRITABLE) == 0)
   731 	    : ((mmu_utlb[entryNo].flags & TLB_USERWRITABLE) != TLB_USERWRITABLE) ) {
   732 	    /* protection violation */
   733 	    MMU_TLB_WRITE_PROT_ERROR(addr);
   734 	    return MMU_VMA_ERROR;
   735 	}
   737 	if( (mmu_utlb[entryNo].flags & TLB_DIRTY) == 0 ) {
   738 	    MMU_TLB_INITIAL_WRITE_ERROR(addr);
   739 	    return MMU_VMA_ERROR;
   740 	}
   742 	/* finally generate the target address */
   743 	return (mmu_utlb[entryNo].ppn & mmu_utlb[entryNo].mask) | 
   744 	    (addr & (~mmu_utlb[entryNo].mask));
   745     }
   746 }
   748 /**
   749  * Update the icache for an untranslated address
   750  */
   751 void mmu_update_icache_phys( sh4addr_t addr )
   752 {
   753     if( (addr & 0x1C000000) == 0x0C000000 ) {
   754 	/* Main ram */
   755 	sh4_icache.page_vma = addr & 0xFF000000;
   756 	sh4_icache.page_ppa = 0x0C000000;
   757 	sh4_icache.mask = 0xFF000000;
   758 	sh4_icache.page = sh4_main_ram;
   759     } else if( (addr & 0x1FE00000) == 0 ) {
   760 	/* BIOS ROM */
   761 	sh4_icache.page_vma = addr & 0xFFE00000;
   762 	sh4_icache.page_ppa = 0;
   763 	sh4_icache.mask = 0xFFE00000;
   764 	sh4_icache.page = mem_get_region(0);
   765     } else {
   766 	/* not supported */
   767 	sh4_icache.page_vma = -1;
   768     }
   769 }
   771 /**
   772  * Update the sh4_icache structure to describe the page(s) containing the
   773  * given vma. If the address does not reference a RAM/ROM region, the icache
   774  * will be invalidated instead.
   775  * If AT is on, this method will raise TLB exceptions normally
   776  * (hence this method should only be used immediately prior to execution of
   777  * code), and otherwise will set the icache according to the matching TLB entry.
   778  * If AT is off, this method will set the entire referenced RAM/ROM region in
   779  * the icache.
   780  * @return TRUE if the update completed (successfully or otherwise), FALSE
   781  * if an exception was raised.
   782  */
   783 gboolean mmu_update_icache( sh4vma_t addr )
   784 {
   785     int entryNo;
   786     if( IS_SH4_PRIVMODE()  ) {
   787 	if( addr & 0x80000000 ) {
   788 	    if( addr < 0xC0000000 ) {
   789 		/* P1, P2 and P4 regions are pass-through (no translation) */
   790 		mmu_update_icache_phys(addr);
   791 		return TRUE;
   792 	    } else if( addr >= 0xE0000000 && addr < 0xFFFFFF00 ) {
   793 		MMU_READ_ADDR_ERROR();
   794 		return FALSE;
   795 	    }
   796 	}
   798 	uint32_t mmucr = MMIO_READ(MMU,MMUCR);
   799 	if( (mmucr & MMUCR_AT) == 0 ) {
   800 	    mmu_update_icache_phys(addr);
   801 	    return TRUE;
   802 	}
   804 	entryNo = mmu_itlb_lookup_vpn( addr );
   805     } else {
   806 	if( addr & 0x80000000 ) {
   807 	    MMU_READ_ADDR_ERROR();
   808 	    return FALSE;
   809 	}
   811 	uint32_t mmucr = MMIO_READ(MMU,MMUCR);
   812 	if( (mmucr & MMUCR_AT) == 0 ) {
   813 	    mmu_update_icache_phys(addr);
   814 	    return TRUE;
   815 	}
   817 	if( mmucr & MMUCR_SV ) {
   818 	    entryNo = mmu_itlb_lookup_vpn( addr );
   819 	} else {
   820 	    entryNo = mmu_itlb_lookup_vpn_asid( addr );
   821 	}
   822 	if( entryNo != -1 && (mmu_itlb[entryNo].flags & TLB_USERMODE) == 0 ) {
   823 	    MMU_TLB_READ_PROT_ERROR(addr);
   824 	    return FALSE;
   825 	}
   826     }
   828     switch(entryNo) {
   829     case -1:
   830 	MMU_TLB_READ_MISS_ERROR(addr);
   831 	return FALSE;
   832     case -2:
   833 	MMU_TLB_MULTI_HIT_ERROR(addr);
   834 	return FALSE;
   835     default:
   836 	sh4_icache.page_ppa = mmu_itlb[entryNo].ppn & mmu_itlb[entryNo].mask;
   837 	sh4_icache.page = mem_get_region( sh4_icache.page_ppa );
   838 	if( sh4_icache.page == NULL ) {
   839 	    sh4_icache.page_vma = -1;
   840 	} else {
   841 	    sh4_icache.page_vma = mmu_itlb[entryNo].vpn & mmu_itlb[entryNo].mask;
   842 	    sh4_icache.mask = mmu_itlb[entryNo].mask;
   843 	}
   844 	return TRUE;
   845     }
   846 }
.