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lxdream.org :: lxdream/src/sh4/sh4core.in
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4core.in
changeset 570:d2893980fbf5
prev569:a1c49e1e8776
next576:4945fa2ed24f
author nkeynes
date Sun Jan 06 12:24:18 2008 +0000 (12 years ago)
branchlxdream-mmu
permissions -rw-r--r--
last change Change to generate different code for mmu on/off cases
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     1 /**
     2  * $Id$
     3  * 
     4  * SH4 emulation core, and parent module for all the SH4 peripheral
     5  * modules.
     6  *
     7  * Copyright (c) 2005 Nathan Keynes.
     8  *
     9  * This program is free software; you can redistribute it and/or modify
    10  * it under the terms of the GNU General Public License as published by
    11  * the Free Software Foundation; either version 2 of the License, or
    12  * (at your option) any later version.
    13  *
    14  * This program is distributed in the hope that it will be useful,
    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17  * GNU General Public License for more details.
    18  */
    20 #define MODULE sh4_module
    21 #include <math.h>
    22 #include "dream.h"
    23 #include "dreamcast.h"
    24 #include "eventq.h"
    25 #include "mem.h"
    26 #include "clock.h"
    27 #include "syscall.h"
    28 #include "sh4/sh4core.h"
    29 #include "sh4/sh4mmio.h"
    30 #include "sh4/intc.h"
    32 #define SH4_CALLTRACE 1
    34 #define MAX_INT 0x7FFFFFFF
    35 #define MIN_INT 0x80000000
    36 #define MAX_INTF 2147483647.0
    37 #define MIN_INTF -2147483648.0
    39 /********************** SH4 Module Definition ****************************/
    41 uint32_t sh4_run_slice( uint32_t nanosecs ) 
    42 {
    43     int i;
    44     sh4r.slice_cycle = 0;
    46     if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
    47 	if( sh4r.event_pending < nanosecs ) {
    48 	    sh4r.sh4_state = SH4_STATE_RUNNING;
    49 	    sh4r.slice_cycle = sh4r.event_pending;
    50 	}
    51     }
    53     if( sh4_breakpoint_count == 0 ) {
    54 	for( ; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
    55 	    if( SH4_EVENT_PENDING() ) {
    56 		if( sh4r.event_types & PENDING_EVENT ) {
    57 		    event_execute();
    58 		}
    59 		/* Eventq execute may (quite likely) deliver an immediate IRQ */
    60 		if( sh4r.event_types & PENDING_IRQ ) {
    61 		    sh4_accept_interrupt();
    62 		}
    63 	    }
    64 	    if( !sh4_execute_instruction() ) {
    65 		break;
    66 	    }
    67 	}
    68     } else {
    69 	for( ;sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
    70 	    if( SH4_EVENT_PENDING() ) {
    71 		if( sh4r.event_types & PENDING_EVENT ) {
    72 		    event_execute();
    73 		}
    74 		/* Eventq execute may (quite likely) deliver an immediate IRQ */
    75 		if( sh4r.event_types & PENDING_IRQ ) {
    76 		    sh4_accept_interrupt();
    77 		}
    78 	    }
    80 	    if( !sh4_execute_instruction() )
    81 		break;
    82 #ifdef ENABLE_DEBUG_MODE
    83 	    for( i=0; i<sh4_breakpoint_count; i++ ) {
    84 		if( sh4_breakpoints[i].address == sh4r.pc ) {
    85 		    break;
    86 		}
    87 	    }
    88 	    if( i != sh4_breakpoint_count ) {
    89 		dreamcast_stop();
    90 		if( sh4_breakpoints[i].type == BREAK_ONESHOT )
    91 		    sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );
    92 		break;
    93 	    }
    94 #endif	
    95 	}
    96     }
    98     /* If we aborted early, but the cpu is still technically running,
    99      * we're doing a hard abort - cut the timeslice back to what we
   100      * actually executed
   101      */
   102     if( sh4r.slice_cycle != nanosecs && sh4r.sh4_state == SH4_STATE_RUNNING ) {
   103 	nanosecs = sh4r.slice_cycle;
   104     }
   105     if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
   106 	TMU_run_slice( nanosecs );
   107 	SCIF_run_slice( nanosecs );
   108     }
   109     return nanosecs;
   110 }
   112 /********************** SH4 emulation core  ****************************/
   114 #define UNDEF(ir) return sh4_raise_slot_exception(EXC_ILLEGAL, EXC_SLOT_ILLEGAL)
   115 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)
   117 #if(SH4_CALLTRACE == 1)
   118 #define MAX_CALLSTACK 32
   119 static struct call_stack {
   120     sh4addr_t call_addr;
   121     sh4addr_t target_addr;
   122     sh4addr_t stack_pointer;
   123 } call_stack[MAX_CALLSTACK];
   125 static int call_stack_depth = 0;
   126 int sh4_call_trace_on = 0;
   128 static inline void trace_call( sh4addr_t source, sh4addr_t dest ) 
   129 {
   130     if( call_stack_depth < MAX_CALLSTACK ) {
   131 	call_stack[call_stack_depth].call_addr = source;
   132 	call_stack[call_stack_depth].target_addr = dest;
   133 	call_stack[call_stack_depth].stack_pointer = sh4r.r[15];
   134     }
   135     call_stack_depth++;
   136 }
   138 static inline void trace_return( sh4addr_t source, sh4addr_t dest )
   139 {
   140     if( call_stack_depth > 0 ) {
   141 	call_stack_depth--;
   142     }
   143 }
   145 void fprint_stack_trace( FILE *f )
   146 {
   147     int i = call_stack_depth -1;
   148     if( i >= MAX_CALLSTACK )
   149 	i = MAX_CALLSTACK - 1;
   150     for( ; i >= 0; i-- ) {
   151 	fprintf( f, "%d. Call from %08X => %08X, SP=%08X\n", 
   152 		 (call_stack_depth - i), call_stack[i].call_addr,
   153 		 call_stack[i].target_addr, call_stack[i].stack_pointer );
   154     }
   155 }
   157 #define TRACE_CALL( source, dest ) trace_call(source, dest)
   158 #define TRACE_RETURN( source, dest ) trace_return(source, dest)
   159 #else
   160 #define TRACE_CALL( dest, rts ) 
   161 #define TRACE_RETURN( source, dest )
   162 #endif
   164 #define MEM_READ_BYTE( addr, val ) memtmp = mmu_vma_to_phys_read(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { val = sh4_read_byte(memtmp); }
   165 #define MEM_READ_WORD( addr, val ) memtmp = mmu_vma_to_phys_read(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { val = sh4_read_word(memtmp); }
   166 #define MEM_READ_LONG( addr, val ) memtmp = mmu_vma_to_phys_read(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { val = sh4_read_long(memtmp); }
   167 #define MEM_WRITE_BYTE( addr, val ) memtmp = mmu_vma_to_phys_write(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { sh4_write_byte(memtmp, val); }
   168 #define MEM_WRITE_WORD( addr, val ) memtmp = mmu_vma_to_phys_write(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { sh4_write_word(memtmp, val); }
   169 #define MEM_WRITE_LONG( addr, val ) memtmp = mmu_vma_to_phys_write(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { sh4_write_long(memtmp, val); }
   171 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
   173 #define MEM_FP_READ( addr, reg ) sh4_read_float( addr, reg );
   174 #define MEM_FP_WRITE( addr, reg ) sh4_write_float( addr, reg );
   176 #define CHECKPRIV() if( !IS_SH4_PRIVMODE() ) return sh4_raise_slot_exception( EXC_ILLEGAL, EXC_SLOT_ILLEGAL )
   177 #define CHECKRALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )
   178 #define CHECKRALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )
   179 #define CHECKWALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )
   180 #define CHECKWALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )
   182 #define CHECKFPUEN() if( !IS_FPU_ENABLED() ) { if( ir == 0xFFFD ) { UNDEF(ir); } else { return sh4_raise_slot_exception( EXC_FPU_DISABLED, EXC_SLOT_FPU_DISABLED ); } }
   183 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); dreamcast_stop(); return FALSE; }
   184 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) return sh4_raise_exception(EXC_SLOT_ILLEGAL)
   186 static void sh4_write_float( uint32_t addr, int reg )
   187 {
   188     if( IS_FPU_DOUBLESIZE() ) {
   189 	if( reg & 1 ) {
   190 	    sh4_write_long( addr, *((uint32_t *)&XF((reg)&0x0E)) );
   191 	    sh4_write_long( addr+4, *((uint32_t *)&XF(reg)) );
   192 	} else {
   193 	    sh4_write_long( addr, *((uint32_t *)&FR(reg)) ); 
   194 	    sh4_write_long( addr+4, *((uint32_t *)&FR((reg)|0x01)) );
   195 	}
   196     } else {
   197 	sh4_write_long( addr, *((uint32_t *)&FR((reg))) );
   198     }
   199 }
   201 static void sh4_read_float( uint32_t addr, int reg )
   202 {
   203     if( IS_FPU_DOUBLESIZE() ) {
   204 	if( reg & 1 ) {
   205 	    *((uint32_t *)&XF((reg) & 0x0E)) = sh4_read_long(addr);
   206 	    *((uint32_t *)&XF(reg)) = sh4_read_long(addr+4);
   207 	} else {
   208 	    *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
   209 	    *((uint32_t *)&FR((reg) | 0x01)) = sh4_read_long(addr+4);
   210 	}
   211     } else {
   212 	*((uint32_t *)&FR(reg)) = sh4_read_long(addr);
   213     }
   214 }
   216 gboolean sh4_execute_instruction( void )
   217 {
   218     uint32_t pc;
   219     unsigned short ir;
   220     uint32_t tmp;
   221     float ftmp;
   222     double dtmp;
   223     int64_t memtmp; // temporary holder for memory reads
   225 #define R0 sh4r.r[0]
   226     pc = sh4r.pc;
   227     if( pc > 0xFFFFFF00 ) {
   228 	/* SYSCALL Magic */
   229 	syscall_invoke( pc );
   230 	sh4r.in_delay_slot = 0;
   231 	pc = sh4r.pc = sh4r.pr;
   232 	sh4r.new_pc = sh4r.pc + 2;
   233     }
   234     CHECKRALIGN16(pc);
   236     /* Read instruction */
   237     uint32_t pageaddr = pc >> 12;
   238     if( !IS_IN_ICACHE(pc) ) {
   239 	mmu_update_icache(pc);
   240     }
   241     if( IS_IN_ICACHE(pc) ) {
   242 	ir = *(uint16_t *)GET_ICACHE_PTR(pc);
   243     } else {
   244 	ir = sh4_read_word(pc);
   245     }
   246 %%
   247 AND Rm, Rn {: sh4r.r[Rn] &= sh4r.r[Rm]; :}
   248 AND #imm, R0 {: R0 &= imm; :}
   249  AND.B #imm, @(R0, GBR) {: MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm & tmp ); :}
   250 NOT Rm, Rn {: sh4r.r[Rn] = ~sh4r.r[Rm]; :}
   251 OR Rm, Rn {: sh4r.r[Rn] |= sh4r.r[Rm]; :}
   252 OR #imm, R0  {: R0 |= imm; :}
   253  OR.B #imm, @(R0, GBR) {: MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm | tmp ); :}
   254 TAS.B @Rn {:
   255     MEM_READ_BYTE( sh4r.r[Rn], tmp );
   256     sh4r.t = ( tmp == 0 ? 1 : 0 );
   257     MEM_WRITE_BYTE( sh4r.r[Rn], tmp | 0x80 );
   258 :}
   259 TST Rm, Rn {: sh4r.t = (sh4r.r[Rn]&sh4r.r[Rm] ? 0 : 1); :}
   260 TST #imm, R0 {: sh4r.t = (R0 & imm ? 0 : 1); :}
   261  TST.B #imm, @(R0, GBR) {: MEM_READ_BYTE(R0+sh4r.gbr, tmp); sh4r.t = ( tmp & imm ? 0 : 1 ); :}
   262 XOR Rm, Rn {: sh4r.r[Rn] ^= sh4r.r[Rm]; :}
   263 XOR #imm, R0 {: R0 ^= imm; :}
   264  XOR.B #imm, @(R0, GBR) {: MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm ^ tmp ); :}
   265 XTRCT Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rn]>>16) | (sh4r.r[Rm]<<16); :}
   267 ROTL Rn {:
   268     sh4r.t = sh4r.r[Rn] >> 31;
   269     sh4r.r[Rn] <<= 1;
   270     sh4r.r[Rn] |= sh4r.t;
   271 :}
   272 ROTR Rn {:
   273     sh4r.t = sh4r.r[Rn] & 0x00000001;
   274     sh4r.r[Rn] >>= 1;
   275     sh4r.r[Rn] |= (sh4r.t << 31);
   276 :}
   277 ROTCL Rn {:
   278     tmp = sh4r.r[Rn] >> 31;
   279     sh4r.r[Rn] <<= 1;
   280     sh4r.r[Rn] |= sh4r.t;
   281     sh4r.t = tmp;
   282 :}
   283 ROTCR Rn {:
   284     tmp = sh4r.r[Rn] & 0x00000001;
   285     sh4r.r[Rn] >>= 1;
   286     sh4r.r[Rn] |= (sh4r.t << 31 );
   287     sh4r.t = tmp;
   288 :}
   289 SHAD Rm, Rn {:
   290     tmp = sh4r.r[Rm];
   291     if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
   292     else if( (tmp & 0x1F) == 0 )  
   293         sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 31;
   294     else 
   295 	sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> (((~sh4r.r[Rm]) & 0x1F)+1);
   296 :}
   297 SHLD Rm, Rn {:
   298     tmp = sh4r.r[Rm];
   299     if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
   300     else if( (tmp & 0x1F) == 0 ) sh4r.r[Rn] = 0;
   301     else sh4r.r[Rn] >>= (((~tmp) & 0x1F)+1);
   302 :}
   303 SHAL Rn {:
   304     sh4r.t = sh4r.r[Rn] >> 31;
   305     sh4r.r[Rn] <<= 1;
   306 :}
   307 SHAR Rn {:
   308     sh4r.t = sh4r.r[Rn] & 0x00000001;
   309     sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 1;
   310 :}
   311 SHLL Rn {: sh4r.t = sh4r.r[Rn] >> 31; sh4r.r[Rn] <<= 1; :}
   312 SHLR Rn {: sh4r.t = sh4r.r[Rn] & 0x00000001; sh4r.r[Rn] >>= 1; :}
   313 SHLL2 Rn {: sh4r.r[Rn] <<= 2; :}
   314 SHLR2 Rn {: sh4r.r[Rn] >>= 2; :}
   315 SHLL8 Rn {: sh4r.r[Rn] <<= 8; :}
   316 SHLR8 Rn {: sh4r.r[Rn] >>= 8; :}
   317 SHLL16 Rn {: sh4r.r[Rn] <<= 16; :}
   318 SHLR16 Rn {: sh4r.r[Rn] >>= 16; :}
   320 EXTU.B Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]&0x000000FF; :}
   321 EXTU.W Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]&0x0000FFFF; :}
   322 EXTS.B Rm, Rn {: sh4r.r[Rn] = SIGNEXT8( sh4r.r[Rm]&0x000000FF ); :}
   323 EXTS.W Rm, Rn {: sh4r.r[Rn] = SIGNEXT16( sh4r.r[Rm]&0x0000FFFF ); :}
   324 SWAP.B Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rm]&0xFFFF0000) | ((sh4r.r[Rm]&0x0000FF00)>>8) | ((sh4r.r[Rm]&0x000000FF)<<8); :}
   325 SWAP.W Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rm]>>16) | (sh4r.r[Rm]<<16); :}
   327 CLRT {: sh4r.t = 0; :}
   328 SETT {: sh4r.t = 1; :}
   329 CLRMAC {: sh4r.mac = 0; :}
   330 LDTLB {: MMU_ldtlb(); :}
   331 CLRS {: sh4r.s = 0; :}
   332 SETS {: sh4r.s = 1; :}
   333 MOVT Rn {: sh4r.r[Rn] = sh4r.t; :}
   334 NOP {: /* NOP */ :}
   336 PREF @Rn {:
   337      tmp = sh4r.r[Rn];
   338      if( (tmp & 0xFC000000) == 0xE0000000 ) {
   339 	 sh4_flush_store_queue(tmp);
   340      }
   341 :}
   342 OCBI @Rn {: :}
   343 OCBP @Rn {: :}
   344 OCBWB @Rn {: :}
   345 MOVCA.L R0, @Rn {:
   346     tmp = sh4r.r[Rn];
   347     CHECKWALIGN32(tmp);
   348     MEM_WRITE_LONG( tmp, R0 );
   349 :}
   350 MOV.B Rm, @(R0, Rn) {: MEM_WRITE_BYTE( R0 + sh4r.r[Rn], sh4r.r[Rm] ); :}
   351 MOV.W Rm, @(R0, Rn) {: 
   352     CHECKWALIGN16( R0 + sh4r.r[Rn] );
   353     MEM_WRITE_WORD( R0 + sh4r.r[Rn], sh4r.r[Rm] );
   354 :}
   355 MOV.L Rm, @(R0, Rn) {:
   356     CHECKWALIGN32( R0 + sh4r.r[Rn] );
   357     MEM_WRITE_LONG( R0 + sh4r.r[Rn], sh4r.r[Rm] );
   358 :}
   359 MOV.B @(R0, Rm), Rn {: MEM_READ_BYTE( R0 + sh4r.r[Rm], sh4r.r[Rn] ); :}
   360 MOV.W @(R0, Rm), Rn {: CHECKRALIGN16( R0 + sh4r.r[Rm] );
   361     MEM_READ_WORD( R0 + sh4r.r[Rm], sh4r.r[Rn] );
   362 :}
   363 MOV.L @(R0, Rm), Rn {: CHECKRALIGN32( R0 + sh4r.r[Rm] );
   364     MEM_READ_LONG( R0 + sh4r.r[Rm], sh4r.r[Rn] );
   365 :}
   366 MOV.L Rm, @(disp, Rn) {:
   367     tmp = sh4r.r[Rn] + disp;
   368     CHECKWALIGN32( tmp );
   369     MEM_WRITE_LONG( tmp, sh4r.r[Rm] );
   370 :}
   371 MOV.B Rm, @Rn {: MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] ); :}
   372 MOV.W Rm, @Rn {: CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] ); :}
   373 MOV.L Rm, @Rn {: CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] ); :}
   374 MOV.B Rm, @-Rn {: sh4r.r[Rn] --; MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] ); :}
   375 MOV.W Rm, @-Rn {: sh4r.r[Rn] -= 2; CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] ); :}
   376 MOV.L Rm, @-Rn {: sh4r.r[Rn] -= 4; CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] ); :}
   377 MOV.L @(disp, Rm), Rn {:
   378     tmp = sh4r.r[Rm] + disp;
   379     CHECKRALIGN32( tmp );
   380     MEM_READ_LONG( tmp, sh4r.r[Rn] );
   381 :}
   382 MOV.B @Rm, Rn {: MEM_READ_BYTE( sh4r.r[Rm], sh4r.r[Rn] ); :}
   383  MOV.W @Rm, Rn {: CHECKRALIGN16( sh4r.r[Rm] ); MEM_READ_WORD( sh4r.r[Rm], sh4r.r[Rn] ); :}
   384  MOV.L @Rm, Rn {: CHECKRALIGN32( sh4r.r[Rm] ); MEM_READ_LONG( sh4r.r[Rm], sh4r.r[Rn] ); :}
   385 MOV Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]; :}
   386  MOV.B @Rm+, Rn {: MEM_READ_BYTE( sh4r.r[Rm], sh4r.r[Rn] ); sh4r.r[Rm] ++; :}
   387  MOV.W @Rm+, Rn {: CHECKRALIGN16( sh4r.r[Rm] ); MEM_READ_WORD( sh4r.r[Rm], sh4r.r[Rn] ); sh4r.r[Rm] += 2; :}
   388  MOV.L @Rm+, Rn {: CHECKRALIGN32( sh4r.r[Rm] ); MEM_READ_LONG( sh4r.r[Rm], sh4r.r[Rn] ); sh4r.r[Rm] += 4; :}
   389 MOV.L @(disp, PC), Rn {:
   390     CHECKSLOTILLEGAL();
   391     tmp = (pc&0xFFFFFFFC) + disp + 4;
   392     MEM_READ_LONG( tmp, sh4r.r[Rn] );
   393 :}
   394 MOV.B R0, @(disp, GBR) {: MEM_WRITE_BYTE( sh4r.gbr + disp, R0 ); :}
   395 MOV.W R0, @(disp, GBR) {:
   396     tmp = sh4r.gbr + disp;
   397     CHECKWALIGN16( tmp );
   398     MEM_WRITE_WORD( tmp, R0 );
   399 :}
   400 MOV.L R0, @(disp, GBR) {:
   401     tmp = sh4r.gbr + disp;
   402     CHECKWALIGN32( tmp );
   403     MEM_WRITE_LONG( tmp, R0 );
   404 :}
   405  MOV.B @(disp, GBR), R0 {: MEM_READ_BYTE( sh4r.gbr + disp, R0 ); :}
   406 MOV.W @(disp, GBR), R0 {: 
   407     tmp = sh4r.gbr + disp;
   408     CHECKRALIGN16( tmp );
   409     MEM_READ_WORD( tmp, R0 );
   410 :}
   411 MOV.L @(disp, GBR), R0 {:
   412     tmp = sh4r.gbr + disp;
   413     CHECKRALIGN32( tmp );
   414     MEM_READ_LONG( tmp, R0 );
   415 :}
   416 MOV.B R0, @(disp, Rn) {: MEM_WRITE_BYTE( sh4r.r[Rn] + disp, R0 ); :}
   417 MOV.W R0, @(disp, Rn) {: 
   418     tmp = sh4r.r[Rn] + disp;
   419     CHECKWALIGN16( tmp );
   420     MEM_WRITE_WORD( tmp, R0 );
   421 :}
   422  MOV.B @(disp, Rm), R0 {: MEM_READ_BYTE( sh4r.r[Rm] + disp, R0 ); :}
   423 MOV.W @(disp, Rm), R0 {: 
   424     tmp = sh4r.r[Rm] + disp;
   425     CHECKRALIGN16( tmp );
   426     MEM_READ_WORD( tmp, R0 );
   427 :}
   428 MOV.W @(disp, PC), Rn {:
   429     CHECKSLOTILLEGAL();
   430     tmp = pc + 4 + disp;
   431     MEM_READ_WORD( tmp, sh4r.r[Rn] );
   432 :}
   433 MOVA @(disp, PC), R0 {:
   434     CHECKSLOTILLEGAL();
   435     R0 = (pc&0xFFFFFFFC) + disp + 4;
   436 :}
   437 MOV #imm, Rn {:  sh4r.r[Rn] = imm; :}
   439 CMP/EQ #imm, R0 {: sh4r.t = ( R0 == imm ? 1 : 0 ); :}
   440 CMP/EQ Rm, Rn {: sh4r.t = ( sh4r.r[Rm] == sh4r.r[Rn] ? 1 : 0 ); :}
   441 CMP/GE Rm, Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= ((int32_t)sh4r.r[Rm]) ? 1 : 0 ); :}
   442 CMP/GT Rm, Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) > ((int32_t)sh4r.r[Rm]) ? 1 : 0 ); :}
   443 CMP/HI Rm, Rn {: sh4r.t = ( sh4r.r[Rn] > sh4r.r[Rm] ? 1 : 0 ); :}
   444 CMP/HS Rm, Rn {: sh4r.t = ( sh4r.r[Rn] >= sh4r.r[Rm] ? 1 : 0 ); :}
   445 CMP/PL Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) > 0 ? 1 : 0 ); :}
   446 CMP/PZ Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= 0 ? 1 : 0 ); :}
   447 CMP/STR Rm, Rn {: 
   448     /* set T = 1 if any byte in RM & RN is the same */
   449     tmp = sh4r.r[Rm] ^ sh4r.r[Rn];
   450     sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
   451              (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
   452 :}
   454 ADD Rm, Rn {: sh4r.r[Rn] += sh4r.r[Rm]; :}
   455 ADD #imm, Rn {: sh4r.r[Rn] += imm; :}
   456 ADDC Rm, Rn {:
   457     tmp = sh4r.r[Rn];
   458     sh4r.r[Rn] += sh4r.r[Rm] + sh4r.t;
   459     sh4r.t = ( sh4r.r[Rn] < tmp || (sh4r.r[Rn] == tmp && sh4r.t != 0) ? 1 : 0 );
   460 :}
   461 ADDV Rm, Rn {:
   462     tmp = sh4r.r[Rn] + sh4r.r[Rm];
   463     sh4r.t = ( (sh4r.r[Rn]>>31) == (sh4r.r[Rm]>>31) && ((sh4r.r[Rn]>>31) != (tmp>>31)) );
   464     sh4r.r[Rn] = tmp;
   465 :}
   466 DIV0U {: sh4r.m = sh4r.q = sh4r.t = 0; :}
   467 DIV0S Rm, Rn {: 
   468     sh4r.q = sh4r.r[Rn]>>31;
   469     sh4r.m = sh4r.r[Rm]>>31;
   470     sh4r.t = sh4r.q ^ sh4r.m;
   471 :}
   472 DIV1 Rm, Rn {:
   473     /* This is derived from the sh4 manual with some simplifications */
   474     uint32_t tmp0, tmp1, tmp2, dir;
   476     dir = sh4r.q ^ sh4r.m;
   477     sh4r.q = (sh4r.r[Rn] >> 31);
   478     tmp2 = sh4r.r[Rm];
   479     sh4r.r[Rn] = (sh4r.r[Rn] << 1) | sh4r.t;
   480     tmp0 = sh4r.r[Rn];
   481     if( dir ) {
   482          sh4r.r[Rn] += tmp2;
   483          tmp1 = (sh4r.r[Rn]<tmp0 ? 1 : 0 );
   484     } else {
   485          sh4r.r[Rn] -= tmp2;
   486          tmp1 = (sh4r.r[Rn]>tmp0 ? 1 : 0 );
   487     }
   488     sh4r.q ^= sh4r.m ^ tmp1;
   489     sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
   490 :}
   491 DMULS.L Rm, Rn {: sh4r.mac = SIGNEXT32(sh4r.r[Rm]) * SIGNEXT32(sh4r.r[Rn]); :}
   492 DMULU.L Rm, Rn {: sh4r.mac = ((uint64_t)sh4r.r[Rm]) * ((uint64_t)sh4r.r[Rn]); :}
   493 DT Rn {:
   494     sh4r.r[Rn] --;
   495     sh4r.t = ( sh4r.r[Rn] == 0 ? 1 : 0 );
   496 :}
   497 MAC.W @Rm+, @Rn+ {:
   498     CHECKRALIGN16( sh4r.r[Rn] );
   499     CHECKRALIGN16( sh4r.r[Rm] );
   500     MEM_READ_WORD(sh4r.r[Rn], tmp);
   501     int32_t stmp = SIGNEXT16(tmp);
   502     sh4r.r[Rn] += 2;
   503     MEM_READ_WORD(sh4r.r[Rm], tmp);
   504     stmp = stmp * SIGNEXT16(tmp);
   505     sh4r.r[Rm] += 2;
   506     if( sh4r.s ) {
   507 	int64_t tmpl = (int64_t)((int32_t)sh4r.mac) + (int64_t)stmp;
   508 	if( tmpl > (int64_t)0x000000007FFFFFFFLL ) {
   509 	    sh4r.mac = 0x000000017FFFFFFFLL;
   510 	} else if( tmpl < (int64_t)0xFFFFFFFF80000000LL ) {
   511 	    sh4r.mac = 0x0000000180000000LL;
   512 	} else {
   513 	    sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
   514 		((uint32_t)(sh4r.mac + stmp));
   515 	}
   516     } else {
   517 	sh4r.mac += SIGNEXT32(stmp);
   518     }
   519 :}
   520 MAC.L @Rm+, @Rn+ {:
   521     CHECKRALIGN32( sh4r.r[Rm] );
   522     CHECKRALIGN32( sh4r.r[Rn] );
   523     MEM_READ_LONG(sh4r.r[Rn], tmp);
   524     int64_t tmpl = SIGNEXT32(tmp);
   525     sh4r.r[Rn] += 4;
   526     MEM_READ_LONG(sh4r.r[Rm], tmp);
   527     tmpl = tmpl * SIGNEXT32(tmp) + sh4r.mac;
   528     sh4r.r[Rm] += 4;
   529     if( sh4r.s ) {
   530         /* 48-bit Saturation. Yuch */
   531         if( tmpl < (int64_t)0xFFFF800000000000LL )
   532             tmpl = 0xFFFF800000000000LL;
   533         else if( tmpl > (int64_t)0x00007FFFFFFFFFFFLL )
   534             tmpl = 0x00007FFFFFFFFFFFLL;
   535     }
   536     sh4r.mac = tmpl;
   537 :}
   538 MUL.L Rm, Rn {: sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   539                         (sh4r.r[Rm] * sh4r.r[Rn]); :}
   540 MULU.W Rm, Rn {:
   541     sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   542                (uint32_t)((sh4r.r[Rm]&0xFFFF) * (sh4r.r[Rn]&0xFFFF));
   543 :}
   544 MULS.W Rm, Rn {:
   545     sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   546                (uint32_t)(SIGNEXT32(sh4r.r[Rm]&0xFFFF) * SIGNEXT32(sh4r.r[Rn]&0xFFFF));
   547 :}
   548 NEGC Rm, Rn {:
   549     tmp = 0 - sh4r.r[Rm];
   550     sh4r.r[Rn] = tmp - sh4r.t;
   551     sh4r.t = ( 0<tmp || tmp<sh4r.r[Rn] ? 1 : 0 );
   552 :}
   553 NEG Rm, Rn {: sh4r.r[Rn] = 0 - sh4r.r[Rm]; :}
   554 SUB Rm, Rn {: sh4r.r[Rn] -= sh4r.r[Rm]; :}
   555 SUBC Rm, Rn {: 
   556     tmp = sh4r.r[Rn];
   557     sh4r.r[Rn] = sh4r.r[Rn] - sh4r.r[Rm] - sh4r.t;
   558     sh4r.t = (sh4r.r[Rn] > tmp || (sh4r.r[Rn] == tmp && sh4r.t == 1));
   559 :}
   561 BRAF Rn {:
   562      CHECKSLOTILLEGAL();
   563      CHECKDEST( pc + 4 + sh4r.r[Rn] );
   564      sh4r.in_delay_slot = 1;
   565      sh4r.pc = sh4r.new_pc;
   566      sh4r.new_pc = pc + 4 + sh4r.r[Rn];
   567      return TRUE;
   568 :}
   569 BSRF Rn {:
   570      CHECKSLOTILLEGAL();
   571      CHECKDEST( pc + 4 + sh4r.r[Rn] );
   572      sh4r.in_delay_slot = 1;
   573      sh4r.pr = sh4r.pc + 4;
   574      sh4r.pc = sh4r.new_pc;
   575      sh4r.new_pc = pc + 4 + sh4r.r[Rn];
   576      TRACE_CALL( pc, sh4r.new_pc );
   577      return TRUE;
   578 :}
   579 BT disp {:
   580     CHECKSLOTILLEGAL();
   581     if( sh4r.t ) {
   582         CHECKDEST( sh4r.pc + disp + 4 )
   583         sh4r.pc += disp + 4;
   584         sh4r.new_pc = sh4r.pc + 2;
   585         return TRUE;
   586     }
   587 :}
   588 BF disp {:
   589     CHECKSLOTILLEGAL();
   590     if( !sh4r.t ) {
   591         CHECKDEST( sh4r.pc + disp + 4 )
   592         sh4r.pc += disp + 4;
   593         sh4r.new_pc = sh4r.pc + 2;
   594         return TRUE;
   595     }
   596 :}
   597 BT/S disp {:
   598     CHECKSLOTILLEGAL();
   599     if( sh4r.t ) {
   600         CHECKDEST( sh4r.pc + disp + 4 )
   601         sh4r.in_delay_slot = 1;
   602         sh4r.pc = sh4r.new_pc;
   603         sh4r.new_pc = pc + disp + 4;
   604         sh4r.in_delay_slot = 1;
   605         return TRUE;
   606     }
   607 :}
   608 BF/S disp {:
   609     CHECKSLOTILLEGAL();
   610     if( !sh4r.t ) {
   611         CHECKDEST( sh4r.pc + disp + 4 )
   612         sh4r.in_delay_slot = 1;
   613         sh4r.pc = sh4r.new_pc;
   614         sh4r.new_pc = pc + disp + 4;
   615         return TRUE;
   616     }
   617 :}
   618 BRA disp {:
   619     CHECKSLOTILLEGAL();
   620     CHECKDEST( sh4r.pc + disp + 4 );
   621     sh4r.in_delay_slot = 1;
   622     sh4r.pc = sh4r.new_pc;
   623     sh4r.new_pc = pc + 4 + disp;
   624     return TRUE;
   625 :}
   626 BSR disp {:
   627     CHECKDEST( sh4r.pc + disp + 4 );
   628     CHECKSLOTILLEGAL();
   629     sh4r.in_delay_slot = 1;
   630     sh4r.pr = pc + 4;
   631     sh4r.pc = sh4r.new_pc;
   632     sh4r.new_pc = pc + 4 + disp;
   633     TRACE_CALL( pc, sh4r.new_pc );
   634     return TRUE;
   635 :}
   636 TRAPA #imm {:
   637     CHECKSLOTILLEGAL();
   638     MMIO_WRITE( MMU, TRA, imm<<2 );
   639     sh4r.pc += 2;
   640     sh4_raise_exception( EXC_TRAP );
   641 :}
   642 RTS {: 
   643     CHECKSLOTILLEGAL();
   644     CHECKDEST( sh4r.pr );
   645     sh4r.in_delay_slot = 1;
   646     sh4r.pc = sh4r.new_pc;
   647     sh4r.new_pc = sh4r.pr;
   648     TRACE_RETURN( pc, sh4r.new_pc );
   649     return TRUE;
   650 :}
   651 SLEEP {:
   652     if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
   653 	sh4r.sh4_state = SH4_STATE_STANDBY;
   654     } else {
   655 	sh4r.sh4_state = SH4_STATE_SLEEP;
   656     }
   657     return FALSE; /* Halt CPU */
   658 :}
   659 RTE {:
   660     CHECKPRIV();
   661     CHECKDEST( sh4r.spc );
   662     CHECKSLOTILLEGAL();
   663     sh4r.in_delay_slot = 1;
   664     sh4r.pc = sh4r.new_pc;
   665     sh4r.new_pc = sh4r.spc;
   666     sh4_write_sr( sh4r.ssr );
   667     return TRUE;
   668 :}
   669 JMP @Rn {:
   670     CHECKDEST( sh4r.r[Rn] );
   671     CHECKSLOTILLEGAL();
   672     sh4r.in_delay_slot = 1;
   673     sh4r.pc = sh4r.new_pc;
   674     sh4r.new_pc = sh4r.r[Rn];
   675     return TRUE;
   676 :}
   677 JSR @Rn {:
   678     CHECKDEST( sh4r.r[Rn] );
   679     CHECKSLOTILLEGAL();
   680     sh4r.in_delay_slot = 1;
   681     sh4r.pc = sh4r.new_pc;
   682     sh4r.new_pc = sh4r.r[Rn];
   683     sh4r.pr = pc + 4;
   684     TRACE_CALL( pc, sh4r.new_pc );
   685     return TRUE;
   686 :}
   687 STS MACH, Rn {: sh4r.r[Rn] = (sh4r.mac>>32); :}
   688 STS.L MACH, @-Rn {:
   689     sh4r.r[Rn] -= 4;
   690     CHECKWALIGN32( sh4r.r[Rn] );
   691     MEM_WRITE_LONG( sh4r.r[Rn], (sh4r.mac>>32) );
   692 :}
   693 STC.L SR, @-Rn {:
   694     CHECKPRIV();
   695     sh4r.r[Rn] -= 4;
   696     CHECKWALIGN32( sh4r.r[Rn] );
   697     MEM_WRITE_LONG( sh4r.r[Rn], sh4_read_sr() );
   698 :}
   699 LDS.L @Rm+, MACH {:
   700     CHECKRALIGN32( sh4r.r[Rm] );
   701     MEM_READ_LONG(sh4r.r[Rm], tmp);
   702     sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
   703 	(((uint64_t)tmp)<<32);
   704     sh4r.r[Rm] += 4;
   705 :}
   706 LDC.L @Rm+, SR {:
   707     CHECKSLOTILLEGAL();
   708     CHECKPRIV();
   709     CHECKWALIGN32( sh4r.r[Rm] );
   710     MEM_READ_LONG(sh4r.r[Rm], tmp);
   711     sh4_write_sr( tmp );
   712     sh4r.r[Rm] +=4;
   713 :}
   714 LDS Rm, MACH {:
   715     sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
   716                (((uint64_t)sh4r.r[Rm])<<32);
   717 :}
   718 LDC Rm, SR {:
   719     CHECKSLOTILLEGAL();
   720     CHECKPRIV();
   721     sh4_write_sr( sh4r.r[Rm] );
   722 :}
   723 LDC Rm, SGR {:
   724     CHECKPRIV();
   725     sh4r.sgr = sh4r.r[Rm];
   726 :}
   727 LDC.L @Rm+, SGR {:
   728     CHECKPRIV();
   729     CHECKRALIGN32( sh4r.r[Rm] );
   730     MEM_READ_LONG(sh4r.r[Rm], sh4r.sgr);
   731     sh4r.r[Rm] +=4;
   732 :}
   733 STS MACL, Rn {: sh4r.r[Rn] = (uint32_t)sh4r.mac; :}
   734 STS.L MACL, @-Rn {:
   735     sh4r.r[Rn] -= 4;
   736     CHECKWALIGN32( sh4r.r[Rn] );
   737     MEM_WRITE_LONG( sh4r.r[Rn], (uint32_t)sh4r.mac );
   738 :}
   739 STC.L GBR, @-Rn {:
   740     sh4r.r[Rn] -= 4;
   741     CHECKWALIGN32( sh4r.r[Rn] );
   742     MEM_WRITE_LONG( sh4r.r[Rn], sh4r.gbr );
   743 :}
   744 LDS.L @Rm+, MACL {:
   745     CHECKRALIGN32( sh4r.r[Rm] );
   746     MEM_READ_LONG(sh4r.r[Rm], tmp);
   747     sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
   748                (uint64_t)((uint32_t)tmp);
   749     sh4r.r[Rm] += 4;
   750 :}
   751 LDC.L @Rm+, GBR {:
   752     CHECKRALIGN32( sh4r.r[Rm] );
   753     MEM_READ_LONG(sh4r.r[Rm], sh4r.gbr);
   754     sh4r.r[Rm] +=4;
   755 :}
   756 LDS Rm, MACL {:
   757     sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
   758                (uint64_t)((uint32_t)(sh4r.r[Rm]));
   759 :}
   760 LDC Rm, GBR {: sh4r.gbr = sh4r.r[Rm]; :}
   761 STS PR, Rn {: sh4r.r[Rn] = sh4r.pr; :}
   762 STS.L PR, @-Rn {:
   763     sh4r.r[Rn] -= 4;
   764     CHECKWALIGN32( sh4r.r[Rn] );
   765     MEM_WRITE_LONG( sh4r.r[Rn], sh4r.pr );
   766 :}
   767 STC.L VBR, @-Rn {:
   768     CHECKPRIV();
   769     sh4r.r[Rn] -= 4;
   770     CHECKWALIGN32( sh4r.r[Rn] );
   771     MEM_WRITE_LONG( sh4r.r[Rn], sh4r.vbr );
   772 :}
   773 LDS.L @Rm+, PR {:
   774     CHECKRALIGN32( sh4r.r[Rm] );
   775     MEM_READ_LONG( sh4r.r[Rm], sh4r.pr );
   776     sh4r.r[Rm] += 4;
   777 :}
   778 LDC.L @Rm+, VBR {:
   779     CHECKPRIV();
   780     CHECKRALIGN32( sh4r.r[Rm] );
   781     MEM_READ_LONG(sh4r.r[Rm], sh4r.vbr);
   782     sh4r.r[Rm] +=4;
   783 :}
   784 LDS Rm, PR {: sh4r.pr = sh4r.r[Rm]; :}
   785 LDC Rm, VBR {:
   786     CHECKPRIV();
   787     sh4r.vbr = sh4r.r[Rm];
   788 :}
   789 STC SGR, Rn {:
   790     CHECKPRIV();
   791     sh4r.r[Rn] = sh4r.sgr;
   792 :}
   793 STC.L SGR, @-Rn {:
   794     CHECKPRIV();
   795     sh4r.r[Rn] -= 4;
   796     CHECKWALIGN32( sh4r.r[Rn] );
   797     MEM_WRITE_LONG( sh4r.r[Rn], sh4r.sgr );
   798 :}
   799 STC.L SSR, @-Rn {:
   800     CHECKPRIV();
   801     sh4r.r[Rn] -= 4;
   802     CHECKWALIGN32( sh4r.r[Rn] );
   803     MEM_WRITE_LONG( sh4r.r[Rn], sh4r.ssr );
   804 :}
   805 LDC.L @Rm+, SSR {:
   806     CHECKPRIV();
   807     CHECKRALIGN32( sh4r.r[Rm] );
   808     MEM_READ_LONG(sh4r.r[Rm], sh4r.ssr);
   809     sh4r.r[Rm] +=4;
   810 :}
   811 LDC Rm, SSR {:
   812     CHECKPRIV();
   813     sh4r.ssr = sh4r.r[Rm];
   814 :}
   815 STC.L SPC, @-Rn {:
   816     CHECKPRIV();
   817     sh4r.r[Rn] -= 4;
   818     CHECKWALIGN32( sh4r.r[Rn] );
   819     MEM_WRITE_LONG( sh4r.r[Rn], sh4r.spc );
   820 :}
   821 LDC.L @Rm+, SPC {:
   822     CHECKPRIV();
   823     CHECKRALIGN32( sh4r.r[Rm] );
   824     MEM_READ_LONG(sh4r.r[Rm], sh4r.spc);
   825     sh4r.r[Rm] +=4;
   826 :}
   827 LDC Rm, SPC {:
   828     CHECKPRIV();
   829     sh4r.spc = sh4r.r[Rm];
   830 :}
   831 STS FPUL, Rn {: sh4r.r[Rn] = sh4r.fpul; :}
   832 STS.L FPUL, @-Rn {:
   833     sh4r.r[Rn] -= 4;
   834     CHECKWALIGN32( sh4r.r[Rn] );
   835     MEM_WRITE_LONG( sh4r.r[Rn], sh4r.fpul );
   836 :}
   837 LDS.L @Rm+, FPUL {:
   838     CHECKRALIGN32( sh4r.r[Rm] );
   839     MEM_READ_LONG(sh4r.r[Rm], sh4r.fpul);
   840     sh4r.r[Rm] +=4;
   841 :}
   842 LDS Rm, FPUL {: sh4r.fpul = sh4r.r[Rm]; :}
   843 STS FPSCR, Rn {: sh4r.r[Rn] = sh4r.fpscr; :}
   844 STS.L FPSCR, @-Rn {:
   845     sh4r.r[Rn] -= 4;
   846     CHECKWALIGN32( sh4r.r[Rn] );
   847     MEM_WRITE_LONG( sh4r.r[Rn], sh4r.fpscr );
   848 :}
   849 LDS.L @Rm+, FPSCR {:
   850     CHECKRALIGN32( sh4r.r[Rm] );
   851     MEM_READ_LONG(sh4r.r[Rm], sh4r.fpscr);
   852     sh4r.r[Rm] +=4;
   853     sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
   854 :}
   855 LDS Rm, FPSCR {: 
   856     sh4r.fpscr = sh4r.r[Rm]; 
   857     sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
   858 :}
   859 STC DBR, Rn {: CHECKPRIV(); sh4r.r[Rn] = sh4r.dbr; :}
   860 STC.L DBR, @-Rn {:
   861     CHECKPRIV();
   862     sh4r.r[Rn] -= 4;
   863     CHECKWALIGN32( sh4r.r[Rn] );
   864     MEM_WRITE_LONG( sh4r.r[Rn], sh4r.dbr );
   865 :}
   866 LDC.L @Rm+, DBR {:
   867     CHECKPRIV();
   868     CHECKRALIGN32( sh4r.r[Rm] );
   869     MEM_READ_LONG(sh4r.r[Rm], sh4r.dbr);
   870     sh4r.r[Rm] +=4;
   871 :}
   872 LDC Rm, DBR {:
   873     CHECKPRIV();
   874     sh4r.dbr = sh4r.r[Rm];
   875 :}
   876 STC.L Rm_BANK, @-Rn {:
   877     CHECKPRIV();
   878     sh4r.r[Rn] -= 4;
   879     CHECKWALIGN32( sh4r.r[Rn] );
   880     MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r_bank[Rm_BANK] );
   881 :}
   882 LDC.L @Rm+, Rn_BANK {:
   883     CHECKPRIV();
   884     CHECKRALIGN32( sh4r.r[Rm] );
   885     MEM_READ_LONG( sh4r.r[Rm], sh4r.r_bank[Rn_BANK] );
   886     sh4r.r[Rm] += 4;
   887 :}
   888 LDC Rm, Rn_BANK {:
   889     CHECKPRIV();
   890     sh4r.r_bank[Rn_BANK] = sh4r.r[Rm];
   891 :}
   892 STC SR, Rn {: 
   893     CHECKPRIV();
   894     sh4r.r[Rn] = sh4_read_sr();
   895 :}
   896 STC GBR, Rn {:
   897     CHECKPRIV();
   898     sh4r.r[Rn] = sh4r.gbr;
   899 :}
   900 STC VBR, Rn {:
   901     CHECKPRIV();
   902     sh4r.r[Rn] = sh4r.vbr;
   903 :}
   904 STC SSR, Rn {:
   905     CHECKPRIV();
   906     sh4r.r[Rn] = sh4r.ssr;
   907 :}
   908 STC SPC, Rn {:
   909     CHECKPRIV();
   910     sh4r.r[Rn] = sh4r.spc;
   911 :}
   912 STC Rm_BANK, Rn {:
   913     CHECKPRIV();
   914     sh4r.r[Rn] = sh4r.r_bank[Rm_BANK];
   915 :}
   917 FADD FRm, FRn {:
   918     CHECKFPUEN();
   919     if( IS_FPU_DOUBLEPREC() ) {
   920 	DR(FRn) += DR(FRm);
   921     } else {
   922 	FR(FRn) += FR(FRm);
   923     }
   924 :}
   925 FSUB FRm, FRn {:
   926     CHECKFPUEN();
   927     if( IS_FPU_DOUBLEPREC() ) {
   928 	DR(FRn) -= DR(FRm);
   929     } else {
   930 	FR(FRn) -= FR(FRm);
   931     }
   932 :}
   934 FMUL FRm, FRn {:
   935     CHECKFPUEN();
   936     if( IS_FPU_DOUBLEPREC() ) {
   937 	DR(FRn) *= DR(FRm);
   938     } else {
   939 	FR(FRn) *= FR(FRm);
   940     }
   941 :}
   943 FDIV FRm, FRn {:
   944     CHECKFPUEN();
   945     if( IS_FPU_DOUBLEPREC() ) {
   946 	DR(FRn) /= DR(FRm);
   947     } else {
   948 	FR(FRn) /= FR(FRm);
   949     }
   950 :}
   952 FCMP/EQ FRm, FRn {:
   953     CHECKFPUEN();
   954     if( IS_FPU_DOUBLEPREC() ) {
   955 	sh4r.t = ( DR(FRn) == DR(FRm) ? 1 : 0 );
   956     } else {
   957 	sh4r.t = ( FR(FRn) == FR(FRm) ? 1 : 0 );
   958     }
   959 :}
   961 FCMP/GT FRm, FRn {:
   962     CHECKFPUEN();
   963     if( IS_FPU_DOUBLEPREC() ) {
   964 	sh4r.t = ( DR(FRn) > DR(FRm) ? 1 : 0 );
   965     } else {
   966 	sh4r.t = ( FR(FRn) > FR(FRm) ? 1 : 0 );
   967     }
   968 :}
   970 FMOV @(R0, Rm), FRn {: MEM_FP_READ( sh4r.r[Rm] + R0, FRn ); :}
   971 FMOV FRm, @(R0, Rn) {: MEM_FP_WRITE( sh4r.r[Rn] + R0, FRm ); :}
   972 FMOV @Rm, FRn {: MEM_FP_READ( sh4r.r[Rm], FRn ); :}
   973 FMOV @Rm+, FRn {: MEM_FP_READ( sh4r.r[Rm], FRn ); sh4r.r[Rm] += FP_WIDTH; :}
   974 FMOV FRm, @Rn {: MEM_FP_WRITE( sh4r.r[Rn], FRm ); :}
   975 FMOV FRm, @-Rn {: sh4r.r[Rn] -= FP_WIDTH; MEM_FP_WRITE( sh4r.r[Rn], FRm ); :}
   976 FMOV FRm, FRn {: 
   977     if( IS_FPU_DOUBLESIZE() )
   978 	DR(FRn) = DR(FRm);
   979     else
   980 	FR(FRn) = FR(FRm);
   981 :}
   982 FSTS FPUL, FRn {: CHECKFPUEN(); FR(FRn) = FPULf; :}
   983 FLDS FRm, FPUL {: CHECKFPUEN(); FPULf = FR(FRm); :}
   984 FLOAT FPUL, FRn {: 
   985     CHECKFPUEN();
   986     if( IS_FPU_DOUBLEPREC() ) {
   987 	if( FRn&1 ) { // No, really...
   988 	    dtmp = (double)FPULi;
   989 	    FR(FRn) = *(((float *)&dtmp)+1);
   990 	} else {
   991 	    DRF(FRn>>1) = (double)FPULi;
   992 	}
   993     } else {
   994 	FR(FRn) = (float)FPULi;
   995     }
   996 :}
   997 FTRC FRm, FPUL {:
   998     CHECKFPUEN();
   999     if( IS_FPU_DOUBLEPREC() ) {
  1000 	if( FRm&1 ) {
  1001 	    dtmp = 0;
  1002 	    *(((float *)&dtmp)+1) = FR(FRm);
  1003 	} else {
  1004 	    dtmp = DRF(FRm>>1);
  1006         if( dtmp >= MAX_INTF )
  1007             FPULi = MAX_INT;
  1008         else if( dtmp <= MIN_INTF )
  1009             FPULi = MIN_INT;
  1010         else 
  1011             FPULi = (int32_t)dtmp;
  1012     } else {
  1013 	ftmp = FR(FRm);
  1014 	if( ftmp >= MAX_INTF )
  1015 	    FPULi = MAX_INT;
  1016 	else if( ftmp <= MIN_INTF )
  1017 	    FPULi = MIN_INT;
  1018 	else
  1019 	    FPULi = (int32_t)ftmp;
  1021 :}
  1022 FNEG FRn {:
  1023     CHECKFPUEN();
  1024     if( IS_FPU_DOUBLEPREC() ) {
  1025 	DR(FRn) = -DR(FRn);
  1026     } else {
  1027         FR(FRn) = -FR(FRn);
  1029 :}
  1030 FABS FRn {:
  1031     CHECKFPUEN();
  1032     if( IS_FPU_DOUBLEPREC() ) {
  1033 	DR(FRn) = fabs(DR(FRn));
  1034     } else {
  1035         FR(FRn) = fabsf(FR(FRn));
  1037 :}
  1038 FSQRT FRn {:
  1039     CHECKFPUEN();
  1040     if( IS_FPU_DOUBLEPREC() ) {
  1041 	DR(FRn) = sqrt(DR(FRn));
  1042     } else {
  1043         FR(FRn) = sqrtf(FR(FRn));
  1045 :}
  1046 FLDI0 FRn {:
  1047     CHECKFPUEN();
  1048     if( IS_FPU_DOUBLEPREC() ) {
  1049 	DR(FRn) = 0.0;
  1050     } else {
  1051         FR(FRn) = 0.0;
  1053 :}
  1054 FLDI1 FRn {:
  1055     CHECKFPUEN();
  1056     if( IS_FPU_DOUBLEPREC() ) {
  1057 	DR(FRn) = 1.0;
  1058     } else {
  1059         FR(FRn) = 1.0;
  1061 :}
  1062 FMAC FR0, FRm, FRn {:
  1063     CHECKFPUEN();
  1064     if( IS_FPU_DOUBLEPREC() ) {
  1065         DR(FRn) += DR(FRm)*DR(0);
  1066     } else {
  1067 	FR(FRn) += FR(FRm)*FR(0);
  1069 :}
  1070 FRCHG {: 
  1071     CHECKFPUEN(); 
  1072     sh4r.fpscr ^= FPSCR_FR; 
  1073     sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
  1074 :}
  1075 FSCHG {: CHECKFPUEN(); sh4r.fpscr ^= FPSCR_SZ; :}
  1076 FCNVSD FPUL, FRn {:
  1077     CHECKFPUEN();
  1078     if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
  1079 	DR(FRn) = (double)FPULf;
  1081 :}
  1082 FCNVDS FRm, FPUL {:
  1083     CHECKFPUEN();
  1084     if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
  1085 	FPULf = (float)DR(FRm);
  1087 :}
  1089 FSRRA FRn {:
  1090     CHECKFPUEN();
  1091     if( !IS_FPU_DOUBLEPREC() ) {
  1092 	FR(FRn) = 1.0/sqrtf(FR(FRn));
  1094 :}
  1095 FIPR FVm, FVn {:
  1096     CHECKFPUEN();
  1097     if( !IS_FPU_DOUBLEPREC() ) {
  1098         int tmp2 = FVn<<2;
  1099         tmp = FVm<<2;
  1100         FR(tmp2+3) = FR(tmp)*FR(tmp2) +
  1101             FR(tmp+1)*FR(tmp2+1) +
  1102             FR(tmp+2)*FR(tmp2+2) +
  1103             FR(tmp+3)*FR(tmp2+3);
  1105 :}
  1106 FSCA FPUL, FRn {:
  1107     CHECKFPUEN();
  1108     if( !IS_FPU_DOUBLEPREC() ) {
  1109 	sh4_fsca( FPULi, &(DRF(FRn>>1)) );
  1110 	/*
  1111         float angle = (((float)(FPULi&0xFFFF))/65536.0) * 2 * M_PI;
  1112         FR(FRn) = sinf(angle);
  1113         FR((FRn)+1) = cosf(angle);
  1114 	*/
  1116 :}
  1117 FTRV XMTRX, FVn {:
  1118     CHECKFPUEN();
  1119     if( !IS_FPU_DOUBLEPREC() ) {
  1120 	sh4_ftrv(&(DRF(FVn<<1)), &sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21][0]);
  1121 	/*
  1122         tmp = FVn<<2;
  1123 	float *xf = &sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21][0];
  1124         float fv[4] = { FR(tmp), FR(tmp+1), FR(tmp+2), FR(tmp+3) };
  1125         FR(tmp) = xf[1] * fv[0] + xf[5]*fv[1] +
  1126 	    xf[9]*fv[2] + xf[13]*fv[3];
  1127         FR(tmp+1) = xf[0] * fv[0] + xf[4]*fv[1] +
  1128 	    xf[8]*fv[2] + xf[12]*fv[3];
  1129         FR(tmp+2) = xf[3] * fv[0] + xf[7]*fv[1] +
  1130 	    xf[11]*fv[2] + xf[15]*fv[3];
  1131         FR(tmp+3) = xf[2] * fv[0] + xf[6]*fv[1] +
  1132 	    xf[10]*fv[2] + xf[14]*fv[3];
  1133 	*/
  1135 :}
  1136 UNDEF {:
  1137     UNDEF(ir);
  1138 :}
  1139 %%
  1140     sh4r.pc = sh4r.new_pc;
  1141     sh4r.new_pc += 2;
  1142     sh4r.in_delay_slot = 0;
  1143     return TRUE;
.