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lxdream.org :: lxdream/src/sh4/sh4x86.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.c
changeset 570:d2893980fbf5
prev569:a1c49e1e8776
next571:9bc09948d0f2
author nkeynes
date Sun Jan 06 12:24:18 2008 +0000 (14 years ago)
branchlxdream-mmu
permissions -rw-r--r--
last change Change to generate different code for mmu on/off cases
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     1 /**
     2  * $Id$
     3  * 
     4  * SH4 => x86 translation. This version does no real optimization, it just
     5  * outputs straight-line x86 code - it mainly exists to provide a baseline
     6  * to test the optimizing versions against.
     7  *
     8  * Copyright (c) 2007 Nathan Keynes.
     9  *
    10  * This program is free software; you can redistribute it and/or modify
    11  * it under the terms of the GNU General Public License as published by
    12  * the Free Software Foundation; either version 2 of the License, or
    13  * (at your option) any later version.
    14  *
    15  * This program is distributed in the hope that it will be useful,
    16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    18  * GNU General Public License for more details.
    19  */
    21 #include <assert.h>
    22 #include <math.h>
    24 #ifndef NDEBUG
    25 #define DEBUG_JUMPS 1
    26 #endif
    28 #include "sh4/xltcache.h"
    29 #include "sh4/sh4core.h"
    30 #include "sh4/sh4trans.h"
    31 #include "sh4/sh4mmio.h"
    32 #include "sh4/x86op.h"
    33 #include "clock.h"
    35 #define DEFAULT_BACKPATCH_SIZE 4096
    37 struct backpatch_record {
    38     uint32_t *fixup_addr;
    39     uint32_t fixup_icount;
    40     uint32_t exc_code;
    41 };
    43 /** 
    44  * Struct to manage internal translation state. This state is not saved -
    45  * it is only valid between calls to sh4_translate_begin_block() and
    46  * sh4_translate_end_block()
    47  */
    48 struct sh4_x86_state {
    49     gboolean in_delay_slot;
    50     gboolean priv_checked; /* true if we've already checked the cpu mode. */
    51     gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
    52     gboolean branch_taken; /* true if we branched unconditionally */
    53     uint32_t block_start_pc;
    54     uint32_t stack_posn;   /* Trace stack height for alignment purposes */
    55     int tstate;
    57     /* mode flags */
    58     gboolean tlb_on; /* True if tlb translation is active */
    60     /* Allocated memory for the (block-wide) back-patch list */
    61     struct backpatch_record *backpatch_list;
    62     uint32_t backpatch_posn;
    63     uint32_t backpatch_size;
    64 };
    66 #define TSTATE_NONE -1
    67 #define TSTATE_O    0
    68 #define TSTATE_C    2
    69 #define TSTATE_E    4
    70 #define TSTATE_NE   5
    71 #define TSTATE_G    0xF
    72 #define TSTATE_GE   0xD
    73 #define TSTATE_A    7
    74 #define TSTATE_AE   3
    76 /** Branch if T is set (either in the current cflags, or in sh4r.t) */
    77 #define JT_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
    78 	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
    79     OP(0x70+sh4_x86.tstate); OP(rel8); \
    80     MARK_JMP(rel8,label)
    81 /** Branch if T is clear (either in the current cflags or in sh4r.t) */
    82 #define JF_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
    83 	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
    84     OP(0x70+ (sh4_x86.tstate^1)); OP(rel8); \
    85     MARK_JMP(rel8, label)
    87 static struct sh4_x86_state sh4_x86;
    89 static uint32_t max_int = 0x7FFFFFFF;
    90 static uint32_t min_int = 0x80000000;
    91 static uint32_t save_fcw; /* save value for fpu control word */
    92 static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
    94 void sh4_x86_init()
    95 {
    96     sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
    97     sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(struct backpatch_record);
    98 }
   101 static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code )
   102 {
   103     if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
   104 	sh4_x86.backpatch_size <<= 1;
   105 	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, 
   106 					  sh4_x86.backpatch_size * sizeof(struct backpatch_record));
   107 	assert( sh4_x86.backpatch_list != NULL );
   108     }
   109     if( sh4_x86.in_delay_slot ) {
   110 	fixup_pc -= 2;
   111     }
   112     sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_addr = (uint32_t *)fixup_addr;
   113     sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1;
   114     sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code;
   115     sh4_x86.backpatch_posn++;
   116 }
   118 /**
   119  * Emit an instruction to load an SH4 reg into a real register
   120  */
   121 static inline void load_reg( int x86reg, int sh4reg ) 
   122 {
   123     /* mov [bp+n], reg */
   124     OP(0x8B);
   125     OP(0x45 + (x86reg<<3));
   126     OP(REG_OFFSET(r[sh4reg]));
   127 }
   129 static inline void load_reg16s( int x86reg, int sh4reg )
   130 {
   131     OP(0x0F);
   132     OP(0xBF);
   133     MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
   134 }
   136 static inline void load_reg16u( int x86reg, int sh4reg )
   137 {
   138     OP(0x0F);
   139     OP(0xB7);
   140     MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
   142 }
   144 #define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
   145 #define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
   146 /**
   147  * Emit an instruction to load an immediate value into a register
   148  */
   149 static inline void load_imm32( int x86reg, uint32_t value ) {
   150     /* mov #value, reg */
   151     OP(0xB8 + x86reg);
   152     OP32(value);
   153 }
   155 /**
   156  * Load an immediate 64-bit quantity (note: x86-64 only)
   157  */
   158 static inline void load_imm64( int x86reg, uint32_t value ) {
   159     /* mov #value, reg */
   160     REXW();
   161     OP(0xB8 + x86reg);
   162     OP64(value);
   163 }
   166 /**
   167  * Emit an instruction to store an SH4 reg (RN)
   168  */
   169 void static inline store_reg( int x86reg, int sh4reg ) {
   170     /* mov reg, [bp+n] */
   171     OP(0x89);
   172     OP(0x45 + (x86reg<<3));
   173     OP(REG_OFFSET(r[sh4reg]));
   174 }
   176 #define load_fr_bank(bankreg) load_spreg( bankreg, REG_OFFSET(fr_bank))
   178 /**
   179  * Load an FR register (single-precision floating point) into an integer x86
   180  * register (eg for register-to-register moves)
   181  */
   182 void static inline load_fr( int bankreg, int x86reg, int frm )
   183 {
   184     OP(0x8B); OP(0x40+bankreg+(x86reg<<3)); OP((frm^1)<<2);
   185 }
   187 /**
   188  * Store an FR register (single-precision floating point) into an integer x86
   189  * register (eg for register-to-register moves)
   190  */
   191 void static inline store_fr( int bankreg, int x86reg, int frn )
   192 {
   193     OP(0x89);  OP(0x40+bankreg+(x86reg<<3)); OP((frn^1)<<2);
   194 }
   197 /**
   198  * Load a pointer to the back fp back into the specified x86 register. The
   199  * bankreg must have been previously loaded with FPSCR.
   200  * NB: 12 bytes
   201  */
   202 static inline void load_xf_bank( int bankreg )
   203 {
   204     NOT_r32( bankreg );
   205     SHR_imm8_r32( (21 - 6), bankreg ); // Extract bit 21 then *64 for bank size
   206     AND_imm8s_r32( 0x40, bankreg );    // Complete extraction
   207     OP(0x8D); OP(0x44+(bankreg<<3)); OP(0x28+bankreg); OP(REG_OFFSET(fr)); // LEA [ebp+bankreg+disp], bankreg
   208 }
   210 /**
   211  * Update the fr_bank pointer based on the current fpscr value.
   212  */
   213 static inline void update_fr_bank( int fpscrreg )
   214 {
   215     SHR_imm8_r32( (21 - 6), fpscrreg ); // Extract bit 21 then *64 for bank size
   216     AND_imm8s_r32( 0x40, fpscrreg );    // Complete extraction
   217     OP(0x8D); OP(0x44+(fpscrreg<<3)); OP(0x28+fpscrreg); OP(REG_OFFSET(fr)); // LEA [ebp+fpscrreg+disp], fpscrreg
   218     store_spreg( fpscrreg, REG_OFFSET(fr_bank) );
   219 }
   220 /**
   221  * Push FPUL (as a 32-bit float) onto the FPU stack
   222  */
   223 static inline void push_fpul( )
   224 {
   225     OP(0xD9); OP(0x45); OP(R_FPUL);
   226 }
   228 /**
   229  * Pop FPUL (as a 32-bit float) from the FPU stack
   230  */
   231 static inline void pop_fpul( )
   232 {
   233     OP(0xD9); OP(0x5D); OP(R_FPUL);
   234 }
   236 /**
   237  * Push a 32-bit float onto the FPU stack, with bankreg previously loaded
   238  * with the location of the current fp bank.
   239  */
   240 static inline void push_fr( int bankreg, int frm ) 
   241 {
   242     OP(0xD9); OP(0x40 + bankreg); OP((frm^1)<<2);  // FLD.S [bankreg + frm^1*4]
   243 }
   245 /**
   246  * Pop a 32-bit float from the FPU stack and store it back into the fp bank, 
   247  * with bankreg previously loaded with the location of the current fp bank.
   248  */
   249 static inline void pop_fr( int bankreg, int frm )
   250 {
   251     OP(0xD9); OP(0x58 + bankreg); OP((frm^1)<<2); // FST.S [bankreg + frm^1*4]
   252 }
   254 /**
   255  * Push a 64-bit double onto the FPU stack, with bankreg previously loaded
   256  * with the location of the current fp bank.
   257  */
   258 static inline void push_dr( int bankreg, int frm )
   259 {
   260     OP(0xDD); OP(0x40 + bankreg); OP(frm<<2); // FLD.D [bankreg + frm*4]
   261 }
   263 static inline void pop_dr( int bankreg, int frm )
   264 {
   265     OP(0xDD); OP(0x58 + bankreg); OP(frm<<2); // FST.D [bankreg + frm*4]
   266 }
   268 /* Exception checks - Note that all exception checks will clobber EAX */
   270 #define check_priv( ) \
   271     if( !sh4_x86.priv_checked ) { \
   272 	sh4_x86.priv_checked = TRUE;\
   273 	load_spreg( R_EAX, R_SR );\
   274 	AND_imm32_r32( SR_MD, R_EAX );\
   275 	if( sh4_x86.in_delay_slot ) {\
   276 	    JE_exc( EXC_SLOT_ILLEGAL );\
   277 	} else {\
   278 	    JE_exc( EXC_ILLEGAL );\
   279 	}\
   280     }\
   282 #define check_fpuen( ) \
   283     if( !sh4_x86.fpuen_checked ) {\
   284 	sh4_x86.fpuen_checked = TRUE;\
   285 	load_spreg( R_EAX, R_SR );\
   286 	AND_imm32_r32( SR_FD, R_EAX );\
   287 	if( sh4_x86.in_delay_slot ) {\
   288 	    JNE_exc(EXC_SLOT_FPU_DISABLED);\
   289 	} else {\
   290 	    JNE_exc(EXC_FPU_DISABLED);\
   291 	}\
   292     }
   294 #define check_ralign16( x86reg ) \
   295     TEST_imm32_r32( 0x00000001, x86reg ); \
   296     JNE_exc(EXC_DATA_ADDR_READ)
   298 #define check_walign16( x86reg ) \
   299     TEST_imm32_r32( 0x00000001, x86reg ); \
   300     JNE_exc(EXC_DATA_ADDR_WRITE);
   302 #define check_ralign32( x86reg ) \
   303     TEST_imm32_r32( 0x00000003, x86reg ); \
   304     JNE_exc(EXC_DATA_ADDR_READ)
   306 #define check_walign32( x86reg ) \
   307     TEST_imm32_r32( 0x00000003, x86reg ); \
   308     JNE_exc(EXC_DATA_ADDR_WRITE);
   310 #define UNDEF()
   311 #define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
   312 #define MEM_READ_BYTE_PHYS( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
   313 #define MEM_READ_WORD_PHYS( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
   314 #define MEM_READ_LONG_PHYS( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
   315 #define MEM_WRITE_BYTE_PHYS( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
   316 #define MEM_WRITE_WORD_PHYS( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
   317 #define MEM_WRITE_LONG_PHYS( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
   319 #define MEM_READ_BYTE_VMA( addr_reg, value_reg ) call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); call_func1(sh4_read_byte, R_EAX); MEM_RESULT(value_reg)
   320 #define MEM_READ_WORD_VMA( addr_reg, value_reg ) call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); call_func1(sh4_read_word, R_EAX); MEM_RESULT(value_reg)
   321 #define MEM_READ_LONG_VMA( addr_reg, value_reg ) call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); call_func1(sh4_read_long, R_EAX); MEM_RESULT(value_reg)
   322 #define MEM_WRITE_BYTE_VMA( addr_reg, value_reg ) call_func1(mmu_vma_to_phys_write, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); call_func2(sh4_write_byte, R_EAX, value_reg)
   323 #define MEM_WRITE_WORD_VMA( addr_reg, value_reg ) call_func1(mmu_vma_to_phys_write, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); call_func2(sh4_write_word, R_EAX, value_reg)
   324 #define MEM_WRITE_LONG_VMA( addr_reg, value_reg ) call_func1(mmu_vma_to_phys_write, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); call_func2(sh4_write_long, R_EAX, value_reg)
   326 #define MEM_READ_BYTE( addr_reg, value_reg ) if(sh4_x86.tlb_on){MEM_READ_BYTE_VMA(addr_reg,value_reg);}else{MEM_READ_BYTE_PHYS(addr_reg, value_reg);}
   327 #define MEM_READ_WORD( addr_reg, value_reg ) if(sh4_x86.tlb_on){MEM_READ_WORD_VMA(addr_reg,value_reg);}else{MEM_READ_WORD_PHYS(addr_reg, value_reg);}
   328 #define MEM_READ_LONG( addr_reg, value_reg ) if(sh4_x86.tlb_on){MEM_READ_LONG_VMA(addr_reg,value_reg);}else{MEM_READ_LONG_PHYS(addr_reg, value_reg);}
   329 #define MEM_WRITE_BYTE( addr_reg, value_reg ) if(sh4_x86.tlb_on){MEM_WRITE_BYTE_VMA(addr_reg,value_reg);}else{MEM_WRITE_BYTE_PHYS(addr_reg, value_reg);}
   330 #define MEM_WRITE_WORD( addr_reg, value_reg ) if(sh4_x86.tlb_on){MEM_WRITE_WORD_VMA(addr_reg,value_reg);}else{MEM_WRITE_WORD_PHYS(addr_reg, value_reg);}
   331 #define MEM_WRITE_LONG( addr_reg, value_reg ) if(sh4_x86.tlb_on){MEM_WRITE_LONG_VMA(addr_reg,value_reg);}else{MEM_WRITE_LONG_PHYS(addr_reg, value_reg);}
   333 #define MEM_READ_SIZE_PHYS (CALL_FUNC1_SIZE)
   334 #define MEM_WRITE_SIZE_PHYS (CALL_FUNC2_SIZE)
   335 #define MEM_READ_SIZE_VMA (CALL_FUNC1_SIZE + CALL_FUNC1_SIZE + 12)
   336 #define MEM_WRITE_SIZE_VMA (CALL_FUNC1_SIZE + CALL_FUNC2_SIZE + 12)
   338 #define MEM_READ_SIZE (sh4_x86.tlb_on?MEM_READ_SIZE_VMA:MEM_READ_SIZE_PHYS)
   339 #define MEM_WRITE_SIZE (sh4_x86.tlb_on?MEM_WRITE_SIZE_VMA:MEM_WRITE_SIZE_PHYS)
   341 #define SLOTILLEGAL() JMP_exc(EXC_SLOT_ILLEGAL); sh4_x86.in_delay_slot = FALSE; return 1;
   343 /****** Import appropriate calling conventions ******/
   344 #if SH4_TRANSLATOR == TARGET_X86_64
   345 #include "sh4/ia64abi.h"
   346 #else /* SH4_TRANSLATOR == TARGET_X86 */
   347 #ifdef APPLE_BUILD
   348 #include "sh4/ia32mac.h"
   349 #else
   350 #include "sh4/ia32abi.h"
   351 #endif
   352 #endif
   355 /**
   356  * Translate a single instruction. Delayed branches are handled specially
   357  * by translating both branch and delayed instruction as a single unit (as
   358  * 
   359  *
   360  * @return true if the instruction marks the end of a basic block
   361  * (eg a branch or 
   362  */
   363 uint32_t sh4_translate_instruction( sh4addr_t pc )
   364 {
   365     uint32_t ir;
   366     /* Read instruction */
   367     if( IS_IN_ICACHE(pc) ) {
   368 	ir = *(uint16_t *)GET_ICACHE_PTR(pc);
   369     } else {
   370 	ir = sh4_read_word(pc);
   371     }
   372         switch( (ir&0xF000) >> 12 ) {
   373             case 0x0:
   374                 switch( ir&0xF ) {
   375                     case 0x2:
   376                         switch( (ir&0x80) >> 7 ) {
   377                             case 0x0:
   378                                 switch( (ir&0x70) >> 4 ) {
   379                                     case 0x0:
   380                                         { /* STC SR, Rn */
   381                                         uint32_t Rn = ((ir>>8)&0xF); 
   382                                         check_priv();
   383                                         call_func0(sh4_read_sr);
   384                                         store_reg( R_EAX, Rn );
   385                                         sh4_x86.tstate = TSTATE_NONE;
   386                                         }
   387                                         break;
   388                                     case 0x1:
   389                                         { /* STC GBR, Rn */
   390                                         uint32_t Rn = ((ir>>8)&0xF); 
   391                                         load_spreg( R_EAX, R_GBR );
   392                                         store_reg( R_EAX, Rn );
   393                                         }
   394                                         break;
   395                                     case 0x2:
   396                                         { /* STC VBR, Rn */
   397                                         uint32_t Rn = ((ir>>8)&0xF); 
   398                                         check_priv();
   399                                         load_spreg( R_EAX, R_VBR );
   400                                         store_reg( R_EAX, Rn );
   401                                         sh4_x86.tstate = TSTATE_NONE;
   402                                         }
   403                                         break;
   404                                     case 0x3:
   405                                         { /* STC SSR, Rn */
   406                                         uint32_t Rn = ((ir>>8)&0xF); 
   407                                         check_priv();
   408                                         load_spreg( R_EAX, R_SSR );
   409                                         store_reg( R_EAX, Rn );
   410                                         sh4_x86.tstate = TSTATE_NONE;
   411                                         }
   412                                         break;
   413                                     case 0x4:
   414                                         { /* STC SPC, Rn */
   415                                         uint32_t Rn = ((ir>>8)&0xF); 
   416                                         check_priv();
   417                                         load_spreg( R_EAX, R_SPC );
   418                                         store_reg( R_EAX, Rn );
   419                                         sh4_x86.tstate = TSTATE_NONE;
   420                                         }
   421                                         break;
   422                                     default:
   423                                         UNDEF();
   424                                         break;
   425                                 }
   426                                 break;
   427                             case 0x1:
   428                                 { /* STC Rm_BANK, Rn */
   429                                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
   430                                 check_priv();
   431                                 load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
   432                                 store_reg( R_EAX, Rn );
   433                                 sh4_x86.tstate = TSTATE_NONE;
   434                                 }
   435                                 break;
   436                         }
   437                         break;
   438                     case 0x3:
   439                         switch( (ir&0xF0) >> 4 ) {
   440                             case 0x0:
   441                                 { /* BSRF Rn */
   442                                 uint32_t Rn = ((ir>>8)&0xF); 
   443                                 if( sh4_x86.in_delay_slot ) {
   444                             	SLOTILLEGAL();
   445                                 } else {
   446                             	load_imm32( R_ECX, pc + 4 );
   447                             	store_spreg( R_ECX, R_PR );
   448                             	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_ECX );
   449                             	store_spreg( R_ECX, REG_OFFSET(pc) );
   450                             	sh4_x86.in_delay_slot = TRUE;
   451                             	sh4_x86.tstate = TSTATE_NONE;
   452                             	sh4_translate_instruction( pc + 2 );
   453                             	exit_block_pcset(pc+2);
   454                             	sh4_x86.branch_taken = TRUE;
   455                             	return 4;
   456                                 }
   457                                 }
   458                                 break;
   459                             case 0x2:
   460                                 { /* BRAF Rn */
   461                                 uint32_t Rn = ((ir>>8)&0xF); 
   462                                 if( sh4_x86.in_delay_slot ) {
   463                             	SLOTILLEGAL();
   464                                 } else {
   465                             	load_reg( R_EAX, Rn );
   466                             	ADD_imm32_r32( pc + 4, R_EAX );
   467                             	store_spreg( R_EAX, REG_OFFSET(pc) );
   468                             	sh4_x86.in_delay_slot = TRUE;
   469                             	sh4_x86.tstate = TSTATE_NONE;
   470                             	sh4_translate_instruction( pc + 2 );
   471                             	exit_block_pcset(pc+2);
   472                             	sh4_x86.branch_taken = TRUE;
   473                             	return 4;
   474                                 }
   475                                 }
   476                                 break;
   477                             case 0x8:
   478                                 { /* PREF @Rn */
   479                                 uint32_t Rn = ((ir>>8)&0xF); 
   480                                 load_reg( R_EAX, Rn );
   481                                 MOV_r32_r32( R_EAX, R_ECX );
   482                                 AND_imm32_r32( 0xFC000000, R_EAX );
   483                                 CMP_imm32_r32( 0xE0000000, R_EAX );
   484                                 JNE_rel8(CALL_FUNC1_SIZE, end);
   485                                 call_func1( sh4_flush_store_queue, R_ECX );
   486                                 JMP_TARGET(end);
   487                                 sh4_x86.tstate = TSTATE_NONE;
   488                                 }
   489                                 break;
   490                             case 0x9:
   491                                 { /* OCBI @Rn */
   492                                 uint32_t Rn = ((ir>>8)&0xF); 
   493                                 }
   494                                 break;
   495                             case 0xA:
   496                                 { /* OCBP @Rn */
   497                                 uint32_t Rn = ((ir>>8)&0xF); 
   498                                 }
   499                                 break;
   500                             case 0xB:
   501                                 { /* OCBWB @Rn */
   502                                 uint32_t Rn = ((ir>>8)&0xF); 
   503                                 }
   504                                 break;
   505                             case 0xC:
   506                                 { /* MOVCA.L R0, @Rn */
   507                                 uint32_t Rn = ((ir>>8)&0xF); 
   508                                 load_reg( R_EAX, 0 );
   509                                 load_reg( R_ECX, Rn );
   510                                 check_walign32( R_ECX );
   511                                 MEM_WRITE_LONG( R_ECX, R_EAX );
   512                                 sh4_x86.tstate = TSTATE_NONE;
   513                                 }
   514                                 break;
   515                             default:
   516                                 UNDEF();
   517                                 break;
   518                         }
   519                         break;
   520                     case 0x4:
   521                         { /* MOV.B Rm, @(R0, Rn) */
   522                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   523                         load_reg( R_EAX, 0 );
   524                         load_reg( R_ECX, Rn );
   525                         ADD_r32_r32( R_EAX, R_ECX );
   526                         load_reg( R_EAX, Rm );
   527                         MEM_WRITE_BYTE( R_ECX, R_EAX );
   528                         sh4_x86.tstate = TSTATE_NONE;
   529                         }
   530                         break;
   531                     case 0x5:
   532                         { /* MOV.W Rm, @(R0, Rn) */
   533                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   534                         load_reg( R_EAX, 0 );
   535                         load_reg( R_ECX, Rn );
   536                         ADD_r32_r32( R_EAX, R_ECX );
   537                         check_walign16( R_ECX );
   538                         load_reg( R_EAX, Rm );
   539                         MEM_WRITE_WORD( R_ECX, R_EAX );
   540                         sh4_x86.tstate = TSTATE_NONE;
   541                         }
   542                         break;
   543                     case 0x6:
   544                         { /* MOV.L Rm, @(R0, Rn) */
   545                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   546                         load_reg( R_EAX, 0 );
   547                         load_reg( R_ECX, Rn );
   548                         ADD_r32_r32( R_EAX, R_ECX );
   549                         check_walign32( R_ECX );
   550                         load_reg( R_EAX, Rm );
   551                         MEM_WRITE_LONG( R_ECX, R_EAX );
   552                         sh4_x86.tstate = TSTATE_NONE;
   553                         }
   554                         break;
   555                     case 0x7:
   556                         { /* MUL.L Rm, Rn */
   557                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   558                         load_reg( R_EAX, Rm );
   559                         load_reg( R_ECX, Rn );
   560                         MUL_r32( R_ECX );
   561                         store_spreg( R_EAX, R_MACL );
   562                         sh4_x86.tstate = TSTATE_NONE;
   563                         }
   564                         break;
   565                     case 0x8:
   566                         switch( (ir&0xFF0) >> 4 ) {
   567                             case 0x0:
   568                                 { /* CLRT */
   569                                 CLC();
   570                                 SETC_t();
   571                                 sh4_x86.tstate = TSTATE_C;
   572                                 }
   573                                 break;
   574                             case 0x1:
   575                                 { /* SETT */
   576                                 STC();
   577                                 SETC_t();
   578                                 sh4_x86.tstate = TSTATE_C;
   579                                 }
   580                                 break;
   581                             case 0x2:
   582                                 { /* CLRMAC */
   583                                 XOR_r32_r32(R_EAX, R_EAX);
   584                                 store_spreg( R_EAX, R_MACL );
   585                                 store_spreg( R_EAX, R_MACH );
   586                                 sh4_x86.tstate = TSTATE_NONE;
   587                                 }
   588                                 break;
   589                             case 0x3:
   590                                 { /* LDTLB */
   591                                 call_func0( MMU_ldtlb );
   592                                 }
   593                                 break;
   594                             case 0x4:
   595                                 { /* CLRS */
   596                                 CLC();
   597                                 SETC_sh4r(R_S);
   598                                 sh4_x86.tstate = TSTATE_C;
   599                                 }
   600                                 break;
   601                             case 0x5:
   602                                 { /* SETS */
   603                                 STC();
   604                                 SETC_sh4r(R_S);
   605                                 sh4_x86.tstate = TSTATE_C;
   606                                 }
   607                                 break;
   608                             default:
   609                                 UNDEF();
   610                                 break;
   611                         }
   612                         break;
   613                     case 0x9:
   614                         switch( (ir&0xF0) >> 4 ) {
   615                             case 0x0:
   616                                 { /* NOP */
   617                                 /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */
   618                                 }
   619                                 break;
   620                             case 0x1:
   621                                 { /* DIV0U */
   622                                 XOR_r32_r32( R_EAX, R_EAX );
   623                                 store_spreg( R_EAX, R_Q );
   624                                 store_spreg( R_EAX, R_M );
   625                                 store_spreg( R_EAX, R_T );
   626                                 sh4_x86.tstate = TSTATE_C; // works for DIV1
   627                                 }
   628                                 break;
   629                             case 0x2:
   630                                 { /* MOVT Rn */
   631                                 uint32_t Rn = ((ir>>8)&0xF); 
   632                                 load_spreg( R_EAX, R_T );
   633                                 store_reg( R_EAX, Rn );
   634                                 }
   635                                 break;
   636                             default:
   637                                 UNDEF();
   638                                 break;
   639                         }
   640                         break;
   641                     case 0xA:
   642                         switch( (ir&0xF0) >> 4 ) {
   643                             case 0x0:
   644                                 { /* STS MACH, Rn */
   645                                 uint32_t Rn = ((ir>>8)&0xF); 
   646                                 load_spreg( R_EAX, R_MACH );
   647                                 store_reg( R_EAX, Rn );
   648                                 }
   649                                 break;
   650                             case 0x1:
   651                                 { /* STS MACL, Rn */
   652                                 uint32_t Rn = ((ir>>8)&0xF); 
   653                                 load_spreg( R_EAX, R_MACL );
   654                                 store_reg( R_EAX, Rn );
   655                                 }
   656                                 break;
   657                             case 0x2:
   658                                 { /* STS PR, Rn */
   659                                 uint32_t Rn = ((ir>>8)&0xF); 
   660                                 load_spreg( R_EAX, R_PR );
   661                                 store_reg( R_EAX, Rn );
   662                                 }
   663                                 break;
   664                             case 0x3:
   665                                 { /* STC SGR, Rn */
   666                                 uint32_t Rn = ((ir>>8)&0xF); 
   667                                 check_priv();
   668                                 load_spreg( R_EAX, R_SGR );
   669                                 store_reg( R_EAX, Rn );
   670                                 sh4_x86.tstate = TSTATE_NONE;
   671                                 }
   672                                 break;
   673                             case 0x5:
   674                                 { /* STS FPUL, Rn */
   675                                 uint32_t Rn = ((ir>>8)&0xF); 
   676                                 load_spreg( R_EAX, R_FPUL );
   677                                 store_reg( R_EAX, Rn );
   678                                 }
   679                                 break;
   680                             case 0x6:
   681                                 { /* STS FPSCR, Rn */
   682                                 uint32_t Rn = ((ir>>8)&0xF); 
   683                                 load_spreg( R_EAX, R_FPSCR );
   684                                 store_reg( R_EAX, Rn );
   685                                 }
   686                                 break;
   687                             case 0xF:
   688                                 { /* STC DBR, Rn */
   689                                 uint32_t Rn = ((ir>>8)&0xF); 
   690                                 check_priv();
   691                                 load_spreg( R_EAX, R_DBR );
   692                                 store_reg( R_EAX, Rn );
   693                                 sh4_x86.tstate = TSTATE_NONE;
   694                                 }
   695                                 break;
   696                             default:
   697                                 UNDEF();
   698                                 break;
   699                         }
   700                         break;
   701                     case 0xB:
   702                         switch( (ir&0xFF0) >> 4 ) {
   703                             case 0x0:
   704                                 { /* RTS */
   705                                 if( sh4_x86.in_delay_slot ) {
   706                             	SLOTILLEGAL();
   707                                 } else {
   708                             	load_spreg( R_ECX, R_PR );
   709                             	store_spreg( R_ECX, REG_OFFSET(pc) );
   710                             	sh4_x86.in_delay_slot = TRUE;
   711                             	sh4_translate_instruction(pc+2);
   712                             	exit_block_pcset(pc+2);
   713                             	sh4_x86.branch_taken = TRUE;
   714                             	return 4;
   715                                 }
   716                                 }
   717                                 break;
   718                             case 0x1:
   719                                 { /* SLEEP */
   720                                 check_priv();
   721                                 call_func0( sh4_sleep );
   722                                 sh4_x86.tstate = TSTATE_NONE;
   723                                 sh4_x86.in_delay_slot = FALSE;
   724                                 return 2;
   725                                 }
   726                                 break;
   727                             case 0x2:
   728                                 { /* RTE */
   729                                 if( sh4_x86.in_delay_slot ) {
   730                             	SLOTILLEGAL();
   731                                 } else {
   732                             	check_priv();
   733                             	load_spreg( R_ECX, R_SPC );
   734                             	store_spreg( R_ECX, REG_OFFSET(pc) );
   735                             	load_spreg( R_EAX, R_SSR );
   736                             	call_func1( sh4_write_sr, R_EAX );
   737                             	sh4_x86.in_delay_slot = TRUE;
   738                             	sh4_x86.priv_checked = FALSE;
   739                             	sh4_x86.fpuen_checked = FALSE;
   740                             	sh4_x86.tstate = TSTATE_NONE;
   741                             	sh4_translate_instruction(pc+2);
   742                             	exit_block_pcset(pc+2);
   743                             	sh4_x86.branch_taken = TRUE;
   744                             	return 4;
   745                                 }
   746                                 }
   747                                 break;
   748                             default:
   749                                 UNDEF();
   750                                 break;
   751                         }
   752                         break;
   753                     case 0xC:
   754                         { /* MOV.B @(R0, Rm), Rn */
   755                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   756                         load_reg( R_EAX, 0 );
   757                         load_reg( R_ECX, Rm );
   758                         ADD_r32_r32( R_EAX, R_ECX );
   759                         MEM_READ_BYTE( R_ECX, R_EAX );
   760                         store_reg( R_EAX, Rn );
   761                         sh4_x86.tstate = TSTATE_NONE;
   762                         }
   763                         break;
   764                     case 0xD:
   765                         { /* MOV.W @(R0, Rm), Rn */
   766                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   767                         load_reg( R_EAX, 0 );
   768                         load_reg( R_ECX, Rm );
   769                         ADD_r32_r32( R_EAX, R_ECX );
   770                         check_ralign16( R_ECX );
   771                         MEM_READ_WORD( R_ECX, R_EAX );
   772                         store_reg( R_EAX, Rn );
   773                         sh4_x86.tstate = TSTATE_NONE;
   774                         }
   775                         break;
   776                     case 0xE:
   777                         { /* MOV.L @(R0, Rm), Rn */
   778                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   779                         load_reg( R_EAX, 0 );
   780                         load_reg( R_ECX, Rm );
   781                         ADD_r32_r32( R_EAX, R_ECX );
   782                         check_ralign32( R_ECX );
   783                         MEM_READ_LONG( R_ECX, R_EAX );
   784                         store_reg( R_EAX, Rn );
   785                         sh4_x86.tstate = TSTATE_NONE;
   786                         }
   787                         break;
   788                     case 0xF:
   789                         { /* MAC.L @Rm+, @Rn+ */
   790                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   791                         load_reg( R_ECX, Rm );
   792                         check_ralign32( R_ECX );
   793                         load_reg( R_ECX, Rn );
   794                         check_ralign32( R_ECX );
   795                         ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
   796                         MEM_READ_LONG( R_ECX, R_EAX );
   797                         PUSH_realigned_r32( R_EAX );
   798                         load_reg( R_ECX, Rm );
   799                         ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
   800                         MEM_READ_LONG( R_ECX, R_EAX );
   801                         POP_realigned_r32( R_ECX );
   802                         IMUL_r32( R_ECX );
   803                         ADD_r32_sh4r( R_EAX, R_MACL );
   804                         ADC_r32_sh4r( R_EDX, R_MACH );
   806                         load_spreg( R_ECX, R_S );
   807                         TEST_r32_r32(R_ECX, R_ECX);
   808                         JE_rel8( CALL_FUNC0_SIZE, nosat );
   809                         call_func0( signsat48 );
   810                         JMP_TARGET( nosat );
   811                         sh4_x86.tstate = TSTATE_NONE;
   812                         }
   813                         break;
   814                     default:
   815                         UNDEF();
   816                         break;
   817                 }
   818                 break;
   819             case 0x1:
   820                 { /* MOV.L Rm, @(disp, Rn) */
   821                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
   822                 load_reg( R_ECX, Rn );
   823                 load_reg( R_EAX, Rm );
   824                 ADD_imm32_r32( disp, R_ECX );
   825                 check_walign32( R_ECX );
   826                 MEM_WRITE_LONG( R_ECX, R_EAX );
   827                 sh4_x86.tstate = TSTATE_NONE;
   828                 }
   829                 break;
   830             case 0x2:
   831                 switch( ir&0xF ) {
   832                     case 0x0:
   833                         { /* MOV.B Rm, @Rn */
   834                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   835                         load_reg( R_EAX, Rm );
   836                         load_reg( R_ECX, Rn );
   837                         MEM_WRITE_BYTE( R_ECX, R_EAX );
   838                         sh4_x86.tstate = TSTATE_NONE;
   839                         }
   840                         break;
   841                     case 0x1:
   842                         { /* MOV.W Rm, @Rn */
   843                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   844                         load_reg( R_ECX, Rn );
   845                         check_walign16( R_ECX );
   846                         load_reg( R_EAX, Rm );
   847                         MEM_WRITE_WORD( R_ECX, R_EAX );
   848                         sh4_x86.tstate = TSTATE_NONE;
   849                         }
   850                         break;
   851                     case 0x2:
   852                         { /* MOV.L Rm, @Rn */
   853                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   854                         load_reg( R_EAX, Rm );
   855                         load_reg( R_ECX, Rn );
   856                         check_walign32(R_ECX);
   857                         MEM_WRITE_LONG( R_ECX, R_EAX );
   858                         sh4_x86.tstate = TSTATE_NONE;
   859                         }
   860                         break;
   861                     case 0x4:
   862                         { /* MOV.B Rm, @-Rn */
   863                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   864                         load_reg( R_EAX, Rm );
   865                         load_reg( R_ECX, Rn );
   866                         ADD_imm8s_r32( -1, R_ECX );
   867                         store_reg( R_ECX, Rn );
   868                         MEM_WRITE_BYTE( R_ECX, R_EAX );
   869                         sh4_x86.tstate = TSTATE_NONE;
   870                         }
   871                         break;
   872                     case 0x5:
   873                         { /* MOV.W Rm, @-Rn */
   874                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   875                         load_reg( R_ECX, Rn );
   876                         check_walign16( R_ECX );
   877                         load_reg( R_EAX, Rm );
   878                         ADD_imm8s_r32( -2, R_ECX );
   879                         store_reg( R_ECX, Rn );
   880                         MEM_WRITE_WORD( R_ECX, R_EAX );
   881                         sh4_x86.tstate = TSTATE_NONE;
   882                         }
   883                         break;
   884                     case 0x6:
   885                         { /* MOV.L Rm, @-Rn */
   886                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   887                         load_reg( R_EAX, Rm );
   888                         load_reg( R_ECX, Rn );
   889                         check_walign32( R_ECX );
   890                         ADD_imm8s_r32( -4, R_ECX );
   891                         store_reg( R_ECX, Rn );
   892                         MEM_WRITE_LONG( R_ECX, R_EAX );
   893                         sh4_x86.tstate = TSTATE_NONE;
   894                         }
   895                         break;
   896                     case 0x7:
   897                         { /* DIV0S Rm, Rn */
   898                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   899                         load_reg( R_EAX, Rm );
   900                         load_reg( R_ECX, Rn );
   901                         SHR_imm8_r32( 31, R_EAX );
   902                         SHR_imm8_r32( 31, R_ECX );
   903                         store_spreg( R_EAX, R_M );
   904                         store_spreg( R_ECX, R_Q );
   905                         CMP_r32_r32( R_EAX, R_ECX );
   906                         SETNE_t();
   907                         sh4_x86.tstate = TSTATE_NE;
   908                         }
   909                         break;
   910                     case 0x8:
   911                         { /* TST Rm, Rn */
   912                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   913                         load_reg( R_EAX, Rm );
   914                         load_reg( R_ECX, Rn );
   915                         TEST_r32_r32( R_EAX, R_ECX );
   916                         SETE_t();
   917                         sh4_x86.tstate = TSTATE_E;
   918                         }
   919                         break;
   920                     case 0x9:
   921                         { /* AND Rm, Rn */
   922                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   923                         load_reg( R_EAX, Rm );
   924                         load_reg( R_ECX, Rn );
   925                         AND_r32_r32( R_EAX, R_ECX );
   926                         store_reg( R_ECX, Rn );
   927                         sh4_x86.tstate = TSTATE_NONE;
   928                         }
   929                         break;
   930                     case 0xA:
   931                         { /* XOR Rm, Rn */
   932                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   933                         load_reg( R_EAX, Rm );
   934                         load_reg( R_ECX, Rn );
   935                         XOR_r32_r32( R_EAX, R_ECX );
   936                         store_reg( R_ECX, Rn );
   937                         sh4_x86.tstate = TSTATE_NONE;
   938                         }
   939                         break;
   940                     case 0xB:
   941                         { /* OR Rm, Rn */
   942                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   943                         load_reg( R_EAX, Rm );
   944                         load_reg( R_ECX, Rn );
   945                         OR_r32_r32( R_EAX, R_ECX );
   946                         store_reg( R_ECX, Rn );
   947                         sh4_x86.tstate = TSTATE_NONE;
   948                         }
   949                         break;
   950                     case 0xC:
   951                         { /* CMP/STR Rm, Rn */
   952                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   953                         load_reg( R_EAX, Rm );
   954                         load_reg( R_ECX, Rn );
   955                         XOR_r32_r32( R_ECX, R_EAX );
   956                         TEST_r8_r8( R_AL, R_AL );
   957                         JE_rel8(13, target1);
   958                         TEST_r8_r8( R_AH, R_AH ); // 2
   959                         JE_rel8(9, target2);
   960                         SHR_imm8_r32( 16, R_EAX ); // 3
   961                         TEST_r8_r8( R_AL, R_AL ); // 2
   962                         JE_rel8(2, target3);
   963                         TEST_r8_r8( R_AH, R_AH ); // 2
   964                         JMP_TARGET(target1);
   965                         JMP_TARGET(target2);
   966                         JMP_TARGET(target3);
   967                         SETE_t();
   968                         sh4_x86.tstate = TSTATE_E;
   969                         }
   970                         break;
   971                     case 0xD:
   972                         { /* XTRCT Rm, Rn */
   973                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   974                         load_reg( R_EAX, Rm );
   975                         load_reg( R_ECX, Rn );
   976                         SHL_imm8_r32( 16, R_EAX );
   977                         SHR_imm8_r32( 16, R_ECX );
   978                         OR_r32_r32( R_EAX, R_ECX );
   979                         store_reg( R_ECX, Rn );
   980                         sh4_x86.tstate = TSTATE_NONE;
   981                         }
   982                         break;
   983                     case 0xE:
   984                         { /* MULU.W Rm, Rn */
   985                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   986                         load_reg16u( R_EAX, Rm );
   987                         load_reg16u( R_ECX, Rn );
   988                         MUL_r32( R_ECX );
   989                         store_spreg( R_EAX, R_MACL );
   990                         sh4_x86.tstate = TSTATE_NONE;
   991                         }
   992                         break;
   993                     case 0xF:
   994                         { /* MULS.W Rm, Rn */
   995                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   996                         load_reg16s( R_EAX, Rm );
   997                         load_reg16s( R_ECX, Rn );
   998                         MUL_r32( R_ECX );
   999                         store_spreg( R_EAX, R_MACL );
  1000                         sh4_x86.tstate = TSTATE_NONE;
  1002                         break;
  1003                     default:
  1004                         UNDEF();
  1005                         break;
  1007                 break;
  1008             case 0x3:
  1009                 switch( ir&0xF ) {
  1010                     case 0x0:
  1011                         { /* CMP/EQ Rm, Rn */
  1012                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1013                         load_reg( R_EAX, Rm );
  1014                         load_reg( R_ECX, Rn );
  1015                         CMP_r32_r32( R_EAX, R_ECX );
  1016                         SETE_t();
  1017                         sh4_x86.tstate = TSTATE_E;
  1019                         break;
  1020                     case 0x2:
  1021                         { /* CMP/HS Rm, Rn */
  1022                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1023                         load_reg( R_EAX, Rm );
  1024                         load_reg( R_ECX, Rn );
  1025                         CMP_r32_r32( R_EAX, R_ECX );
  1026                         SETAE_t();
  1027                         sh4_x86.tstate = TSTATE_AE;
  1029                         break;
  1030                     case 0x3:
  1031                         { /* CMP/GE Rm, Rn */
  1032                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1033                         load_reg( R_EAX, Rm );
  1034                         load_reg( R_ECX, Rn );
  1035                         CMP_r32_r32( R_EAX, R_ECX );
  1036                         SETGE_t();
  1037                         sh4_x86.tstate = TSTATE_GE;
  1039                         break;
  1040                     case 0x4:
  1041                         { /* DIV1 Rm, Rn */
  1042                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1043                         load_spreg( R_ECX, R_M );
  1044                         load_reg( R_EAX, Rn );
  1045                         if( sh4_x86.tstate != TSTATE_C ) {
  1046                     	LDC_t();
  1048                         RCL1_r32( R_EAX );
  1049                         SETC_r8( R_DL ); // Q'
  1050                         CMP_sh4r_r32( R_Q, R_ECX );
  1051                         JE_rel8(5, mqequal);
  1052                         ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
  1053                         JMP_rel8(3, end);
  1054                         JMP_TARGET(mqequal);
  1055                         SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
  1056                         JMP_TARGET(end);
  1057                         store_reg( R_EAX, Rn ); // Done with Rn now
  1058                         SETC_r8(R_AL); // tmp1
  1059                         XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
  1060                         XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
  1061                         store_spreg( R_ECX, R_Q );
  1062                         XOR_imm8s_r32( 1, R_AL );   // T = !Q'
  1063                         MOVZX_r8_r32( R_AL, R_EAX );
  1064                         store_spreg( R_EAX, R_T );
  1065                         sh4_x86.tstate = TSTATE_NONE;
  1067                         break;
  1068                     case 0x5:
  1069                         { /* DMULU.L Rm, Rn */
  1070                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1071                         load_reg( R_EAX, Rm );
  1072                         load_reg( R_ECX, Rn );
  1073                         MUL_r32(R_ECX);
  1074                         store_spreg( R_EDX, R_MACH );
  1075                         store_spreg( R_EAX, R_MACL );    
  1076                         sh4_x86.tstate = TSTATE_NONE;
  1078                         break;
  1079                     case 0x6:
  1080                         { /* CMP/HI Rm, Rn */
  1081                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1082                         load_reg( R_EAX, Rm );
  1083                         load_reg( R_ECX, Rn );
  1084                         CMP_r32_r32( R_EAX, R_ECX );
  1085                         SETA_t();
  1086                         sh4_x86.tstate = TSTATE_A;
  1088                         break;
  1089                     case 0x7:
  1090                         { /* CMP/GT Rm, Rn */
  1091                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1092                         load_reg( R_EAX, Rm );
  1093                         load_reg( R_ECX, Rn );
  1094                         CMP_r32_r32( R_EAX, R_ECX );
  1095                         SETG_t();
  1096                         sh4_x86.tstate = TSTATE_G;
  1098                         break;
  1099                     case 0x8:
  1100                         { /* SUB Rm, Rn */
  1101                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1102                         load_reg( R_EAX, Rm );
  1103                         load_reg( R_ECX, Rn );
  1104                         SUB_r32_r32( R_EAX, R_ECX );
  1105                         store_reg( R_ECX, Rn );
  1106                         sh4_x86.tstate = TSTATE_NONE;
  1108                         break;
  1109                     case 0xA:
  1110                         { /* SUBC Rm, Rn */
  1111                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1112                         load_reg( R_EAX, Rm );
  1113                         load_reg( R_ECX, Rn );
  1114                         if( sh4_x86.tstate != TSTATE_C ) {
  1115                     	LDC_t();
  1117                         SBB_r32_r32( R_EAX, R_ECX );
  1118                         store_reg( R_ECX, Rn );
  1119                         SETC_t();
  1120                         sh4_x86.tstate = TSTATE_C;
  1122                         break;
  1123                     case 0xB:
  1124                         { /* SUBV Rm, Rn */
  1125                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1126                         load_reg( R_EAX, Rm );
  1127                         load_reg( R_ECX, Rn );
  1128                         SUB_r32_r32( R_EAX, R_ECX );
  1129                         store_reg( R_ECX, Rn );
  1130                         SETO_t();
  1131                         sh4_x86.tstate = TSTATE_O;
  1133                         break;
  1134                     case 0xC:
  1135                         { /* ADD Rm, Rn */
  1136                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1137                         load_reg( R_EAX, Rm );
  1138                         load_reg( R_ECX, Rn );
  1139                         ADD_r32_r32( R_EAX, R_ECX );
  1140                         store_reg( R_ECX, Rn );
  1141                         sh4_x86.tstate = TSTATE_NONE;
  1143                         break;
  1144                     case 0xD:
  1145                         { /* DMULS.L Rm, Rn */
  1146                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1147                         load_reg( R_EAX, Rm );
  1148                         load_reg( R_ECX, Rn );
  1149                         IMUL_r32(R_ECX);
  1150                         store_spreg( R_EDX, R_MACH );
  1151                         store_spreg( R_EAX, R_MACL );
  1152                         sh4_x86.tstate = TSTATE_NONE;
  1154                         break;
  1155                     case 0xE:
  1156                         { /* ADDC Rm, Rn */
  1157                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1158                         if( sh4_x86.tstate != TSTATE_C ) {
  1159                     	LDC_t();
  1161                         load_reg( R_EAX, Rm );
  1162                         load_reg( R_ECX, Rn );
  1163                         ADC_r32_r32( R_EAX, R_ECX );
  1164                         store_reg( R_ECX, Rn );
  1165                         SETC_t();
  1166                         sh4_x86.tstate = TSTATE_C;
  1168                         break;
  1169                     case 0xF:
  1170                         { /* ADDV Rm, Rn */
  1171                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1172                         load_reg( R_EAX, Rm );
  1173                         load_reg( R_ECX, Rn );
  1174                         ADD_r32_r32( R_EAX, R_ECX );
  1175                         store_reg( R_ECX, Rn );
  1176                         SETO_t();
  1177                         sh4_x86.tstate = TSTATE_O;
  1179                         break;
  1180                     default:
  1181                         UNDEF();
  1182                         break;
  1184                 break;
  1185             case 0x4:
  1186                 switch( ir&0xF ) {
  1187                     case 0x0:
  1188                         switch( (ir&0xF0) >> 4 ) {
  1189                             case 0x0:
  1190                                 { /* SHLL Rn */
  1191                                 uint32_t Rn = ((ir>>8)&0xF); 
  1192                                 load_reg( R_EAX, Rn );
  1193                                 SHL1_r32( R_EAX );
  1194                                 SETC_t();
  1195                                 store_reg( R_EAX, Rn );
  1196                                 sh4_x86.tstate = TSTATE_C;
  1198                                 break;
  1199                             case 0x1:
  1200                                 { /* DT Rn */
  1201                                 uint32_t Rn = ((ir>>8)&0xF); 
  1202                                 load_reg( R_EAX, Rn );
  1203                                 ADD_imm8s_r32( -1, R_EAX );
  1204                                 store_reg( R_EAX, Rn );
  1205                                 SETE_t();
  1206                                 sh4_x86.tstate = TSTATE_E;
  1208                                 break;
  1209                             case 0x2:
  1210                                 { /* SHAL Rn */
  1211                                 uint32_t Rn = ((ir>>8)&0xF); 
  1212                                 load_reg( R_EAX, Rn );
  1213                                 SHL1_r32( R_EAX );
  1214                                 SETC_t();
  1215                                 store_reg( R_EAX, Rn );
  1216                                 sh4_x86.tstate = TSTATE_C;
  1218                                 break;
  1219                             default:
  1220                                 UNDEF();
  1221                                 break;
  1223                         break;
  1224                     case 0x1:
  1225                         switch( (ir&0xF0) >> 4 ) {
  1226                             case 0x0:
  1227                                 { /* SHLR Rn */
  1228                                 uint32_t Rn = ((ir>>8)&0xF); 
  1229                                 load_reg( R_EAX, Rn );
  1230                                 SHR1_r32( R_EAX );
  1231                                 SETC_t();
  1232                                 store_reg( R_EAX, Rn );
  1233                                 sh4_x86.tstate = TSTATE_C;
  1235                                 break;
  1236                             case 0x1:
  1237                                 { /* CMP/PZ Rn */
  1238                                 uint32_t Rn = ((ir>>8)&0xF); 
  1239                                 load_reg( R_EAX, Rn );
  1240                                 CMP_imm8s_r32( 0, R_EAX );
  1241                                 SETGE_t();
  1242                                 sh4_x86.tstate = TSTATE_GE;
  1244                                 break;
  1245                             case 0x2:
  1246                                 { /* SHAR Rn */
  1247                                 uint32_t Rn = ((ir>>8)&0xF); 
  1248                                 load_reg( R_EAX, Rn );
  1249                                 SAR1_r32( R_EAX );
  1250                                 SETC_t();
  1251                                 store_reg( R_EAX, Rn );
  1252                                 sh4_x86.tstate = TSTATE_C;
  1254                                 break;
  1255                             default:
  1256                                 UNDEF();
  1257                                 break;
  1259                         break;
  1260                     case 0x2:
  1261                         switch( (ir&0xF0) >> 4 ) {
  1262                             case 0x0:
  1263                                 { /* STS.L MACH, @-Rn */
  1264                                 uint32_t Rn = ((ir>>8)&0xF); 
  1265                                 load_reg( R_ECX, Rn );
  1266                                 check_walign32( R_ECX );
  1267                                 ADD_imm8s_r32( -4, R_ECX );
  1268                                 store_reg( R_ECX, Rn );
  1269                                 load_spreg( R_EAX, R_MACH );
  1270                                 MEM_WRITE_LONG( R_ECX, R_EAX );
  1271                                 sh4_x86.tstate = TSTATE_NONE;
  1273                                 break;
  1274                             case 0x1:
  1275                                 { /* STS.L MACL, @-Rn */
  1276                                 uint32_t Rn = ((ir>>8)&0xF); 
  1277                                 load_reg( R_ECX, Rn );
  1278                                 check_walign32( R_ECX );
  1279                                 ADD_imm8s_r32( -4, R_ECX );
  1280                                 store_reg( R_ECX, Rn );
  1281                                 load_spreg( R_EAX, R_MACL );
  1282                                 MEM_WRITE_LONG( R_ECX, R_EAX );
  1283                                 sh4_x86.tstate = TSTATE_NONE;
  1285                                 break;
  1286                             case 0x2:
  1287                                 { /* STS.L PR, @-Rn */
  1288                                 uint32_t Rn = ((ir>>8)&0xF); 
  1289                                 load_reg( R_ECX, Rn );
  1290                                 check_walign32( R_ECX );
  1291                                 ADD_imm8s_r32( -4, R_ECX );
  1292                                 store_reg( R_ECX, Rn );
  1293                                 load_spreg( R_EAX, R_PR );
  1294                                 MEM_WRITE_LONG( R_ECX, R_EAX );
  1295                                 sh4_x86.tstate = TSTATE_NONE;
  1297                                 break;
  1298                             case 0x3:
  1299                                 { /* STC.L SGR, @-Rn */
  1300                                 uint32_t Rn = ((ir>>8)&0xF); 
  1301                                 check_priv();
  1302                                 load_reg( R_ECX, Rn );
  1303                                 check_walign32( R_ECX );
  1304                                 ADD_imm8s_r32( -4, R_ECX );
  1305                                 store_reg( R_ECX, Rn );
  1306                                 load_spreg( R_EAX, R_SGR );
  1307                                 MEM_WRITE_LONG( R_ECX, R_EAX );
  1308                                 sh4_x86.tstate = TSTATE_NONE;
  1310                                 break;
  1311                             case 0x5:
  1312                                 { /* STS.L FPUL, @-Rn */
  1313                                 uint32_t Rn = ((ir>>8)&0xF); 
  1314                                 load_reg( R_ECX, Rn );
  1315                                 check_walign32( R_ECX );
  1316                                 ADD_imm8s_r32( -4, R_ECX );
  1317                                 store_reg( R_ECX, Rn );
  1318                                 load_spreg( R_EAX, R_FPUL );
  1319                                 MEM_WRITE_LONG( R_ECX, R_EAX );
  1320                                 sh4_x86.tstate = TSTATE_NONE;
  1322                                 break;
  1323                             case 0x6:
  1324                                 { /* STS.L FPSCR, @-Rn */
  1325                                 uint32_t Rn = ((ir>>8)&0xF); 
  1326                                 load_reg( R_ECX, Rn );
  1327                                 check_walign32( R_ECX );
  1328                                 ADD_imm8s_r32( -4, R_ECX );
  1329                                 store_reg( R_ECX, Rn );
  1330                                 load_spreg( R_EAX, R_FPSCR );
  1331                                 MEM_WRITE_LONG( R_ECX, R_EAX );
  1332                                 sh4_x86.tstate = TSTATE_NONE;
  1334                                 break;
  1335                             case 0xF:
  1336                                 { /* STC.L DBR, @-Rn */
  1337                                 uint32_t Rn = ((ir>>8)&0xF); 
  1338                                 check_priv();
  1339                                 load_reg( R_ECX, Rn );
  1340                                 check_walign32( R_ECX );
  1341                                 ADD_imm8s_r32( -4, R_ECX );
  1342                                 store_reg( R_ECX, Rn );
  1343                                 load_spreg( R_EAX, R_DBR );
  1344                                 MEM_WRITE_LONG( R_ECX, R_EAX );
  1345                                 sh4_x86.tstate = TSTATE_NONE;
  1347                                 break;
  1348                             default:
  1349                                 UNDEF();
  1350                                 break;
  1352                         break;
  1353                     case 0x3:
  1354                         switch( (ir&0x80) >> 7 ) {
  1355                             case 0x0:
  1356                                 switch( (ir&0x70) >> 4 ) {
  1357                                     case 0x0:
  1358                                         { /* STC.L SR, @-Rn */
  1359                                         uint32_t Rn = ((ir>>8)&0xF); 
  1360                                         check_priv();
  1361                                         call_func0( sh4_read_sr );
  1362                                         load_reg( R_ECX, Rn );
  1363                                         check_walign32( R_ECX );
  1364                                         ADD_imm8s_r32( -4, R_ECX );
  1365                                         store_reg( R_ECX, Rn );
  1366                                         MEM_WRITE_LONG( R_ECX, R_EAX );
  1367                                         sh4_x86.tstate = TSTATE_NONE;
  1369                                         break;
  1370                                     case 0x1:
  1371                                         { /* STC.L GBR, @-Rn */
  1372                                         uint32_t Rn = ((ir>>8)&0xF); 
  1373                                         load_reg( R_ECX, Rn );
  1374                                         check_walign32( R_ECX );
  1375                                         ADD_imm8s_r32( -4, R_ECX );
  1376                                         store_reg( R_ECX, Rn );
  1377                                         load_spreg( R_EAX, R_GBR );
  1378                                         MEM_WRITE_LONG( R_ECX, R_EAX );
  1379                                         sh4_x86.tstate = TSTATE_NONE;
  1381                                         break;
  1382                                     case 0x2:
  1383                                         { /* STC.L VBR, @-Rn */
  1384                                         uint32_t Rn = ((ir>>8)&0xF); 
  1385                                         check_priv();
  1386                                         load_reg( R_ECX, Rn );
  1387                                         check_walign32( R_ECX );
  1388                                         ADD_imm8s_r32( -4, R_ECX );
  1389                                         store_reg( R_ECX, Rn );
  1390                                         load_spreg( R_EAX, R_VBR );
  1391                                         MEM_WRITE_LONG( R_ECX, R_EAX );
  1392                                         sh4_x86.tstate = TSTATE_NONE;
  1394                                         break;
  1395                                     case 0x3:
  1396                                         { /* STC.L SSR, @-Rn */
  1397                                         uint32_t Rn = ((ir>>8)&0xF); 
  1398                                         check_priv();
  1399                                         load_reg( R_ECX, Rn );
  1400                                         check_walign32( R_ECX );
  1401                                         ADD_imm8s_r32( -4, R_ECX );
  1402                                         store_reg( R_ECX, Rn );
  1403                                         load_spreg( R_EAX, R_SSR );
  1404                                         MEM_WRITE_LONG( R_ECX, R_EAX );
  1405                                         sh4_x86.tstate = TSTATE_NONE;
  1407                                         break;
  1408                                     case 0x4:
  1409                                         { /* STC.L SPC, @-Rn */
  1410                                         uint32_t Rn = ((ir>>8)&0xF); 
  1411                                         check_priv();
  1412                                         load_reg( R_ECX, Rn );
  1413                                         check_walign32( R_ECX );
  1414                                         ADD_imm8s_r32( -4, R_ECX );
  1415                                         store_reg( R_ECX, Rn );
  1416                                         load_spreg( R_EAX, R_SPC );
  1417                                         MEM_WRITE_LONG( R_ECX, R_EAX );
  1418                                         sh4_x86.tstate = TSTATE_NONE;
  1420                                         break;
  1421                                     default:
  1422                                         UNDEF();
  1423                                         break;
  1425                                 break;
  1426                             case 0x1:
  1427                                 { /* STC.L Rm_BANK, @-Rn */
  1428                                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
  1429                                 check_priv();
  1430                                 load_reg( R_ECX, Rn );
  1431                                 check_walign32( R_ECX );
  1432                                 ADD_imm8s_r32( -4, R_ECX );
  1433                                 store_reg( R_ECX, Rn );
  1434                                 load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
  1435                                 MEM_WRITE_LONG( R_ECX, R_EAX );
  1436                                 sh4_x86.tstate = TSTATE_NONE;
  1438                                 break;
  1440                         break;
  1441                     case 0x4:
  1442                         switch( (ir&0xF0) >> 4 ) {
  1443                             case 0x0:
  1444                                 { /* ROTL Rn */
  1445                                 uint32_t Rn = ((ir>>8)&0xF); 
  1446                                 load_reg( R_EAX, Rn );
  1447                                 ROL1_r32( R_EAX );
  1448                                 store_reg( R_EAX, Rn );
  1449                                 SETC_t();
  1450                                 sh4_x86.tstate = TSTATE_C;
  1452                                 break;
  1453                             case 0x2:
  1454                                 { /* ROTCL Rn */
  1455                                 uint32_t Rn = ((ir>>8)&0xF); 
  1456                                 load_reg( R_EAX, Rn );
  1457                                 if( sh4_x86.tstate != TSTATE_C ) {
  1458                             	LDC_t();
  1460                                 RCL1_r32( R_EAX );
  1461                                 store_reg( R_EAX, Rn );
  1462                                 SETC_t();
  1463                                 sh4_x86.tstate = TSTATE_C;
  1465                                 break;
  1466                             default:
  1467                                 UNDEF();
  1468                                 break;
  1470                         break;
  1471                     case 0x5:
  1472                         switch( (ir&0xF0) >> 4 ) {
  1473                             case 0x0:
  1474                                 { /* ROTR Rn */
  1475                                 uint32_t Rn = ((ir>>8)&0xF); 
  1476                                 load_reg( R_EAX, Rn );
  1477                                 ROR1_r32( R_EAX );
  1478                                 store_reg( R_EAX, Rn );
  1479                                 SETC_t();
  1480                                 sh4_x86.tstate = TSTATE_C;
  1482                                 break;
  1483                             case 0x1:
  1484                                 { /* CMP/PL Rn */
  1485                                 uint32_t Rn = ((ir>>8)&0xF); 
  1486                                 load_reg( R_EAX, Rn );
  1487                                 CMP_imm8s_r32( 0, R_EAX );
  1488                                 SETG_t();
  1489                                 sh4_x86.tstate = TSTATE_G;
  1491                                 break;
  1492                             case 0x2:
  1493                                 { /* ROTCR Rn */
  1494                                 uint32_t Rn = ((ir>>8)&0xF); 
  1495                                 load_reg( R_EAX, Rn );
  1496                                 if( sh4_x86.tstate != TSTATE_C ) {
  1497                             	LDC_t();
  1499                                 RCR1_r32( R_EAX );
  1500                                 store_reg( R_EAX, Rn );
  1501                                 SETC_t();
  1502                                 sh4_x86.tstate = TSTATE_C;
  1504                                 break;
  1505                             default:
  1506                                 UNDEF();
  1507                                 break;
  1509                         break;
  1510                     case 0x6:
  1511                         switch( (ir&0xF0) >> 4 ) {
  1512                             case 0x0:
  1513                                 { /* LDS.L @Rm+, MACH */
  1514                                 uint32_t Rm = ((ir>>8)&0xF); 
  1515                                 load_reg( R_EAX, Rm );
  1516                                 check_ralign32( R_EAX );
  1517                                 MOV_r32_r32( R_EAX, R_ECX );
  1518                                 ADD_imm8s_r32( 4, R_EAX );
  1519                                 store_reg( R_EAX, Rm );
  1520                                 MEM_READ_LONG( R_ECX, R_EAX );
  1521                                 store_spreg( R_EAX, R_MACH );
  1522                                 sh4_x86.tstate = TSTATE_NONE;
  1524                                 break;
  1525                             case 0x1:
  1526                                 { /* LDS.L @Rm+, MACL */
  1527                                 uint32_t Rm = ((ir>>8)&0xF); 
  1528                                 load_reg( R_EAX, Rm );
  1529                                 check_ralign32( R_EAX );
  1530                                 MOV_r32_r32( R_EAX, R_ECX );
  1531                                 ADD_imm8s_r32( 4, R_EAX );
  1532                                 store_reg( R_EAX, Rm );
  1533                                 MEM_READ_LONG( R_ECX, R_EAX );
  1534                                 store_spreg( R_EAX, R_MACL );
  1535                                 sh4_x86.tstate = TSTATE_NONE;
  1537                                 break;
  1538                             case 0x2:
  1539                                 { /* LDS.L @Rm+, PR */
  1540                                 uint32_t Rm = ((ir>>8)&0xF); 
  1541                                 load_reg( R_EAX, Rm );
  1542                                 check_ralign32( R_EAX );
  1543                                 MOV_r32_r32( R_EAX, R_ECX );
  1544                                 ADD_imm8s_r32( 4, R_EAX );
  1545                                 store_reg( R_EAX, Rm );
  1546                                 MEM_READ_LONG( R_ECX, R_EAX );
  1547                                 store_spreg( R_EAX, R_PR );
  1548                                 sh4_x86.tstate = TSTATE_NONE;
  1550                                 break;
  1551                             case 0x3:
  1552                                 { /* LDC.L @Rm+, SGR */
  1553                                 uint32_t Rm = ((ir>>8)&0xF); 
  1554                                 check_priv();
  1555                                 load_reg( R_EAX, Rm );
  1556                                 check_ralign32( R_EAX );
  1557                                 MOV_r32_r32( R_EAX, R_ECX );
  1558                                 ADD_imm8s_r32( 4, R_EAX );
  1559                                 store_reg( R_EAX, Rm );
  1560                                 MEM_READ_LONG( R_ECX, R_EAX );
  1561                                 store_spreg( R_EAX, R_SGR );
  1562                                 sh4_x86.tstate = TSTATE_NONE;
  1564                                 break;
  1565                             case 0x5:
  1566                                 { /* LDS.L @Rm+, FPUL */
  1567                                 uint32_t Rm = ((ir>>8)&0xF); 
  1568                                 load_reg( R_EAX, Rm );
  1569                                 check_ralign32( R_EAX );
  1570                                 MOV_r32_r32( R_EAX, R_ECX );
  1571                                 ADD_imm8s_r32( 4, R_EAX );
  1572                                 store_reg( R_EAX, Rm );
  1573                                 MEM_READ_LONG( R_ECX, R_EAX );
  1574                                 store_spreg( R_EAX, R_FPUL );
  1575                                 sh4_x86.tstate = TSTATE_NONE;
  1577                                 break;
  1578                             case 0x6:
  1579                                 { /* LDS.L @Rm+, FPSCR */
  1580                                 uint32_t Rm = ((ir>>8)&0xF); 
  1581                                 load_reg( R_EAX, Rm );
  1582                                 check_ralign32( R_EAX );
  1583                                 MOV_r32_r32( R_EAX, R_ECX );
  1584                                 ADD_imm8s_r32( 4, R_EAX );
  1585                                 store_reg( R_EAX, Rm );
  1586                                 MEM_READ_LONG( R_ECX, R_EAX );
  1587                                 store_spreg( R_EAX, R_FPSCR );
  1588                                 update_fr_bank( R_EAX );
  1589                                 sh4_x86.tstate = TSTATE_NONE;
  1591                                 break;
  1592                             case 0xF:
  1593                                 { /* LDC.L @Rm+, DBR */
  1594                                 uint32_t Rm = ((ir>>8)&0xF); 
  1595                                 check_priv();
  1596                                 load_reg( R_EAX, Rm );
  1597                                 check_ralign32( R_EAX );
  1598                                 MOV_r32_r32( R_EAX, R_ECX );
  1599                                 ADD_imm8s_r32( 4, R_EAX );
  1600                                 store_reg( R_EAX, Rm );
  1601                                 MEM_READ_LONG( R_ECX, R_EAX );
  1602                                 store_spreg( R_EAX, R_DBR );
  1603                                 sh4_x86.tstate = TSTATE_NONE;
  1605                                 break;
  1606                             default:
  1607                                 UNDEF();
  1608                                 break;
  1610                         break;
  1611                     case 0x7:
  1612                         switch( (ir&0x80) >> 7 ) {
  1613                             case 0x0:
  1614                                 switch( (ir&0x70) >> 4 ) {
  1615                                     case 0x0:
  1616                                         { /* LDC.L @Rm+, SR */
  1617                                         uint32_t Rm = ((ir>>8)&0xF); 
  1618                                         if( sh4_x86.in_delay_slot ) {
  1619                                     	SLOTILLEGAL();
  1620                                         } else {
  1621                                     	check_priv();
  1622                                     	load_reg( R_EAX, Rm );
  1623                                     	check_ralign32( R_EAX );
  1624                                     	MOV_r32_r32( R_EAX, R_ECX );
  1625                                     	ADD_imm8s_r32( 4, R_EAX );
  1626                                     	store_reg( R_EAX, Rm );
  1627                                     	MEM_READ_LONG( R_ECX, R_EAX );
  1628                                     	call_func1( sh4_write_sr, R_EAX );
  1629                                     	sh4_x86.priv_checked = FALSE;
  1630                                     	sh4_x86.fpuen_checked = FALSE;
  1631                                     	sh4_x86.tstate = TSTATE_NONE;
  1634                                         break;
  1635                                     case 0x1:
  1636                                         { /* LDC.L @Rm+, GBR */
  1637                                         uint32_t Rm = ((ir>>8)&0xF); 
  1638                                         load_reg( R_EAX, Rm );
  1639                                         check_ralign32( R_EAX );
  1640                                         MOV_r32_r32( R_EAX, R_ECX );
  1641                                         ADD_imm8s_r32( 4, R_EAX );
  1642                                         store_reg( R_EAX, Rm );
  1643                                         MEM_READ_LONG( R_ECX, R_EAX );
  1644                                         store_spreg( R_EAX, R_GBR );
  1645                                         sh4_x86.tstate = TSTATE_NONE;
  1647                                         break;
  1648                                     case 0x2:
  1649                                         { /* LDC.L @Rm+, VBR */
  1650                                         uint32_t Rm = ((ir>>8)&0xF); 
  1651                                         check_priv();
  1652                                         load_reg( R_EAX, Rm );
  1653                                         check_ralign32( R_EAX );
  1654                                         MOV_r32_r32( R_EAX, R_ECX );
  1655                                         ADD_imm8s_r32( 4, R_EAX );
  1656                                         store_reg( R_EAX, Rm );
  1657                                         MEM_READ_LONG( R_ECX, R_EAX );
  1658                                         store_spreg( R_EAX, R_VBR );
  1659                                         sh4_x86.tstate = TSTATE_NONE;
  1661                                         break;
  1662                                     case 0x3:
  1663                                         { /* LDC.L @Rm+, SSR */
  1664                                         uint32_t Rm = ((ir>>8)&0xF); 
  1665                                         check_priv();
  1666                                         load_reg( R_EAX, Rm );
  1667                                         check_ralign32( R_EAX );
  1668                                         MOV_r32_r32( R_EAX, R_ECX );
  1669                                         ADD_imm8s_r32( 4, R_EAX );
  1670                                         store_reg( R_EAX, Rm );
  1671                                         MEM_READ_LONG( R_ECX, R_EAX );
  1672                                         store_spreg( R_EAX, R_SSR );
  1673                                         sh4_x86.tstate = TSTATE_NONE;
  1675                                         break;
  1676                                     case 0x4:
  1677                                         { /* LDC.L @Rm+, SPC */
  1678                                         uint32_t Rm = ((ir>>8)&0xF); 
  1679                                         check_priv();
  1680                                         load_reg( R_EAX, Rm );
  1681                                         check_ralign32( R_EAX );
  1682                                         MOV_r32_r32( R_EAX, R_ECX );
  1683                                         ADD_imm8s_r32( 4, R_EAX );
  1684                                         store_reg( R_EAX, Rm );
  1685                                         MEM_READ_LONG( R_ECX, R_EAX );
  1686                                         store_spreg( R_EAX, R_SPC );
  1687                                         sh4_x86.tstate = TSTATE_NONE;
  1689                                         break;
  1690                                     default:
  1691                                         UNDEF();
  1692                                         break;
  1694                                 break;
  1695                             case 0x1:
  1696                                 { /* LDC.L @Rm+, Rn_BANK */
  1697                                 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
  1698                                 check_priv();
  1699                                 load_reg( R_EAX, Rm );
  1700                                 check_ralign32( R_EAX );
  1701                                 MOV_r32_r32( R_EAX, R_ECX );
  1702                                 ADD_imm8s_r32( 4, R_EAX );
  1703                                 store_reg( R_EAX, Rm );
  1704                                 MEM_READ_LONG( R_ECX, R_EAX );
  1705                                 store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
  1706                                 sh4_x86.tstate = TSTATE_NONE;
  1708                                 break;
  1710                         break;
  1711                     case 0x8:
  1712                         switch( (ir&0xF0) >> 4 ) {
  1713                             case 0x0:
  1714                                 { /* SHLL2 Rn */
  1715                                 uint32_t Rn = ((ir>>8)&0xF); 
  1716                                 load_reg( R_EAX, Rn );
  1717                                 SHL_imm8_r32( 2, R_EAX );
  1718                                 store_reg( R_EAX, Rn );
  1719                                 sh4_x86.tstate = TSTATE_NONE;
  1721                                 break;
  1722                             case 0x1:
  1723                                 { /* SHLL8 Rn */
  1724                                 uint32_t Rn = ((ir>>8)&0xF); 
  1725                                 load_reg( R_EAX, Rn );
  1726                                 SHL_imm8_r32( 8, R_EAX );
  1727                                 store_reg( R_EAX, Rn );
  1728                                 sh4_x86.tstate = TSTATE_NONE;
  1730                                 break;
  1731                             case 0x2:
  1732                                 { /* SHLL16 Rn */
  1733                                 uint32_t Rn = ((ir>>8)&0xF); 
  1734                                 load_reg( R_EAX, Rn );
  1735                                 SHL_imm8_r32( 16, R_EAX );
  1736                                 store_reg( R_EAX, Rn );
  1737                                 sh4_x86.tstate = TSTATE_NONE;
  1739                                 break;
  1740                             default:
  1741                                 UNDEF();
  1742                                 break;
  1744                         break;
  1745                     case 0x9:
  1746                         switch( (ir&0xF0) >> 4 ) {
  1747                             case 0x0:
  1748                                 { /* SHLR2 Rn */
  1749                                 uint32_t Rn = ((ir>>8)&0xF); 
  1750                                 load_reg( R_EAX, Rn );
  1751                                 SHR_imm8_r32( 2, R_EAX );
  1752                                 store_reg( R_EAX, Rn );
  1753                                 sh4_x86.tstate = TSTATE_NONE;
  1755                                 break;
  1756                             case 0x1:
  1757                                 { /* SHLR8 Rn */
  1758                                 uint32_t Rn = ((ir>>8)&0xF); 
  1759                                 load_reg( R_EAX, Rn );
  1760                                 SHR_imm8_r32( 8, R_EAX );
  1761                                 store_reg( R_EAX, Rn );
  1762                                 sh4_x86.tstate = TSTATE_NONE;
  1764                                 break;
  1765                             case 0x2:
  1766                                 { /* SHLR16 Rn */
  1767                                 uint32_t Rn = ((ir>>8)&0xF); 
  1768                                 load_reg( R_EAX, Rn );
  1769                                 SHR_imm8_r32( 16, R_EAX );
  1770                                 store_reg( R_EAX, Rn );
  1771                                 sh4_x86.tstate = TSTATE_NONE;
  1773                                 break;
  1774                             default:
  1775                                 UNDEF();
  1776                                 break;
  1778                         break;
  1779                     case 0xA:
  1780                         switch( (ir&0xF0) >> 4 ) {
  1781                             case 0x0:
  1782                                 { /* LDS Rm, MACH */
  1783                                 uint32_t Rm = ((ir>>8)&0xF); 
  1784                                 load_reg( R_EAX, Rm );
  1785                                 store_spreg( R_EAX, R_MACH );
  1787                                 break;
  1788                             case 0x1:
  1789                                 { /* LDS Rm, MACL */
  1790                                 uint32_t Rm = ((ir>>8)&0xF); 
  1791                                 load_reg( R_EAX, Rm );
  1792                                 store_spreg( R_EAX, R_MACL );
  1794                                 break;
  1795                             case 0x2:
  1796                                 { /* LDS Rm, PR */
  1797                                 uint32_t Rm = ((ir>>8)&0xF); 
  1798                                 load_reg( R_EAX, Rm );
  1799                                 store_spreg( R_EAX, R_PR );
  1801                                 break;
  1802                             case 0x3:
  1803                                 { /* LDC Rm, SGR */
  1804                                 uint32_t Rm = ((ir>>8)&0xF); 
  1805                                 check_priv();
  1806                                 load_reg( R_EAX, Rm );
  1807                                 store_spreg( R_EAX, R_SGR );
  1808                                 sh4_x86.tstate = TSTATE_NONE;
  1810                                 break;
  1811                             case 0x5:
  1812                                 { /* LDS Rm, FPUL */
  1813                                 uint32_t Rm = ((ir>>8)&0xF); 
  1814                                 load_reg( R_EAX, Rm );
  1815                                 store_spreg( R_EAX, R_FPUL );
  1817                                 break;
  1818                             case 0x6:
  1819                                 { /* LDS Rm, FPSCR */
  1820                                 uint32_t Rm = ((ir>>8)&0xF); 
  1821                                 load_reg( R_EAX, Rm );
  1822                                 store_spreg( R_EAX, R_FPSCR );
  1823                                 update_fr_bank( R_EAX );
  1824                                 sh4_x86.tstate = TSTATE_NONE;
  1826                                 break;
  1827                             case 0xF:
  1828                                 { /* LDC Rm, DBR */
  1829                                 uint32_t Rm = ((ir>>8)&0xF); 
  1830                                 check_priv();
  1831                                 load_reg( R_EAX, Rm );
  1832                                 store_spreg( R_EAX, R_DBR );
  1833                                 sh4_x86.tstate = TSTATE_NONE;
  1835                                 break;
  1836                             default:
  1837                                 UNDEF();
  1838                                 break;
  1840                         break;
  1841                     case 0xB:
  1842                         switch( (ir&0xF0) >> 4 ) {
  1843                             case 0x0:
  1844                                 { /* JSR @Rn */
  1845                                 uint32_t Rn = ((ir>>8)&0xF); 
  1846                                 if( sh4_x86.in_delay_slot ) {
  1847                             	SLOTILLEGAL();
  1848                                 } else {
  1849                             	load_imm32( R_EAX, pc + 4 );
  1850                             	store_spreg( R_EAX, R_PR );
  1851                             	load_reg( R_ECX, Rn );
  1852                             	store_spreg( R_ECX, REG_OFFSET(pc) );
  1853                             	sh4_x86.in_delay_slot = TRUE;
  1854                             	sh4_translate_instruction(pc+2);
  1855                             	exit_block_pcset(pc+2);
  1856                             	sh4_x86.branch_taken = TRUE;
  1857                             	return 4;
  1860                                 break;
  1861                             case 0x1:
  1862                                 { /* TAS.B @Rn */
  1863                                 uint32_t Rn = ((ir>>8)&0xF); 
  1864                                 load_reg( R_ECX, Rn );
  1865                                 MEM_READ_BYTE( R_ECX, R_EAX );
  1866                                 TEST_r8_r8( R_AL, R_AL );
  1867                                 SETE_t();
  1868                                 OR_imm8_r8( 0x80, R_AL );
  1869                                 load_reg( R_ECX, Rn );
  1870                                 MEM_WRITE_BYTE( R_ECX, R_EAX );
  1871                                 sh4_x86.tstate = TSTATE_NONE;
  1873                                 break;
  1874                             case 0x2:
  1875                                 { /* JMP @Rn */
  1876                                 uint32_t Rn = ((ir>>8)&0xF); 
  1877                                 if( sh4_x86.in_delay_slot ) {
  1878                             	SLOTILLEGAL();
  1879                                 } else {
  1880                             	load_reg( R_ECX, Rn );
  1881                             	store_spreg( R_ECX, REG_OFFSET(pc) );
  1882                             	sh4_x86.in_delay_slot = TRUE;
  1883                             	sh4_translate_instruction(pc+2);
  1884                             	exit_block_pcset(pc+2);
  1885                             	sh4_x86.branch_taken = TRUE;
  1886                             	return 4;
  1889                                 break;
  1890                             default:
  1891                                 UNDEF();
  1892                                 break;
  1894                         break;
  1895                     case 0xC:
  1896                         { /* SHAD Rm, Rn */
  1897                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1898                         /* Annoyingly enough, not directly convertible */
  1899                         load_reg( R_EAX, Rn );
  1900                         load_reg( R_ECX, Rm );
  1901                         CMP_imm32_r32( 0, R_ECX );
  1902                         JGE_rel8(16, doshl);
  1904                         NEG_r32( R_ECX );      // 2
  1905                         AND_imm8_r8( 0x1F, R_CL ); // 3
  1906                         JE_rel8( 4, emptysar);     // 2
  1907                         SAR_r32_CL( R_EAX );       // 2
  1908                         JMP_rel8(10, end);          // 2
  1910                         JMP_TARGET(emptysar);
  1911                         SAR_imm8_r32(31, R_EAX );  // 3
  1912                         JMP_rel8(5, end2);
  1914                         JMP_TARGET(doshl);
  1915                         AND_imm8_r8( 0x1F, R_CL ); // 3
  1916                         SHL_r32_CL( R_EAX );       // 2
  1917                         JMP_TARGET(end);
  1918                         JMP_TARGET(end2);
  1919                         store_reg( R_EAX, Rn );
  1920                         sh4_x86.tstate = TSTATE_NONE;
  1922                         break;
  1923                     case 0xD:
  1924                         { /* SHLD Rm, Rn */
  1925                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1926                         load_reg( R_EAX, Rn );
  1927                         load_reg( R_ECX, Rm );
  1928                         CMP_imm32_r32( 0, R_ECX );
  1929                         JGE_rel8(15, doshl);
  1931                         NEG_r32( R_ECX );      // 2
  1932                         AND_imm8_r8( 0x1F, R_CL ); // 3
  1933                         JE_rel8( 4, emptyshr );
  1934                         SHR_r32_CL( R_EAX );       // 2
  1935                         JMP_rel8(9, end);          // 2
  1937                         JMP_TARGET(emptyshr);
  1938                         XOR_r32_r32( R_EAX, R_EAX );
  1939                         JMP_rel8(5, end2);
  1941                         JMP_TARGET(doshl);
  1942                         AND_imm8_r8( 0x1F, R_CL ); // 3
  1943                         SHL_r32_CL( R_EAX );       // 2
  1944                         JMP_TARGET(end);
  1945                         JMP_TARGET(end2);
  1946                         store_reg( R_EAX, Rn );
  1947                         sh4_x86.tstate = TSTATE_NONE;
  1949                         break;
  1950                     case 0xE:
  1951                         switch( (ir&0x80) >> 7 ) {
  1952                             case 0x0:
  1953                                 switch( (ir&0x70) >> 4 ) {
  1954                                     case 0x0:
  1955                                         { /* LDC Rm, SR */
  1956                                         uint32_t Rm = ((ir>>8)&0xF); 
  1957                                         if( sh4_x86.in_delay_slot ) {
  1958                                     	SLOTILLEGAL();
  1959                                         } else {
  1960                                     	check_priv();
  1961                                     	load_reg( R_EAX, Rm );
  1962                                     	call_func1( sh4_write_sr, R_EAX );
  1963                                     	sh4_x86.priv_checked = FALSE;
  1964                                     	sh4_x86.fpuen_checked = FALSE;
  1965                                     	sh4_x86.tstate = TSTATE_NONE;
  1968                                         break;
  1969                                     case 0x1:
  1970                                         { /* LDC Rm, GBR */
  1971                                         uint32_t Rm = ((ir>>8)&0xF); 
  1972                                         load_reg( R_EAX, Rm );
  1973                                         store_spreg( R_EAX, R_GBR );
  1975                                         break;
  1976                                     case 0x2:
  1977                                         { /* LDC Rm, VBR */
  1978                                         uint32_t Rm = ((ir>>8)&0xF); 
  1979                                         check_priv();
  1980                                         load_reg( R_EAX, Rm );
  1981                                         store_spreg( R_EAX, R_VBR );
  1982                                         sh4_x86.tstate = TSTATE_NONE;
  1984                                         break;
  1985                                     case 0x3:
  1986                                         { /* LDC Rm, SSR */
  1987                                         uint32_t Rm = ((ir>>8)&0xF); 
  1988                                         check_priv();
  1989                                         load_reg( R_EAX, Rm );
  1990                                         store_spreg( R_EAX, R_SSR );
  1991                                         sh4_x86.tstate = TSTATE_NONE;
  1993                                         break;
  1994                                     case 0x4:
  1995                                         { /* LDC Rm, SPC */
  1996                                         uint32_t Rm = ((ir>>8)&0xF); 
  1997                                         check_priv();
  1998                                         load_reg( R_EAX, Rm );
  1999                                         store_spreg( R_EAX, R_SPC );
  2000                                         sh4_x86.tstate = TSTATE_NONE;
  2002                                         break;
  2003                                     default:
  2004                                         UNDEF();
  2005                                         break;
  2007                                 break;
  2008                             case 0x1:
  2009                                 { /* LDC Rm, Rn_BANK */
  2010                                 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
  2011                                 check_priv();
  2012                                 load_reg( R_EAX, Rm );
  2013                                 store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
  2014                                 sh4_x86.tstate = TSTATE_NONE;
  2016                                 break;
  2018                         break;
  2019                     case 0xF:
  2020                         { /* MAC.W @Rm+, @Rn+ */
  2021                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2022                         load_reg( R_ECX, Rm );
  2023                         check_ralign16( R_ECX );
  2024                         load_reg( R_ECX, Rn );
  2025                         check_ralign16( R_ECX );
  2026                         ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
  2027                         MEM_READ_WORD( R_ECX, R_EAX );
  2028                         PUSH_realigned_r32( R_EAX );
  2029                         load_reg( R_ECX, Rm );
  2030                         ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
  2031                         MEM_READ_WORD( R_ECX, R_EAX );
  2032                         POP_realigned_r32( R_ECX );
  2033                         IMUL_r32( R_ECX );
  2035                         load_spreg( R_ECX, R_S );
  2036                         TEST_r32_r32( R_ECX, R_ECX );
  2037                         JE_rel8( 47, nosat );
  2039                         ADD_r32_sh4r( R_EAX, R_MACL );  // 6
  2040                         JNO_rel8( 51, end );            // 2
  2041                         load_imm32( R_EDX, 1 );         // 5
  2042                         store_spreg( R_EDX, R_MACH );   // 6
  2043                         JS_rel8( 13, positive );        // 2
  2044                         load_imm32( R_EAX, 0x80000000 );// 5
  2045                         store_spreg( R_EAX, R_MACL );   // 6
  2046                         JMP_rel8( 25, end2 );           // 2
  2048                         JMP_TARGET(positive);
  2049                         load_imm32( R_EAX, 0x7FFFFFFF );// 5
  2050                         store_spreg( R_EAX, R_MACL );   // 6
  2051                         JMP_rel8( 12, end3);            // 2
  2053                         JMP_TARGET(nosat);
  2054                         ADD_r32_sh4r( R_EAX, R_MACL );  // 6
  2055                         ADC_r32_sh4r( R_EDX, R_MACH );  // 6
  2056                         JMP_TARGET(end);
  2057                         JMP_TARGET(end2);
  2058                         JMP_TARGET(end3);
  2059                         sh4_x86.tstate = TSTATE_NONE;
  2061                         break;
  2063                 break;
  2064             case 0x5:
  2065                 { /* MOV.L @(disp, Rm), Rn */
  2066                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
  2067                 load_reg( R_ECX, Rm );
  2068                 ADD_imm8s_r32( disp, R_ECX );
  2069                 check_ralign32( R_ECX );
  2070                 MEM_READ_LONG( R_ECX, R_EAX );
  2071                 store_reg( R_EAX, Rn );
  2072                 sh4_x86.tstate = TSTATE_NONE;
  2074                 break;
  2075             case 0x6:
  2076                 switch( ir&0xF ) {
  2077                     case 0x0:
  2078                         { /* MOV.B @Rm, Rn */
  2079                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2080                         load_reg( R_ECX, Rm );
  2081                         MEM_READ_BYTE( R_ECX, R_EAX );
  2082                         store_reg( R_EAX, Rn );
  2083                         sh4_x86.tstate = TSTATE_NONE;
  2085                         break;
  2086                     case 0x1:
  2087                         { /* MOV.W @Rm, Rn */
  2088                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2089                         load_reg( R_ECX, Rm );
  2090                         check_ralign16( R_ECX );
  2091                         MEM_READ_WORD( R_ECX, R_EAX );
  2092                         store_reg( R_EAX, Rn );
  2093                         sh4_x86.tstate = TSTATE_NONE;
  2095                         break;
  2096                     case 0x2:
  2097                         { /* MOV.L @Rm, Rn */
  2098                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2099                         load_reg( R_ECX, Rm );
  2100                         check_ralign32( R_ECX );
  2101                         MEM_READ_LONG( R_ECX, R_EAX );
  2102                         store_reg( R_EAX, Rn );
  2103                         sh4_x86.tstate = TSTATE_NONE;
  2105                         break;
  2106                     case 0x3:
  2107                         { /* MOV Rm, Rn */
  2108                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2109                         load_reg( R_EAX, Rm );
  2110                         store_reg( R_EAX, Rn );
  2112                         break;
  2113                     case 0x4:
  2114                         { /* MOV.B @Rm+, Rn */
  2115                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2116                         load_reg( R_ECX, Rm );
  2117                         MOV_r32_r32( R_ECX, R_EAX );
  2118                         ADD_imm8s_r32( 1, R_EAX );
  2119                         store_reg( R_EAX, Rm );
  2120                         MEM_READ_BYTE( R_ECX, R_EAX );
  2121                         store_reg( R_EAX, Rn );
  2122                         sh4_x86.tstate = TSTATE_NONE;
  2124                         break;
  2125                     case 0x5:
  2126                         { /* MOV.W @Rm+, Rn */
  2127                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2128                         load_reg( R_EAX, Rm );
  2129                         check_ralign16( R_EAX );
  2130                         MOV_r32_r32( R_EAX, R_ECX );
  2131                         ADD_imm8s_r32( 2, R_EAX );
  2132                         store_reg( R_EAX, Rm );
  2133                         MEM_READ_WORD( R_ECX, R_EAX );
  2134                         store_reg( R_EAX, Rn );
  2135                         sh4_x86.tstate = TSTATE_NONE;
  2137                         break;
  2138                     case 0x6:
  2139                         { /* MOV.L @Rm+, Rn */
  2140                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2141                         load_reg( R_EAX, Rm );
  2142                         check_ralign32( R_EAX );
  2143                         MOV_r32_r32( R_EAX, R_ECX );
  2144                         ADD_imm8s_r32( 4, R_EAX );
  2145                         store_reg( R_EAX, Rm );
  2146                         MEM_READ_LONG( R_ECX, R_EAX );
  2147                         store_reg( R_EAX, Rn );
  2148                         sh4_x86.tstate = TSTATE_NONE;
  2150                         break;
  2151                     case 0x7:
  2152                         { /* NOT Rm, Rn */
  2153                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2154                         load_reg( R_EAX, Rm );
  2155                         NOT_r32( R_EAX );
  2156                         store_reg( R_EAX, Rn );
  2157                         sh4_x86.tstate = TSTATE_NONE;
  2159                         break;
  2160                     case 0x8:
  2161                         { /* SWAP.B Rm, Rn */
  2162                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2163                         load_reg( R_EAX, Rm );
  2164                         XCHG_r8_r8( R_AL, R_AH );
  2165                         store_reg( R_EAX, Rn );
  2167                         break;
  2168                     case 0x9:
  2169                         { /* SWAP.W Rm, Rn */
  2170                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2171                         load_reg( R_EAX, Rm );
  2172                         MOV_r32_r32( R_EAX, R_ECX );
  2173                         SHL_imm8_r32( 16, R_ECX );
  2174                         SHR_imm8_r32( 16, R_EAX );
  2175                         OR_r32_r32( R_EAX, R_ECX );
  2176                         store_reg( R_ECX, Rn );
  2177                         sh4_x86.tstate = TSTATE_NONE;
  2179                         break;
  2180                     case 0xA:
  2181                         { /* NEGC Rm, Rn */
  2182                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2183                         load_reg( R_EAX, Rm );
  2184                         XOR_r32_r32( R_ECX, R_ECX );
  2185                         LDC_t();
  2186                         SBB_r32_r32( R_EAX, R_ECX );
  2187                         store_reg( R_ECX, Rn );
  2188                         SETC_t();
  2189                         sh4_x86.tstate = TSTATE_C;
  2191                         break;
  2192                     case 0xB:
  2193                         { /* NEG Rm, Rn */
  2194                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2195                         load_reg( R_EAX, Rm );
  2196                         NEG_r32( R_EAX );
  2197                         store_reg( R_EAX, Rn );
  2198                         sh4_x86.tstate = TSTATE_NONE;
  2200                         break;
  2201                     case 0xC:
  2202                         { /* EXTU.B Rm, Rn */
  2203                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2204                         load_reg( R_EAX, Rm );
  2205                         MOVZX_r8_r32( R_EAX, R_EAX );
  2206                         store_reg( R_EAX, Rn );
  2208                         break;
  2209                     case 0xD:
  2210                         { /* EXTU.W Rm, Rn */
  2211                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2212                         load_reg( R_EAX, Rm );
  2213                         MOVZX_r16_r32( R_EAX, R_EAX );
  2214                         store_reg( R_EAX, Rn );
  2216                         break;
  2217                     case 0xE:
  2218                         { /* EXTS.B Rm, Rn */
  2219                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2220                         load_reg( R_EAX, Rm );
  2221                         MOVSX_r8_r32( R_EAX, R_EAX );
  2222                         store_reg( R_EAX, Rn );
  2224                         break;
  2225                     case 0xF:
  2226                         { /* EXTS.W Rm, Rn */
  2227                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2228                         load_reg( R_EAX, Rm );
  2229                         MOVSX_r16_r32( R_EAX, R_EAX );
  2230                         store_reg( R_EAX, Rn );
  2232                         break;
  2234                 break;
  2235             case 0x7:
  2236                 { /* ADD #imm, Rn */
  2237                 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
  2238                 load_reg( R_EAX, Rn );
  2239                 ADD_imm8s_r32( imm, R_EAX );
  2240                 store_reg( R_EAX, Rn );
  2241                 sh4_x86.tstate = TSTATE_NONE;
  2243                 break;
  2244             case 0x8:
  2245                 switch( (ir&0xF00) >> 8 ) {
  2246                     case 0x0:
  2247                         { /* MOV.B R0, @(disp, Rn) */
  2248                         uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
  2249                         load_reg( R_EAX, 0 );
  2250                         load_reg( R_ECX, Rn );
  2251                         ADD_imm32_r32( disp, R_ECX );
  2252                         MEM_WRITE_BYTE( R_ECX, R_EAX );
  2253                         sh4_x86.tstate = TSTATE_NONE;
  2255                         break;
  2256                     case 0x1:
  2257                         { /* MOV.W R0, @(disp, Rn) */
  2258                         uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
  2259                         load_reg( R_ECX, Rn );
  2260                         load_reg( R_EAX, 0 );
  2261                         ADD_imm32_r32( disp, R_ECX );
  2262                         check_walign16( R_ECX );
  2263                         MEM_WRITE_WORD( R_ECX, R_EAX );
  2264                         sh4_x86.tstate = TSTATE_NONE;
  2266                         break;
  2267                     case 0x4:
  2268                         { /* MOV.B @(disp, Rm), R0 */
  2269                         uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
  2270                         load_reg( R_ECX, Rm );
  2271                         ADD_imm32_r32( disp, R_ECX );
  2272                         MEM_READ_BYTE( R_ECX, R_EAX );
  2273                         store_reg( R_EAX, 0 );
  2274                         sh4_x86.tstate = TSTATE_NONE;
  2276                         break;
  2277                     case 0x5:
  2278                         { /* MOV.W @(disp, Rm), R0 */
  2279                         uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
  2280                         load_reg( R_ECX, Rm );
  2281                         ADD_imm32_r32( disp, R_ECX );
  2282                         check_ralign16( R_ECX );
  2283                         MEM_READ_WORD( R_ECX, R_EAX );
  2284                         store_reg( R_EAX, 0 );
  2285                         sh4_x86.tstate = TSTATE_NONE;
  2287                         break;
  2288                     case 0x8:
  2289                         { /* CMP/EQ #imm, R0 */
  2290                         int32_t imm = SIGNEXT8(ir&0xFF); 
  2291                         load_reg( R_EAX, 0 );
  2292                         CMP_imm8s_r32(imm, R_EAX);
  2293                         SETE_t();
  2294                         sh4_x86.tstate = TSTATE_E;
  2296                         break;
  2297                     case 0x9:
  2298                         { /* BT disp */
  2299                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  2300                         if( sh4_x86.in_delay_slot ) {
  2301                     	SLOTILLEGAL();
  2302                         } else {
  2303                     	JF_rel8( EXIT_BLOCK_SIZE, nottaken );
  2304                     	exit_block( disp + pc + 4, pc+2 );
  2305                     	JMP_TARGET(nottaken);
  2306                     	return 2;
  2309                         break;
  2310                     case 0xB:
  2311                         { /* BF disp */
  2312                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  2313                         if( sh4_x86.in_delay_slot ) {
  2314                     	SLOTILLEGAL();
  2315                         } else {
  2316                     	JT_rel8( EXIT_BLOCK_SIZE, nottaken );
  2317                     	exit_block( disp + pc + 4, pc+2 );
  2318                     	JMP_TARGET(nottaken);
  2319                     	return 2;
  2322                         break;
  2323                     case 0xD:
  2324                         { /* BT/S disp */
  2325                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  2326                         if( sh4_x86.in_delay_slot ) {
  2327                     	SLOTILLEGAL();
  2328                         } else {
  2329                     	sh4_x86.in_delay_slot = TRUE;
  2330                     	if( sh4_x86.tstate == TSTATE_NONE ) {
  2331                     	    CMP_imm8s_sh4r( 1, R_T );
  2332                     	    sh4_x86.tstate = TSTATE_E;
  2334                     	OP(0x0F); OP(0x80+(sh4_x86.tstate^1)); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JE rel32
  2335                     	sh4_translate_instruction(pc+2);
  2336                     	exit_block( disp + pc + 4, pc+4 );
  2337                     	// not taken
  2338                     	*patch = (xlat_output - ((uint8_t *)patch)) - 4;
  2339                     	sh4_translate_instruction(pc+2);
  2340                     	return 4;
  2343                         break;
  2344                     case 0xF:
  2345                         { /* BF/S disp */
  2346                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  2347                         if( sh4_x86.in_delay_slot ) {
  2348                     	SLOTILLEGAL();
  2349                         } else {
  2350                     	sh4_x86.in_delay_slot = TRUE;
  2351                     	if( sh4_x86.tstate == TSTATE_NONE ) {
  2352                     	    CMP_imm8s_sh4r( 1, R_T );
  2353                     	    sh4_x86.tstate = TSTATE_E;
  2355                     	OP(0x0F); OP(0x80+sh4_x86.tstate); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JNE rel32
  2356                     	sh4_translate_instruction(pc+2);
  2357                     	exit_block( disp + pc + 4, pc+4 );
  2358                     	// not taken
  2359                     	*patch = (xlat_output - ((uint8_t *)patch)) - 4;
  2360                     	sh4_translate_instruction(pc+2);
  2361                     	return 4;
  2364                         break;
  2365                     default:
  2366                         UNDEF();
  2367                         break;
  2369                 break;
  2370             case 0x9:
  2371                 { /* MOV.W @(disp, PC), Rn */
  2372                 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1; 
  2373                 if( sh4_x86.in_delay_slot ) {
  2374             	SLOTILLEGAL();
  2375                 } else {
  2376             	// See comments for MOV.L @(disp, PC), Rn
  2377             	uint32_t target = pc + disp + 4;
  2378             	if( IS_IN_ICACHE(target) ) {
  2379             	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
  2380             	    MOV_moff32_EAX( ptr );
  2381             	    MOVSX_r16_r32( R_EAX, R_EAX );
  2382             	} else {
  2383             	    load_imm32( R_ECX, (pc - sh4_x86.block_start_pc) + disp + 4 );
  2384             	    ADD_sh4r_r32( R_PC, R_ECX );
  2385             	    MEM_READ_WORD( R_ECX, R_EAX );
  2386             	    sh4_x86.tstate = TSTATE_NONE;
  2388             	store_reg( R_EAX, Rn );
  2391                 break;
  2392             case 0xA:
  2393                 { /* BRA disp */
  2394                 int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
  2395                 if( sh4_x86.in_delay_slot ) {
  2396             	SLOTILLEGAL();
  2397                 } else {
  2398             	sh4_x86.in_delay_slot = TRUE;
  2399             	sh4_translate_instruction( pc + 2 );
  2400             	exit_block( disp + pc + 4, pc+4 );
  2401             	sh4_x86.branch_taken = TRUE;
  2402             	return 4;
  2405                 break;
  2406             case 0xB:
  2407                 { /* BSR disp */
  2408                 int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
  2409                 if( sh4_x86.in_delay_slot ) {
  2410             	SLOTILLEGAL();
  2411                 } else {
  2412             	load_imm32( R_EAX, pc + 4 );
  2413             	store_spreg( R_EAX, R_PR );
  2414             	sh4_x86.in_delay_slot = TRUE;
  2415             	sh4_translate_instruction( pc + 2 );
  2416             	exit_block( disp + pc + 4, pc+4 );
  2417             	sh4_x86.branch_taken = TRUE;
  2418             	return 4;
  2421                 break;
  2422             case 0xC:
  2423                 switch( (ir&0xF00) >> 8 ) {
  2424                     case 0x0:
  2425                         { /* MOV.B R0, @(disp, GBR) */
  2426                         uint32_t disp = (ir&0xFF); 
  2427                         load_reg( R_EAX, 0 );
  2428                         load_spreg( R_ECX, R_GBR );
  2429                         ADD_imm32_r32( disp, R_ECX );
  2430                         MEM_WRITE_BYTE( R_ECX, R_EAX );
  2431                         sh4_x86.tstate = TSTATE_NONE;
  2433                         break;
  2434                     case 0x1:
  2435                         { /* MOV.W R0, @(disp, GBR) */
  2436                         uint32_t disp = (ir&0xFF)<<1; 
  2437                         load_spreg( R_ECX, R_GBR );
  2438                         load_reg( R_EAX, 0 );
  2439                         ADD_imm32_r32( disp, R_ECX );
  2440                         check_walign16( R_ECX );
  2441                         MEM_WRITE_WORD( R_ECX, R_EAX );
  2442                         sh4_x86.tstate = TSTATE_NONE;
  2444                         break;
  2445                     case 0x2:
  2446                         { /* MOV.L R0, @(disp, GBR) */
  2447                         uint32_t disp = (ir&0xFF)<<2; 
  2448                         load_spreg( R_ECX, R_GBR );
  2449                         load_reg( R_EAX, 0 );
  2450                         ADD_imm32_r32( disp, R_ECX );
  2451                         check_walign32( R_ECX );
  2452                         MEM_WRITE_LONG( R_ECX, R_EAX );
  2453                         sh4_x86.tstate = TSTATE_NONE;
  2455                         break;
  2456                     case 0x3:
  2457                         { /* TRAPA #imm */
  2458                         uint32_t imm = (ir&0xFF); 
  2459                         if( sh4_x86.in_delay_slot ) {
  2460                     	SLOTILLEGAL();
  2461                         } else {
  2462                     	load_imm32( R_ECX, pc+2 );
  2463                     	store_spreg( R_ECX, REG_OFFSET(pc) );
  2464                     	load_imm32( R_EAX, imm );
  2465                     	call_func1( sh4_raise_trap, R_EAX );
  2466                     	sh4_x86.tstate = TSTATE_NONE;
  2467                     	exit_block_pcset(pc);
  2468                     	sh4_x86.branch_taken = TRUE;
  2469                     	return 2;
  2472                         break;
  2473                     case 0x4:
  2474                         { /* MOV.B @(disp, GBR), R0 */
  2475                         uint32_t disp = (ir&0xFF); 
  2476                         load_spreg( R_ECX, R_GBR );
  2477                         ADD_imm32_r32( disp, R_ECX );
  2478                         MEM_READ_BYTE( R_ECX, R_EAX );
  2479                         store_reg( R_EAX, 0 );
  2480                         sh4_x86.tstate = TSTATE_NONE;
  2482                         break;
  2483                     case 0x5:
  2484                         { /* MOV.W @(disp, GBR), R0 */
  2485                         uint32_t disp = (ir&0xFF)<<1; 
  2486                         load_spreg( R_ECX, R_GBR );
  2487                         ADD_imm32_r32( disp, R_ECX );
  2488                         check_ralign16( R_ECX );
  2489                         MEM_READ_WORD( R_ECX, R_EAX );
  2490                         store_reg( R_EAX, 0 );
  2491                         sh4_x86.tstate = TSTATE_NONE;
  2493                         break;
  2494                     case 0x6:
  2495                         { /* MOV.L @(disp, GBR), R0 */
  2496                         uint32_t disp = (ir&0xFF)<<2; 
  2497                         load_spreg( R_ECX, R_GBR );
  2498                         ADD_imm32_r32( disp, R_ECX );
  2499                         check_ralign32( R_ECX );
  2500                         MEM_READ_LONG( R_ECX, R_EAX );
  2501                         store_reg( R_EAX, 0 );
  2502                         sh4_x86.tstate = TSTATE_NONE;
  2504                         break;
  2505                     case 0x7:
  2506                         { /* MOVA @(disp, PC), R0 */
  2507                         uint32_t disp = (ir&0xFF)<<2; 
  2508                         if( sh4_x86.in_delay_slot ) {
  2509                     	SLOTILLEGAL();
  2510                         } else {
  2511                     	load_imm32( R_ECX, (pc - sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
  2512                     	ADD_sh4r_r32( R_PC, R_ECX );
  2513                     	store_reg( R_ECX, 0 );
  2516                         break;
  2517                     case 0x8:
  2518                         { /* TST #imm, R0 */
  2519                         uint32_t imm = (ir&0xFF); 
  2520                         load_reg( R_EAX, 0 );
  2521                         TEST_imm32_r32( imm, R_EAX );
  2522                         SETE_t();
  2523                         sh4_x86.tstate = TSTATE_E;
  2525                         break;
  2526                     case 0x9:
  2527                         { /* AND #imm, R0 */
  2528                         uint32_t imm = (ir&0xFF); 
  2529                         load_reg( R_EAX, 0 );
  2530                         AND_imm32_r32(imm, R_EAX); 
  2531                         store_reg( R_EAX, 0 );
  2532                         sh4_x86.tstate = TSTATE_NONE;
  2534                         break;
  2535                     case 0xA:
  2536                         { /* XOR #imm, R0 */
  2537                         uint32_t imm = (ir&0xFF); 
  2538                         load_reg( R_EAX, 0 );
  2539                         XOR_imm32_r32( imm, R_EAX );
  2540                         store_reg( R_EAX, 0 );
  2541                         sh4_x86.tstate = TSTATE_NONE;
  2543                         break;
  2544                     case 0xB:
  2545                         { /* OR #imm, R0 */
  2546                         uint32_t imm = (ir&0xFF); 
  2547                         load_reg( R_EAX, 0 );
  2548                         OR_imm32_r32(imm, R_EAX);
  2549                         store_reg( R_EAX, 0 );
  2550                         sh4_x86.tstate = TSTATE_NONE;
  2552                         break;
  2553                     case 0xC:
  2554                         { /* TST.B #imm, @(R0, GBR) */
  2555                         uint32_t imm = (ir&0xFF); 
  2556                         load_reg( R_EAX, 0);
  2557                         load_reg( R_ECX, R_GBR);
  2558                         ADD_r32_r32( R_EAX, R_ECX );
  2559                         MEM_READ_BYTE( R_ECX, R_EAX );
  2560                         TEST_imm8_r8( imm, R_AL );
  2561                         SETE_t();
  2562                         sh4_x86.tstate = TSTATE_E;
  2564                         break;
  2565                     case 0xD:
  2566                         { /* AND.B #imm, @(R0, GBR) */
  2567                         uint32_t imm = (ir&0xFF); 
  2568                         load_reg( R_EAX, 0 );
  2569                         load_spreg( R_ECX, R_GBR );
  2570                         ADD_r32_r32( R_EAX, R_ECX );
  2571                         PUSH_realigned_r32(R_ECX);
  2572                         MEM_READ_BYTE( R_ECX, R_EAX );
  2573                         POP_realigned_r32(R_ECX);
  2574                         AND_imm32_r32(imm, R_EAX );
  2575                         MEM_WRITE_BYTE( R_ECX, R_EAX );
  2576                         sh4_x86.tstate = TSTATE_NONE;
  2578                         break;
  2579                     case 0xE:
  2580                         { /* XOR.B #imm, @(R0, GBR) */
  2581                         uint32_t imm = (ir&0xFF); 
  2582                         load_reg( R_EAX, 0 );
  2583                         load_spreg( R_ECX, R_GBR );
  2584                         ADD_r32_r32( R_EAX, R_ECX );
  2585                         PUSH_realigned_r32(R_ECX);
  2586                         MEM_READ_BYTE(R_ECX, R_EAX);
  2587                         POP_realigned_r32(R_ECX);
  2588                         XOR_imm32_r32( imm, R_EAX );
  2589                         MEM_WRITE_BYTE( R_ECX, R_EAX );
  2590                         sh4_x86.tstate = TSTATE_NONE;
  2592                         break;
  2593                     case 0xF:
  2594                         { /* OR.B #imm, @(R0, GBR) */
  2595                         uint32_t imm = (ir&0xFF); 
  2596                         load_reg( R_EAX, 0 );
  2597                         load_spreg( R_ECX, R_GBR );
  2598                         ADD_r32_r32( R_EAX, R_ECX );
  2599                         PUSH_realigned_r32(R_ECX);
  2600                         MEM_READ_BYTE( R_ECX, R_EAX );
  2601                         POP_realigned_r32(R_ECX);
  2602                         OR_imm32_r32(imm, R_EAX );
  2603                         MEM_WRITE_BYTE( R_ECX, R_EAX );
  2604                         sh4_x86.tstate = TSTATE_NONE;
  2606                         break;
  2608                 break;
  2609             case 0xD:
  2610                 { /* MOV.L @(disp, PC), Rn */
  2611                 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<2; 
  2612                 if( sh4_x86.in_delay_slot ) {
  2613             	SLOTILLEGAL();
  2614                 } else {
  2615             	uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
  2616             	if( IS_IN_ICACHE(target) ) {
  2617             	    // If the target address is in the same page as the code, it's
  2618             	    // pretty safe to just ref it directly and circumvent the whole
  2619             	    // memory subsystem. (this is a big performance win)
  2621             	    // FIXME: There's a corner-case that's not handled here when
  2622             	    // the current code-page is in the ITLB but not in the UTLB.
  2623             	    // (should generate a TLB miss although need to test SH4 
  2624             	    // behaviour to confirm) Unlikely to be anyone depending on this
  2625             	    // behaviour though.
  2626             	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
  2627             	    MOV_moff32_EAX( ptr );
  2628             	} else {
  2629             	    // Note: we use sh4r.pc for the calc as we could be running at a
  2630             	    // different virtual address than the translation was done with,
  2631             	    // but we can safely assume that the low bits are the same.
  2632             	    load_imm32( R_ECX, (pc-sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
  2633             	    ADD_sh4r_r32( R_PC, R_ECX );
  2634             	    MEM_READ_LONG( R_ECX, R_EAX );
  2635             	    sh4_x86.tstate = TSTATE_NONE;
  2637             	store_reg( R_EAX, Rn );
  2640                 break;
  2641             case 0xE:
  2642                 { /* MOV #imm, Rn */
  2643                 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
  2644                 load_imm32( R_EAX, imm );
  2645                 store_reg( R_EAX, Rn );
  2647                 break;
  2648             case 0xF:
  2649                 switch( ir&0xF ) {
  2650                     case 0x0:
  2651                         { /* FADD FRm, FRn */
  2652                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2653                         check_fpuen();
  2654                         load_spreg( R_ECX, R_FPSCR );
  2655                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  2656                         load_fr_bank( R_EDX );
  2657                         JNE_rel8(13,doubleprec);
  2658                         push_fr(R_EDX, FRm);
  2659                         push_fr(R_EDX, FRn);
  2660                         FADDP_st(1);
  2661                         pop_fr(R_EDX, FRn);
  2662                         JMP_rel8(11,end);
  2663                         JMP_TARGET(doubleprec);
  2664                         push_dr(R_EDX, FRm);
  2665                         push_dr(R_EDX, FRn);
  2666                         FADDP_st(1);
  2667                         pop_dr(R_EDX, FRn);
  2668                         JMP_TARGET(end);
  2669                         sh4_x86.tstate = TSTATE_NONE;
  2671                         break;
  2672                     case 0x1:
  2673                         { /* FSUB FRm, FRn */
  2674                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2675                         check_fpuen();
  2676                         load_spreg( R_ECX, R_FPSCR );
  2677                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  2678                         load_fr_bank( R_EDX );
  2679                         JNE_rel8(13, doubleprec);
  2680                         push_fr(R_EDX, FRn);
  2681                         push_fr(R_EDX, FRm);
  2682                         FSUBP_st(1);
  2683                         pop_fr(R_EDX, FRn);
  2684                         JMP_rel8(11, end);
  2685                         JMP_TARGET(doubleprec);
  2686                         push_dr(R_EDX, FRn);
  2687                         push_dr(R_EDX, FRm);
  2688                         FSUBP_st(1);
  2689                         pop_dr(R_EDX, FRn);
  2690                         JMP_TARGET(end);
  2691                         sh4_x86.tstate = TSTATE_NONE;
  2693                         break;
  2694                     case 0x2:
  2695                         { /* FMUL FRm, FRn */
  2696                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2697                         check_fpuen();
  2698                         load_spreg( R_ECX, R_FPSCR );
  2699                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  2700                         load_fr_bank( R_EDX );
  2701                         JNE_rel8(13, doubleprec);
  2702                         push_fr(R_EDX, FRm);
  2703                         push_fr(R_EDX, FRn);
  2704                         FMULP_st(1);
  2705                         pop_fr(R_EDX, FRn);
  2706                         JMP_rel8(11, end);
  2707                         JMP_TARGET(doubleprec);
  2708                         push_dr(R_EDX, FRm);
  2709                         push_dr(R_EDX, FRn);
  2710                         FMULP_st(1);
  2711                         pop_dr(R_EDX, FRn);
  2712                         JMP_TARGET(end);
  2713                         sh4_x86.tstate = TSTATE_NONE;
  2715                         break;
  2716                     case 0x3:
  2717                         { /* FDIV FRm, FRn */
  2718                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2719                         check_fpuen();
  2720                         load_spreg( R_ECX, R_FPSCR );
  2721                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  2722                         load_fr_bank( R_EDX );
  2723                         JNE_rel8(13, doubleprec);
  2724                         push_fr(R_EDX, FRn);
  2725                         push_fr(R_EDX, FRm);
  2726                         FDIVP_st(1);
  2727                         pop_fr(R_EDX, FRn);
  2728                         JMP_rel8(11, end);
  2729                         JMP_TARGET(doubleprec);
  2730                         push_dr(R_EDX, FRn);
  2731                         push_dr(R_EDX, FRm);
  2732                         FDIVP_st(1);
  2733                         pop_dr(R_EDX, FRn);
  2734                         JMP_TARGET(end);
  2735                         sh4_x86.tstate = TSTATE_NONE;
  2737                         break;
  2738                     case 0x4:
  2739                         { /* FCMP/EQ FRm, FRn */
  2740                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2741                         check_fpuen();
  2742                         load_spreg( R_ECX, R_FPSCR );
  2743                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  2744                         load_fr_bank( R_EDX );
  2745                         JNE_rel8(8, doubleprec);
  2746                         push_fr(R_EDX, FRm);
  2747                         push_fr(R_EDX, FRn);
  2748                         JMP_rel8(6, end);
  2749                         JMP_TARGET(doubleprec);
  2750                         push_dr(R_EDX, FRm);
  2751                         push_dr(R_EDX, FRn);
  2752                         JMP_TARGET(end);
  2753                         FCOMIP_st(1);
  2754                         SETE_t();
  2755                         FPOP_st();
  2756                         sh4_x86.tstate = TSTATE_NONE;
  2758                         break;
  2759                     case 0x5:
  2760                         { /* FCMP/GT FRm, FRn */
  2761                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2762                         check_fpuen();
  2763                         load_spreg( R_ECX, R_FPSCR );
  2764                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  2765                         load_fr_bank( R_EDX );
  2766                         JNE_rel8(8, doubleprec);
  2767                         push_fr(R_EDX, FRm);
  2768                         push_fr(R_EDX, FRn);
  2769                         JMP_rel8(6, end);
  2770                         JMP_TARGET(doubleprec);
  2771                         push_dr(R_EDX, FRm);
  2772                         push_dr(R_EDX, FRn);
  2773                         JMP_TARGET(end);
  2774                         FCOMIP_st(1);
  2775                         SETA_t();
  2776                         FPOP_st();
  2777                         sh4_x86.tstate = TSTATE_NONE;
  2779                         break;
  2780                     case 0x6:
  2781                         { /* FMOV @(R0, Rm), FRn */
  2782                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2783                         check_fpuen();
  2784                         load_reg( R_ECX, Rm );
  2785                         ADD_sh4r_r32( REG_OFFSET(r[0]), R_ECX );
  2786                         check_ralign32( R_ECX );
  2787                         load_spreg( R_EDX, R_FPSCR );
  2788                         TEST_imm32_r32( FPSCR_SZ, R_EDX );
  2789                         JNE_rel8(8 + MEM_READ_SIZE, doublesize);
  2790                         MEM_READ_LONG( R_ECX, R_EAX );
  2791                         load_fr_bank( R_EDX );
  2792                         store_fr( R_EDX, R_EAX, FRn );
  2793                         if( FRn&1 ) {
  2794                     	JMP_rel8(21 + MEM_READ_DOUBLE_SIZE, end);
  2795                     	JMP_TARGET(doublesize);
  2796                     	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
  2797                     	load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
  2798                     	load_xf_bank( R_EDX );
  2799                     	store_fr( R_EDX, R_EAX, FRn&0x0E );
  2800                     	store_fr( R_EDX, R_ECX, FRn|0x01 );
  2801                     	JMP_TARGET(end);
  2802                         } else {
  2803                     	JMP_rel8(9 + MEM_READ_DOUBLE_SIZE, end);
  2804                     	JMP_TARGET(doublesize);
  2805                     	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
  2806                     	load_fr_bank( R_EDX );
  2807                     	store_fr( R_EDX, R_EAX, FRn&0x0E );
  2808                     	store_fr( R_EDX, R_ECX, FRn|0x01 );
  2809                     	JMP_TARGET(end);
  2811                         sh4_x86.tstate = TSTATE_NONE;
  2813                         break;
  2814                     case 0x7:
  2815                         { /* FMOV FRm, @(R0, Rn) */
  2816                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2817                         check_fpuen();
  2818                         load_reg( R_ECX, Rn );
  2819                         ADD_sh4r_r32( REG_OFFSET(r[0]), R_ECX );
  2820                         check_walign32( R_ECX );
  2821                         load_spreg( R_EDX, R_FPSCR );
  2822                         TEST_imm32_r32( FPSCR_SZ, R_EDX );
  2823                         JNE_rel8(8 + MEM_WRITE_SIZE, doublesize);
  2824                         load_fr_bank( R_EDX );
  2825                         load_fr( R_EDX, R_EAX, FRm );
  2826                         MEM_WRITE_LONG( R_ECX, R_EAX ); // 12
  2827                         if( FRm&1 ) {
  2828                     	JMP_rel8( 18 + MEM_WRITE_DOUBLE_SIZE, end );
  2829                     	JMP_TARGET(doublesize);
  2830                     	load_xf_bank( R_EDX );
  2831                     	load_fr( R_EDX, R_EAX, FRm&0x0E );
  2832                     	load_fr( R_EDX, R_EDX, FRm|0x01 );
  2833                     	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
  2834                     	JMP_TARGET(end);
  2835                         } else {
  2836                     	JMP_rel8( 9 + MEM_WRITE_DOUBLE_SIZE, end );
  2837                     	JMP_TARGET(doublesize);
  2838                     	load_fr_bank( R_EDX );
  2839                     	load_fr( R_EDX, R_EAX, FRm&0x0E );
  2840                     	load_fr( R_EDX, R_EDX, FRm|0x01 );
  2841                     	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
  2842                     	JMP_TARGET(end);
  2844                         sh4_x86.tstate = TSTATE_NONE;
  2846                         break;
  2847                     case 0x8:
  2848                         { /* FMOV @Rm, FRn */
  2849                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2850                         check_fpuen();
  2851                         load_reg( R_ECX, Rm );
  2852                         check_ralign32( R_ECX );
  2853                         load_spreg( R_EDX, R_FPSCR );
  2854                         TEST_imm32_r32( FPSCR_SZ, R_EDX );
  2855                         JNE_rel8(8 + MEM_READ_SIZE, doublesize);
  2856                         MEM_READ_LONG( R_ECX, R_EAX );
  2857                         load_fr_bank( R_EDX );
  2858                         store_fr( R_EDX, R_EAX, FRn );
  2859                         if( FRn&1 ) {
  2860                     	JMP_rel8(21 + MEM_READ_DOUBLE_SIZE, end);
  2861                     	JMP_TARGET(doublesize);
  2862                     	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
  2863                     	load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
  2864                     	load_xf_bank( R_EDX );
  2865                     	store_fr( R_EDX, R_EAX, FRn&0x0E );
  2866                     	store_fr( R_EDX, R_ECX, FRn|0x01 );
  2867                     	JMP_TARGET(end);
  2868                         } else {
  2869                     	JMP_rel8(9 + MEM_READ_DOUBLE_SIZE, end);
  2870                     	JMP_TARGET(doublesize);
  2871                     	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
  2872                     	load_fr_bank( R_EDX );
  2873                     	store_fr( R_EDX, R_EAX, FRn&0x0E );
  2874                     	store_fr( R_EDX, R_ECX, FRn|0x01 );
  2875                     	JMP_TARGET(end);
  2877                         sh4_x86.tstate = TSTATE_NONE;
  2879                         break;
  2880                     case 0x9:
  2881                         { /* FMOV @Rm+, FRn */
  2882                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2883                         check_fpuen();
  2884                         load_reg( R_ECX, Rm );
  2885                         check_ralign32( R_ECX );
  2886                         MOV_r32_r32( R_ECX, R_EAX );
  2887                         load_spreg( R_EDX, R_FPSCR );
  2888                         TEST_imm32_r32( FPSCR_SZ, R_EDX );
  2889                         JNE_rel8(14 + MEM_READ_SIZE, doublesize);
  2890                         ADD_imm8s_r32( 4, R_EAX );
  2891                         store_reg( R_EAX, Rm );
  2892                         MEM_READ_LONG( R_ECX, R_EAX );
  2893                         load_fr_bank( R_EDX );
  2894                         store_fr( R_EDX, R_EAX, FRn );
  2895                         if( FRn&1 ) {
  2896                     	JMP_rel8(27 + MEM_READ_DOUBLE_SIZE, end);
  2897                     	JMP_TARGET(doublesize);
  2898                     	ADD_imm8s_r32( 8, R_EAX );
  2899                     	store_reg(R_EAX, Rm);
  2900                     	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
  2901                     	load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
  2902                     	load_xf_bank( R_EDX );
  2903                     	store_fr( R_EDX, R_EAX, FRn&0x0E );
  2904                     	store_fr( R_EDX, R_ECX, FRn|0x01 );
  2905                     	JMP_TARGET(end);
  2906                         } else {
  2907                     	JMP_rel8(15 + MEM_READ_DOUBLE_SIZE, end);
  2908                     	ADD_imm8s_r32( 8, R_EAX );
  2909                     	store_reg(R_EAX, Rm);
  2910                     	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
  2911                     	load_fr_bank( R_EDX );
  2912                     	store_fr( R_EDX, R_EAX, FRn&0x0E );
  2913                     	store_fr( R_EDX, R_ECX, FRn|0x01 );
  2914                     	JMP_TARGET(end);
  2916                         sh4_x86.tstate = TSTATE_NONE;
  2918                         break;
  2919                     case 0xA:
  2920                         { /* FMOV FRm, @Rn */
  2921                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2922                         check_fpuen();
  2923                         load_reg( R_ECX, Rn );
  2924                         check_walign32( R_ECX );
  2925                         load_spreg( R_EDX, R_FPSCR );
  2926                         TEST_imm32_r32( FPSCR_SZ, R_EDX );
  2927                         JNE_rel8(8 + MEM_WRITE_SIZE, doublesize);
  2928                         load_fr_bank( R_EDX );
  2929                         load_fr( R_EDX, R_EAX, FRm );
  2930                         MEM_WRITE_LONG( R_ECX, R_EAX ); // 12
  2931                         if( FRm&1 ) {
  2932                     	JMP_rel8( 18 + MEM_WRITE_DOUBLE_SIZE, end );
  2933                     	JMP_TARGET(doublesize);
  2934                     	load_xf_bank( R_EDX );
  2935                     	load_fr( R_EDX, R_EAX, FRm&0x0E );
  2936                     	load_fr( R_EDX, R_EDX, FRm|0x01 );
  2937                     	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
  2938                     	JMP_TARGET(end);
  2939                         } else {
  2940                     	JMP_rel8( 9 + MEM_WRITE_DOUBLE_SIZE, end );
  2941                     	JMP_TARGET(doublesize);
  2942                     	load_fr_bank( R_EDX );
  2943                     	load_fr( R_EDX, R_EAX, FRm&0x0E );
  2944                     	load_fr( R_EDX, R_EDX, FRm|0x01 );
  2945                     	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
  2946                     	JMP_TARGET(end);
  2948                         sh4_x86.tstate = TSTATE_NONE;
  2950                         break;
  2951                     case 0xB:
  2952                         { /* FMOV FRm, @-Rn */
  2953                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2954                         check_fpuen();
  2955                         load_reg( R_ECX, Rn );
  2956                         check_walign32( R_ECX );
  2957                         load_spreg( R_EDX, R_FPSCR );
  2958                         TEST_imm32_r32( FPSCR_SZ, R_EDX );
  2959                         JNE_rel8(14 + MEM_WRITE_SIZE, doublesize);
  2960                         load_fr_bank( R_EDX );
  2961                         load_fr( R_EDX, R_EAX, FRm );
  2962                         ADD_imm8s_r32(-4,R_ECX);
  2963                         store_reg( R_ECX, Rn );
  2964                         MEM_WRITE_LONG( R_ECX, R_EAX ); // 12
  2965                         if( FRm&1 ) {
  2966                     	JMP_rel8( 24 + MEM_WRITE_DOUBLE_SIZE, end );
  2967                     	JMP_TARGET(doublesize);
  2968                     	load_xf_bank( R_EDX );
  2969                     	load_fr( R_EDX, R_EAX, FRm&0x0E );
  2970                     	load_fr( R_EDX, R_EDX, FRm|0x01 );
  2971                     	ADD_imm8s_r32(-8,R_ECX);
  2972                     	store_reg( R_ECX, Rn );
  2973                     	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
  2974                     	JMP_TARGET(end);
  2975                         } else {
  2976                     	JMP_rel8( 15 + MEM_WRITE_DOUBLE_SIZE, end );
  2977                     	JMP_TARGET(doublesize);
  2978                     	load_fr_bank( R_EDX );
  2979                     	load_fr( R_EDX, R_EAX, FRm&0x0E );
  2980                     	load_fr( R_EDX, R_EDX, FRm|0x01 );
  2981                     	ADD_imm8s_r32(-8,R_ECX);
  2982                     	store_reg( R_ECX, Rn );
  2983                     	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
  2984                     	JMP_TARGET(end);
  2986                         sh4_x86.tstate = TSTATE_NONE;
  2988                         break;
  2989                     case 0xC:
  2990                         { /* FMOV FRm, FRn */
  2991                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2992                         /* As horrible as this looks, it's actually covering 5 separate cases:
  2993                          * 1. 32-bit fr-to-fr (PR=0)
  2994                          * 2. 64-bit dr-to-dr (PR=1, FRm&1 == 0, FRn&1 == 0 )
  2995                          * 3. 64-bit dr-to-xd (PR=1, FRm&1 == 0, FRn&1 == 1 )
  2996                          * 4. 64-bit xd-to-dr (PR=1, FRm&1 == 1, FRn&1 == 0 )
  2997                          * 5. 64-bit xd-to-xd (PR=1, FRm&1 == 1, FRn&1 == 1 )
  2998                          */
  2999                         check_fpuen();
  3000                         load_spreg( R_ECX, R_FPSCR );
  3001                         load_fr_bank( R_EDX );
  3002                         TEST_imm32_r32( FPSCR_SZ, R_ECX );
  3003                         JNE_rel8(8, doublesize);
  3004                         load_fr( R_EDX, R_EAX, FRm ); // PR=0 branch
  3005                         store_fr( R_EDX, R_EAX, FRn );
  3006                         if( FRm&1 ) {
  3007                     	JMP_rel8(24, end);
  3008                     	JMP_TARGET(doublesize);
  3009                     	load_xf_bank( R_ECX ); 
  3010                     	load_fr( R_ECX, R_EAX, FRm-1 );
  3011                     	if( FRn&1 ) {
  3012                     	    load_fr( R_ECX, R_EDX, FRm );
  3013                     	    store_fr( R_ECX, R_EAX, FRn-1 );
  3014                     	    store_fr( R_ECX, R_EDX, FRn );
  3015                     	} else /* FRn&1 == 0 */ {
  3016                     	    load_fr( R_ECX, R_ECX, FRm );
  3017                     	    store_fr( R_EDX, R_EAX, FRn );
  3018                     	    store_fr( R_EDX, R_ECX, FRn+1 );
  3020                     	JMP_TARGET(end);
  3021                         } else /* FRm&1 == 0 */ {
  3022                     	if( FRn&1 ) {
  3023                     	    JMP_rel8(24, end);
  3024                     	    load_xf_bank( R_ECX );
  3025                     	    load_fr( R_EDX, R_EAX, FRm );
  3026                     	    load_fr( R_EDX, R_EDX, FRm+1 );
  3027                     	    store_fr( R_ECX, R_EAX, FRn-1 );
  3028                     	    store_fr( R_ECX, R_EDX, FRn );
  3029                     	    JMP_TARGET(end);
  3030                     	} else /* FRn&1 == 0 */ {
  3031                     	    JMP_rel8(12, end);
  3032                     	    load_fr( R_EDX, R_EAX, FRm );
  3033                     	    load_fr( R_EDX, R_ECX, FRm+1 );
  3034                     	    store_fr( R_EDX, R_EAX, FRn );
  3035                     	    store_fr( R_EDX, R_ECX, FRn+1 );
  3036                     	    JMP_TARGET(end);
  3039                         sh4_x86.tstate = TSTATE_NONE;
  3041                         break;
  3042                     case 0xD:
  3043                         switch( (ir&0xF0) >> 4 ) {
  3044                             case 0x0:
  3045                                 { /* FSTS FPUL, FRn */
  3046                                 uint32_t FRn = ((ir>>8)&0xF); 
  3047                                 check_fpuen();
  3048                                 load_fr_bank( R_ECX );
  3049                                 load_spreg( R_EAX, R_FPUL );
  3050                                 store_fr( R_ECX, R_EAX, FRn );
  3051                                 sh4_x86.tstate = TSTATE_NONE;
  3053                                 break;
  3054                             case 0x1:
  3055                                 { /* FLDS FRm, FPUL */
  3056                                 uint32_t FRm = ((ir>>8)&0xF); 
  3057                                 check_fpuen();
  3058                                 load_fr_bank( R_ECX );
  3059                                 load_fr( R_ECX, R_EAX, FRm );
  3060                                 store_spreg( R_EAX, R_FPUL );
  3061                                 sh4_x86.tstate = TSTATE_NONE;
  3063                                 break;
  3064                             case 0x2:
  3065                                 { /* FLOAT FPUL, FRn */
  3066                                 uint32_t FRn = ((ir>>8)&0xF); 
  3067                                 check_fpuen();
  3068                                 load_spreg( R_ECX, R_FPSCR );
  3069                                 load_spreg(R_EDX, REG_OFFSET(fr_bank));
  3070                                 FILD_sh4r(R_FPUL);
  3071                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3072                                 JNE_rel8(5, doubleprec);
  3073                                 pop_fr( R_EDX, FRn );
  3074                                 JMP_rel8(3, end);
  3075                                 JMP_TARGET(doubleprec);
  3076                                 pop_dr( R_EDX, FRn );
  3077                                 JMP_TARGET(end);
  3078                                 sh4_x86.tstate = TSTATE_NONE;
  3080                                 break;
  3081                             case 0x3:
  3082                                 { /* FTRC FRm, FPUL */
  3083                                 uint32_t FRm = ((ir>>8)&0xF); 
  3084                                 check_fpuen();
  3085                                 load_spreg( R_ECX, R_FPSCR );
  3086                                 load_fr_bank( R_EDX );
  3087                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3088                                 JNE_rel8(5, doubleprec);
  3089                                 push_fr( R_EDX, FRm );
  3090                                 JMP_rel8(3, doop);
  3091                                 JMP_TARGET(doubleprec);
  3092                                 push_dr( R_EDX, FRm );
  3093                                 JMP_TARGET( doop );
  3094                                 load_imm32( R_ECX, (uint32_t)&max_int );
  3095                                 FILD_r32ind( R_ECX );
  3096                                 FCOMIP_st(1);
  3097                                 JNA_rel8( 32, sat );
  3098                                 load_imm32( R_ECX, (uint32_t)&min_int );  // 5
  3099                                 FILD_r32ind( R_ECX );           // 2
  3100                                 FCOMIP_st(1);                   // 2
  3101                                 JAE_rel8( 21, sat2 );            // 2
  3102                                 load_imm32( R_EAX, (uint32_t)&save_fcw );
  3103                                 FNSTCW_r32ind( R_EAX );
  3104                                 load_imm32( R_EDX, (uint32_t)&trunc_fcw );
  3105                                 FLDCW_r32ind( R_EDX );
  3106                                 FISTP_sh4r(R_FPUL);             // 3
  3107                                 FLDCW_r32ind( R_EAX );
  3108                                 JMP_rel8( 9, end );             // 2
  3110                                 JMP_TARGET(sat);
  3111                                 JMP_TARGET(sat2);
  3112                                 MOV_r32ind_r32( R_ECX, R_ECX ); // 2
  3113                                 store_spreg( R_ECX, R_FPUL );
  3114                                 FPOP_st();
  3115                                 JMP_TARGET(end);
  3116                                 sh4_x86.tstate = TSTATE_NONE;
  3118                                 break;
  3119                             case 0x4:
  3120                                 { /* FNEG FRn */
  3121                                 uint32_t FRn = ((ir>>8)&0xF); 
  3122                                 check_fpuen();
  3123                                 load_spreg( R_ECX, R_FPSCR );
  3124                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3125                                 load_fr_bank( R_EDX );
  3126                                 JNE_rel8(10, doubleprec);
  3127                                 push_fr(R_EDX, FRn);
  3128                                 FCHS_st0();
  3129                                 pop_fr(R_EDX, FRn);
  3130                                 JMP_rel8(8, end);
  3131                                 JMP_TARGET(doubleprec);
  3132                                 push_dr(R_EDX, FRn);
  3133                                 FCHS_st0();
  3134                                 pop_dr(R_EDX, FRn);
  3135                                 JMP_TARGET(end);
  3136                                 sh4_x86.tstate = TSTATE_NONE;
  3138                                 break;
  3139                             case 0x5:
  3140                                 { /* FABS FRn */
  3141                                 uint32_t FRn = ((ir>>8)&0xF); 
  3142                                 check_fpuen();
  3143                                 load_spreg( R_ECX, R_FPSCR );
  3144                                 load_fr_bank( R_EDX );
  3145                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3146                                 JNE_rel8(10, doubleprec);
  3147                                 push_fr(R_EDX, FRn); // 3
  3148                                 FABS_st0(); // 2
  3149                                 pop_fr( R_EDX, FRn); //3
  3150                                 JMP_rel8(8,end); // 2
  3151                                 JMP_TARGET(doubleprec);
  3152                                 push_dr(R_EDX, FRn);
  3153                                 FABS_st0();
  3154                                 pop_dr(R_EDX, FRn);
  3155                                 JMP_TARGET(end);
  3156                                 sh4_x86.tstate = TSTATE_NONE;
  3158                                 break;
  3159                             case 0x6:
  3160                                 { /* FSQRT FRn */
  3161                                 uint32_t FRn = ((ir>>8)&0xF); 
  3162                                 check_fpuen();
  3163                                 load_spreg( R_ECX, R_FPSCR );
  3164                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3165                                 load_fr_bank( R_EDX );
  3166                                 JNE_rel8(10, doubleprec);
  3167                                 push_fr(R_EDX, FRn);
  3168                                 FSQRT_st0();
  3169                                 pop_fr(R_EDX, FRn);
  3170                                 JMP_rel8(8, end);
  3171                                 JMP_TARGET(doubleprec);
  3172                                 push_dr(R_EDX, FRn);
  3173                                 FSQRT_st0();
  3174                                 pop_dr(R_EDX, FRn);
  3175                                 JMP_TARGET(end);
  3176                                 sh4_x86.tstate = TSTATE_NONE;
  3178                                 break;
  3179                             case 0x7:
  3180                                 { /* FSRRA FRn */
  3181                                 uint32_t FRn = ((ir>>8)&0xF); 
  3182                                 check_fpuen();
  3183                                 load_spreg( R_ECX, R_FPSCR );
  3184                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3185                                 load_fr_bank( R_EDX );
  3186                                 JNE_rel8(12, end); // PR=0 only
  3187                                 FLD1_st0();
  3188                                 push_fr(R_EDX, FRn);
  3189                                 FSQRT_st0();
  3190                                 FDIVP_st(1);
  3191                                 pop_fr(R_EDX, FRn);
  3192                                 JMP_TARGET(end);
  3193                                 sh4_x86.tstate = TSTATE_NONE;
  3195                                 break;
  3196                             case 0x8:
  3197                                 { /* FLDI0 FRn */
  3198                                 uint32_t FRn = ((ir>>8)&0xF); 
  3199                                 /* IFF PR=0 */
  3200                                   check_fpuen();
  3201                                   load_spreg( R_ECX, R_FPSCR );
  3202                                   TEST_imm32_r32( FPSCR_PR, R_ECX );
  3203                                   JNE_rel8(8, end);
  3204                                   XOR_r32_r32( R_EAX, R_EAX );
  3205                                   load_spreg( R_ECX, REG_OFFSET(fr_bank) );
  3206                                   store_fr( R_ECX, R_EAX, FRn );
  3207                                   JMP_TARGET(end);
  3208                                   sh4_x86.tstate = TSTATE_NONE;
  3210                                 break;
  3211                             case 0x9:
  3212                                 { /* FLDI1 FRn */
  3213                                 uint32_t FRn = ((ir>>8)&0xF); 
  3214                                 /* IFF PR=0 */
  3215                                   check_fpuen();
  3216                                   load_spreg( R_ECX, R_FPSCR );
  3217                                   TEST_imm32_r32( FPSCR_PR, R_ECX );
  3218                                   JNE_rel8(11, end);
  3219                                   load_imm32(R_EAX, 0x3F800000);
  3220                                   load_spreg( R_ECX, REG_OFFSET(fr_bank) );
  3221                                   store_fr( R_ECX, R_EAX, FRn );
  3222                                   JMP_TARGET(end);
  3223                                   sh4_x86.tstate = TSTATE_NONE;
  3225                                 break;
  3226                             case 0xA:
  3227                                 { /* FCNVSD FPUL, FRn */
  3228                                 uint32_t FRn = ((ir>>8)&0xF); 
  3229                                 check_fpuen();
  3230                                 load_spreg( R_ECX, R_FPSCR );
  3231                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3232                                 JE_rel8(9, end); // only when PR=1
  3233                                 load_fr_bank( R_ECX );
  3234                                 push_fpul();
  3235                                 pop_dr( R_ECX, FRn );
  3236                                 JMP_TARGET(end);
  3237                                 sh4_x86.tstate = TSTATE_NONE;
  3239                                 break;
  3240                             case 0xB:
  3241                                 { /* FCNVDS FRm, FPUL */
  3242                                 uint32_t FRm = ((ir>>8)&0xF); 
  3243                                 check_fpuen();
  3244                                 load_spreg( R_ECX, R_FPSCR );
  3245                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3246                                 JE_rel8(9, end); // only when PR=1
  3247                                 load_fr_bank( R_ECX );
  3248                                 push_dr( R_ECX, FRm );
  3249                                 pop_fpul();
  3250                                 JMP_TARGET(end);
  3251                                 sh4_x86.tstate = TSTATE_NONE;
  3253                                 break;
  3254                             case 0xE:
  3255                                 { /* FIPR FVm, FVn */
  3256                                 uint32_t FVn = ((ir>>10)&0x3); uint32_t FVm = ((ir>>8)&0x3); 
  3257                                 check_fpuen();
  3258                                 load_spreg( R_ECX, R_FPSCR );
  3259                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3260                                 JNE_rel8(44, doubleprec);
  3262                                 load_fr_bank( R_ECX );
  3263                                 push_fr( R_ECX, FVm<<2 );
  3264                                 push_fr( R_ECX, FVn<<2 );
  3265                                 FMULP_st(1);
  3266                                 push_fr( R_ECX, (FVm<<2)+1);
  3267                                 push_fr( R_ECX, (FVn<<2)+1);
  3268                                 FMULP_st(1);
  3269                                 FADDP_st(1);
  3270                                 push_fr( R_ECX, (FVm<<2)+2);
  3271                                 push_fr( R_ECX, (FVn<<2)+2);
  3272                                 FMULP_st(1);
  3273                                 FADDP_st(1);
  3274                                 push_fr( R_ECX, (FVm<<2)+3);
  3275                                 push_fr( R_ECX, (FVn<<2)+3);
  3276                                 FMULP_st(1);
  3277                                 FADDP_st(1);
  3278                                 pop_fr( R_ECX, (FVn<<2)+3);
  3279                                 JMP_TARGET(doubleprec);
  3280                                 sh4_x86.tstate = TSTATE_NONE;
  3282                                 break;
  3283                             case 0xF:
  3284                                 switch( (ir&0x100) >> 8 ) {
  3285                                     case 0x0:
  3286                                         { /* FSCA FPUL, FRn */
  3287                                         uint32_t FRn = ((ir>>9)&0x7)<<1; 
  3288                                         check_fpuen();
  3289                                         load_spreg( R_ECX, R_FPSCR );
  3290                                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  3291                                         JNE_rel8( CALL_FUNC2_SIZE + 9, doubleprec );
  3292                                         load_fr_bank( R_ECX );
  3293                                         ADD_imm8s_r32( (FRn&0x0E)<<2, R_ECX );
  3294                                         load_spreg( R_EDX, R_FPUL );
  3295                                         call_func2( sh4_fsca, R_EDX, R_ECX );
  3296                                         JMP_TARGET(doubleprec);
  3297                                         sh4_x86.tstate = TSTATE_NONE;
  3299                                         break;
  3300                                     case 0x1:
  3301                                         switch( (ir&0x200) >> 9 ) {
  3302                                             case 0x0:
  3303                                                 { /* FTRV XMTRX, FVn */
  3304                                                 uint32_t FVn = ((ir>>10)&0x3); 
  3305                                                 check_fpuen();
  3306                                                 load_spreg( R_ECX, R_FPSCR );
  3307                                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3308                                                 JNE_rel8( 18 + CALL_FUNC2_SIZE, doubleprec );
  3309                                                 load_fr_bank( R_EDX );                 // 3
  3310                                                 ADD_imm8s_r32( FVn<<4, R_EDX );        // 3
  3311                                                 load_xf_bank( R_ECX );                 // 12
  3312                                                 call_func2( sh4_ftrv, R_EDX, R_ECX );  // 12
  3313                                                 JMP_TARGET(doubleprec);
  3314                                                 sh4_x86.tstate = TSTATE_NONE;
  3316                                                 break;
  3317                                             case 0x1:
  3318                                                 switch( (ir&0xC00) >> 10 ) {
  3319                                                     case 0x0:
  3320                                                         { /* FSCHG */
  3321                                                         check_fpuen();
  3322                                                         load_spreg( R_ECX, R_FPSCR );
  3323                                                         XOR_imm32_r32( FPSCR_SZ, R_ECX );
  3324                                                         store_spreg( R_ECX, R_FPSCR );
  3325                                                         sh4_x86.tstate = TSTATE_NONE;
  3327                                                         break;
  3328                                                     case 0x2:
  3329                                                         { /* FRCHG */
  3330                                                         check_fpuen();
  3331                                                         load_spreg( R_ECX, R_FPSCR );
  3332                                                         XOR_imm32_r32( FPSCR_FR, R_ECX );
  3333                                                         store_spreg( R_ECX, R_FPSCR );
  3334                                                         update_fr_bank( R_ECX );
  3335                                                         sh4_x86.tstate = TSTATE_NONE;
  3337                                                         break;
  3338                                                     case 0x3:
  3339                                                         { /* UNDEF */
  3340                                                         if( sh4_x86.in_delay_slot ) {
  3341                                                     	SLOTILLEGAL();
  3342                                                         } else {
  3343                                                     	JMP_exc(EXC_ILLEGAL);
  3344                                                     	return 2;
  3347                                                         break;
  3348                                                     default:
  3349                                                         UNDEF();
  3350                                                         break;
  3352                                                 break;
  3354                                         break;
  3356                                 break;
  3357                             default:
  3358                                 UNDEF();
  3359                                 break;
  3361                         break;
  3362                     case 0xE:
  3363                         { /* FMAC FR0, FRm, FRn */
  3364                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  3365                         check_fpuen();
  3366                         load_spreg( R_ECX, R_FPSCR );
  3367                         load_spreg( R_EDX, REG_OFFSET(fr_bank));
  3368                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  3369                         JNE_rel8(18, doubleprec);
  3370                         push_fr( R_EDX, 0 );
  3371                         push_fr( R_EDX, FRm );
  3372                         FMULP_st(1);
  3373                         push_fr( R_EDX, FRn );
  3374                         FADDP_st(1);
  3375                         pop_fr( R_EDX, FRn );
  3376                         JMP_rel8(16, end);
  3377                         JMP_TARGET(doubleprec);
  3378                         push_dr( R_EDX, 0 );
  3379                         push_dr( R_EDX, FRm );
  3380                         FMULP_st(1);
  3381                         push_dr( R_EDX, FRn );
  3382                         FADDP_st(1);
  3383                         pop_dr( R_EDX, FRn );
  3384                         JMP_TARGET(end);
  3385                         sh4_x86.tstate = TSTATE_NONE;
  3387                         break;
  3388                     default:
  3389                         UNDEF();
  3390                         break;
  3392                 break;
  3395     sh4_x86.in_delay_slot = FALSE;
  3396     return 0;
.