4 * This file defines the internal functions exported/used by the SH4 core,
5 * except for disassembly functions defined in sh4dasm.h
7 * Copyright (c) 2005 Nathan Keynes.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
20 #ifndef lxdream_sh4core_H
21 #define lxdream_sh4core_H 1
23 #include <glib/gtypes.h>
33 /* Breakpoint data structure */
34 extern struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
35 extern int sh4_breakpoint_count;
36 extern sh4ptr_t sh4_main_ram;
37 extern gboolean sh4_starting;
40 * Cached direct pointer to the current instruction page. If AT is on, this
41 * is derived from the ITLB, otherwise this will be the entire memory region.
42 * This is actually a fairly useful optimization, as we can make a lot of
43 * assumptions about the "current page" that we can't make in general for
44 * arbitrary virtual addresses.
46 struct sh4_icache_struct {
47 sh4ptr_t page; // Page pointer (NULL if no page)
48 sh4vma_t page_vma; // virtual address of the page.
49 sh4addr_t page_ppa; // physical address of the page
50 uint32_t mask; // page mask
52 extern struct sh4_icache_struct sh4_icache;
55 * Test if a given address is contained in the current icache entry
57 #define IS_IN_ICACHE(addr) (sh4_icache.page_vma == ((addr) & sh4_icache.mask))
59 * Return a pointer for the given vma, under the assumption that it is
60 * actually contained in the current icache entry.
62 #define GET_ICACHE_PTR(addr) (sh4_icache.page + ((addr)-sh4_icache.page_vma))
64 * Return the physical (external) address for the given vma, assuming that it is
65 * actually contained in the current icache entry.
67 #define GET_ICACHE_PHYS(addr) (sh4_icache.page_ppa + ((addr)-sh4_icache.page_vma))
70 * Return the virtual (vma) address for the first address past the end of the
71 * cache entry. Assumes that there is in fact a current icache entry.
73 #define GET_ICACHE_END() (sh4_icache.page_vma + (~sh4_icache.mask) + 1)
77 * SH4 vm-exit flag - exit the current block but continue (eg exception handling)
79 #define CORE_EXIT_CONTINUE 1
82 * SH4 vm-exit flag - exit the current block and halt immediately (eg fatal error)
84 #define CORE_EXIT_HALT 2
87 * SH4 vm-exit flag - exit the current block and halt immediately for a system
90 #define CORE_EXIT_BREAKPOINT 3
93 * SH4 vm-exit flag - exit the current block and continue after performing a full
94 * system reset (dreamcast_reset())
96 #define CORE_EXIT_SYSRESET 4
99 * SH4 vm-exit flag - exit the current block and continue after the next IRQ.
101 #define CORE_EXIT_SLEEP 5
104 * SH4 vm-exit flag - exit the current block and flush all instruction caches (ie
105 * if address translation has changed)
107 #define CORE_EXIT_FLUSH_ICACHE 6
109 typedef uint32_t (*sh4_run_slice_fn)(uint32_t);
111 /* SH4 module functions */
112 void sh4_init( void );
113 void sh4_reset( void );
114 void sh4_run( void );
115 void sh4_stop( void );
116 uint32_t sh4_run_slice( uint32_t nanos ); // Run single timeslice using emulator
117 uint32_t sh4_xlat_run_slice( uint32_t nanos ); // Run single timeslice using translator
118 uint32_t sh4_sleep_run_slice( uint32_t nanos ); // Run single timeslice while the CPU is asleep
121 * Immediately exit from the currently executing instruction with the given
122 * exit code. This method does not return.
124 void sh4_core_exit( int exit_code );
127 * Exit the current block at the end of the current instruction, flush the
128 * translation cache (completely) and return control to sh4_xlat_run_slice.
130 * As a special case, if the current instruction is actually the last
131 * instruction in the block (ie it's in a delay slot), this function
132 * returns to allow normal completion of the translation block. Otherwise
133 * this function never returns.
135 * Must only be invoked (indirectly) from within translated code.
137 void sh4_flush_icache();
139 /* SH4 peripheral module functions */
140 void CPG_reset( void );
141 void DMAC_reset( void );
142 void DMAC_run_slice( uint32_t );
143 void DMAC_save_state( FILE * );
144 int DMAC_load_state( FILE * );
145 void INTC_reset( void );
146 void INTC_save_state( FILE *f );
147 int INTC_load_state( FILE *f );
148 void MMU_init( void );
149 void MMU_reset( void );
150 void MMU_save_state( FILE *f );
151 int MMU_load_state( FILE *f );
153 void SCIF_reset( void );
154 void SCIF_run_slice( uint32_t );
155 void SCIF_save_state( FILE *f );
156 int SCIF_load_state( FILE *f );
157 void SCIF_update_line_speed(void);
158 void TMU_init( void );
159 void TMU_reset( void );
160 void TMU_run_slice( uint32_t );
161 void TMU_save_state( FILE * );
162 int TMU_load_state( FILE * );
163 void TMU_update_clocks( void );
164 uint32_t sh4_translate_run_slice(uint32_t);
165 uint32_t sh4_emulate_run_slice(uint32_t);
167 /* SH4 instruction support methods */
168 void sh4_sleep( void );
169 void sh4_fsca( uint32_t angle, float *fr );
170 void sh4_ftrv( float *fv );
171 uint32_t sh4_read_sr(void);
172 void sh4_write_sr(uint32_t val);
173 void sh4_write_fpscr(uint32_t val);
174 void sh4_switch_fr_banks(void);
175 void signsat48(void);
176 gboolean sh4_has_page( sh4vma_t vma );
179 #define MMU_VMA_ERROR 0x80000000
181 * Update the sh4_icache structure to contain the specified vma. If the vma
182 * cannot be resolved, an MMU exception is raised and the function returns
183 * FALSE. Otherwise, returns TRUE and updates sh4_icache accordingly.
184 * Note: If the vma resolves to a non-memory area, sh4_icache will be
185 * invalidated, but the function will still return TRUE.
186 * @return FALSE if an MMU exception was raised, otherwise TRUE.
188 gboolean mmu_update_icache( sh4vma_t addr );
191 * Resolve a virtual address through the TLB for a read operation, returning
192 * the resultant P4 or external address. If the resolution fails, the
193 * appropriate MMU exception is raised and the value MMU_VMA_ERROR is returned.
194 * @return An external address (0x00000000-0x1FFFFFFF), a P4 address
195 * (0xE0000000 - 0xFFFFFFFF), or MMU_VMA_ERROR.
197 sh4addr_t mmu_vma_to_phys_read( sh4vma_t addr );
198 sh4addr_t mmu_vma_to_phys_write( sh4vma_t addr );
199 sh4addr_t mmu_vma_to_phys_disasm( sh4vma_t addr );
201 int64_t sh4_read_quad( sh4addr_t addr );
202 int32_t sh4_read_long( sh4addr_t addr );
203 int32_t sh4_read_word( sh4addr_t addr );
204 int32_t sh4_read_byte( sh4addr_t addr );
205 void sh4_write_quad( sh4addr_t addr, uint64_t val );
206 void sh4_write_long( sh4addr_t addr, uint32_t val );
207 void sh4_write_word( sh4addr_t addr, uint32_t val );
208 void sh4_write_byte( sh4addr_t addr, uint32_t val );
209 int32_t sh4_read_phys_word( sh4addr_t addr );
210 gboolean sh4_flush_store_queue( sh4addr_t addr );
213 #define EXC_POWER_RESET 0x000 /* reset vector */
214 #define EXC_MANUAL_RESET 0x020 /* reset vector */
215 #define EXC_TLB_MISS_READ 0x040 /* TLB vector */
216 #define EXC_TLB_MISS_WRITE 0x060 /* TLB vector */
217 #define EXC_INIT_PAGE_WRITE 0x080
218 #define EXC_TLB_PROT_READ 0x0A0
219 #define EXC_TLB_PROT_WRITE 0x0C0
220 #define EXC_DATA_ADDR_READ 0x0E0
221 #define EXC_DATA_ADDR_WRITE 0x100
222 #define EXC_TLB_MULTI_HIT 0x140
223 #define EXC_SLOT_ILLEGAL 0x1A0
224 #define EXC_ILLEGAL 0x180
225 #define EXC_TRAP 0x160
226 #define EXC_FPU_DISABLED 0x800
227 #define EXC_SLOT_FPU_DISABLED 0x820
229 #define EXV_EXCEPTION 0x100 /* General exception vector */
230 #define EXV_TLBMISS 0x400 /* TLB-miss exception vector */
231 #define EXV_INTERRUPT 0x600 /* External interrupt vector */
233 gboolean sh4_raise_exception( int );
234 gboolean sh4_raise_reset( int );
235 gboolean sh4_raise_trap( int );
236 gboolean sh4_raise_slot_exception( int, int );
237 gboolean sh4_raise_tlb_exception( int );
238 void sh4_accept_interrupt( void );
240 #define SIGNEXT4(n) ((((int32_t)(n))<<28)>>28)
241 #define SIGNEXT8(n) ((int32_t)((int8_t)(n)))
242 #define SIGNEXT12(n) ((((int32_t)(n))<<20)>>20)
243 #define SIGNEXT16(n) ((int32_t)((int16_t)(n)))
244 #define SIGNEXT32(n) ((int64_t)((int32_t)(n)))
245 #define SIGNEXT48(n) ((((int64_t)(n))<<16)>>16)
246 #define ZEROEXT32(n) ((int64_t)((uint64_t)((uint32_t)(n))))
248 /* Status Register (SR) bits */
249 #define SR_MD 0x40000000 /* Processor mode ( User=0, Privileged=1 ) */
250 #define SR_RB 0x20000000 /* Register bank (priviledged mode only) */
251 #define SR_BL 0x10000000 /* Exception/interupt block (1 = masked) */
252 #define SR_FD 0x00008000 /* FPU disable */
253 #define SR_M 0x00000200
254 #define SR_Q 0x00000100
255 #define SR_IMASK 0x000000F0 /* Interrupt mask level */
256 #define SR_S 0x00000002 /* Saturation operation for MAC instructions */
257 #define SR_T 0x00000001 /* True/false or carry/borrow */
258 #define SR_MASK 0x700083F3
259 #define SR_MQSTMASK 0xFFFFFCFC /* Mask to clear the flags we're keeping separately */
260 #define SR_MDRB 0x60000000 /* MD+RB mask for convenience */
262 #define IS_SH4_PRIVMODE() (sh4r.sr&SR_MD)
263 #define SH4_INTMASK() ((sh4r.sr&SR_IMASK)>>4)
264 #define SH4_EVENT_PENDING() (sh4r.event_pending <= sh4r.slice_cycle && !sh4r.in_delay_slot)
266 #define FPSCR_FR 0x00200000 /* FPU register bank */
267 #define FPSCR_SZ 0x00100000 /* FPU transfer size (0=32 bits, 1=64 bits) */
268 #define FPSCR_PR 0x00080000 /* Precision (0=32 bites, 1=64 bits) */
269 #define FPSCR_DN 0x00040000 /* Denormalization mode (1 = treat as 0) */
270 #define FPSCR_CAUSE 0x0003F000
271 #define FPSCR_ENABLE 0x00000F80
272 #define FPSCR_FLAG 0x0000007C
273 #define FPSCR_RM 0x00000003 /* Rounding mode (0=nearest, 1=to zero) */
275 #define IS_FPU_DOUBLEPREC() (sh4r.fpscr&FPSCR_PR)
276 #define IS_FPU_DOUBLESIZE() (sh4r.fpscr&FPSCR_SZ)
277 #define IS_FPU_ENABLED() ((sh4r.sr&SR_FD)==0)
279 #define FR(x) sh4r.fr[0][(x)^1]
280 #define DRF(x) *((double *)&sh4r.fr[0][(x)<<1])
281 #define XF(x) sh4r.fr[1][(x)^1]
282 #define XDR(x) *((double *)&sh4r.fr[1][(x)<<1])
283 #define DRb(x,b) *((double *)&sh4r.fr[b][(x)<<1])
284 #define DR(x) *((double *)&sh4r.fr[x&1][x&0x0E])
285 #define FPULf (sh4r.fpul.f)
286 #define FPULi (sh4r.fpul.i)
288 #define SH4_WRITE_STORE_QUEUE(addr,val) sh4r.store_queue[(addr>>2)&0xF] = val;
294 #endif /* !lxdream_sh4core_H */
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