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lxdream.org :: lxdream/src/pvr2/pvr2.c
lxdream 0.9.1
released Jun 29
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filename src/pvr2/pvr2.c
changeset 1067:d3c00ffccfcd
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author nkeynes
date Sun Jul 05 13:54:48 2009 +1000 (12 years ago)
permissions -rw-r--r--
last change No-op merge lxdream-mem to tip to remove head (Long since merged in
actuality)
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     1 /**
     2  * $Id$
     3  *
     4  * PVR2 (Video) Core module implementation and MMIO registers.
     5  *
     6  * Copyright (c) 2005 Nathan Keynes.
     7  *
     8  * This program is free software; you can redistribute it and/or modify
     9  * it under the terms of the GNU General Public License as published by
    10  * the Free Software Foundation; either version 2 of the License, or
    11  * (at your option) any later version.
    12  *
    13  * This program is distributed in the hope that it will be useful,
    14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    16  * GNU General Public License for more details.
    17  */
    18 #define MODULE pvr2_module
    20 #include <assert.h>
    21 #include "dream.h"
    22 #include "eventq.h"
    23 #include "display.h"
    24 #include "mem.h"
    25 #include "asic.h"
    26 #include "clock.h"
    27 #include "pvr2/pvr2.h"
    28 #include "pvr2/pvr2mmio.h"
    29 #include "pvr2/scene.h"
    30 #include "sh4/sh4.h"
    31 #define MMIO_IMPL
    32 #include "pvr2/pvr2mmio.h"
    34 #define MAX_RENDER_BUFFERS 4
    36 #define HPOS_PER_FRAME 0
    37 #define HPOS_PER_LINECOUNT 1
    39 static void pvr2_init( void );
    40 static void pvr2_reset( void );
    41 static uint32_t pvr2_run_slice( uint32_t );
    42 static void pvr2_save_state( FILE *f );
    43 static int pvr2_load_state( FILE *f );
    44 static void pvr2_update_raster_posn( uint32_t nanosecs );
    45 static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int line_time_ns );
    46 static render_buffer_t pvr2_get_render_buffer( frame_buffer_t frame );
    47 static render_buffer_t pvr2_next_render_buffer( );
    48 static render_buffer_t pvr2_frame_buffer_to_render_buffer( frame_buffer_t frame );
    49 uint32_t pvr2_get_sync_status();
    51 void pvr2_display_frame( void );
    53 static int output_colour_formats[] = { COLFMT_BGRA1555, COLFMT_RGB565, COLFMT_BGR888, COLFMT_BGRA8888 };
    54 static int render_colour_formats[8] = {
    55         COLFMT_BGRA1555, COLFMT_RGB565, COLFMT_BGRA4444, COLFMT_BGRA1555,
    56         COLFMT_BGR888, COLFMT_BGRA8888, COLFMT_BGRA8888, COLFMT_BGRA4444 };
    59 struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, pvr2_reset, NULL, 
    60         pvr2_run_slice, NULL,
    61         pvr2_save_state, pvr2_load_state };
    64 display_driver_t display_driver = NULL;
    66 struct pvr2_state {
    67     uint32_t frame_count;
    68     uint32_t line_count;
    69     uint32_t line_remainder;
    70     uint32_t cycles_run; /* Cycles already executed prior to main time slice */
    71     uint32_t irq_hpos_line;
    72     uint32_t irq_hpos_line_count;
    73     uint32_t irq_hpos_mode;
    74     uint32_t irq_hpos_time_ns; /* Time within the line */
    75     uint32_t irq_vpos1;
    76     uint32_t irq_vpos2;
    77     uint32_t odd_even_field; /* 1 = odd, 0 = even */
    78     int32_t palette_changed; /* TRUE if palette has changed since last render */
    79     /* timing */
    80     uint32_t dot_clock;
    81     uint32_t total_lines;
    82     uint32_t line_size;
    83     uint32_t line_time_ns;
    84     uint32_t vsync_lines;
    85     uint32_t hsync_width_ns;
    86     uint32_t front_porch_ns;
    87     uint32_t back_porch_ns;
    88     uint32_t retrace_start_line;
    89     uint32_t retrace_end_line;
    90     int32_t interlaced;
    91 } pvr2_state;
    93 static gchar *save_next_render_filename;
    94 static render_buffer_t render_buffers[MAX_RENDER_BUFFERS];
    95 static uint32_t render_buffer_count = 0;
    96 static render_buffer_t displayed_render_buffer = NULL;
    97 static uint32_t displayed_border_colour = 0;
    99 /**
   100  * Event handler for the hpos callback
   101  */
   102 static void pvr2_hpos_callback( int eventid ) {
   103     asic_event( eventid );
   104     pvr2_update_raster_posn(sh4r.slice_cycle);
   105     if( pvr2_state.irq_hpos_mode == HPOS_PER_LINECOUNT ) {
   106         pvr2_state.irq_hpos_line += pvr2_state.irq_hpos_line_count;
   107         while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {
   108             pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);
   109         }
   110     }
   111     pvr2_schedule_scanline_event( eventid, pvr2_state.irq_hpos_line, 1, 
   112                                   pvr2_state.irq_hpos_time_ns );
   113 }
   115 /**
   116  * Event handler for the scanline callbacks. Fires the corresponding
   117  * ASIC event, and resets the timer for the next field.
   118  */
   119 static void pvr2_scanline_callback( int eventid ) 
   120 {
   121     asic_event( eventid );
   122     pvr2_update_raster_posn(sh4r.slice_cycle);
   123     if( eventid == EVENT_SCANLINE1 ) {
   124         pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos1, 1, 0 );
   125     } else {
   126         pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos2, 1, 0 );
   127     }
   128 }
   130 static void pvr2_gunpos_callback( int eventid ) 
   131 {
   132     pvr2_update_raster_posn(sh4r.slice_cycle);
   133     int hpos = pvr2_state.line_remainder * pvr2_state.dot_clock / 1000000;
   134     MMIO_WRITE( PVR2, GUNPOS, ((pvr2_state.line_count<<16)|(hpos&0x3FF)) );
   135     asic_event( EVENT_MAPLE_DMA );
   136 }
   138 static void pvr2_init( void )
   139 {
   140     int i;
   141     register_io_region( &mmio_region_PVR2 );
   142     register_io_region( &mmio_region_PVR2PAL );
   143     register_event_callback( EVENT_HPOS, pvr2_hpos_callback );
   144     register_event_callback( EVENT_SCANLINE1, pvr2_scanline_callback );
   145     register_event_callback( EVENT_SCANLINE2, pvr2_scanline_callback );
   146     register_event_callback( EVENT_GUNPOS, pvr2_gunpos_callback );
   147     texcache_init();
   148     pvr2_reset();
   149     pvr2_ta_reset();
   150     save_next_render_filename = NULL;
   151     for( i=0; i<MAX_RENDER_BUFFERS; i++ ) {
   152         render_buffers[i] = NULL;
   153     }
   154     render_buffer_count = 0;
   155     displayed_render_buffer = NULL;
   156     displayed_border_colour = 0;
   157 }
   159 static void pvr2_reset( void )
   160 {
   161     int i;
   162     pvr2_state.line_count = 0;
   163     pvr2_state.line_remainder = 0;
   164     pvr2_state.cycles_run = 0;
   165     pvr2_state.irq_vpos1 = 0;
   166     pvr2_state.irq_vpos2 = 0;
   167     pvr2_state.dot_clock = PVR2_DOT_CLOCK;
   168     pvr2_state.back_porch_ns = 4000;
   169     pvr2_state.palette_changed = FALSE;
   170     mmio_region_PVR2_write( DISP_TOTAL, 0x0270035F );
   171     mmio_region_PVR2_write( DISP_SYNCTIME, 0x07D6A53F );
   172     mmio_region_PVR2_write( YUV_ADDR, 0 );
   173     mmio_region_PVR2_write( YUV_CFG, 0 );
   175     pvr2_ta_init();
   176     texcache_flush();
   177     if( display_driver ) {
   178         display_driver->display_blank(0);
   179         for( i=0; i<render_buffer_count; i++ ) {
   180             display_driver->destroy_render_buffer(render_buffers[i]);
   181             render_buffers[i] = NULL;
   182         }
   183         render_buffer_count = 0;
   184     }
   185 }
   187 void pvr2_save_render_buffer( FILE *f, render_buffer_t buffer )
   188 {
   189     struct frame_buffer fbuf;
   191     fbuf.width = buffer->width;
   192     fbuf.height = buffer->height;
   193     fbuf.rowstride = fbuf.width*3;
   194     fbuf.colour_format = COLFMT_BGR888;
   195     fbuf.inverted = buffer->inverted;
   196     fbuf.data = g_malloc0( buffer->width * buffer->height * 3 );
   198     display_driver->read_render_buffer( fbuf.data, buffer, fbuf.rowstride, COLFMT_BGR888 );
   199     write_png_to_stream( f, &fbuf );
   200     g_free( fbuf.data );
   202     fwrite( &buffer->rowstride, sizeof(buffer->rowstride), 1, f );
   203     fwrite( &buffer->colour_format, sizeof(buffer->colour_format), 1, f );
   204     fwrite( &buffer->address, sizeof(buffer->address), 1, f );
   205     fwrite( &buffer->scale, sizeof(buffer->scale), 1, f );
   206     int32_t flushed = (int32_t)buffer->flushed; // Force to 32-bits for save-file consistency
   207     fwrite( &flushed, sizeof(flushed), 1, f );
   209 }
   211 render_buffer_t pvr2_load_render_buffer( FILE *f, gboolean *status )
   212 {
   213     frame_buffer_t frame = read_png_from_stream( f );
   214     if( frame == NULL ) {
   215         *status = FALSE;
   216         return NULL;
   217     }
   218     *status = TRUE;
   220     render_buffer_t buffer = pvr2_frame_buffer_to_render_buffer(frame);
   221     if( buffer != NULL ) {
   222         int32_t flushed;
   223         fread( &buffer->rowstride, sizeof(buffer->rowstride), 1, f );
   224         fread( &buffer->colour_format, sizeof(buffer->colour_format), 1, f );
   225         fread( &buffer->address, sizeof(buffer->address), 1, f );
   226         fread( &buffer->scale, sizeof(buffer->scale), 1, f );
   227         fread( &flushed, sizeof(flushed), 1, f );
   228         buffer->flushed = (gboolean)flushed;
   229     } else {
   230         fseek( f, sizeof(buffer->rowstride)+sizeof(buffer->colour_format)+
   231                 sizeof(buffer->address)+sizeof(buffer->scale)+
   232                 sizeof(int32_t), SEEK_CUR );
   233     }
   234     return buffer;
   235 }
   240 void pvr2_save_render_buffers( FILE *f )
   241 {
   242     int i;
   243     uint32_t has_frontbuffer;
   244     fwrite( &render_buffer_count, sizeof(render_buffer_count), 1, f );
   245     if( displayed_render_buffer != NULL ) {
   246         has_frontbuffer = 1;
   247         fwrite( &has_frontbuffer, sizeof(has_frontbuffer), 1, f );
   248         pvr2_save_render_buffer( f, displayed_render_buffer );
   249     } else {
   250         has_frontbuffer = 0;
   251         fwrite( &has_frontbuffer, sizeof(has_frontbuffer), 1, f );
   252     }
   254     for( i=0; i<render_buffer_count; i++ ) {
   255         if( render_buffers[i] != displayed_render_buffer && render_buffers[i] != NULL ) {
   256             pvr2_save_render_buffer( f, render_buffers[i] );
   257         }
   258     }
   259 }
   261 gboolean pvr2_load_render_buffers( FILE *f )
   262 {
   263     uint32_t count, has_frontbuffer;
   264     gboolean loadok;
   265     int i;
   267     fread( &count, sizeof(count), 1, f );
   268     if( count > MAX_RENDER_BUFFERS ) {
   269         return FALSE;
   270     }
   271     fread( &has_frontbuffer, sizeof(has_frontbuffer), 1, f );
   272     for( i=0; i<render_buffer_count; i++ ) {
   273         display_driver->destroy_render_buffer(render_buffers[i]);
   274         render_buffers[i] = NULL;
   275     }
   276     render_buffer_count = 0;
   278     if( has_frontbuffer ) {
   279         displayed_render_buffer = pvr2_load_render_buffer(f, &loadok);
   280         if( displayed_render_buffer != NULL )
   281             display_driver->display_render_buffer( displayed_render_buffer );
   282         else if( !loadok )
   283             return FALSE;
   284         count--;
   285     }
   287     for( i=0; i<count; i++ ) {
   288         pvr2_load_render_buffer( f, &loadok );
   289         if( !loadok )
   290         	return FALSE;
   291     }
   292     return TRUE;
   293 }
   296 static void pvr2_save_state( FILE *f )
   297 {
   298     pvr2_save_render_buffers( f );
   299     fwrite( &pvr2_state, sizeof(pvr2_state), 1, f );
   300     pvr2_ta_save_state( f );
   301     pvr2_yuv_save_state( f );
   302 }
   304 static int pvr2_load_state( FILE *f )
   305 {
   306     if( !pvr2_load_render_buffers(f) )
   307         return 1;
   308     if( fread( &pvr2_state, sizeof(pvr2_state), 1, f ) != 1 )
   309         return 1;
   310     if( pvr2_ta_load_state(f) ) {
   311         return 1;
   312     }
   313     return pvr2_yuv_load_state(f);
   314 }
   316 /**
   317  * Update the current raster position to the given number of nanoseconds,
   318  * relative to the last time slice. (ie the raster will be adjusted forward
   319  * by nanosecs - nanosecs_already_run_this_timeslice)
   320  */
   321 static void pvr2_update_raster_posn( uint32_t nanosecs )
   322 {
   323     uint32_t old_line_count = pvr2_state.line_count;
   324     if( pvr2_state.line_time_ns == 0 ) {
   325         return; /* do nothing */
   326     }
   327     pvr2_state.line_remainder += (nanosecs - pvr2_state.cycles_run);
   328     pvr2_state.cycles_run = nanosecs;
   329     while( pvr2_state.line_remainder >= pvr2_state.line_time_ns ) {
   330         pvr2_state.line_count ++;
   331         pvr2_state.line_remainder -= pvr2_state.line_time_ns;
   332     }
   334     if( pvr2_state.line_count >= pvr2_state.total_lines ) {
   335         pvr2_state.line_count -= pvr2_state.total_lines;
   336         if( pvr2_state.interlaced ) {
   337             pvr2_state.odd_even_field = !pvr2_state.odd_even_field;
   338         }
   339     }
   340     if( pvr2_state.line_count >= pvr2_state.retrace_end_line &&
   341             (old_line_count < pvr2_state.retrace_end_line ||
   342                     old_line_count > pvr2_state.line_count) ) {
   343         pvr2_state.frame_count++;
   344         pvr2_display_frame();
   345     }
   346 }
   348 static uint32_t pvr2_run_slice( uint32_t nanosecs ) 
   349 {
   350     pvr2_update_raster_posn( nanosecs );
   351     pvr2_state.cycles_run = 0;
   352     return nanosecs;
   353 }
   355 int pvr2_get_frame_count() 
   356 {
   357     return pvr2_state.frame_count;
   358 }
   360 void pvr2_redraw_display()
   361 {
   362     if( display_driver != NULL ) {
   363         if( displayed_render_buffer == NULL ) {
   364             display_driver->display_blank(displayed_border_colour);
   365         } else {
   366             display_driver->display_render_buffer(displayed_render_buffer);
   367         }
   368     }
   369 }
   371 gboolean pvr2_save_next_scene( const gchar *filename )
   372 {
   373     if( save_next_render_filename != NULL ) {
   374         g_free( save_next_render_filename );
   375     } 
   376     save_next_render_filename = g_strdup(filename);
   377     return TRUE;
   378 }
   382 /**
   383  * Display the next frame, copying the current contents of video ram to
   384  * the window. If the video configuration has changed, first recompute the
   385  * new frame size/depth.
   386  */
   387 void pvr2_display_frame( void )
   388 {
   389     int dispmode = MMIO_READ( PVR2, DISP_MODE );
   390     int vidcfg = MMIO_READ( PVR2, DISP_SYNCCFG );
   391     gboolean bEnabled = (dispmode & DISPMODE_ENABLE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE;
   393     if( display_driver == NULL ) {
   394         return; /* can't really do anything much */
   395     } else if( !bEnabled ) {
   396         /* Output disabled == black */
   397         displayed_render_buffer = NULL;
   398         displayed_border_colour = 0;
   399         display_driver->display_blank( 0 ); 
   400     } else if( MMIO_READ( PVR2, DISP_CFG2 ) & 0x08 ) { 
   401         /* Enabled but blanked - border colour */
   402         displayed_border_colour = MMIO_READ( PVR2, DISP_BORDER );
   403         displayed_render_buffer = NULL;
   404         display_driver->display_blank( displayed_border_colour );
   405     } else {
   406         /* Real output - determine dimensions etc */
   407         struct frame_buffer fbuf;
   408         uint32_t dispsize = MMIO_READ( PVR2, DISP_SIZE );
   409         int vid_stride = (((dispsize & DISPSIZE_MODULO) >> 20) - 1);
   410         int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
   412         fbuf.colour_format = output_colour_formats[(dispmode & DISPMODE_COLFMT) >> 2];
   413         fbuf.width = (vid_ppl << 2) / colour_formats[fbuf.colour_format].bpp;
   414         fbuf.height = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
   415         fbuf.size = (vid_ppl << 2) * fbuf.height;
   416         fbuf.rowstride = (vid_ppl + vid_stride) << 2;
   418         /* Determine the field to display, and deinterlace if possible */
   419         if( pvr2_state.interlaced ) {
   420             if( vid_ppl == vid_stride ) { /* Magic deinterlace */
   421                 fbuf.height = fbuf.height << 1;
   422                 fbuf.rowstride = vid_ppl << 2;
   423                 fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
   424             } else { 
   425                 /* Just display the field as is, folks. This is slightly tricky -
   426                  * we pick the field based on which frame is about to come through,
   427                  * which may not be the same as the odd_even_field.
   428                  */
   429                 gboolean oddfield = pvr2_state.odd_even_field;
   430                 if( pvr2_state.line_count >= pvr2_state.retrace_start_line ) {
   431                     oddfield = !oddfield;
   432                 }
   433                 if( oddfield ) {
   434                     fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
   435                 } else {
   436                     fbuf.address = MMIO_READ( PVR2, DISP_ADDR2 );
   437                 }
   438             }
   439         } else {
   440             fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
   441         }
   442         fbuf.address = (fbuf.address & 0x00FFFFFF) + PVR2_RAM_BASE;
   443         fbuf.inverted = FALSE;
   444         fbuf.data = pvr2_main_ram + (fbuf.address&0x00FFFFFF);
   446         render_buffer_t rbuf = pvr2_get_render_buffer( &fbuf );
   447         if( rbuf == NULL ) {
   448             rbuf = pvr2_frame_buffer_to_render_buffer( &fbuf );
   449         }
   450         displayed_render_buffer = rbuf;
   451         if( rbuf != NULL ) {
   452             display_driver->display_render_buffer( rbuf );
   453         }
   454     }
   455 }
   457 /**
   458  * This has to handle every single register individually as they all get masked 
   459  * off differently (and its easier to do it at write time)
   460  */
   461 MMIO_REGION_WRITE_FN( PVR2, reg, val )
   462 {
   463     reg &= 0xFFF;
   464     if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
   465         MMIO_WRITE( PVR2, reg, val );
   466         return;
   467     }
   469     switch(reg) {
   470     case PVRID:
   471     case PVRVER:
   472     case GUNPOS: /* Read only registers */
   473         break;
   474     case PVRRESET:
   475         val &= 0x00000007; /* Do stuff? */
   476         MMIO_WRITE( PVR2, reg, val );
   477         break;
   478     case RENDER_START: /* Don't really care what value */
   479         if( save_next_render_filename != NULL ) {
   480             if( pvr2_render_save_scene(save_next_render_filename) == 0 ) {
   481                 INFO( "Saved scene to %s", save_next_render_filename);
   482             }
   483             g_free( save_next_render_filename );
   484             save_next_render_filename = NULL;
   485         }
   486         pvr2_scene_read();
   487         render_buffer_t buffer = pvr2_next_render_buffer();
   488         if( buffer != NULL ) {
   489             pvr2_scene_render( buffer );
   490             if( buffer->address < PVR2_RAM_BASE ) {
   491                 // Flush immediately - optimize this later. Otherwise this gets
   492                 // complicated very quickly trying to second-guess how it's
   493                 // going to be used as a texture.
   494                 pvr2_finish_render_buffer( buffer );
   495                 pvr2_render_buffer_copy_to_sh4( buffer );
   496             }
   497         }
   498         asic_event( EVENT_PVR_RENDER_DONE );
   499         break;
   500     case RENDER_POLYBASE:
   501         MMIO_WRITE( PVR2, reg, val&0x00F00000 );
   502         break;
   503     case RENDER_TSPCFG:
   504         MMIO_WRITE( PVR2, reg, val&0x00010101 );
   505         break;
   506     case DISP_BORDER:
   507         MMIO_WRITE( PVR2, reg, val&0x01FFFFFF );
   508         break;
   509     case DISP_MODE:
   510         MMIO_WRITE( PVR2, reg, val&0x00FFFF7F );
   511         break;
   512     case RENDER_MODE:
   513         MMIO_WRITE( PVR2, reg, val&0x00FFFF0F );
   514         break;
   515     case RENDER_SIZE:
   516         MMIO_WRITE( PVR2, reg, val&0x000001FF );
   517         break;
   518     case DISP_ADDR1:
   519         val &= 0x00FFFFFC;
   520         MMIO_WRITE( PVR2, reg, val );
   521         pvr2_update_raster_posn(sh4r.slice_cycle);
   522         break;
   523     case DISP_ADDR2:
   524         MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
   525         pvr2_update_raster_posn(sh4r.slice_cycle);
   526         break;
   527     case DISP_SIZE:
   528         MMIO_WRITE( PVR2, reg, val&0x3FFFFFFF );
   529         break;
   530     case RENDER_ADDR1:
   531     case RENDER_ADDR2:
   532         MMIO_WRITE( PVR2, reg, val&0x01FFFFFC );
   533         break;
   534     case RENDER_HCLIP:
   535         MMIO_WRITE( PVR2, reg, val&0x07FF07FF );
   536         break;
   537     case RENDER_VCLIP:
   538         MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
   539         break;
   540     case DISP_HPOSIRQ:
   541         MMIO_WRITE( PVR2, reg, val&0x03FF33FF );
   542         pvr2_state.irq_hpos_line = val & 0x03FF;
   543         pvr2_state.irq_hpos_time_ns = 2000000*((val>>16)&0x03FF)/pvr2_state.dot_clock;
   544         pvr2_state.irq_hpos_mode = (val >> 12) & 0x03;
   545         switch( pvr2_state.irq_hpos_mode ) {
   546         case 3: /* Reserved - treat as 0 */
   547         case 0: /* Once per frame at specified line */
   548             pvr2_state.irq_hpos_mode = HPOS_PER_FRAME;
   549             break;
   550         case 2: /* Once per line - as per-line-count */
   551             pvr2_state.irq_hpos_line = 1;
   552             pvr2_state.irq_hpos_mode = 1;
   553         case 1: /* Once per N lines */
   554             pvr2_state.irq_hpos_line_count = pvr2_state.irq_hpos_line;
   555             pvr2_state.irq_hpos_line = (pvr2_state.line_count >> 1) + 
   556             pvr2_state.irq_hpos_line_count;
   557             while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {
   558                 pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);
   559             }
   560             pvr2_state.irq_hpos_mode = HPOS_PER_LINECOUNT;
   561         }
   562         pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0,
   563                                       pvr2_state.irq_hpos_time_ns );
   564         break;
   565         case DISP_VPOSIRQ:
   566             val = val & 0x03FF03FF;
   567             pvr2_state.irq_vpos1 = (val >> 16);
   568             pvr2_state.irq_vpos2 = val & 0x03FF;
   569             pvr2_update_raster_posn(sh4r.slice_cycle);
   570             pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );
   571             pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );
   572             MMIO_WRITE( PVR2, reg, val );
   573             break;
   574         case RENDER_NEARCLIP:
   575             MMIO_WRITE( PVR2, reg, val & 0x7FFFFFFF );
   576             break;
   577         case RENDER_SHADOW:
   578             MMIO_WRITE( PVR2, reg, val&0x000001FF );
   579             break;
   580         case RENDER_OBJCFG:
   581             MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
   582             break;
   583         case RENDER_TSPCLIP:
   584             MMIO_WRITE( PVR2, reg, val&0x7FFFFFFF );
   585             break;
   586         case RENDER_FARCLIP:
   587             MMIO_WRITE( PVR2, reg, val&0xFFFFFFF0 );
   588             break;
   589         case RENDER_BGPLANE:
   590             MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
   591             break;
   592         case RENDER_ISPCFG:
   593             MMIO_WRITE( PVR2, reg, val&0x00FFFFF9 );
   594             break;
   595         case VRAM_CFG1:
   596             MMIO_WRITE( PVR2, reg, val&0x000000FF );
   597             break;
   598         case VRAM_CFG2:
   599             MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
   600             break;
   601         case VRAM_CFG3:
   602             MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
   603             break;
   604         case RENDER_FOGTBLCOL:
   605         case RENDER_FOGVRTCOL:
   606             MMIO_WRITE( PVR2, reg, val&0x00FFFFFF );
   607             break;
   608         case RENDER_FOGCOEFF:
   609             MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
   610             break;
   611         case RENDER_CLAMPHI:
   612         case RENDER_CLAMPLO:
   613             MMIO_WRITE( PVR2, reg, val );
   614             break;
   615         case RENDER_TEXSIZE:
   616             MMIO_WRITE( PVR2, reg, val&0x00031F1F );
   617             break;
   618         case RENDER_PALETTE:
   619             MMIO_WRITE( PVR2, reg, val&0x00000003 );
   620             break;
   621         case RENDER_ALPHA_REF:
   622             MMIO_WRITE( PVR2, reg, val&0x000000FF );
   623             break;
   624             /********** CRTC registers *************/
   625         case DISP_HBORDER:
   626         case DISP_VBORDER:
   627             MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
   628             break;
   629         case DISP_TOTAL:
   630             val = val & 0x03FF03FF;
   631             MMIO_WRITE( PVR2, reg, val );
   632             pvr2_update_raster_posn(sh4r.slice_cycle);
   633             pvr2_state.total_lines = (val >> 16) + 1;
   634             pvr2_state.line_size = (val & 0x03FF) + 1;
   635             pvr2_state.line_time_ns = 1000000 * pvr2_state.line_size / pvr2_state.dot_clock;
   636             pvr2_state.retrace_end_line = 0x2A;
   637             pvr2_state.retrace_start_line = pvr2_state.total_lines - 6;
   638             pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );
   639             pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );
   640             pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0, 
   641                                           pvr2_state.irq_hpos_time_ns );
   642             break;
   643         case DISP_SYNCCFG:
   644             MMIO_WRITE( PVR2, reg, val&0x000003FF );
   645             pvr2_state.interlaced = (val & 0x0010) ? TRUE : FALSE;
   646             break;
   647         case DISP_SYNCTIME:
   648             pvr2_state.vsync_lines = (val >> 8) & 0x0F;
   649             pvr2_state.hsync_width_ns = ((val & 0x7F) + 1) * 2000000 / pvr2_state.dot_clock;
   650             MMIO_WRITE( PVR2, reg, val&0xFFFFFF7F );
   651             break;
   652         case DISP_CFG2:
   653             MMIO_WRITE( PVR2, reg, val&0x003F01FF );
   654             break;
   655         case DISP_HPOS:
   656             val = val & 0x03FF;
   657             pvr2_state.front_porch_ns = (val + 1) * 1000000 / pvr2_state.dot_clock;
   658             MMIO_WRITE( PVR2, reg, val );
   659             break;
   660         case DISP_VPOS:
   661             MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
   662             break;
   664             /*********** Tile accelerator registers ***********/
   665         case TA_POLYPOS:
   666         case TA_LISTPOS:
   667             /* Readonly registers */
   668             break;
   669         case TA_TILEBASE:
   670         case TA_LISTEND:
   671         case TA_LISTBASE:
   672             MMIO_WRITE( PVR2, reg, val&0x00FFFFE0 );
   673             break;
   674         case RENDER_TILEBASE:
   675         case TA_POLYBASE:
   676         case TA_POLYEND:
   677             MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
   678             break;
   679         case TA_TILESIZE:
   680             MMIO_WRITE( PVR2, reg, val&0x000F003F );
   681             break;
   682         case TA_TILECFG:
   683             MMIO_WRITE( PVR2, reg, val&0x00133333 );
   684             break;
   685         case TA_INIT:
   686             if( val & 0x80000000 )
   687                 pvr2_ta_init();
   688             break;
   689         case TA_REINIT:
   690             break;
   691             /**************** Scaler registers? ****************/
   692         case RENDER_SCALER:
   693             MMIO_WRITE( PVR2, reg, val&0x0007FFFF );
   694             break;
   696         case YUV_ADDR:
   697             val = val & 0x00FFFFF8;
   698             MMIO_WRITE( PVR2, reg, val );
   699             pvr2_yuv_init( val );
   700             break;
   701         case YUV_CFG:
   702             MMIO_WRITE( PVR2, reg, val&0x01013F3F );
   703             pvr2_yuv_set_config(val);
   704             break;
   706             /**************** Unknowns ***************/
   707         case PVRUNK1:
   708             MMIO_WRITE( PVR2, reg, val&0x000007FF );
   709             break;
   710         case PVRUNK2:
   711             MMIO_WRITE( PVR2, reg, val&0x00000007 );
   712             break;
   713         case PVRUNK3:
   714             MMIO_WRITE( PVR2, reg, val&0x000FFF3F );
   715             break;
   716         case PVRUNK5:
   717             MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
   718             break;
   719         case PVRUNK7:
   720             MMIO_WRITE( PVR2, reg, val&0x00000001 );
   721             break;
   722         case PVRUNK8:
   723             MMIO_WRITE( PVR2, reg, val&0x0300FFFF );
   724             break;
   725     }
   726 }
   728 /**
   729  * Calculate the current read value of the syncstat register, using
   730  * the current SH4 clock time as an offset from the last timeslice.
   731  * The register reads (LSB to MSB) as:
   732  *     0..9  Current scan line
   733  *     10    Odd/even field (1 = odd, 0 = even)
   734  *     11    Display active (including border and overscan)
   735  *     12    Horizontal sync off
   736  *     13    Vertical sync off
   737  * Note this method is probably incorrect for anything other than straight
   738  * interlaced PAL/NTSC, and needs further testing. 
   739  */
   740 uint32_t pvr2_get_sync_status()
   741 {
   742     pvr2_update_raster_posn(sh4r.slice_cycle);
   743     uint32_t result = pvr2_state.line_count;
   745     if( pvr2_state.odd_even_field ) {
   746         result |= 0x0400;
   747     }
   748     if( (pvr2_state.line_count & 0x01) == pvr2_state.odd_even_field ) {
   749         if( pvr2_state.line_remainder > pvr2_state.hsync_width_ns ) {
   750             result |= 0x1000; /* !HSYNC */
   751         }
   752         if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
   753             if( pvr2_state.line_remainder > pvr2_state.front_porch_ns ) {
   754                 result |= 0x2800; /* Display active */
   755             } else {
   756                 result |= 0x2000; /* Front porch */
   757             }
   758         }
   759     } else {
   760         if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
   761             if( pvr2_state.line_remainder < (pvr2_state.line_time_ns - pvr2_state.back_porch_ns)) {
   762                 result |= 0x3800; /* Display active */
   763             } else {
   764                 result |= 0x3000;
   765             }
   766         } else {
   767             result |= 0x1000; /* Back porch */
   768         }
   769     }
   770     return result;
   771 }
   773 /**
   774  * Schedule a "scanline" event. This actually goes off at
   775  * 2 * line in even fields and 2 * line + 1 in odd fields.
   776  * Otherwise this behaves as per pvr2_schedule_line_event().
   777  * The raster position should be updated before calling this
   778  * method.
   779  * @param eventid Event to fire at the specified time
   780  * @param line Line on which to fire the event (this is 2n/2n+1 for interlaced
   781  *  displays). 
   782  * @param hpos_ns Nanoseconds into the line at which to fire.
   783  */
   784 static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int hpos_ns )
   785 {
   786     uint32_t field = pvr2_state.odd_even_field;
   787     if( line <= pvr2_state.line_count && pvr2_state.interlaced ) {
   788         field = !field;
   789     }
   790     if( hpos_ns > pvr2_state.line_time_ns ) {
   791         hpos_ns = pvr2_state.line_time_ns;
   792     }
   794     line <<= 1;
   795     if( field ) {
   796         line += 1;
   797     }
   799     if( line < pvr2_state.total_lines ) {
   800         uint32_t lines;
   801         uint32_t time;
   802         if( line <= pvr2_state.line_count ) {
   803             lines = (pvr2_state.total_lines - pvr2_state.line_count + line);
   804         } else {
   805             lines = (line - pvr2_state.line_count);
   806         }
   807         if( lines <= minimum_lines ) {
   808             lines += pvr2_state.total_lines;
   809         }
   810         time = (lines * pvr2_state.line_time_ns) - pvr2_state.line_remainder + hpos_ns;
   811         event_schedule( eventid, time );
   812     } else {
   813         event_cancel( eventid );
   814     }
   815 }
   817 void pvr2_queue_gun_event( int xpos, int ypos )
   818 {
   819     pvr2_update_raster_posn(sh4r.slice_cycle);
   820     pvr2_schedule_scanline_event( EVENT_GUNPOS, (ypos >> 1) + pvr2_state.vsync_lines, 0,  
   821             (1000000 * xpos / pvr2_state.dot_clock) + pvr2_state.hsync_width_ns ); 
   822 }
   824 MMIO_REGION_READ_FN( PVR2, reg )
   825 {
   826     reg &= 0xFFF;
   827     switch( reg ) {
   828     case DISP_SYNCSTAT:
   829         return pvr2_get_sync_status();
   830     default:
   831         return MMIO_READ( PVR2, reg );
   832     }
   833 }
   834 MMIO_REGION_READ_DEFSUBFNS(PVR2)
   835 MMIO_REGION_READ_DEFSUBFNS(PVR2PAL)
   837 MMIO_REGION_WRITE_FN( PVR2PAL, reg, val )
   838 {
   839     reg &= 0xFFF;
   840     MMIO_WRITE( PVR2PAL, reg, val );
   841     pvr2_state.palette_changed = TRUE;
   842 }
   844 void pvr2_check_palette_changed()
   845 {
   846     if( pvr2_state.palette_changed ) {
   847         texcache_invalidate_palette();
   848         pvr2_state.palette_changed = FALSE;
   849     }
   850 }
   852 MMIO_REGION_READ_DEFFN( PVR2PAL );
   854 void pvr2_set_base_address( uint32_t base ) 
   855 {
   856     mmio_region_PVR2_write( DISP_ADDR1, base );
   857 }
   859 render_buffer_t pvr2_create_render_buffer( sh4addr_t addr, int width, int height, GLuint tex_id )
   860 {
   861     if( display_driver != NULL && display_driver->create_render_buffer != NULL ) {
   862         render_buffer_t buffer = display_driver->create_render_buffer(width,height,tex_id);
   863         buffer->address = addr;
   864         return buffer;
   865     }
   866     return NULL;
   867 }
   869 void pvr2_destroy_render_buffer( render_buffer_t buffer )
   870 {
   871     if( !buffer->flushed )
   872         pvr2_render_buffer_copy_to_sh4( buffer );
   873      display_driver->destroy_render_buffer( buffer );
   874 }
   876 void pvr2_finish_render_buffer( render_buffer_t buffer )
   877 {
   878     display_driver->finish_render( buffer );
   879 }
   881 /**
   882  * Find the render buffer corresponding to the requested output frame
   883  * (does not consider texture renders). 
   884  * @return the render_buffer if found, or null if no such buffer.
   885  *
   886  * Note: Currently does not consider "partial matches", ie partial
   887  * frame overlap - it probably needs to do this.
   888  */
   889 render_buffer_t pvr2_get_render_buffer( frame_buffer_t frame )
   890 {
   891     int i;
   892     for( i=0; i<render_buffer_count; i++ ) {
   893         if( render_buffers[i] != NULL && render_buffers[i]->address == frame->address ) {
   894             return render_buffers[i];
   895         }
   896     }
   897     return NULL;
   898 }
   900 /**
   901  * Allocate a render buffer with the requested parameters.
   902  * The order of preference is:
   903  *   1. An existing buffer with the same address. (not flushed unless the new
   904  * size is smaller than the old one).
   905  *   2. An existing buffer with the same size chosen by LRU order. Old buffer
   906  *       is flushed to vram.
   907  *   3. A new buffer if one can be created.
   908  *   4. The current display buff
   909  * Note: The current display field(s) will never be overwritten except as a last
   910  * resort.
   911  */
   912 render_buffer_t pvr2_alloc_render_buffer( sh4addr_t render_addr, int width, int height )
   913 {
   914     int i;
   915     render_buffer_t result = NULL;
   917     /* Check existing buffers for an available buffer */
   918     for( i=0; i<render_buffer_count; i++ ) {
   919         if( render_buffers[i]->width == width && render_buffers[i]->height == height ) {
   920             /* needs to be the right dimensions */
   921             if( render_buffers[i]->address == render_addr ) {
   922                 if( displayed_render_buffer == render_buffers[i] ) {
   923                     /* Same address, but we can't use it because the
   924                      * display has it. Mark it as unaddressed for later.
   925                      */
   926                     render_buffers[i]->address = -1;
   927                 } else {
   928                     /* perfect */
   929                     result = render_buffers[i];
   930                     break;
   931                 }
   932             } else if( render_buffers[i]->address == -1 && result == NULL && 
   933                     displayed_render_buffer != render_buffers[i] ) {
   934                 result = render_buffers[i];
   935             }
   937         } else if( render_buffers[i]->address == render_addr ) {
   938             /* right address, wrong size - if it's larger, flush it, otherwise 
   939              * nuke it quietly */
   940             if( render_buffers[i]->width * render_buffers[i]->height >
   941             width*height ) {
   942                 pvr2_render_buffer_copy_to_sh4( render_buffers[i] );
   943             }
   944             render_buffers[i]->address = -1;
   945         }
   946     }
   948     /* Nothing available - make one */
   949     if( result == NULL ) {
   950         if( render_buffer_count == MAX_RENDER_BUFFERS ) {
   951             /* maximum buffers reached - need to throw one away */
   952             uint32_t field1_addr = MMIO_READ( PVR2, DISP_ADDR1 );
   953             uint32_t field2_addr = MMIO_READ( PVR2, DISP_ADDR2 );
   954             for( i=0; i<render_buffer_count; i++ ) {
   955                 if( render_buffers[i]->address != field1_addr &&
   956                         render_buffers[i]->address != field2_addr &&
   957                         render_buffers[i] != displayed_render_buffer ) {
   958                     /* Never throw away the current "front buffer(s)" */
   959                     result = render_buffers[i];
   960                     if( !result->flushed && result->address != -1 ) {
   961                         pvr2_render_buffer_copy_to_sh4( result );
   962                     }
   963                     if( result->width != width || result->height != height ) {
   964                         display_driver->destroy_render_buffer(render_buffers[i]);
   965                         result = display_driver->create_render_buffer(width,height,0);
   966                         render_buffers[i] = result;
   967                     }
   968                     break;
   969                 }
   970             }
   971         } else {
   972             result = display_driver->create_render_buffer(width,height,0);
   973             if( result != NULL ) { 
   974                 render_buffers[render_buffer_count++] = result;
   975             }
   976         }
   977     }
   979     if( result != NULL ) {
   980         result->address = render_addr;
   981     }
   982     return result;
   983 }
   985 /**
   986  * Allocate a render buffer based on the current rendering settings
   987  */
   988 render_buffer_t pvr2_next_render_buffer()
   989 {
   990     render_buffer_t result = NULL;
   991     uint32_t render_addr = MMIO_READ( PVR2, RENDER_ADDR1 );
   992     uint32_t render_mode = MMIO_READ( PVR2, RENDER_MODE );
   993     uint32_t render_scale = MMIO_READ( PVR2, RENDER_SCALER );
   994     uint32_t render_stride = MMIO_READ( PVR2, RENDER_SIZE ) << 3;
   996     int width = pvr2_scene_buffer_width();
   997     int height = pvr2_scene_buffer_height();
   998     int colour_format = render_colour_formats[render_mode&0x07];
  1000     if( render_addr & 0x01000000 ) { /* vram64 */
  1001         render_addr = (render_addr & 0x00FFFFFF) + PVR2_RAM_BASE_INT;
  1002     } else { /* vram32 */
  1003         render_addr = (render_addr & 0x00FFFFFF) + PVR2_RAM_BASE;
  1005     result = pvr2_alloc_render_buffer( render_addr, width, height );
  1007     /* Setup the buffer */
  1008     if( result != NULL ) {
  1009         result->rowstride = render_stride;
  1010         result->colour_format = colour_format;
  1011         result->scale = render_scale;
  1012         result->size = width * height * colour_formats[colour_format].bpp;
  1013         result->flushed = FALSE;
  1014         result->inverted = TRUE; // render buffers are inverted normally
  1016     return result;
  1019 static render_buffer_t pvr2_frame_buffer_to_render_buffer( frame_buffer_t frame )
  1021     render_buffer_t result = pvr2_alloc_render_buffer( frame->address, frame->width, frame->height );
  1022     if( result != NULL ) {
  1023         int bpp = colour_formats[frame->colour_format].bpp;
  1024         result->rowstride = frame->rowstride;
  1025         result->colour_format = frame->colour_format;
  1026         result->scale = 0x400;
  1027         result->size = frame->width * frame->height * bpp;
  1028         result->flushed = TRUE;
  1029         result->inverted = frame->inverted;
  1030         display_driver->load_frame_buffer( frame, result );
  1032     return result;
  1036 /**
  1037  * Invalidate any caching on the supplied address. Specifically, if it falls
  1038  * within any of the render buffers, flush the buffer back to PVR2 ram.
  1039  */
  1040 gboolean pvr2_render_buffer_invalidate( sh4addr_t address, gboolean isWrite )
  1042     int i;
  1043     address = address & 0x1FFFFFFF;
  1044     for( i=0; i<render_buffer_count; i++ ) {
  1045         uint32_t bufaddr = render_buffers[i]->address;
  1046         if( bufaddr != -1 && bufaddr <= address && 
  1047                 (bufaddr + render_buffers[i]->size) > address ) {
  1048             if( !render_buffers[i]->flushed ) {
  1049                 pvr2_render_buffer_copy_to_sh4( render_buffers[i] );
  1051             if( isWrite ) {
  1052                 render_buffers[i]->address = -1; /* Invalid */
  1054             return TRUE; /* should never have overlapping buffers */
  1057     return FALSE;
.