lxdream 0.9.1| filename | src/sh4/mmu.h |
| changeset | 946:d41ee7994db7 |
| prev | 945:787729653236 |
| next | 1067:d3c00ffccfcd |
| author | nkeynes |
| date | Tue Jan 06 01:58:08 2009 +0000 (15 years ago) |
| branch | lxdream-mem |
| permissions | -rw-r--r-- |
| last change | Fully integrate SQ with the new address space code - added additional 'prefetch' memory accessor. TLB is utterly untested, but non-TLB at least still works. |
| view | annotate | diff | log | raw |
1 /**
2 * $Id$
3 *
4 * MMU/TLB definitions.
5 *
6 * Copyright (c) 2005 Nathan Keynes.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
20 #ifndef lxdream_sh4_mmu_H
21 #define lxdream_sh4_mmu_H 1
23 #include "lxdream.h"
25 #ifdef __cplusplus
26 extern "C" {
27 #endif
29 #define VMA_TO_EXT_ADDR(vma) ((vma)&0x1FFFFFFF)
31 /************************** UTLB/ITLB Definitions ***************************/
32 /* mmucr register bits */
33 #define MMUCR_AT 0x00000001 /* Address Translation enabled */
34 #define MMUCR_TI 0x00000004 /* TLB invalidate (always read as 0) */
35 #define MMUCR_SV 0x00000100 /* Single Virtual mode=1 / multiple virtual=0 */
36 #define MMUCR_SQMD 0x00000200 /* Store queue mode bit (0=user, 1=priv only) */
37 #define MMUCR_URC 0x0000FC00 /* UTLB access counter */
38 #define MMUCR_URB 0x00FC0000 /* UTLB entry boundary */
39 #define MMUCR_LRUI 0xFC000000 /* Least recently used ITLB */
40 #define MMUCR_MASK 0xFCFCFF05
41 #define MMUCR_RMASK 0xFCFCFF01 /* Read mask */
43 #define IS_TLB_ENABLED() (MMIO_READ(MMU, MMUCR)&MMUCR_AT)
44 #define IS_SV_ENABLED() (MMIO_READ(MMU,MMUCR)&MMUCR_SV)
46 #define ITLB_ENTRY_COUNT 4
47 #define UTLB_ENTRY_COUNT 64
49 /* Entry address */
50 #define TLB_VALID 0x00000100
51 #define TLB_USERMODE 0x00000040
52 #define TLB_WRITABLE 0x00000020
53 #define TLB_USERWRITABLE (TLB_WRITABLE|TLB_USERMODE)
54 #define TLB_SIZE_MASK 0x00000090
55 #define TLB_SIZE_1K 0x00000000
56 #define TLB_SIZE_4K 0x00000010
57 #define TLB_SIZE_64K 0x00000080
58 #define TLB_SIZE_1M 0x00000090
59 #define TLB_CACHEABLE 0x00000008
60 #define TLB_DIRTY 0x00000004
61 #define TLB_SHARE 0x00000002
62 #define TLB_WRITETHRU 0x00000001
64 #define MASK_1K 0xFFFFFC00
65 #define MASK_4K 0xFFFFF000
66 #define MASK_64K 0xFFFF0000
67 #define MASK_1M 0xFFF00000
69 struct itlb_entry {
70 sh4addr_t vpn; // Virtual Page Number
71 uint32_t asid; // Process ID
72 uint32_t mask;
73 sh4addr_t ppn; // Physical Page Number
74 uint32_t flags;
75 };
77 struct utlb_entry {
78 sh4addr_t vpn; // Virtual Page Number
79 uint32_t mask; // Page size mask
80 uint32_t asid; // Process ID
81 sh4addr_t ppn; // Physical Page Number
82 uint32_t flags;
83 uint32_t pcmcia; // extra pcmcia data - not used in this implementation
84 };
86 #define TLB_FUNC_SIZE 48
88 struct utlb_page_entry {
89 struct mem_region_fn fn;
90 struct mem_region_fn *user_fn;
91 mem_region_fn_t target;
92 unsigned char code[TLB_FUNC_SIZE*9];
93 };
95 struct utlb_1k_entry {
96 struct mem_region_fn fn;
97 struct mem_region_fn user_fn;
98 struct mem_region_fn *subpages[4];
99 struct mem_region_fn *user_subpages[4];
100 unsigned char code[TLB_FUNC_SIZE*18];
101 };
103 struct utlb_default_regions {
104 mem_region_fn_t tlb_miss;
105 mem_region_fn_t tlb_prot;
106 mem_region_fn_t tlb_multihit;
107 };
110 void mmu_utlb_init_vtable( struct utlb_entry *ent, struct utlb_page_entry *page, gboolean writable );
111 void mmu_utlb_1k_init_vtable( struct utlb_1k_entry *ent );
112 void mmu_utlb_init_storequeue_vtable( struct utlb_entry *ent, struct utlb_page_entry *page );
114 extern uint32_t mmu_urc;
115 extern uint32_t mmu_urb;
117 /** Primary SH4 address space (privileged and user access)
118 * Page map (4KB) of the entire 32-bit address space
119 * Note: only callable from the SH4 cores as it depends on the caller setting
120 * up an appropriate exception environment.
121 **/
122 extern struct mem_region_fn **sh4_address_space;
123 extern struct mem_region_fn **sh4_user_address_space;
125 /************ Storequeue/cache functions ***********/
126 void FASTCALL ccn_storequeue_write_long( sh4addr_t addr, uint32_t val );
127 int32_t FASTCALL ccn_storequeue_read_long( sh4addr_t addr );
129 /** Default storequeue prefetch when TLB is disabled */
130 void FASTCALL ccn_storequeue_prefetch( sh4addr_t addr );
132 /** TLB-enabled variant of the storequeue prefetch */
133 void FASTCALL ccn_storequeue_prefetch_tlb( sh4addr_t addr );
135 /** Non-storequeue prefetch */
136 void FASTCALL ccn_prefetch( sh4addr_t addr );
138 /** Non-cached prefetch (ie, no-op) */
139 void FASTCALL ccn_uncached_prefetch( sh4addr_t addr );
142 extern struct mem_region_fn mem_region_address_error;
143 extern struct mem_region_fn mem_region_tlb_miss;
144 extern struct mem_region_fn mem_region_tlb_multihit;
145 extern struct mem_region_fn mem_region_tlb_protected;
147 extern struct mem_region_fn p4_region_storequeue;
148 extern struct mem_region_fn p4_region_storequeue_multihit;
149 extern struct mem_region_fn p4_region_storequeue_miss;
150 extern struct mem_region_fn p4_region_storequeue_protected;
151 extern struct mem_region_fn p4_region_storequeue_sqmd;
152 extern struct mem_region_fn p4_region_storequeue_sqmd_miss;
153 extern struct mem_region_fn p4_region_storequeue_sqmd_multihit;
154 extern struct mem_region_fn p4_region_storequeue_sqmd_protected;
156 #ifdef __cplusplus
157 }
158 #endif
159 #endif /* !lxdream_sh4_mmu_H */
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